WEBVTT 00:00.000 --> 00:13.000 Hello everyone, my name is Jonas Künstler, and I'm from Heidelberg University. 00:13.000 --> 00:21.000 We'll start my PhD there next month, and I'm one of the main tannies of fabulous, 00:21.000 --> 00:28.000 and I will show you a bit around what you can do there, and let's start. 00:28.000 --> 00:33.000 A little bit of background for those who don't know maybe FPGA architecture. 00:33.000 --> 00:38.000 Yeah, you have basic tiles. 00:38.000 --> 00:42.000 In this case, it's like a COB tile, which implements a little bit of logic, 00:42.000 --> 00:46.000 and they are connected through routing network with just a bunch of wires that are going to, 00:46.000 --> 00:51.000 from every tile to the next one, and it's fun multiple tiles with. 00:51.000 --> 00:56.000 And inside one, each COB, there's, you have a switch matrix, 00:56.000 --> 01:04.000 which is basically a bunch of multiplexers that can connect arbitraw wires 01:04.000 --> 01:10.000 to every other wire of every tile, and to the logic. 01:10.000 --> 01:20.000 The lookup tables that are inside the tile, and the lookup table can basically implement an arbitraw 01:20.000 --> 01:25.000 logic function, in this case, what you can see here, 01:25.000 --> 01:28.000 maybe some of you will figure out what this is something you do. 01:28.000 --> 01:33.000 Usually, don't want to have a new FPGA with this circuit implements, 01:33.000 --> 01:36.000 but it's maybe nice example. 01:36.000 --> 01:38.000 Maybe some of you will get it. 01:38.000 --> 01:41.000 Yeah. 01:41.000 --> 01:48.000 So for fabulous FPGA fabric generator, so you can build your own FPGA 01:48.000 --> 01:49.000 with this. 01:49.000 --> 01:54.000 We integrate cat rules, joses, and next piano automatically, 01:54.000 --> 02:00.000 so we generate the model files for this that you can also actually use your FPGA. 02:00.000 --> 02:04.000 Once you have fabricated, it's relatively easy to use, 02:04.000 --> 02:08.000 if you just want to do basic stuff, but if you want to dive in deep, 02:08.000 --> 02:14.000 you can technically fully customize every single bit and piece inside. 02:14.000 --> 02:20.000 That's pretty good results, so far, and it's still you can through and through. 02:20.000 --> 02:27.000 I think now 18 tape outs, from at least that we know of, not all them by us, 02:27.000 --> 02:34.000 but also other universities, and yeah. 02:34.000 --> 02:41.000 Down here, you can see maybe a little comparison that Leo Moza did. 02:41.000 --> 02:46.000 It's like implementing, on a fabulous FPGA, a little risk-wife core, 02:46.000 --> 02:51.000 and compared to a small letters FPGA, and it's just the lab count. 02:51.000 --> 02:58.000 You can see you get like in a similar region, so just show that the fabric is performing quite well. 02:58.000 --> 03:04.000 And we ship with a tile library that you can choose off, like, basically logic tiles. 03:04.000 --> 03:08.000 We have register files and multiply accumulate units. 03:08.000 --> 03:12.000 I odd tiles, and whatever use need. 03:12.000 --> 03:16.000 We have a full simulation set-up that chips out automatically, 03:16.000 --> 03:23.000 where you can simulate the whole fabric, and also simulate a user design on top of the simulated fabric. 03:23.000 --> 03:27.000 And we have a fabulous GUI, I will show later, a bit. 03:27.000 --> 03:30.000 The fabric actually supports partial reconfiguration. 03:30.000 --> 03:35.000 The software support for this is the Lexibut, but we are working on this. 03:35.000 --> 03:38.000 And we have like a pretty extensive documentation. 03:38.000 --> 03:43.000 And for fabulous version 2, which we are working for, like, one and a half years now. 03:43.000 --> 03:50.000 We actually integrated liberal line for, let's say, push button flow to generate the, 03:50.000 --> 03:53.000 a tile then optimized fabric GDS. 03:53.000 --> 04:03.000 So basically you can get from your specification down to real implementation that you can integrate in your chip, 04:03.000 --> 04:06.000 in, like, let's say, one and a half hours. 04:06.000 --> 04:10.000 And this mostly is the runtime, everything is mostly automated. 04:10.000 --> 04:14.000 We also implement now the timing model generation. 04:14.000 --> 04:21.000 So it extracts the actual timing from your chip implementation and feeds it back into the next peer model, 04:21.000 --> 04:28.000 that you actually know how fast your design can run on the FPGA later. 04:28.000 --> 04:33.000 Yeah, we have custom type generation, so you can throw in custom primitives and generate a tile. 04:33.000 --> 04:38.000 For example, you want to do, like, an, I don't know, special X or a tile or whatever. 04:38.000 --> 04:42.000 You can do this, just constantly in a primitive a bit. 04:42.000 --> 04:47.000 It's just need to be a very log or BHDL file and the rest of it generated for you. 04:47.000 --> 04:54.000 Customize our generation if you need some fancy stuff to connect with the rest of the world. 04:54.000 --> 04:59.000 This is also inside. And a lot of improvements, like, we have a Python package now in Pi Pi. 04:59.000 --> 05:08.000 It's still beta, but yeah, we have an X package for the X folks, which also includes the Libre in directly settings management. 05:08.000 --> 05:17.000 We improve the UI, test you, then, yeah, a lot of clean up and, like, a lot of infrastructure work was involved in there. 05:17.000 --> 05:22.000 And this is basically, you know, you're the flow. 05:22.000 --> 05:25.000 You can basically divide this in, like, three parts. 05:25.000 --> 05:31.000 First, you start with, like, you have a few configuration or specification files. 05:31.000 --> 05:37.000 And that you need to provide for fabulous. 05:37.000 --> 05:43.000 And then you run the fabulous flow, which generates, like, RTL for your fabric. 05:43.000 --> 05:50.000 And also the models and primitives for a primitive library and everything for your cultural flow later. 05:50.000 --> 05:58.000 The back end flow for the actual physical implementation of your chip, which you now automated with the Libre lane. 05:58.000 --> 06:04.000 And we're working also on automating the constraints, the generation for commercial tools. 06:04.000 --> 06:17.000 And then you have, like, the user design flow that you really can use this FPGA with, like, the standard open source tools for FPGA, like, Joseph's and XPNR. 06:17.000 --> 06:22.000 And, yeah, this is just the rough overview. 06:22.000 --> 06:27.000 Let's dive a little bit into the concepts of fabulous. 06:27.000 --> 06:32.000 As I said, FPGA is usually implemented in, like, a tile manner. 06:32.000 --> 06:42.000 And we have, like, standard tiles for, let's say, standard lookup table and DSP, and I owe. 06:42.000 --> 06:58.000 And what you have is, like, the routing connection around here, what you can see, these are the routing between the tiles and the switch metrics in the middle and the primitives. 06:58.000 --> 07:07.000 And what you also can do, for example, if you have, like, really big primitives, you can share, like, the routing of multiple tiles and so called super tiles. 07:07.000 --> 07:15.000 This is, for example, done for DSP, since, you know, an hardware, like, multiplies and stuff, or get expand pretty big, an area. 07:15.000 --> 07:22.000 So you share, like, routing, that you have, well, defined interfaces between every tile. 07:22.000 --> 07:27.000 You want to have, like, a similar interface between every tile. 07:27.000 --> 07:32.000 And how do you actually then work with fabulous, it's quite simple. 07:32.000 --> 07:46.000 You, you go on, on a high level view, to do, like, your basic floor planning of their FPGA, you want to do, like, to shuffle around your tiles, however you want to implement them in a CSV file. 07:46.000 --> 07:52.000 You say, okay, you want to waste, I owe there, I want my lookup table tiles there. 07:52.000 --> 07:55.000 What you usually do is to implement this in rows. 07:55.000 --> 08:12.000 And that you have rows of similar tiles that the different, that the height of every tile is always the same in the physical implementation. 08:12.000 --> 08:24.000 And if you need bigger tiles, you expand them in width, for example, the DSP slices are slightly wider than the, a lot slices in physical implementation later. 08:24.000 --> 08:31.000 But, yeah, and for a tile, you basically specify also, in a simple CSV file. 08:31.000 --> 08:39.000 The basic connection interface, you say, okay, we have wired that go from a, a not begin port to a north endpoint. 08:39.000 --> 08:46.000 They have an offset of one and it's a, a, a itm, a, a, a, a, a, a itm, a, a itm, a, a itm. 08:46.000 --> 08:50.000 So you have a routing channel of it wires created. 08:50.000 --> 08:53.000 And this is how you define basically all the tile interfaces. 08:53.000 --> 09:00.000 And then we have a concept called jump wires, which basically are just internal wires for 09:00.000 --> 09:09.560 the switch matrix to build hierarchies inside more in this in a second. 09:09.560 --> 09:17.200 And then you just throw in like your primitives and define where you, for your switch matrix. 09:17.200 --> 09:25.760 This has an own specification file where you just say, okay, all the ports I defined 09:25.760 --> 09:29.200 beforehand, how are they connected. 09:29.200 --> 09:33.560 So you define the internal adjacency of the switch matrix. 09:33.560 --> 09:38.480 And for example, one of those lines where you have like one of these jump ports would 09:38.480 --> 09:47.480 like hierarchy, connects to these four ports we define. 09:47.480 --> 09:54.600 And this will, for example, physically implement a max four later. 09:54.600 --> 09:58.440 And yeah, then you have done your specification. 09:58.440 --> 10:05.560 I mean, we provide a lot of like default tiles for basically everything you need and you 10:05.560 --> 10:07.480 can just adapt it for your needs. 10:07.480 --> 10:11.960 And then you just run everything through the type of CLI. 10:11.960 --> 10:14.800 And it will basically generate everything you need. 10:14.800 --> 10:19.520 And to do this, we will, I will now try to do this life. 10:19.520 --> 10:21.720 I hope you can see it. 10:21.720 --> 10:28.080 And I hope, yeah, demos are always a little bit cursed. 10:28.080 --> 10:33.680 You just start with like, okay, let us create a project. 10:33.680 --> 10:38.240 And say, okay, this is my demo project, you know, we name it now, false demo. 10:38.240 --> 10:41.480 And let me go in there. 10:41.480 --> 10:50.720 And then you can see here, we already provide all our basic configuration files for our 10:50.720 --> 10:57.400 standard tiles and test environment and stuff. 10:57.400 --> 11:00.400 So we already provide you a lot. 11:00.400 --> 11:08.720 And here you can also see your fabric CSV with like our default fabric, how this design. 11:08.720 --> 11:18.920 And then you can see here, for example, the CSV file for the, let's see this CSV. 11:18.960 --> 11:20.440 Which is our basic LATIL. 11:20.440 --> 11:28.440 And they can see, okay, we include here, we have like include files and to show this. 11:28.440 --> 11:32.440 Since usually all the standard tiles have like the same interfaces. 11:32.440 --> 11:35.240 So we can have like an include for this. 11:35.240 --> 11:43.720 And this just defines our interfaces for the tiles as I showed before. 11:43.720 --> 11:50.040 So, and what we then do, okay, we have now defined like the the floor plan of our tiles. 11:50.040 --> 12:00.480 We have defined our tiles and then we say fabulous and run and the command is like run fabulous fabric. 12:00.480 --> 12:09.160 And now fabulous reads in all the files and starts to generate the RTL for this. 12:09.400 --> 12:17.480 It generates the configuration memory layout, it generates the models for next PNR and everything. 12:17.480 --> 12:24.360 And then you can see here also, okay, we have like a bunch more very look files in each of the 12:24.360 --> 12:34.360 tile folders, which basically implement the, you have the the RTL implementation of all the tiles. 12:34.360 --> 12:43.560 And also see like here, okay, in the fabric folder, you see like the top level where everything is put together. 12:43.560 --> 12:53.320 And what you then can do is, since we also have like ship like a basic simulation flow, 12:53.320 --> 13:03.400 where you can run like the simulated fabric and to do to do this, we first look into our, 13:03.480 --> 13:09.880 we have like a simple test design, which is a basic counter running in, which will be run later on the fabric. 13:09.880 --> 13:22.760 So, what we do now is, we build the, the bitstream for our test design. 13:22.760 --> 13:28.840 We already generated the models for next PNR, everything. So, now it called Joseph, 13:28.920 --> 13:33.160 next PNR build the bitstream for our test design. And what we now can do is, 13:40.440 --> 13:48.120 say run simulation and we provide here the bitstream file for, that we previously generated. 13:48.840 --> 13:56.520 And what now happens is like, okay, it will, simulate the whole fabric in Echorus very 13:57.400 --> 14:06.280 and pumps in the actual bitstream that we generated previously. And we have like a test bench 14:06.280 --> 14:14.280 that compares like the output of the fabric with like golden reference, which the same design is 14:14.280 --> 14:20.200 running in parallel and we just compare the output. It takes a few seconds up to a half minute. 14:21.160 --> 14:29.960 And yeah, let's see, the bitstream is loaded and then, yeah, a few asserts will 14:31.960 --> 14:38.520 fire in a second. See, yeah. And so, it's okay here, we are comparing like the output of the fabric top 14:38.520 --> 14:46.600 with the golden reference. And what we also can do is, I already told we have like the 14:46.600 --> 14:51.960 calculator, which is like a graphical user interface for all of this, that you can see, 14:55.960 --> 15:04.040 actually what did you actually implement there? And you can also see how your user design is implemented. 15:04.040 --> 15:15.720 So, I will quickly show this. So, first, first demo, you have to load like a geometry file, 15:17.320 --> 15:24.360 which is basically rendering information for the, for the fibrillator and it's generated through 15:24.360 --> 15:38.040 the usual fabric flow and it takes a second and there you see, this is rendering of the fabric 15:38.040 --> 15:46.600 we build. And you can see here, this is our, our basically look-up paper type, all tiles, 15:46.600 --> 15:54.760 this is register files. And what you now can do is reload the fuzzom, which is basically the 15:54.760 --> 16:05.880 placed and routed net list of our test design. And you can see how this is, which connections in the 16:05.960 --> 16:16.440 switch matrix, implement this design. And yeah, this is quite nice for also like debugging some 16:16.440 --> 16:25.400 stuff since maybe you had some configuration wrong or whatever. And yeah. And what is any 16:25.400 --> 16:32.600 can show here is like the, the physical design flows since this takes like, 16:34.440 --> 16:41.160 yeah, an hour to run through like the whole fabric. And, but I brought a few, 16:43.240 --> 16:49.720 oh, this was like up a few images. As you can see, this is on the left side, the open road, 16:49.880 --> 16:59.080 GUI on the right side is the output of fabulous. And as you can see, these are the 17:00.680 --> 17:10.760 actual tiles, how they are implemented. As, yeah, this is like the, the GDS that you would 17:10.840 --> 17:20.920 basically send to the, to the FAP or integrate to your chip. And this is in the layout of one 17:20.920 --> 17:30.840 single tile. And what you can see here, this green little, what's here on the side, these are the 17:30.840 --> 17:38.200 actual ports and of each tile. And we built everything in a way and optimize it, that every tile 17:38.280 --> 17:46.840 implements like the same, um, and the same pins and the same, um, um, and the same pin lay out 17:46.840 --> 17:51.880 that you can directly stitch each tile to the next. There's really no routing in between. 17:51.880 --> 17:56.760 What you can see here, this is this small dots here. This is the physical implementation of the, 17:56.760 --> 18:01.480 of the, of the, of the stitched fabric. And you can see this is like port to port, 18:02.360 --> 18:11.000 connection here. And, um, yeah. And yeah, we fully automated this. And this is basically 18:11.560 --> 18:20.040 two commands to get everything out there. And it's going to be, with liberal lanes, so it's basically 18:20.040 --> 18:28.680 just for the open source tools. And the open source PDKs that out there. So, um, HP 130, 18:29.400 --> 18:38.840 skyward and sweaty and, uh, TSN global fund is 180. Um, but yeah, we'll see how this goes in the future. 18:38.840 --> 18:43.880 And we're working on doing something similar also for commercial flows. Um, this is now in, 18:43.880 --> 18:50.680 uh, the physical layout of the whole chip. I just flipped it around, um, it's for reference. And yeah. 18:51.240 --> 19:01.240 And you see, we already have like a lot of users in the, um, academic world. Uh, let's say, 19:01.240 --> 19:09.480 um, there are, um, yeah, you see like Stanford University Berkeley, uh, New York University. 19:09.480 --> 19:17.960 And a lot more, this is, this are at least the ones we know of. Um, there are a bunch more, um, 19:18.040 --> 19:26.920 I guess, but they never really contact us. Um, uh, some of them just contacted us after they 19:26.920 --> 19:33.800 taped out a chip and got it back and said, hey, the stuff was actually working. Um, um, and of course, 19:33.800 --> 19:41.240 we, we also did a lot of, uh, tape outs. I think we did, uh, now nearly 10, uh, on our own. And, uh, 19:41.320 --> 19:50.120 you see like, you know, all the major, in all the major, um, uh, open source PDKs and, um, a few commercial ones, 19:51.720 --> 19:58.440 and we're currently working on a 22 nanometer, um, version, uh, implementation and this will fly off 19:58.440 --> 20:07.480 in more advanced notes will come soon. And another thing we're working on this year, um, is, uh, 20:07.560 --> 20:13.560 our open board. Um, this is like the first revision. This is just, 20:13.560 --> 20:19.960 only just, um, and, and, uh, FPGA. But the whole ideas we want to build and, um, um, an open board 20:19.960 --> 20:25.800 for educational purposes, would like having a risk pipe tightly coupled with an, uh, FPGA, 20:26.600 --> 20:35.000 and that you, for example, um, can do, um, um, um, custom instructions, custom, 20:35.560 --> 20:41.320 a risk pipe instructions inside the FPGA. Also, let's say reconfigurable custom instructions. 20:41.320 --> 20:47.880 And, uh, but having everything in a manner that you can just hand it out to students, 20:47.880 --> 20:56.520 you plug it in, uh, something like a, um, uh, a Python shell pops up immediately. So the 20:56.600 --> 21:04.280 ideas to have something that students can fully understand to down to every transistor and with 21:04.280 --> 21:12.360 like open source, um, PDKs and, uh, the open source tools, we can actually do this. So we are 21:12.360 --> 21:19.000 then allowed to like publish everything we have. And, uh, to build something, um, um, yeah, 21:19.960 --> 21:29.400 really entirely understandable. Um, and, yeah, um, we're seeking for contributors, uh, software and hardware, 21:29.400 --> 21:38.120 uh, whatever you want, uh, just contact me. And, yeah. Another thing in hard work, we also, um, we are, 21:38.120 --> 21:45.320 um, doing, uh, summer school every year, um, it's the high-chip summer school, um, it's usually three days 21:45.320 --> 21:52.360 off, um, yeah, um, lectures, note, uh, keynotes and talks and everything. And then there's a two-day 21:52.360 --> 22:00.120 hackathon where the students, uh, or the, the participants, uh, actually implement, uh, designs. 22:00.840 --> 22:08.680 And, um, we throw everything together in, uh, let's say, tiny tape out manner, um, and connect 22:08.680 --> 22:15.160 everything to an FPGA that, um, designs can be shared that they can share resources, uh, like 22:15.480 --> 22:23.000 RAM, and stuff. And, um, yeah, this is like our last tape out that what will, uh, uh, it's a 22:23.000 --> 22:29.320 coin state of it, and it would be taped out in the next I HP run. And everything done only with 22:29.320 --> 22:36.920 open source tools, of course. Um, yeah, you can sign up. And, uh, I think the website for this year 22:36.920 --> 22:43.000 isn't all right, uh, not there yet, but it will come soon. Um, it's, it will redirect to the old 22:43.000 --> 22:50.600 one, um, and yeah, um, yeah. And of course, we are, we are sponsored for this by 22:50.600 --> 22:57.880 a chip design Germany and the BMFTR, which is the German, um, uh, ministry for 22:58.920 --> 23:08.440 research, technology and space, um, this, yeah. Yeah, um, that's it. Here you find our, uh, 23:08.520 --> 23:15.240 GitHub repo documentation, all the other projects we are working on, um, uh, in the, in the, 23:15.240 --> 23:20.360 in the group in Hidalburg. And here are some pictures of some of the tape outs we did. 23:21.080 --> 23:27.480 Um, this one is quite interesting. Uh, for example, this is our um based FPGA, um, the fabulous 23:27.480 --> 23:34.760 architecture allows to put easily, um, swap out parts with different parts, for example, the configuration 23:34.840 --> 23:42.760 memory, uh, to an RR configuration memory, um, just an example. Yeah, um, questions. 23:45.480 --> 23:51.960 Um, yeah. Yeah, there's the most recent, uh, chip that you've got back from a open 23:51.960 --> 24:01.320 dedicated, other treatment tested. Um, the most, uh, sorry, um, yeah, the question was, um, the most 24:01.400 --> 24:10.040 recent, um, chip that we got back and tested with and, uh, that was produced with an open PDK, um, 24:11.080 --> 24:19.080 the, we have a few that haven't done, bring up, but the most recent one was the MPW five, um, 24:19.080 --> 24:30.760 which was sky 130, um, and we, um, are awaiting, uh, um, we had done a few in the, uh, so this one was 24:30.840 --> 24:40.920 working. I have it here. Um, and, um, we have, um, we're also waiting for a recent HP run, and we also 24:40.920 --> 24:49.560 had a few sky runs in between, uh, which, uh, where the, bring up isn't finally done yet. Um, yeah. 24:51.560 --> 24:52.040 Um, yeah. 24:53.240 --> 24:57.080 It's one of the, um, the explainer bit more how you're getting the timing for the, uh, the 24:58.040 --> 25:04.520 right. Yeah. Um, we actually, um, uh, the question was how we get out the timing model, um, 25:05.800 --> 25:12.680 out of the, uh, physical design. So we run through, uh, everything with, with, uh, a liberal 25:12.680 --> 25:21.400 line and get out the GDS and, uh, STC files, so the standard delay, um, format. And then we, very, um, 25:21.480 --> 25:31.000 for every, we have in the next pin, our model, all the, um, all the, pips. So every, um, um, um, 25:31.000 --> 25:35.720 programmable interconnect points for every place that, uh, every pin that can be implemented or 25:35.720 --> 25:42.280 every connection can be implemented and we query with, um, open STA, the STF files and match the 25:42.280 --> 25:49.080 pips and the actual physical implementation, uh, and extract the timing for every path and match 25:49.160 --> 26:00.920 back to the pips. And um, for the, um, bells, it's, um, the thing is that the next pin, our model 26:00.920 --> 26:09.960 doesn't, um, how we can, we have it, um, only represents the routing and not the bells, but we can 26:09.960 --> 26:15.400 query the bell in the same way. So we get the timing for the bells, um, but this needs a little bit 26:15.560 --> 26:23.880 more, um, refinement and, uh, in the next pin, our implementation, but, uh, this is something 26:23.880 --> 26:28.360 we are also, uh, working on, yeah. Yes? 26:28.360 --> 26:33.560 Your place around the floor where you're using the power grid analysis, and is that you have 26:33.560 --> 26:40.840 worried for three? Um, the question was, what we are using for power grid analysis, um, 26:41.080 --> 26:51.480 in the, in the, uh, place and route flow, um, this is, um, whatever the, uh, liberal lane flow 26:51.480 --> 27:00.920 provides. I'm not entirely sure. Um, I'm more on the fabulous implementation side. I wasn't that much 27:00.920 --> 27:07.880 into, uh, into this one, um, but we use the, the whole liberal lane flow and whatever is provided in the, 27:07.960 --> 27:14.840 in the open source ecosystem. Um, yeah. What is the biggest tip out if the, um, 27:14.840 --> 27:22.040 publish, uh, first of all, uh, in terms of, um, most interested in LUTs, but, okay. Yeah, um, the biggest 27:22.040 --> 27:29.560 one, um, uh, the question was, uh, what was the biggest tip out we have done so far? Um, 27:29.560 --> 27:34.680 it is the most, uh, one of the, the more recent ones, um, I, 27:35.640 --> 27:46.920 quickly need to think about it. Well, like roughly 4,000 LUTs, if I read, yeah, 4 to 5,000 LUTs, and it was 27:46.920 --> 27:55.320 one on a 22 nanometer. I know, sorry, a 28 nanometer, um, and is done in cooperation with, uh, 27:55.400 --> 28:09.080 New York University. Um, yeah. Um, usually, um, usually the question was, how, how dense 28:09.080 --> 28:18.840 is usually the logic where the virus, uh, on, um, and in terms of, let's say, logic, density, 28:18.920 --> 28:26.040 you mean, look at tables of functionality, you, um, you have? I mean, in jail, when you take out the 28:26.040 --> 28:33.720 chip. Oh, okay. Um, yeah, um, for the HP 130, for example, um, this is quite interesting since 28:33.720 --> 28:43.160 they provide, like, um, seven, uh, metal layers, and, um, FPGA usually routing constraint. And, um, 28:43.320 --> 28:53.960 but with this, we get to, uh, 97% of, um, logic density. Um, so we are not actually routing 28:53.960 --> 29:01.240 constraint on this one, um, but on the, for example, sky 130, um, it was, I don't have exact numbers, 29:01.240 --> 29:08.840 but it was way worse since they just have, like, 5 metal layers, and, um, uh, yeah, this is usually 29:08.920 --> 29:14.920 you are routing constraint, but we have a few optimization games, um, that we can play to get, um, 29:15.800 --> 29:22.120 even denser. I mean, the, the 97, we can't beat, but, uh, for, like, when we are routing constraint, 29:22.120 --> 29:29.800 we can play a few optimization games to squeeze out, like, up to 20, 30% more. Um, yeah. 29:31.480 --> 29:38.200 Okay, um, we're done. Um, if there any question left, we can, uh, talk later, I guess you can find 29:38.200 --> 29:41.480 me somewhere here. Um, yeah, thanks a lot.