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-- HEIG-VD, Haute Ecole d'Ingenierie et de Gestion du canton de Vaud
-- Institut REDS
--
-- Fichier :  top_sim.vhdl
-- Auteur  :  Logisim auto-generated from top_sim.templ > reds@heig-vd.ch
-- Date    :  %date%
--
--------------------------------------------------------------------------------
-- This file has been auto-generated by Logisim, please do not modify.
-- The top sim_file interfaces with all the VHDL components to be
-- simulated by a single instance of the external simulator.
--------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity top_sim is
  port(
    -- %ports%
  );
end top_sim ;

architecture comp of top_sim is

  -- %components%

begin

  -- %map%

end comp;
