# VHDL simulator

Logisim cannot directly perform VHDL content simulation. Instead, QuestaSim is used as a background task.

## Enable simulator

You can enable the simulator through the Simulate > VHDL Simulation Enabled menu. When you do this, the simulator console log appears on the bottom of the drawing pane. At the bottom bar of the simulator log, you have the simulator status indicator. The states are :

- Disabled (console disappears)
- Enabled (but inactive)
- Starting
- Active

The simulator starts automatically when it's enabled and the circuit contains VHDL components. It is not possible to start the simulator when there aren't any VHDL components in the circuit.

## Restart

The VHDL simulation is restarted when you reset the Logisim simulation. This concerns only the simulation state, it does not reload the simulation (and the source files).

If you have changed the content of some VHDL component you have to restart the VHDL simulator. This is never done automatically. You can restart the simulator through the Simulate menu.

## Time

The QuestaSim simulation step time has to be considered unpredictable, as it depends on the number of VHDL components in the circuit. The absolute minimum step is 100ns. Therefore, usage of time-based simulation events must be avoided (like wait for 10ns). You must only have signal-based events.

## Multiple instances

Actually, you can only have a single instance of VHDL simulator. That means that you have to disable it on the first project if you want to have it enabled on a second one. If you try to enable it on two projects it will fail and show you an error message.

Next: Simulating test benchs.