FPGANotSupported = Not supported
FPGASupported = Supported
FPGAUnknown = Unknown
FPGAHdlRequired = Required for HDL
#
# file/FileWriter.java
#
fileCreateHDLFile = Creating HDL file: %s
fileHDLFileExists = HDL file already exists: %s
fileCreateScriptFile = Creating script file: %s
fileScriptsFileExists = Script file already exists: %s
fileUnableToCreate = Unable to create file: %s
fileUnableToWrite = Could not write to file: %s
#
# data/LedArrayDriving.java
#
LedDefault = LED array single pin drive
LedRowScanning = LED array row scanning
LedColumnScanning = LED array column scanning
RgbDefault = RGB array single pin drive
RgbRowScanning = RGB array row scanning
RgbColScanning = RGB array column scanning
#
# data/SevenSegmentScanningDriving.java
#
SevenSegDecoded = 7-segment array with external decoder
SevenSegScanningActiveLow = 7-segment array with active low segment select
SevenSegScanningActiveHi = 7-segment array with active high segment select
#
# data/ComponentMapParser.java
#
BoardMapErrorCD = BUG: Error while creating a DOM document.
BoardMapErrorPF = Error encountered while parsing the loaded file!
BoardMapUnknown = No errors or unknown error encountered.
BoardMapWrongBoard = The loaded file is not a map file for the current selected board.
BoardMapWrongCircuit = The loaded file is not a map file for the current toplevel.
#
# data/ConstantButton.java
#
FpgaMapSpecConst = Specify constant value:
FpgaMapSpecErr = The constant should be specified decimal or hexadecimal (prefixed by 0x)!
#
# data/IOComponentTypes.java
#
FpgaIoPin = Pin
FpgaIoPins = Pin %d
DipSwitchZero = Switch 1 left
DipSwitchCW90 = Switch 1 top
DipSwitchCCW90 = Switch 1 bottom
SevenSegmentZero = Segment a top
SevenSegmentCW90 = Segment a right
SevenSegmentCCW90 = Segment a left
LEDArrayZero = row0 col0 left bottom
LEDArrayCW90 = row0 col0 left top
LEDArrayCCW90 = row0 col0 right bottom
#
# data/MapComponent.java
#
MapOpen = Not connected
#
# designrulecheck/CorrectLabel.java
#
IllegalChar = contains the illegal character “%c”, please rename.
ReservedVerilogKeyword = is a reserved Verilog keyword, please rename.
ReservedVHDLKeyword = is a reserved VHDL keyword, please rename.
VerilogKeywordNameError = The specified label equals a Verilog keyword. Please specify another name.
VHDLKeywordNameError = The specified label equals a VHDL keyword. Please specify another name.
#
# designrulecheck/Netlist.java
#
BuildingNetlistFor = Building netlist for sheet “%s”
CircuitInfoString = Circuit “%s” has %d nets and %d buses.
DRCPassesString = Circuit “%s” passed DRC check.
EmptyNamedSheet = Found a sheet in your design with an empty name. This is not allowed, please specify a name!
FoundBadComponent = Found that the component “%s” in circuit “%s”
HDL_CompNameIsLabel = Found one or more components which have a label equal to the circuit name. This is not supported.
HDL_DuplicatedLabels = Found one or more duplicated labels. Please make label names unique.
HDL_LabelInvalid = Found an invalid label.
HDL_noLabel = Found one or more components without a label. Please label them or use the annotate function.
HDL_Tristate = Found a tri-state driver or floating output(s) for one or more components. This is not supported.
HDL_unsupported = Found one or more components in your circuit that are not supported for HDL generation.
MultipleSheetSameName = Found more than one sheet in your design with the name: “%s”. This is not allowed, please make sure that all sheets have a unique name!
NetAdd_ComponentWidthMismatch = Found two components connected together with different bit widths.
NetList_BitwidthError = Found a bit width connection problem.
NetList_CircuitGated = ----> Gated instance
NetList_CircuitGatedNotGated = Found a circuit that is used with gated and non-gated clock components (see trace list below). This is only for the simplest cases supported!
NetList_CircuitNotGated = ----> Non-gated instance
NetList_duplicatedSplitter = Found identical splitters on same location.
NetList_emptynets = Found unconnected net!
NetList_GatedClock = Found a gated clock. Be careful, the real hardware may not work correctly!
NetList_GatedClockInt = ----> Intermediate gated clock line
NetList_GatedClockSink = ----> Sink(s) of the gated clock line
NetList_GatedClockSource = ----> Source of the gated clock line
NetList_IOError = Found one or more components with I/O pins, this is not supported.
NetList_NoClockConnection = Found a component with an unconnected clock input!
NetList_NoEndSplitterConnections = Found a splitter with one or more pins that are connected to a net, but not to the root bus.
NetList_NoSplitterConnection = Found a splitter that does not transport signals from bus to fan out.
NetList_NoSplitterEndConnections = Found a splitter with one or more unconnected fan-out pins.
NetList_PossibleGatedClock = Found possible gated clock at top level! Be careful, the real hardware may not work correctly!
NetList_ShortCircuit = Found a net with multiple drivers (short circuit).
NetList_SourceWithoutSink = Found a source without (a) sink(s)!
NetList_TraceListBegin = ===> Start of trace list
NetList_TraceListEnd = ===> End of trace list
NetList_UnconnectedInput = Found an unconnected input (bit(s))!
NetList_UnconnectedInputs = Found a component with unconnected inputs!
NetList_UnconnectedOutput = Found an unconnected output (bit(s))!
NetList_UnsourcedSink = Found an sink without a source!
NetListBuild = Building netlist for circuit “%s” (%d/7)
NetMerge_BitWidthError = Trying to merge nets of different size.
TopLevelNoIO = Top level “%s” has no input(s) and/or no output(s)!
#
# download/AlteraDownload.java
#
AlteraCofFile = Generating COF file for flashing
AlteraDetectDevice = Detected connected boards
AlteraErrorCof = Error generating COF file.
AlteraFlash = Flashing bit file
AlteraFlashError = An error occurred during flashing operation.
AlteraFlashFailure = Error flashing bit file.
AlteraJicFile = Generating JIC file for flashing
AlteraJicFileError = Error creating JIC file.
AlteraNoCof = Error, no cof file found.
AlteraNoSofFile = Altera bit file not present, cannot generate JIC file
AlteraOptimize = Optimizing Altera project
AlteraProgSof = Loading flash programmer on device.
AlteraProgSofError = File “%s” not found.
AlteraProgSofFailure = Error loading flash programmer on device.
AlteraProject = Creating Altera project files
AlteraSyntPRBit = Altera synthesizing, P&R, and generating bit file; this may take a while
#
# download/Download.java
#
FPGABoardNotConnected = No connected FPGA board found.
FPGABoardSelection = Select board to be programmed
FPGACancelWait = Canceling… please wait
FPGADownloadAborted = Download aborted.
FPGADownloadBitfile = Downloading design to the board.
FPGADownloadCancel = No, abort
FpgaDownloadInfo = Generating FPGA files and performing download; this may take a while
FPGADownloadOk = Yes, download
FPGAExecutionFailure = Error found in stage “%s”
FpgaGuiCanceling = Cancelling!
FPGAInterrupted = Interrupted by user.
FPGAInterruptedError = %s download interrupted!
FPGAIOError = Internal IO exception in %s download
FPGAMapNotComplete = Not all IO components have been mapped to the board “%s”; please map all components to continue!
FPGAMultipleBoards = I found %d attached boards. Select which one to be programmed…
FPGANameContainsSpaces = The file “%s” contains a space.\nSpaces are not permitted by the HDL synthesis engine.\nPlease rename your file and directory to not have any spaces.
FPGAState0 = Performing Design Rule Check (DRC)
FPGAState1 = Generate Hardware Description Language (HDL) Files
FPGAState2 = Check I/O resources on board
FPGAState3 = Map I/O resources onto board
FPGAState4 = Creating Download Scripts
FPGAStaticExecutionFailure = Error in execution.
FPGAVerifyMsg1 = Verify that your board is connected and you are ready to download.
FPGAVerifyMsg2 = Ready to download?
#
# download/DownloadBase.java
#
FpgaIncompleteMap = Design is not completely mapped!
FpgaNotCompleteMap = Not all components have been mapped.\nAll not mapped inputs will be connected to 0.\nAll not mapped outputs and IOs will be left unconnected.\nContinue?
#
# download/VivadoDownload.java
#
VivadoBitstream = Generate bit stream
VivadoProject = Creating Vivado project
#
# download/XilinxDownload.java
#
XilinxBit = Generating Bit file
XilinxContraints = Adding constraints
XilinxFlashMissing = Unable to find the flash on board “%s”
XilinxMap = Mapping Design
XilinxOpenFailure = Could not access file “%s”
XilinxPAR = Place and routing Design
XilinxSynth = Synthesizing Project
XilinxUsbTmc = Could not find USBTMC device
XilinxUsbTmcError = Failed to download by USBTMC
#
# download/OpenFpgaDownload.java
#
OpenFpgaGhdl = VHDL conversion
OpenFpgaYosys = Yosys synthesis
OpenFpganNextpnr = Nextpnr place & route
OpenFpganEcppack = Trellis bit file generation
#
# file/PNGFileFilter.java
#
FpgaFilePng = PNG files (*.png)
#
# file/XMLFileFilter.java
#
BoardMapXml = XML File Filter
#
# gui/BoardEditor.java
#
FpgaBoardCancel = Cancel
FPGABoardEditor = FPGA Board Editor
FpgaBoardFpgaParam = Configure FPGA
FpgaBoardLoadExternal = Load board
FpgaBoardLoadFile = Choose XML board description file to load
FpgaBoardLoadInternal = Built-in board
FpgaBoardName = Board Name:
FpgaBoardSave = Save board
FpgaBoardSaveDir = Select directory to save the board file:
FpgaBoardSelect = Select build-in board to load:
#
# gui/BoardManipulator.java
#
BoardManipLoad = Load board picture
BoardManipLoadError = Error loading picture file “%s”
BoardManipLoadPng = Choose FPGA board picture to use
BoardMapRelAll = Release all components
BoardMapRelease = Release component
FpgaBoardOverlap = Found Overlapping regions! Cannot process!
#
# gui/BoardPainter.java
#
BoardMapConstant = Constant %s
BoardMapOpen = Unconnected
BoardMapValue = value
BoardPainterError = INTERNAL ERROR!
BoardPainterMsg1 = Click here to add a board picture.
BoardPainterMsg2 = The board picture should have at least a resolution of
BoardPainterMsg3 = %d x %d pixels (width x height)
BoardPainterMsg4 = for best graphical display.
BoardPainterMsg5 = The board picture format must be PNG
BoardPainterMsg6 = Current resolution: %d x %d
#
# gui/ComponentMapDialog.java
#
BoardMapActions = Actions:
BoardMapLoad = Load Map
BoardMapMapped = Mapped Components:
BoardMapSave = Save Map
BoardMapTitle = Component to FPGA board mapping
BoardMapUMTooltip = <html>Select a component and place it on the board.<br>To expand a component (Port, DIP, …) or change type (Button<->Pin),<br>double-click on it.</html>
BoardMapUnmapped = Unmapped Components:
BoarMapFileSaved = Saved changes to the map file.
#
# gui/DialogNotification.java
#
FpgaBoardClose = Close
#
# gui/FPGAClockPanel.java
#
FpgaFreqDivider = Divider value:
FpgaFreqFrequency = Frequency:
FpgaFreqTitle = Clock settings
FpgaFreqPreDivider = Pre-divider:
FpgaFreqPreMultiplier = Pre-multiplier:
#
# gui/FPGACommander.java
#
FpgaGuiAnnotate = Annotate
FpgaGuiAnnotationDone = Annotation done
FpgaGuiAnnotationMethod = Annotation method
FpgaGuiBoardSelect = Target board
FpgaGuiDownload = Download only
FpgaGuiExecute = Execute
FpgaGuiExecution = Action method
FpgaGuiHdlOnly = Generate HDL only
FpgaGuiIdle = Idle
FpgaGuiMainCircuit = Toplevel:
FpgaGuiProgress = Progress bar
FpgaGuiRelabelAll = Relabel all components
FpgaGuiRelabelEmpty = Label only the components without a label
FpgaGuiSettings = Settings
FpgaGuiSoftwareSelect = Design Suite selection
FpgaGuiSyntAndD = Synthesize & Download
FpgaGuiTitle = Synthesize & Download:
FpgaGuiToolpath = Select %s’s software
FpgaGuiWriteFlash = Write to flash
FpgaToolsNotFound = Required tools not found in Directory “%s” !
#
# gui/FPGAIOInformationSettingsDialog.java
#
FpgaRotationDefinition = Map component rotation option:
FpgaBoardClkFreq = Clock frequency:
FpgaBoardClkLoc = Clock pin location:
FpgaBoardClkPin = You have to specify the clock-pin location!
FpgaBoardClkProp = Clock related settings
FpgaBoardClkPul = Clock pin pull behavior:
FpgaBoardClkReq = You have to specify the clock frequency!
FpgaBoardClkStd = Clock pin standard:
FpgaBoardFlashLoc = Flash location:
FpgaBoardFlashType = Flash type:
FpgaBoardFpgaFam = FPGA/CPLD family:
FpgaBoardFpgaFamMis = You have to specify the FPGA family!
FpgaBoardFpgaPack = FPGA/CPLD package:
FpgaBoardFpgaPacMis = You have to specify the FPGA package!
FpgaBoardFpgaPart = FPGA/CPLD part:
FpgaBoardFpgaPartMis = You have to specify the FPGA part!
FpgaBoardFpgaProp = FPGA/CPLD related settings
FpgaBoardFpgaSG = FPGA/CPLD speed grade:
FpgaBoardFpgaSpeedMis = You have to specify the FPGA speed-grade!
FpgaBoardFpgaVend = FPGA/CPLD vendor:
FpgaBoardFracError = The clock frequency cannot be a fraction of a Hz
FpgaBoardFreqError = The clock frequency should only contain the chars ‘0’…‘9’ and ‘.’!
FpgaBoardJtagLoc = FPGA/CPLD location:
FpgaBoardJtagProp = JTAG chain related settings
FpgaBoardMiscProp = Misc. settings
FpgaBoardPinUnused = Unused FPGA pin behavior:
FpgaBoardUSBTMC = Download through USBTMC
FpgaIoActivity = %s activity:
FpgaIoDelete = Delete component
FpgaIoHeight = Height:
FpgaIoInpPins = Input pin(s) definition:
FpgaArrayDefinition = LED/RGB array definition:
FpgaScanningDefinition = Seven segment array definition:
FpgaScanningDriving = Driving mode:
FpgaNrOfSegments = Nr. of segments:
FpgaNrOfDecodeBits = Nr. of address bits:
FpgaArrayDriving = Driving mode:
FpgaArrayRows = Nr. of rows:
FpgaArrayCols = Nr. of columns:
FpgaIoIntError = Integer format error for %s %s
FpgaIoIOPins = IO pins(s) definition:
FpgaIoLabel = Optional label:
FpgaIoLocation = %s location:
FpgaIoOutpPins = Output pin(s) definition:
FpgaIoPinLoc = You have to specify a location for %s!
FpgaIoProperties = properties
FpgaIoPull = Pull behavior:
FpgaIoRecProp = Rectangle
FpgaIoRectError = Newly specified rectangle overlaps with another rectangle!
FpgaIoRectHNLE = Height of rectangle is too small!
FpgaIoRectTHeigt = Newly specified rectangle is too height!
FpgaIoRectTWide = Newly specified rectangle is too wide!
FpgaIoRectWNLE = Width of rectangle is too small!
FpgaIoStandard = I/O standard:
FpgaIoStrength = Drive strength:
FpgaIoWidth = Width:
FpgaIoXpos = X position:
FpgaIoYpos = Y position:
#
# gui/IOComponentSelector.java
#
FpgaBoardDefine = Define a %s
FpgaBoardIOResources = Select an I/O resource:
#
# gui/ListModelCellRenderer.java
#
FATAL_MSG = ****** FATAL ******
SEVERE_MSG = ****** SEVERE ******
#
# gui/PartialMapDialog.java
#
FpgaBoardDone = Done
FpgaInputsMap = Input mapping
FpgaIOsMap = I/O mapping
FpgaMapTo = -> map to ->
FpgaNotMapped = Not mapped
FpgaOutputsMap = Output mapping
#
# menu/MenuFPGA.java
#
FPGACommander = Synthesize & Download…
FPGAMenu = FPGA
#
# prefs/FPGAOptions.java
#
Browse = Browse
EditColHighlight = Defined component highlight color:
EditColMove = Defined component move color:
EditColors = Board editor colors
EditColResize = Defined component resize color:
EditColSel = Defined component color:
FpgaGuiWorkspaceError = Workspace directory may not contain spaces!
FpgaGuiWorkspacePath = Workspace directory Selection
FPGAHelp = All settings related to the FPGA-commander
FPGATitle = FPGA Commander Settings
FPGAWorkSpace = Workspace location:
HDLLanguageUsed = Hardware description language used for FPGA-commander:
MapColor = Mapped component color:
MapColors = Board map colors:
ReporterOptions = DRC reporter options
SelectCol = Selectable component color:
SelectMapCol = Selectable mapped component color:
SelMapCol = Selected mapped component color:
SupressGatedClock = Supress gated clock warnings in the design rule check report.
SupressOpenInput = Supress open input warnings in the design rule check report.
Verilog = Verilog
VHDL = VHDL
VhdlKeywordUpperCase = Use upper case for VHDL keywords
VhdlOptions = VHDL options:
#
# prefs/SoftwaresOptions.java
#
ISEToolPath = Xilinx ISE toolpath:
QuartusToolPath = Altera/Intel Quartus Prime toolpath:
softwaresHelp = Set the paths of third party software
softwaresQuestaPathButton = Browse…
softwaresQuestaPathLabel = Questa Advanced Simulator path:
softwaresQuestaValidationLabel = Use Questa Advanced Simulator to validate HDL entities
softwaresTitle = Software
VivadoToolPath = Xilinx Vivado toolpath:
openfpgaToolPath = OpenFPGA ECP5 toolpath (experimental!):
