PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
PERI_PCLK_GR_Type Struct Reference

## Description

PERI clock domains (PERI_PCLK_GR)

## Data Fields
__IOM uint32_t | DIV_CMD
__IM uint32_t | RESERVED [767]
__IOM uint32_t | CLOCK_CTL [256]
__IOM uint32_t | DIV_8_CTL [256]
__IOM uint32_t | DIV_16_CTL [256]
__IOM uint32_t | DIV_16_5_CTL [256]
__IOM uint32_t | DIV_24_5_CTL [255]
__IM uint32_t | RESERVED1

## Field Documentation

## ◆ DIV_CMD

__IOM uint32_t PERI_PCLK_GR_Type::DIV_CMD

0x00000000 Divider command

## ◆ RESERVED

__IM uint32_t PERI_PCLK_GR_Type::RESERVED[767]

## ◆ CLOCK_CTL

__IOM uint32_t PERI_PCLK_GR_Type::CLOCK_CTL[256]

0x00000C00 Clock control

## ◆ DIV_8_CTL

__IOM uint32_t PERI_PCLK_GR_Type::DIV_8_CTL[256]

0x00001000 Divider control (for 8.0 divider)

## ◆ DIV_16_CTL

__IOM uint32_t PERI_PCLK_GR_Type::DIV_16_CTL[256]

0x00001400 Divider control (for 16.0 divider)

## ◆ DIV_16_5_CTL

__IOM uint32_t PERI_PCLK_GR_Type::DIV_16_5_CTL[256]

0x00001800 Divider control (for 16.5 divider)

## ◆ DIV_24_5_CTL

__IOM uint32_t PERI_PCLK_GR_Type::DIV_24_5_CTL[255]

0x00001C00 Divider control (for 24.5 divider)

## ◆ RESERVED1

__IM uint32_t PERI_PCLK_GR_Type::RESERVED1