PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
USBHS_DWC_OTG_INTREG_Type Struct Reference

## Description

Internal register map (USBHS_DWC_OTG_INTREG)

## Data Fields
__IOM uint32_t | GOTGCTL
__IOM uint32_t | GOTGINT
__IOM uint32_t | GAHBCFG
__IOM uint32_t | GUSBCFG
__IOM uint32_t | GRSTCTL
__IOM uint32_t | GINTSTS
__IOM uint32_t | GINTMSK
__IM uint32_t | GRXSTSR
__IM uint32_t | GRXSTSP
__IOM uint32_t | GRXFSIZ
__IOM uint32_t | GNPTXFSIZ
__IM uint32_t | GNPTXSTS
__IM uint32_t | RESERVED [2]
__IOM uint32_t | GGPIO
__IOM uint32_t | GUID
__IM uint32_t | GSNPSID
__IM uint32_t | GHWCFG1
__IM uint32_t | GHWCFG2
__IM uint32_t | GHWCFG3
__IM uint32_t | GHWCFG4
__IOM uint32_t | GLPMCFG
__IM uint32_t | RESERVED1
__IOM uint32_t | GDFIFOCFG
__IM uint32_t | RESERVED2 [2]
__IOM uint32_t | GINTMSK2
__IOM uint32_t | GINTSTS2
__IM uint32_t | RESERVED3 [36]
__IOM uint32_t | HPTXFSIZ
__IOM uint32_t | DIEPTXF1
__IOM uint32_t | DIEPTXF2
__IOM uint32_t | DIEPTXF3
__IOM uint32_t | DIEPTXF4
__IOM uint32_t | DIEPTXF5
__IOM uint32_t | DIEPTXF6
__IOM uint32_t | DIEPTXF7
__IOM uint32_t | DIEPTXF8
__IM uint32_t | RESERVED4 [183]
__IOM uint32_t | HCFG
__IOM uint32_t | HFIR
__IM uint32_t | HFNUM
__IM uint32_t | RESERVED5
__IM uint32_t | HPTXSTS
__IM uint32_t | HAINT
__IOM uint32_t | HAINTMSK
__IOM uint32_t | HFLBADDR
__IM uint32_t | RESERVED6 [8]
__IOM uint32_t | HPRT
__IM uint32_t | RESERVED7 [47]
__IOM uint32_t | HCCHAR0
__IOM uint32_t | HCSPLT0
__IOM uint32_t | HCINT0
__IOM uint32_t | HCINTMSK0
__IOM uint32_t | HCTSIZ0
__IOM uint32_t | HCDMA0
__IM uint32_t | RESERVED8
__IM uint32_t | HCDMAB0
__IOM uint32_t | HCCHAR1
__IOM uint32_t | HCSPLT1
__IOM uint32_t | HCINT1
__IOM uint32_t | HCINTMSK1
__IOM uint32_t | HCTSIZ1
__IOM uint32_t | HCDMA1
__IM uint32_t | RESERVED9
__IM uint32_t | HCDMAB1
__IOM uint32_t | HCCHAR2
__IOM uint32_t | HCSPLT2
__IOM uint32_t | HCINT2
__IOM uint32_t | HCINTMSK2
__IOM uint32_t | HCTSIZ2
__IOM uint32_t | HCDMA2
__IM uint32_t | RESERVED10
__IM uint32_t | HCDMAB2
__IOM uint32_t | HCCHAR3
__IOM uint32_t | HCSPLT3
__IOM uint32_t | HCINT3
__IOM uint32_t | HCINTMSK3
__IOM uint32_t | HCTSIZ3
__IOM uint32_t | HCDMA3
__IM uint32_t | RESERVED11
__IM uint32_t | HCDMAB3
__IOM uint32_t | HCCHAR4
__IOM uint32_t | HCSPLT4
__IOM uint32_t | HCINT4
__IOM uint32_t | HCINTMSK4
__IOM uint32_t | HCTSIZ4
__IOM uint32_t | HCDMA4
__IM uint32_t | RESERVED12
__IM uint32_t | HCDMAB4
__IOM uint32_t | HCCHAR5
__IOM uint32_t | HCSPLT5
__IOM uint32_t | HCINT5
__IOM uint32_t | HCINTMSK5
__IOM uint32_t | HCTSIZ5
__IOM uint32_t | HCDMA5
__IM uint32_t | RESERVED13
__IM uint32_t | HCDMAB5
__IOM uint32_t | HCCHAR6
__IOM uint32_t | HCSPLT6
__IOM uint32_t | HCINT6
__IOM uint32_t | HCINTMSK6
__IOM uint32_t | HCTSIZ6
__IOM uint32_t | HCDMA6
__IM uint32_t | RESERVED14
__IM uint32_t | HCDMAB6
__IOM uint32_t | HCCHAR7
__IOM uint32_t | HCSPLT7
__IOM uint32_t | HCINT7
__IOM uint32_t | HCINTMSK7
__IOM uint32_t | HCTSIZ7
__IOM uint32_t | HCDMA7
__IM uint32_t | RESERVED15
__IM uint32_t | HCDMAB7
__IOM uint32_t | HCCHAR8
__IOM uint32_t | HCSPLT8
__IOM uint32_t | HCINT8
__IOM uint32_t | HCINTMSK8
__IOM uint32_t | HCTSIZ8
__IOM uint32_t | HCDMA8
__IM uint32_t | RESERVED16
__IM uint32_t | HCDMAB8
__IOM uint32_t | HCCHAR9
__IOM uint32_t | HCSPLT9
__IOM uint32_t | HCINT9
__IOM uint32_t | HCINTMSK9
__IOM uint32_t | HCTSIZ9
__IOM uint32_t | HCDMA9
__IM uint32_t | RESERVED17
__IM uint32_t | HCDMAB9
__IOM uint32_t | HCCHAR10
__IOM uint32_t | HCSPLT10
__IOM uint32_t | HCINT10
__IOM uint32_t | HCINTMSK10
__IOM uint32_t | HCTSIZ10
__IOM uint32_t | HCDMA10
__IM uint32_t | RESERVED18
__IM uint32_t | HCDMAB10
__IOM uint32_t | HCCHAR11
__IOM uint32_t | HCSPLT11
__IOM uint32_t | HCINT11
__IOM uint32_t | HCINTMSK11
__IOM uint32_t | HCTSIZ11
__IOM uint32_t | HCDMA11
__IM uint32_t | RESERVED19
__IM uint32_t | HCDMAB11
__IOM uint32_t | HCCHAR12
__IOM uint32_t | HCSPLT12
__IOM uint32_t | HCINT12
__IOM uint32_t | HCINTMSK12
__IOM uint32_t | HCTSIZ12
__IOM uint32_t | HCDMA12
__IM uint32_t | RESERVED20
__IM uint32_t | HCDMAB12
__IOM uint32_t | HCCHAR13
__IOM uint32_t | HCSPLT13
__IOM uint32_t | HCINT13
__IOM uint32_t | HCINTMSK13
__IOM uint32_t | HCTSIZ13
__IOM uint32_t | HCDMA13
__IM uint32_t | RESERVED21
__IM uint32_t | HCDMAB13
__IOM uint32_t | HCCHAR14
__IOM uint32_t | HCSPLT14
__IOM uint32_t | HCINT14
__IOM uint32_t | HCINTMSK14
__IOM uint32_t | HCTSIZ14
__IOM uint32_t | HCDMA14
__IM uint32_t | RESERVED22
__IM uint32_t | HCDMAB14
__IOM uint32_t | HCCHAR15
__IOM uint32_t | HCSPLT15
__IOM uint32_t | HCINT15
__IOM uint32_t | HCINTMSK15
__IOM uint32_t | HCTSIZ15
__IOM uint32_t | HCDMA15
__IM uint32_t | RESERVED23
__IM uint32_t | HCDMAB15
__IM uint32_t | RESERVED24 [64]
__IOM uint32_t | DCFG
__IOM uint32_t | DCTL
__IM uint32_t | DSTS
__IM uint32_t | RESERVED25
__IOM uint32_t | DIEPMSK
__IOM uint32_t | DOEPMSK
__IM uint32_t | DAINT
__IOM uint32_t | DAINTMSK
__IM uint32_t | RESERVED26 [2]
__IOM uint32_t | DVBUSDIS
__IOM uint32_t | DVBUSPULSE
__IOM uint32_t | DTHRCTL
__IOM uint32_t | DIEPEMPMSK
__IM uint32_t | RESERVED27 [50]
__IOM uint32_t | DIEPCTL0
__IM uint32_t | RESERVED28
__IOM uint32_t | DIEPINT0
__IM uint32_t | RESERVED29
__IOM uint32_t | DIEPTSIZ0
__IOM uint32_t | DIEPDMA0
__IM uint32_t | DTXFSTS0
__IM uint32_t | DIEPDMAB0
__IOM uint32_t | DIEPCTL1
__IM uint32_t | RESERVED30
__IOM uint32_t | DIEPINT1
__IM uint32_t | RESERVED31
__IOM uint32_t | DIEPTSIZ1
__IOM uint32_t | DIEPDMA1
__IM uint32_t | DTXFSTS1
__IM uint32_t | DIEPDMAB1
__IOM uint32_t | DIEPCTL2
__IM uint32_t | RESERVED32
__IOM uint32_t | DIEPINT2
__IM uint32_t | RESERVED33
__IOM uint32_t | DIEPTSIZ2
__IOM uint32_t | DIEPDMA2
__IM uint32_t | DTXFSTS2
__IM uint32_t | DIEPDMAB2
__IOM uint32_t | DIEPCTL3
__IM uint32_t | RESERVED34
__IOM uint32_t | DIEPINT3
__IM uint32_t | RESERVED35
__IOM uint32_t | DIEPTSIZ3
__IOM uint32_t | DIEPDMA3
__IM uint32_t | DTXFSTS3
__IM uint32_t | DIEPDMAB3
__IOM uint32_t | DIEPCTL4
__IM uint32_t | RESERVED36
__IOM uint32_t | DIEPINT4
__IM uint32_t | RESERVED37
__IOM uint32_t | DIEPTSIZ4
__IOM uint32_t | DIEPDMA4
__IM uint32_t | DTXFSTS4
__IM uint32_t | DIEPDMAB4
__IOM uint32_t | DIEPCTL5
__IM uint32_t | RESERVED38
__IOM uint32_t | DIEPINT5
__IM uint32_t | RESERVED39
__IOM uint32_t | DIEPTSIZ5
__IOM uint32_t | DIEPDMA5
__IM uint32_t | DTXFSTS5
__IM uint32_t | DIEPDMAB5
__IOM uint32_t | DIEPCTL6
__IM uint32_t | RESERVED40
__IOM uint32_t | DIEPINT6
__IM uint32_t | RESERVED41
__IOM uint32_t | DIEPTSIZ6
__IOM uint32_t | DIEPDMA6
__IM uint32_t | DTXFSTS6
__IM uint32_t | DIEPDMAB6
__IOM uint32_t | DIEPCTL7
__IM uint32_t | RESERVED42
__IOM uint32_t | DIEPINT7
__IM uint32_t | RESERVED43
__IOM uint32_t | DIEPTSIZ7
__IOM uint32_t | DIEPDMA7
__IM uint32_t | DTXFSTS7
__IM uint32_t | DIEPDMAB7
__IOM uint32_t | DIEPCTL8
__IM uint32_t | RESERVED44
__IOM uint32_t | DIEPINT8
__IM uint32_t | RESERVED45
__IOM uint32_t | DIEPTSIZ8
__IOM uint32_t | DIEPDMA8
__IM uint32_t | DTXFSTS8
__IM uint32_t | DIEPDMAB8
__IM uint32_t | RESERVED46 [56]
__IOM uint32_t | DOEPCTL0
__IM uint32_t | RESERVED47
__IOM uint32_t | DOEPINT0
__IM uint32_t | RESERVED48
__IOM uint32_t | DOEPTSIZ0
__IOM uint32_t | DOEPDMA0
__IM uint32_t | RESERVED49
__IM uint32_t | DOEPDMAB0
__IOM uint32_t | DOEPCTL1
__IM uint32_t | RESERVED50
__IOM uint32_t | DOEPINT1
__IM uint32_t | RESERVED51
__IOM uint32_t | DOEPTSIZ1
__IOM uint32_t | DOEPDMA1
__IM uint32_t | RESERVED52
__IM uint32_t | DOEPDMAB1
__IOM uint32_t | DOEPCTL2
__IM uint32_t | RESERVED53
__IOM uint32_t | DOEPINT2
__IM uint32_t | RESERVED54
__IOM uint32_t | DOEPTSIZ2
__IOM uint32_t | DOEPDMA2
__IM uint32_t | RESERVED55
__IM uint32_t | DOEPDMAB2
__IOM uint32_t | DOEPCTL3
__IM uint32_t | RESERVED56
__IOM uint32_t | DOEPINT3
__IM uint32_t | RESERVED57
__IOM uint32_t | DOEPTSIZ3
__IOM uint32_t | DOEPDMA3
__IM uint32_t | RESERVED58
__IM uint32_t | DOEPDMAB3
__IOM uint32_t | DOEPCTL4
__IM uint32_t | RESERVED59
__IOM uint32_t | DOEPINT4
__IM uint32_t | RESERVED60
__IOM uint32_t | DOEPTSIZ4
__IOM uint32_t | DOEPDMA4
__IM uint32_t | RESERVED61
__IM uint32_t | DOEPDMAB4
__IOM uint32_t | DOEPCTL5
__IM uint32_t | RESERVED62
__IOM uint32_t | DOEPINT5
__IM uint32_t | RESERVED63
__IOM uint32_t | DOEPTSIZ5
__IOM uint32_t | DOEPDMA5
__IM uint32_t | RESERVED64
__IM uint32_t | DOEPDMAB5
__IOM uint32_t | DOEPCTL6
__IM uint32_t | RESERVED65
__IOM uint32_t | DOEPINT6
__IM uint32_t | RESERVED66
__IOM uint32_t | DOEPTSIZ6
__IOM uint32_t | DOEPDMA6
__IM uint32_t | RESERVED67
__IM uint32_t | DOEPDMAB6
__IOM uint32_t | DOEPCTL7
__IM uint32_t | RESERVED68
__IOM uint32_t | DOEPINT7
__IM uint32_t | RESERVED69
__IOM uint32_t | DOEPTSIZ7
__IOM uint32_t | DOEPDMA7
__IM uint32_t | RESERVED70
__IM uint32_t | DOEPDMAB7
__IOM uint32_t | DOEPCTL8
__IM uint32_t | RESERVED71
__IOM uint32_t | DOEPINT8
__IM uint32_t | RESERVED72
__IOM uint32_t | DOEPTSIZ8
__IOM uint32_t | DOEPDMA8
__IM uint32_t | RESERVED73
__IM uint32_t | DOEPDMAB8
__IM uint32_t | RESERVED74 [120]
__IOM uint32_t | PCGCCTL
__IOM uint32_t | PCGCCTL1
__IM uint32_t | RESERVED75 [62]

## Field Documentation

## ◆ GOTGCTL

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GOTGCTL

0x00000000 The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the controller.

## ◆ GOTGINT

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GOTGINT

0x00000004 The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.

## ◆ GAHBCFG

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GAHBCFG

0x00000008 This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.

## ◆ GUSBCFG

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GUSBCFG

0x0000000C This register can be used to configure the core after power-on or when changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. If you are using the HSIC interface, HSIC PHY must be in reset while programming this register. Do not make changes to this register after the initial programming.

## ◆ GRSTCTL

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GRSTCTL

0x00000010 The application uses this register to reset various hardware features inside the controller.

## ◆ GINTSTS

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GINTSTS

0x00000014 This register interrupts the application for system-level events in the current mode (Device mode or Host mode). Some of the bits in this register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 to the bit. The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. Note: Read the reset value of GINTSTS.CurMod only after the following conditions: - If IDDIG_FILTER is disabled, read only after PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the filter timer expires.

## ◆ GINTMSK

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GINTMSK

0x00000018 This register works with the Interrupt Register (GINTSTS) to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the GINTSTS register bit corresponding to that interrupt is still set. Note: The fields of this register change depending on host or device mode.

## ◆ GRXSTSR

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GRXSTSR

0x0000001C A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status read when the receive FIFO is empty and returns a value of 32'h0000_0000. Note: - Use of these fields vary based on whether the core is functioning as a host or a device. - Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation.

## ◆ GRXSTSP

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GRXSTSP

0x00000020 A read to the Receive Status Read and Pop register returns the contents of the top of the Receive FIFO and additionally pops the top data entry out of the RxFIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 32'h0000_0000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. Note: - Use of these fields vary based on whether the core is functioning as a host or a device.

- Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation.

## ◆ GRXFSIZ

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GRXFSIZ

0x00000024 The application can program the RAM size that must be allocated to the RxFIFO.

## ◆ GNPTXFSIZ

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GNPTXFSIZ

0x00000028 The application can program the RAM size and the memory start address for the Non-periodic TxFIFO Note: The fields of this register change depending on host or device mode.

## ◆ GNPTXSTS

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GNPTXSTS

0x0000002C In Device mode, this register is valid only in Shared FIFO operation. This read-only register contains the free space information for the Non-periodic TxFIFO and the Non-periodic Transmit Request Queue.

## ◆ RESERVED

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED[2]

## ◆ GGPIO

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GGPIO

0x00000038 The application can use this register for general purpose input/output ports or for debugging.

## ◆ GUID

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GUID

0x0000003C This is a read/write register containing the User ID. It is implemented only if Remove Optional Features? was deselected during coreConsultant configuration (parameter OTG_RM_OPT_FEATURES = 0). The power-on value for this register is specified as the Power-on Value of User ID Register User Identification Register during coreConsultant configuration (parameter OTG_USERID). This register can be used in the following ways: - To store the version or revision of your system - To store hardware configurations that are outside the DWC_otg core - As a scratch register

## ◆ GSNPSID

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GSNPSID

0x00000040 This read-only register contains the release number of the core being used.

## ◆ GHWCFG1

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GHWCFG1

0x00000044 This register contains the logical endpoint direction(s) selected using coreConsultant.

## ◆ GHWCFG2

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GHWCFG2

0x00000048 This register contains configuration options selected using coreConsultant.

## ◆ GHWCFG3

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GHWCFG3

0x0000004C This register contains configuration options selected using coreConsultant.

## ◆ GHWCFG4

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::GHWCFG4

0x00000050 This register contains configuration options selected using coreConsultant. Note: Bit [31] is available only when Scatter/Gather DMA mode is enabled. When Scatter/Gather DMA mode is disabled, this field is reserved.

## ◆ GLPMCFG

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GLPMCFG

0x00000054 Register to control the LPM functionality of the controller.

## ◆ RESERVED1

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED1

## ◆ GDFIFOCFG

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GDFIFOCFG

0x0000005C Register to configure the DFIFOs for the controller.

## ◆ RESERVED2

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED2[2]

## ◆ GINTMSK2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GINTMSK2

0x00000068 This register works with the Interrupt Register (GINTSTS2) to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the GINTSTS2 register bit corresponding to that interrupt is still set. Note: The fields of this register change depending on host or device mode.

## ◆ GINTSTS2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::GINTSTS2

0x0000006C This register interrupts the application for system-level events in the current mode (Device mode or Host mode). Some of the bits in this register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 to the bit. The application must clear the GINTSTS2 register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.

## ◆ RESERVED3

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED3[36]

## ◆ HPTXFSIZ

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HPTXFSIZ

0x00000100 This register holds the size and the memory start address of the Periodic TxFIFO. Note: Read the reset value of this register only after the following conditions: - If IDDIG_FILTER is disabled, read only after PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the filter timer expires.

## ◆ DIEPTXF1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF1

0x00000104 This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ DIEPTXF2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF2

0x00000108 This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ DIEPTXF3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF3

0x0000010C This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ DIEPTXF4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF4

0x00000110 This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ DIEPTXF5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF5

0x00000114 This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ DIEPTXF6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF6

0x00000118 This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ DIEPTXF7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF7

0x0000011C This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ DIEPTXF8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTXF8

0x00000120 This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.

## ◆ RESERVED4

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED4[183]

## ◆ HCFG

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCFG

0x00000400 This register is used to configure the controller in Host mode.

## ◆ HFIR

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HFIR

0x00000404 This register is used to control the interval between two consecutive SOFs.

## ◆ HFNUM

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HFNUM

0x00000408 This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current (micro)frame. Note: Read the reset value of this register only after the following conditions: - If IDDIG_FILTER is disabled, read only when the PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the filter timer expires.

## ◆ RESERVED5

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED5

## ◆ HPTXSTS

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HPTXSTS

0x00000410 This register contains information about the Periodic Transmit Queue in the Host controller.

## ◆ HAINT

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HAINT

0x00000414 When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). This is shown in the 'Interrupt Hierarchy' figure in the databook. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Host Channel-n Interrupt register.

## ◆ HAINTMSK

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HAINTMSK

0x00000418 The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.

## ◆ HFLBADDR

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HFLBADDR

0x0000041C This register is present only in case of Scatter/Gather DMA. It is implemented as flops. This register holds the starting address of the Frame list information.

## ◆ RESERVED6

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED6[8]

## ◆ HPRT

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HPRT

0x00000440 This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in the 'Interrupt Hierarchy' figure in the databook. The R_SS_WC bits in this register can trigger an interrupt to the application through the Host Port Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit to clear the interrupt.

## ◆ RESERVED7

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED7[47]

## ◆ HCCHAR0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR0

0x00000500 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT0

0x00000504 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT0

0x00000508 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK0

0x0000050C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ0

0x00000510 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA0

0x00000514 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED8

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED8

## ◆ HCDMAB0

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB0

0x0000051C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR1

0x00000520 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT1

0x00000524 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT1

0x00000528 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK1

0x0000052C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ1

0x00000530 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA1

0x00000534 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED9

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED9

## ◆ HCDMAB1

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB1

0x0000053C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR2

0x00000540 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT2

0x00000544 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT2

0x00000548 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK2

0x0000054C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ2

0x00000550 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA2

0x00000554 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED10

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED10

## ◆ HCDMAB2

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB2

0x0000055C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR3

0x00000560 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT3

0x00000564 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT3

0x00000568 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK3

0x0000056C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ3

0x00000570 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA3

0x00000574 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED11

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED11

## ◆ HCDMAB3

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB3

0x0000057C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR4

0x00000580 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT4

0x00000584 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT4

0x00000588 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK4

0x0000058C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ4

0x00000590 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA4

0x00000594 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED12

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED12

## ◆ HCDMAB4

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB4

0x0000059C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR5

0x000005A0 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT5

0x000005A4 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT5

0x000005A8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK5

0x000005AC This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ5

0x000005B0 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA5

0x000005B4 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED13

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED13

## ◆ HCDMAB5

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB5

0x000005BC This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR6

0x000005C0 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT6

0x000005C4 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT6

0x000005C8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK6

0x000005CC This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ6

0x000005D0 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA6

0x000005D4 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED14

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED14

## ◆ HCDMAB6

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB6

0x000005DC This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR7

0x000005E0 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT7

0x000005E4 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT7

0x000005E8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK7

0x000005EC This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ7

0x000005F0 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA7

0x000005F4 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED15

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED15

## ◆ HCDMAB7

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB7

0x000005FC This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR8

0x00000600 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT8

0x00000604 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT8

0x00000608 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK8

0x0000060C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ8

0x00000610 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA8

0x00000614 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED16

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED16

## ◆ HCDMAB8

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB8

0x0000061C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR9

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR9

0x00000620 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT9

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT9

0x00000624 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT9

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT9

0x00000628 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK9

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK9

0x0000062C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ9

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ9

0x00000630 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA9

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA9

0x00000634 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED17

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED17

## ◆ HCDMAB9

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB9

0x0000063C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR10

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR10

0x00000640 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT10

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT10

0x00000644 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT10

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT10

0x00000648 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK10

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK10

0x0000064C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ10

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ10

0x00000650 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA10

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA10

0x00000654 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED18

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED18

## ◆ HCDMAB10

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB10

0x0000065C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR11

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR11

0x00000660 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT11

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT11

0x00000664 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT11

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT11

0x00000668 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK11

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK11

0x0000066C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ11

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ11

0x00000670 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA11

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA11

0x00000674 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED19

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED19

## ◆ HCDMAB11

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB11

0x0000067C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR12

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR12

0x00000680 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT12

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT12

0x00000684 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT12

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT12

0x00000688 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK12

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK12

0x0000068C This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ12

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ12

0x00000690 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA12

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA12

0x00000694 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED20

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED20

## ◆ HCDMAB12

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB12

0x0000069C This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR13

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR13

0x000006A0 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT13

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT13

0x000006A4 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT13

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT13

0x000006A8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK13

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK13

0x000006AC This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ13

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ13

0x000006B0 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA13

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA13

0x000006B4 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED21

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED21

## ◆ HCDMAB13

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB13

0x000006BC This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR14

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR14

0x000006C0 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT14

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT14

0x000006C4 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT14

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT14

0x000006C8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK14

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK14

0x000006CC This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ14

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ14

0x000006D0 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA14

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA14

0x000006D4 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED22

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED22

## ◆ HCDMAB14

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB14

0x000006DC This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ HCCHAR15

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCCHAR15

0x000006E0 This register contains the characteristics of the Host Channel.

## ◆ HCSPLT15

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCSPLT15

0x000006E4 This register contains the Split characteristics of the Host Channel.

## ◆ HCINT15

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINT15

0x000006E8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

## ◆ HCINTMSK15

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCINTMSK15

0x000006EC This register reflects the mask for each channel status described in the previous section.

## ◆ HCTSIZ15

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCTSIZ15

0x000006F0 This register reflects the transfer size for the Host Channel.

## ◆ HCDMA15

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMA15

0x000006F4 This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

## ◆ RESERVED23

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED23

## ◆ HCDMAB15

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::HCDMAB15

0x000006FC This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.

## ◆ RESERVED24

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED24[64]

## ◆ DCFG

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DCFG

0x00000800 This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.

## ◆ DCTL

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DCTL

0x00000804 This register is used to control the characteristics of the Device controller.

## ◆ DSTS

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DSTS

0x00000808 This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (DAINT) register.

## ◆ RESERVED25

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED25

## ◆ DIEPMSK

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPMSK

0x00000810 This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.

## ◆ DOEPMSK

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPMSK

0x00000814 This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTn register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

## ◆ DAINT

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DAINT

0x00000818 When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). This is shown in Figure 5-2. There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).

## ◆ DAINTMSK

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DAINTMSK

0x0000081C The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still set.

## ◆ RESERVED26

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED26[2]

## ◆ DVBUSDIS

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DVBUSDIS

0x00000828 This register specifies the VBUS discharge time after VBUS pulsing during SRP.

## ◆ DVBUSPULSE

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DVBUSPULSE

0x0000082C This register contains the VBUS pulsing time during SRP.

## ◆ DTHRCTL

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DTHRCTL

0x00000830 This register contains the Receive and Transmit Threshold characteristics of the Device controller.

## ◆ DIEPEMPMSK

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPEMPMSK

0x00000834 This register is valid only in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO = 1). This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp).

## ◆ RESERVED27

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED27[50]

## ◆ DIEPCTL0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL0

0x00000900 This register is used to control the characteristics of the IN Endpoint 0 of the Device controller.

## ◆ RESERVED28

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED28

## ◆ DIEPINT0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT0

0x00000908 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in the 'Interrupt Hierarchy' figure in the databook. The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers

## ◆ RESERVED29

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED29

## ◆ DIEPTSIZ0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ0

0x00000910 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 115. When Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros.

## ◆ DIEPDMA0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA0

0x00000914 This register contains the DMA Address for the IN Endpoint 0 of the Device controller.

## ◆ DTXFSTS0

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS0

0x00000918 This register contains information about the IN Endpoint Transmit FIFO of the Device controller.

## ◆ DIEPDMAB0

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB0

0x0000091C This register contains the DMA Buffer Address for the IN Endpoint 0 of the Device controller.

## ◆ DIEPCTL1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL1

0x00000920 This register is used to control the characteristics of Endpoint 1. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED30

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED30

## ◆ DIEPINT1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT1

0x00000928 This register contains the interrupts for the IN Endpoint 1 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED31

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED31

## ◆ DIEPTSIZ1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ1

0x00000930 This register reflects the Transfer Size of the IN Endpoint 1 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA1

0x00000934 This register contains the DMA Address for the IN Endpoint 1 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS1

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS1

0x00000938 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 1 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB1

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB1

0x0000093C This register contains the DMA Buffer Address of the IN Endpoint 1 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPCTL2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL2

0x00000940 This register is used to control the characteristics of Endpoint 2. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED32

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED32

## ◆ DIEPINT2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT2

0x00000948 This register contains the interrupts for the IN Endpoint 2 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED33

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED33

## ◆ DIEPTSIZ2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ2

0x00000950 This register reflects the Transfer Size of the IN Endpoint 2 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA2

0x00000954 This register contains the DMA Address for the IN Endpoint 2 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS2

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS2

0x00000958 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 2 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB2

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB2

0x0000095C This register contains the DMA Buffer Address of the IN Endpoint 2 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPCTL3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL3

0x00000960 This register is used to control the characteristics of Endpoint 3. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED34

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED34

## ◆ DIEPINT3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT3

0x00000968 This register contains the interrupts for the IN Endpoint 3 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED35

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED35

## ◆ DIEPTSIZ3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ3

0x00000970 This register reflects the Transfer Size of the IN Endpoint 3 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA3

0x00000974 This register contains the DMA Address for the IN Endpoint 3 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS3

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS3

0x00000978 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 3 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB3

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB3

0x0000097C This register contains the DMA Buffer Address of the IN Endpoint 3 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPCTL4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL4

0x00000980 This register is used to control the characteristics of Endpoint 4. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED36

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED36

## ◆ DIEPINT4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT4

0x00000988 This register contains the interrupts for the IN Endpoint 4 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED37

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED37

## ◆ DIEPTSIZ4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ4

0x00000990 This register reflects the Transfer Size of the IN Endpoint 4 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA4

0x00000994 This register contains the DMA Address for the IN Endpoint 4 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS4

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS4

0x00000998 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 4 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB4

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB4

0x0000099C This register contains the DMA Buffer Address of the IN Endpoint 4 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPCTL5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL5

0x000009A0 This register is used to control the characteristics of Endpoint 5. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED38

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED38

## ◆ DIEPINT5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT5

0x000009A8 This register contains the interrupts for the IN Endpoint 5 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED39

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED39

## ◆ DIEPTSIZ5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ5

0x000009B0 This register reflects the Transfer Size of the IN Endpoint 5 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA5

0x000009B4 This register contains the DMA Address for the IN Endpoint 5 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS5

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS5

0x000009B8 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 5 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB5

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB5

0x000009BC This register contains the DMA Buffer Address of the IN Endpoint 5 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPCTL6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL6

0x000009C0 This register is used to control the characteristics of Endpoint 6. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED40

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED40

## ◆ DIEPINT6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT6

0x000009C8 This register contains the interrupts for the IN Endpoint 6 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED41

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED41

## ◆ DIEPTSIZ6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ6

0x000009D0 This register reflects the Transfer Size of the IN Endpoint 6 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA6

0x000009D4 This register contains the DMA Address for the IN Endpoint 6 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS6

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS6

0x000009D8 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 6 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB6

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB6

0x000009DC This register contains the DMA Buffer Address of the IN Endpoint 6 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPCTL7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL7

0x000009E0 This register is used to control the characteristics of Endpoint 7. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED42

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED42

## ◆ DIEPINT7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT7

0x000009E8 This register contains the interrupts for the IN Endpoint 7 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED43

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED43

## ◆ DIEPTSIZ7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ7

0x000009F0 This register reflects the Transfer Size of the IN Endpoint 7 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA7

0x000009F4 This register contains the DMA Address for the IN Endpoint 7 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS7

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS7

0x000009F8 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 7 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB7

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB7

0x000009FC This register contains the DMA Buffer Address of the IN Endpoint 7 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPCTL8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPCTL8

0x00000A00 This register is used to control the characteristics of Endpoint 8. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED44

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED44

## ◆ DIEPINT8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPINT8

0x00000A08 This register contains the interrupts for the IN Endpoint 8 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED45

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED45

## ◆ DIEPTSIZ8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPTSIZ8

0x00000A10 This register reflects the Transfer Size of the IN Endpoint 8 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMA8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMA8

0x00000A14 This register contains the DMA Address for the IN Endpoint 8 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DTXFSTS8

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DTXFSTS8

0x00000A18 This register reflects the status of the IN Endpoint Transmit FIFO Status Register 8 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ DIEPDMAB8

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DIEPDMAB8

0x00000A1C This register contains the DMA Buffer Address of the IN Endpoint 8 of the Device controller. Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.

## ◆ RESERVED46

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED46[56]

## ◆ DOEPCTL0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL0

0x00000B00 This register is used to control the characteristics of the OUT Endpoint 0 of the Device controller.

## ◆ RESERVED47

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED47

## ◆ DOEPINT0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT0

0x00000B08 This register contains the interrupts for the OUT Endpoint 0 of the Device controller.

## ◆ RESERVED48

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED48

## ◆ DOEPTSIZ0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ0

0x00000B10 This register contains the Transfer Size for the OUT Endpoint 0 of the Device controller.

## ◆ DOEPDMA0

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA0

0x00000B14 This register contains the DMA Address for the OUT Endpoint 0 of the Device controller.

## ◆ RESERVED49

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED49

## ◆ DOEPDMAB0

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB0

0x00000B1C This register contains the DMA Buffer Address for the OUT Endpoint 0 of the Device controller.

## ◆ DOEPCTL1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL1

0x00000B20 This register is used to control the characteristics of OUT Endpoint 1 of the Device controller.

## ◆ RESERVED50

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED50

## ◆ DOEPINT1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT1

0x00000B28 This register contains the interrupts for the OUT Endpoint 1 of the Device controller.

## ◆ RESERVED51

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED51

## ◆ DOEPTSIZ1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ1

0x00000B30 This register contains the Transfer Size for the OUT Endpoint 1 of the Device controller.

## ◆ DOEPDMA1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA1

0x00000B34 This register contains the DMA Address for the OUT Endpoint 1 of the Device controller.

## ◆ RESERVED52

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED52

## ◆ DOEPDMAB1

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB1

0x00000B3C This register contains the DMA Buffer Address for the OUT Endpoint 1 of the Device controller.

## ◆ DOEPCTL2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL2

0x00000B40 This register is used to control the characteristics of OUT Endpoint 2 of the Device controller.

## ◆ RESERVED53

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED53

## ◆ DOEPINT2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT2

0x00000B48 This register contains the interrupts for the OUT Endpoint 2 of the Device controller.

## ◆ RESERVED54

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED54

## ◆ DOEPTSIZ2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ2

0x00000B50 This register contains the Transfer Size for the OUT Endpoint 2 of the Device controller.

## ◆ DOEPDMA2

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA2

0x00000B54 This register contains the DMA Address for the OUT Endpoint 2 of the Device controller.

## ◆ RESERVED55

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED55

## ◆ DOEPDMAB2

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB2

0x00000B5C This register contains the DMA Buffer Address for the OUT Endpoint 2 of the Device controller.

## ◆ DOEPCTL3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL3

0x00000B60 This register is used to control the characteristics of OUT Endpoint 3 of the Device controller.

## ◆ RESERVED56

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED56

## ◆ DOEPINT3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT3

0x00000B68 This register contains the interrupts for the OUT Endpoint 3 of the Device controller.

## ◆ RESERVED57

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED57

## ◆ DOEPTSIZ3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ3

0x00000B70 This register contains the Transfer Size for the OUT Endpoint 3 of the Device controller.

## ◆ DOEPDMA3

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA3

0x00000B74 This register contains the DMA Address for the OUT Endpoint 3 of the Device controller.

## ◆ RESERVED58

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED58

## ◆ DOEPDMAB3

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB3

0x00000B7C This register contains the DMA Buffer Address for the OUT Endpoint 3 of the Device controller.

## ◆ DOEPCTL4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL4

0x00000B80 This register is used to control the characteristics of OUT Endpoint 4 of the Device controller.

## ◆ RESERVED59

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED59

## ◆ DOEPINT4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT4

0x00000B88 This register contains the interrupts for the OUT Endpoint 4 of the Device controller.

## ◆ RESERVED60

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED60

## ◆ DOEPTSIZ4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ4

0x00000B90 This register contains the Transfer Size for the OUT Endpoint 4 of the Device controller.

## ◆ DOEPDMA4

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA4

0x00000B94 This register contains the DMA Address for the OUT Endpoint 4 of the Device controller.

## ◆ RESERVED61

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED61

## ◆ DOEPDMAB4

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB4

0x00000B9C This register contains the DMA Buffer Address for the OUT Endpoint 4 of the Device controller.

## ◆ DOEPCTL5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL5

0x00000BA0 This register is used to control the characteristics of OUT Endpoint 5 of the Device controller.

## ◆ RESERVED62

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED62

## ◆ DOEPINT5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT5

0x00000BA8 This register contains the interrupts for the OUT Endpoint 5 of the Device controller.

## ◆ RESERVED63

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED63

## ◆ DOEPTSIZ5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ5

0x00000BB0 This register contains the Transfer Size for the OUT Endpoint 5 of the Device controller.

## ◆ DOEPDMA5

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA5

0x00000BB4 This register contains the DMA Address for the OUT Endpoint 5 of the Device controller.

## ◆ RESERVED64

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED64

## ◆ DOEPDMAB5

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB5

0x00000BBC This register contains the DMA Buffer Address for the OUT Endpoint 5 of the Device controller.

## ◆ DOEPCTL6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL6

0x00000BC0 This register is used to control the characteristics of OUT Endpoint 6 of the Device controller.

## ◆ RESERVED65

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED65

## ◆ DOEPINT6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT6

0x00000BC8 This register contains the interrupts for the OUT Endpoint 6 of the Device controller.

## ◆ RESERVED66

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED66

## ◆ DOEPTSIZ6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ6

0x00000BD0 This register contains the Transfer Size for the OUT Endpoint 6 of the Device controller.

## ◆ DOEPDMA6

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA6

0x00000BD4 This register contains the DMA Address for the OUT Endpoint 6 of the Device controller.

## ◆ RESERVED67

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED67

## ◆ DOEPDMAB6

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB6

0x00000BDC This register contains the DMA Buffer Address for the OUT Endpoint 6 of the Device controller.

## ◆ DOEPCTL7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL7

0x00000BE0 This register is used to control the characteristics of OUT Endpoint 7 of the Device controller.

## ◆ RESERVED68

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED68

## ◆ DOEPINT7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT7

0x00000BE8 This register contains the interrupts for the OUT Endpoint 7 of the Device controller.

## ◆ RESERVED69

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED69

## ◆ DOEPTSIZ7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ7

0x00000BF0 This register contains the Transfer Size for the OUT Endpoint 7 of the Device controller.

## ◆ DOEPDMA7

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA7

0x00000BF4 This register contains the DMA Address for the OUT Endpoint 7 of the Device controller.

## ◆ RESERVED70

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED70

## ◆ DOEPDMAB7

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB7

0x00000BFC This register contains the DMA Buffer Address for the OUT Endpoint 7 of the Device controller.

## ◆ DOEPCTL8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPCTL8

0x00000C00 This register is used to control the characteristics of OUT Endpoint 8 of the Device controller.

## ◆ RESERVED71

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED71

## ◆ DOEPINT8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPINT8

0x00000C08 This register contains the interrupts for the OUT Endpoint 8 of the Device controller.

## ◆ RESERVED72

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED72

## ◆ DOEPTSIZ8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPTSIZ8

0x00000C10 This register contains the Transfer Size for the OUT Endpoint 8 of the Device controller.

## ◆ DOEPDMA8

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMA8

0x00000C14 This register contains the DMA Address for the OUT Endpoint 8 of the Device controller.

## ◆ RESERVED73

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED73

## ◆ DOEPDMAB8

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::DOEPDMAB8

0x00000C1C This register contains the DMA Buffer Address for the OUT Endpoint 8 of the Device controller.

## ◆ RESERVED74

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED74[120]

## ◆ PCGCCTL

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::PCGCCTL

0x00000E00 This register is used to control the Power and Clock Gating characteristics of the controller.

## ◆ PCGCCTL1

__IOM uint32_t USBHS_DWC_OTG_INTREG_Type::PCGCCTL1

0x00000E04 This register is used to control the Power and Clock Gating characteristics of the controller.

## ◆ RESERVED75

__IM uint32_t USBHS_DWC_OTG_INTREG_Type::RESERVED75[62]