PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
dma_status0_r Struct Reference

## Data Fields
union {
struct {
uint32_t | cmd_idle: 1
uint32_t | ifm_idle: 1
uint32_t | wgt_idle_c0: 1
uint32_t | bas_idle_c0: 1
uint32_t | m2m_idle: 1
uint32_t | ofm_idle: 1
uint32_t | halt_req: 1
uint32_t | halt_ack: 1
uint32_t | pause_req: 1
uint32_t | pause_ack: 1
uint32_t | ib0_ai_valid_c0: 1
uint32_t | ib0_ai_ready_c0: 1
uint32_t | ib1_ai_valid_c0: 1
uint32_t | ib1_ai_ready_c0: 1
uint32_t | ib0_ao_valid_c0: 1
uint32_t | ib0_ao_ready_c0: 1
uint32_t | ib1_ao_valid_c0: 1
uint32_t | ib1_ao_ready_c0: 1
uint32_t | ob0_valid_c0: 1
uint32_t | ob0_ready_c0: 1
uint32_t | ob1_valid_c0: 1
uint32_t | ob1_ready_c0: 1
uint32_t | cmd_valid: 1
uint32_t | cmd_ready: 1
uint32_t | wd_bitstream_valid_c0: 1
uint32_t | wd_bitstream_ready_c0: 1
uint32_t | bs_bitstream_valid_c0: 1
uint32_t | bs_bitstream_ready_c0: 1
uint32_t | axi0_ar_stalled: 1
uint32_t | axi0_rd_limit_stall: 1
uint32_t | axi0_aw_stalled: 1
uint32_t | axi0_w_stalled: 1
} |
uint32_t | word
}; |
union {
struct {
uint32_t | cmd_idle: 1
uint32_t | ifm_idle: 1
uint32_t | wgt_idle_c0: 1
uint32_t | bas_idle_c0: 1
uint32_t | m2m_idle: 1
uint32_t | ofm_idle: 1
uint32_t | halt_req: 1
uint32_t | halt_ack: 1
uint32_t | pause_req: 1
uint32_t | pause_ack: 1
uint32_t | ib0_ai_valid_c0: 1
uint32_t | ib0_ai_ready_c0: 1
uint32_t | ib1_ai_valid_c0: 1
uint32_t | ib1_ai_ready_c0: 1
uint32_t | ib0_ao_valid_c0: 1
uint32_t | ib0_ao_ready_c0: 1
uint32_t | ib1_ao_valid_c0: 1
uint32_t | ib1_ao_ready_c0: 1
uint32_t | ob0_valid_c0: 1
uint32_t | ob0_ready_c0: 1
uint32_t | ob1_valid_c0: 1
uint32_t | ob1_ready_c0: 1
uint32_t | cmd_valid: 1
uint32_t | cmd_ready: 1
uint32_t | wd_bitstream_valid_c0: 1
uint32_t | wd_bitstream_ready_c0: 1
uint32_t | bs_bitstream_valid_c0: 1
uint32_t | bs_bitstream_ready_c0: 1
uint32_t | axi0_ar_stalled: 1
uint32_t | axi0_rd_limit_stall: 1
uint32_t | axi0_aw_stalled: 1
uint32_t | axi0_w_stalled: 1
} |
uint32_t | word
}; |
union {
struct {
uint32_t | cmd_ch_idle: 1
uint32_t | ifm0_ch_idle: 1
uint32_t | ifm1_ch_idle: 1
uint32_t | wgt_ch_idle: 1
uint32_t | bas_ch_idle: 1
uint32_t | m2m_ch_idle: 1
uint32_t | ofm_ch_idle: 1
uint32_t | axi_halt_req: 1
uint32_t | axi_halt_ack: 1
uint32_t | axi_pause_req: 1
uint32_t | axi_pause_ack: 1
uint32_t | cmd_abort_ack: 1
uint32_t | cmd_abort_req: 1
uint32_t | ifm_mac_if_stall: 1
uint32_t | ifm_tc_if_stall: 1
uint32_t | ifm_ao_if_stall: 1
uint32_t | ofm_if_stall: 1
uint32_t | cmd_if_stall: 1
uint32_t | wd_sc0_if_stall: 1
uint32_t | wd_sc1_if_stall: 1
uint32_t | wd_sc2_if_stall: 1
uint32_t | wd_sc3_if_stall: 1
uint32_t | wd_fc_if_stall: 1
uint32_t | bs_if_stall: 1
uint32_t | lutcfg_if_stall: 1
uint32_t | reserved0: 7
} |
uint32_t | word
}; |

## Field Documentation

## ◆

union { ... } dma_status0_r::@113

## ◆

union { ... } dma_status0_r::@769

## ◆

union { ... } dma_status0_r::@2005