PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Macros
I3C Callback Events
PDL API Reference » I3C (I3C) » Macros

## General Description

Macros to check I3C events passed by cy_cb_i3c_handle_events_t callback.

Each event is encoded in a separate bit, and therefore it is possible to notify about multiple events.

## Macros
#define | CY_I3C_CONTROLLER_WR_CMPLT_EVENT (0x00000001UL)
| The controller write started by Cy_I3C_ControllerWrite is complete.
#define | CY_I3C_CONTROLLER_RD_CMPLT_EVENT (0x00000002UL)
| The controller read started by Cy_I3C_ControllerRead is complete.
#define | CY_I3C_CONTROLLER_WR_EARLY_TERMINATION_EVENT (0x00000004UL)
| CY_I3C_CONTROLLER_WR_EARLY_TERMINATION_EVENT.
#define | CY_I3C_CRC_ERROR_EVENT (0x00000008UL)
| Indicates the I3C hardware has detected an error. More...
#define | CY_I3C_PARITY_ERROR_EVENT (0x00000010UL)
| CY_I3C_PARITY_ERROR_EVENT.
#define | CY_I3C_FRAME_ERROR_EVENT (0x00000020UL)
| CY_I3C_FRAME_ERROR_EVENT.
#define | CY_I3C_BROADCAST_ADDR_NACK_ERROR_EVENT (0x00000040UL)
| CY_I3C_BROADCAST_ADDR_NACK_ERROR_EVENT.
#define | CY_I3C_ADDR_NACK_ERROR_EVENT (0x00000080UL)
| CY_I3C_ADDR_NACK_ERROR_EVENT.
#define | CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT (0x00000100UL)
| CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT.
#define | CY_I3C_XFER_ABORTED_ERROR_EVENT (0x00000200UL)
| CY_I3C_XFER_ABORTED_ERROR_EVENT.
#define | CY_I3C_I2C_TGT_WDATA_NACK_ERROR_EVENT (0x00000400UL)
| CY_I3C_I2C_TGT_WDATA_NACK_ERROR_EVENT.
#define | CY_I3C_CONTROLLER_EARLY_TERMINATION_EVENT (0x00000800UL)
| CY_I3C_CONTROLLER_EARLY_TERMINATION_EVENT.
#define | CY_I3C_CONTROLLER_ERROR_CE0_EVENT (0X00001000UL)
| CY_I3C_CONTROLLER_ERROR_CE0_EVENT.
#define | CY_I3C_CONTROLLER_ERR_EVENT
| CY_I3C_CONTROLLER_ERR_EVENT. More...
#define | CY_I3C_TARGET_ERR_EVENT
| CY_I3C_TARGET_ERR_EVENT. More...
#define | CY_I3C_TARGET_ASSIGNED_DYN_ADDR_EVENT (0X00002000UL)
| The target device is assigned a dynamic address through SETDASA or ENTDAA or SETAASA CCC from the controller.
#define | CY_I3C_TARGET_WR_BUFFER_NOT_CONFIGURED (0x00004000UL)
| The controller has read all data out of the configured Read buffer. More...
#define | CY_I3C_TARGET_MAX_RD_LEN_UPDT_EVENT (0X00008000UL)
| CY_I3C_TARGET_MAX_RD_LEN_UPDT_EVENT.
#define | CY_I3C_TARGET_MAX_WR_LEN_UPDT_EVENT (0X00010000UL)
| CY_I3C_TARGET_MAX_WR_LEN_UPDT_EVENT.
#define | CY_I3C_TARGET_RD_CMPLT_EVENT (0x00020000UL)
| Indicates the controller completed reading from the target (set by the controller NAK or Stop)
#define | CY_I3C_TARGET_WR_CMPLT_EVENT (0x00040000UL)
| Indicates the controller completed writing to the target (set by the controller Stop or Restart)
#define | CY_I3C_TARGET_CCC_REG_UPDATED_EVENT (0x00080000UL)
| One of the CCC register is updated by I3C Controller through CCC commands.
#define | CY_I3C_TARGET_NO_VALID_CMD_IN_CMDQ_EVENT (0x00100000UL)
| There is no valid command in the command queue.
#define | CY_I3C_TARGET_DATA_NOT_READY_EVENT (0x00200000UL)
| The data in Tx FIFO is not equal to the data length size of the command or the TX_START_THLD value or the Response queue is full.
#define | CY_I3C_DEFTGT_EVENT (0x00400000UL)
| DEFTGTS CCC is received.
#define | CY_I3C_CONTROLLER_ROLE_UPDATED_EVENT (0x00800000UL)
| Role of the controller changed from Controller to Target or vice-versa.
#define | CY_I3C_TARGET_RESET_EVENT (0x01000000UL)
| Target reset pattern detected.
#define | CY_I3C_TARGET_IBI_NOT_ATTEMPTED_EVENT (0x02000000UL)
| IBI not attempted by target as bus might be busy.
#define | CY_I3C_TARGET_IBI_ACKNOWLEDGED_EVENT (0x04000000UL)
| IBI Acknowledged by controller.
#define | CY_I3C_TARGET_CR_ACCEPTED_EVENT (0x04000000UL)
| Controllership request accepted.
#define | CY_I3C_TARGET_IBI_EARLY_STOP_EVENT (0x08000000UL)
| FOR TIR with data controller terminated before reading all the data.
#define | CY_I3C_PEC_ERROR_EVENT (0x10000000UL)
| PEC Error event.

## Macro Definition Documentation

## ◆ CY_I3C_CRC_ERROR_EVENT

#define CY_I3C_CRC_ERROR_EVENT (0x00000008UL)

Indicates the I3C hardware has detected an error.

CY_I3C_CRC_ERROR_EVENT

## ◆ CY_I3C_CONTROLLER_ERR_EVENT

#define CY_I3C_CONTROLLER_ERR_EVENT

Value:
(CY_I3C_CRC_ERROR_EVENT| CY_I3C_PARITY_ERROR_EVENT| CY_I3C_FRAME_ERROR_EVENT| \
CY_I3C_BROADCAST_ADDR_NACK_ERROR_EVENT| CY_I3C_ADDR_NACK_ERROR_EVENT| CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT| \
CY_I3C_XFER_ABORTED_ERROR_EVENT| CY_I3C_I2C_TGT_WDATA_NACK_ERROR_EVENT| CY_I3C_CONTROLLER_ERROR_CE0| CY_I3C_PEC_ERROR_EVENT)
CY_I3C_CONTROLLER_ERROR_CE0
@ CY_I3C_CONTROLLER_ERROR_CE0
SDR Controller Error Code CE0 for Illegally formatted CCC Response.
Definition: cy_i3c.h:911
CY_I3C_PEC_ERROR_EVENT
#define CY_I3C_PEC_ERROR_EVENT
PEC Error event.
Definition: cy_i3c.h:567
CY_I3C_FRAME_ERROR_EVENT
#define CY_I3C_FRAME_ERROR_EVENT
CY_I3C_FRAME_ERROR_EVENT.
Definition: cy_i3c.h:492
CY_I3C_ADDR_NACK_ERROR_EVENT
#define CY_I3C_ADDR_NACK_ERROR_EVENT
CY_I3C_ADDR_NACK_ERROR_EVENT.
Definition: cy_i3c.h:496
CY_I3C_I2C_TGT_WDATA_NACK_ERROR_EVENT
#define CY_I3C_I2C_TGT_WDATA_NACK_ERROR_EVENT
CY_I3C_I2C_TGT_WDATA_NACK_ERROR_EVENT.
Definition: cy_i3c.h:502
CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT
#define CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT
CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT.
Definition: cy_i3c.h:498
CY_I3C_PARITY_ERROR_EVENT
#define CY_I3C_PARITY_ERROR_EVENT
CY_I3C_PARITY_ERROR_EVENT.
Definition: cy_i3c.h:490
CY_I3C_CRC_ERROR_EVENT
#define CY_I3C_CRC_ERROR_EVENT
Indicates the I3C hardware has detected an error.
Definition: cy_i3c.h:488

CY_I3C_CONTROLLER_ERR_EVENT.

## ◆ CY_I3C_TARGET_ERR_EVENT

#define CY_I3C_TARGET_ERR_EVENT

Value:
(CY_I3C_CRC_ERROR_EVENT| CY_I3C_PARITY_ERROR_EVENT| CY_I3C_FRAME_ERROR_EVENT| \
CY_I3C_BUFFER_OVERFLOW_ERROR_EVENT | CY_I3C_CONTROLLER_EARLY_TERMINATION_EVENT | CY_I3C_PEC_ERROR_EVENT)
CY_I3C_CONTROLLER_EARLY_TERMINATION_EVENT
#define CY_I3C_CONTROLLER_EARLY_TERMINATION_EVENT
CY_I3C_CONTROLLER_EARLY_TERMINATION_EVENT.
Definition: cy_i3c.h:504

CY_I3C_TARGET_ERR_EVENT.

## ◆ CY_I3C_TARGET_WR_BUFFER_NOT_CONFIGURED

#define CY_I3C_TARGET_WR_BUFFER_NOT_CONFIGURED (0x00004000UL)

The controller has read all data out of the configured Read buffer.

This event can be used to configure the next Read buffer. If the buffer remains empty, the CY_I3C_DEFAULT_TX bytes are returned to the controller. CY_I3C_TARGET_WR_BUFFER_NOT_CONFIGURED