PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

API Reference
EMAC (Ethernet MAC)
PDL API Reference

## General Description

Ethernet is a well-defined industry specification.

Ethernet MAC module transmits and receives IEEE 802.3 frames by connecting with the PHY device using MII/RMII/GMII or RGMII interface. Ethernet MAC also supports 10/100/1000 Transfer rates and IEEE 1588 time stamp feature. Infineon uses a third-party Ethernet MAC IP from Cadence GEM_GXL, which is a Gigabit Ethernet MAC.

Note
  Ethernet MAC does not support "Wake on Lan" feature. So when the system is in deep sleep, it can't receive any Rx frames.

Below block diagram shows the hardware and software partition inside the MCU. Ethernet MAC IP hardware directly interface with external ethernet PHY via MII or RMII or GMII or RGMII interface and MDIO interface is for configuring the Ethernet PHY chip/device. The software section consists of three major layers Ethernet PDL (Peripheral Driver Library), Connectivity Middleware, and Applications. Ethernet PDL implements low level driver for Ethernet MAC and a generic driver for the external Ethernet PHY chips.

Ethernet Block Diagram

The ETHIF driver is wrapper around Cadence's EMAC core driver. This is a network interface driver to Cadence core EMAC driver. It provides APIs to communicate with Ethernet IP. The PHY driver also uses this driver to communicate with PHY chip (via application). This driver has internal buffer management, handling callbacks from Cadence EMAC during transport, etc.

The functions and other declarations used in this driver are in cy_ethif.h. You can include cy_pdl.h (ModusToolbox only) to get access to all functions and declarations in the PDL.

# Tx/Rx Programming

1. Make sure all the pins connected between MAC and PHY is configured properly.
2. Enable Interrupts for Ethernet queues. This is used to receive events from driver.
3. Initialize MAC using Cy_ETHIF_Init() API.
4. Optionally set filters.
5. PHY chip is outside of silicon. Initialize PHY using EPHY driver. Some PHY chip needs configuration using it's proprietary(extended) registers. Fo this refer to PHY data sheet.
6. Wait for link to be up. This can be done using EPHY APIs.
7. Once is link is up, then transmit frame using Cy_ETHIF_TransmitFrame() API.
8. The receive callback is called when there is any frame received by MAC. The receive callback is registered during Cy_ETHIF_Init() API call.

# More Information

Refer to the technical reference manual (TRM) and the device datasheet.

# MISRA-C Compliance

The Ethernet driver has no specific deviations

# Changelog

Version | Changes | Reason for Change
--- | --- | ---
1.50 | Added new Cy_ETHIF_GetPrivateData API getter. | Code enhancement.
1.40 | Added initialization checks for Cy_ETHIF_Get1588TimerValue and Cy_ETHIF_Set1588TimerValue functions, added new cy_en_ethif_status_t CY_ETHIF_NOT_INITIALIZED return status. | Defect fix.
1.30 | Added an internal low power callback. | Code enhancement.
1.20 | Documentation update and updated pre-processor check for CM55. | Code enhancement.
1.10.1 | Build warning fixes due to redefinitions. | Bug fixes.
1.10 | Updated an internal API and fixed MISRA 2012 violations. | MISRA 2012 compliance and code enhancement.
1.0 | Initial version |

## API Reference
| Macros
| Functions
| Data Structures
| Enumerated Types