PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
MXCM55_Type Struct Reference

## Description

MXCM55-0/1 (MXCM55)

## Data Fields
__IOM uint32_t | CM55_CTL
__IOM uint32_t | CM55_CMD
__IM uint32_t | CM55_STATUS
__IOM uint32_t | CM55_TCM_CTL
__IM uint32_t | RESERVED [12]
__IM uint32_t | CM55_INT_STATUS [16]
__IOM uint32_t | CM55_NMI_CTL [4]
__IM uint32_t | RESERVED1 [12]
__IOM uint32_t | CM55_EVENT_CTL
__IM uint32_t | RESERVED2 [975]
__IOM uint32_t | CM55_S_VECTOR_TABLE_BASE
__IOM uint32_t | CM55_NS_VECTOR_TABLE_BASE
__IM uint32_t | RESERVED3 [1070]
__IOM uint32_t | WOUNDING
__IM uint32_t | RESERVED4 [6095]
__IOM uint32_t | CM55_SYSTEM_INT_CTL [1023]

## Field Documentation

## ◆ CM55_CTL

__IOM uint32_t MXCM55_Type::CM55_CTL

0x00000000 Control

## ◆ CM55_CMD

__IOM uint32_t MXCM55_Type::CM55_CMD

0x00000004 Command

## ◆ CM55_STATUS

__IM uint32_t MXCM55_Type::CM55_STATUS

0x00000008 Status

## ◆ CM55_TCM_CTL

__IOM uint32_t MXCM55_Type::CM55_TCM_CTL

0x0000000C TCM control

## ◆ RESERVED

__IM uint32_t MXCM55_Type::RESERVED[12]

## ◆ CM55_INT_STATUS

__IM uint32_t MXCM55_Type::CM55_INT_STATUS[16]

0x00000040 CM55 interrupt status

## ◆ CM55_NMI_CTL

__IOM uint32_t MXCM55_Type::CM55_NMI_CTL[4]

0x00000080 CM55 NMI control

## ◆ RESERVED1

__IM uint32_t MXCM55_Type::RESERVED1[12]

## ◆ CM55_EVENT_CTL

__IOM uint32_t MXCM55_Type::CM55_EVENT_CTL

0x000000C0 CM55 EVENT control

## ◆ RESERVED2

__IM uint32_t MXCM55_Type::RESERVED2[975]

## ◆ CM55_S_VECTOR_TABLE_BASE

__IOM uint32_t MXCM55_Type::CM55_S_VECTOR_TABLE_BASE

0x00001000 CM55 secure vector table base

## ◆ CM55_NS_VECTOR_TABLE_BASE

__IOM uint32_t MXCM55_Type::CM55_NS_VECTOR_TABLE_BASE

0x00001004 CM55 non-secure vector table base

## ◆ RESERVED3

__IM uint32_t MXCM55_Type::RESERVED3[1070]

## ◆ WOUNDING

__IOM uint32_t MXCM55_Type::WOUNDING

0x000020C0 Wounding

## ◆ RESERVED4

__IM uint32_t MXCM55_Type::RESERVED4[6095]

## ◆ CM55_SYSTEM_INT_CTL

__IOM uint32_t MXCM55_Type::CM55_SYSTEM_INT_CTL[1023]

0x00008000 CM55 system interrupt control