PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
SAR_STA_Type Struct Reference

## Description

SAR static configuration registers (SAR_STA)

## Data Fields
__IOM uint32_t | CTRL
__IM uint32_t | RESERVED
__IOM uint32_t | FIR_CFG [2]
__IM uint32_t | RESERVED1 [2]
__IOM uint32_t | TR_SAMPLE_TIME
__IM uint32_t | RESERVED2
__IOM uint32_t | SAMPLE_TIME [4]
__IOM uint32_t | GPIO_CHAN_CFG [8]
__IOM uint32_t | MUX_CHAN_CFG [16]
__IOM uint32_t | STATUS_CFG [4]
__IOM uint32_t | STATUS_RANGE_LOW [4]
__IOM uint32_t | STATUS_RANGE_HIGH [4]
__IM uint32_t | GPIO_CHAN_RESULT [8]
__IM uint32_t | MUX_CHAN_RESULT [16]
__IM uint32_t | FIR_RESULT [2]
__IM uint32_t | RESERVED3 [2]
__IOM uint32_t | CHAN_RESULT_MASK
__IOM uint32_t | FIR_RESULT_MASK
__IOM uint32_t | CHAN_RESULT_UPDATED
__IOM uint32_t | FIR_RESULT_UPDATED
__IM uint32_t | STATUS
__IOM uint32_t | RANGE_STATUS
__IM uint32_t | RESERVED4 [2]
__IOM uint32_t | CHAN_COEFF [8]
__IM uint32_t | RESERVED5 [36]

## Field Documentation

## ◆ CTRL

__IOM uint32_t SAR_STA_Type::CTRL

0x00000000 SAR Control register (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ RESERVED

__IM uint32_t SAR_STA_Type::RESERVED

## ◆ FIR_CFG

__IOM uint32_t SAR_STA_Type::FIR_CFG[2]

0x00000008 FIR Configuration register (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ RESERVED1

__IM uint32_t SAR_STA_Type::RESERVED1[2]

## ◆ TR_SAMPLE_TIME

__IOM uint32_t SAR_STA_Type::TR_SAMPLE_TIME

0x00000018 SAR Trigger Sample Time (Risk Mitigation Only)

## ◆ RESERVED2

__IM uint32_t SAR_STA_Type::RESERVED2

## ◆ SAMPLE_TIME

__IOM uint32_t SAR_STA_Type::SAMPLE_TIME[4]

0x00000020 Sample control register (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ GPIO_CHAN_CFG

__IOM uint32_t SAR_STA_Type::GPIO_CHAN_CFG[8]

0x00000030 High Speed GPIO Channel configuration register (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ MUX_CHAN_CFG

__IOM uint32_t SAR_STA_Type::MUX_CHAN_CFG[16]

0x00000050 High Speed / Low Power Muxed Channel configuration register (Channel 0 routing is used for default routing (i.e. when the SAR gets enabled) (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ STATUS_CFG

__IOM uint32_t SAR_STA_Type::STATUS_CFG[4]

0x00000090 Global range detect mode register (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ STATUS_RANGE_LOW

__IOM uint32_t SAR_STA_Type::STATUS_RANGE_LOW[4]

0x000000A0 Global range detect low value register (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ STATUS_RANGE_HIGH

__IOM uint32_t SAR_STA_Type::STATUS_RANGE_HIGH[4]

0x000000B0 Global range detect high value register (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ GPIO_CHAN_RESULT

__IM uint32_t SAR_STA_Type::GPIO_CHAN_RESULT[8]

0x000000C0 High Speed GPIO Channel result register

## ◆ MUX_CHAN_RESULT

__IM uint32_t SAR_STA_Type::MUX_CHAN_RESULT[16]

0x000000E0 High Speed / Low Power Muxed Channel result register

## ◆ FIR_RESULT

__IM uint32_t SAR_STA_Type::FIR_RESULT[2]

0x00000120 FIR result register

## ◆ RESERVED3

__IM uint32_t SAR_STA_Type::RESERVED3[2]

## ◆ CHAN_RESULT_MASK

__IOM uint32_t SAR_STA_Type::CHAN_RESULT_MASK

0x00000130 Channel result mask (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ FIR_RESULT_MASK

__IOM uint32_t SAR_STA_Type::FIR_RESULT_MASK

0x00000134 FIR result mask (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ CHAN_RESULT_UPDATED

__IOM uint32_t SAR_STA_Type::CHAN_RESULT_UPDATED

0x00000138 Channel result register status

## ◆ FIR_RESULT_UPDATED

__IOM uint32_t SAR_STA_Type::FIR_RESULT_UPDATED

0x0000013C FIR result register status

## ◆ STATUS

__IM uint32_t SAR_STA_Type::STATUS

0x00000140 SAR status register

## ◆ RANGE_STATUS

__IOM uint32_t SAR_STA_Type::RANGE_STATUS

0x00000144 Range status register

## ◆ RESERVED4

__IM uint32_t SAR_STA_Type::RESERVED4[2]

## ◆ CHAN_COEFF

__IOM uint32_t SAR_STA_Type::CHAN_COEFF[8]

0x00000150 Channel correction coefficients (only accessible if ACTRLR.STATUS.MODE=0)

## ◆ RESERVED5

__IM uint32_t SAR_STA_Type::RESERVED5[36]