/*

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   list of conditions and the following disclaimer.

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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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*/

#ifndef NRF7120_ENGA_INTERIM_H__
#define NRF7120_ENGA_INTERIM_H__

#if defined(NRF7120_ENGA_XXAA)


    #define EASYVDMA_PRESENT
    
    #define EGU00_CH_NUM EGU00_CH_NUM_SIZE
    #define EGU10_CH_NUM EGU10_CH_NUM_SIZE
    #define EGU20_CH_NUM EGU20_CH_NUM_SIZE

    #define TIMER00_CC_NUM TIMER00_CC_NUM_SIZE
    #define TIMER10_CC_NUM TIMER10_CC_NUM_SIZE
    #define TIMER20_CC_NUM TIMER20_CC_NUM_SIZE
    #define TIMER21_CC_NUM TIMER21_CC_NUM_SIZE
    #define TIMER22_CC_NUM TIMER22_CC_NUM_SIZE
    #define TIMER23_CC_NUM TIMER23_CC_NUM_SIZE
    #define TIMER24_CC_NUM TIMER24_CC_NUM_SIZE

    #define TIMER00_MAX_SIZE TIMER00_MAX_SIZE_SIZE
    #define TIMER10_MAX_SIZE TIMER10_MAX_SIZE_SIZE
    #define TIMER20_MAX_SIZE TIMER20_MAX_SIZE_SIZE
    #define TIMER21_MAX_SIZE TIMER21_MAX_SIZE_SIZE
    #define TIMER22_MAX_SIZE TIMER22_MAX_SIZE_SIZE
    #define TIMER23_MAX_SIZE TIMER23_MAX_SIZE_SIZE
    #define TIMER24_MAX_SIZE TIMER24_MAX_SIZE_SIZE

    #define LPCOMP_REFSEL_RESOLUTION 16

    #define MPC_MASTER_PORTS_MaxCount (12UL) /*!< Max number of master ports. */

    #define NRF_DOMAIN_COUNT (NRF_DOMAIN_SYSTEM + 1)
    #define SAADC_CH_NUM SAADC_CH_MaxCount

    #define PPIB_CHANNEL_MAX_COUNT 24UL

    #define PPIB00_CH_NUM 8
    #define PPIB10_CH_NUM 8
    #define PPIB11_CH_NUM 16
    #define PPIB21_CH_NUM 16
    #define PPIB22_CH_NUM 4
    #define PPIB30_CH_NUM 4
    #define PPIB20_CH_NUM 8
    #define PPIB01_CH_NUM 8

    #if defined(NRF_FLPR)
        #define GRTC_IRQ_GROUP   0
        #define GPIOTE_IRQ_GROUP 0
    #elif defined(NRF_APPLICATION)
        #if defined(NRF_TRUSTZONE_NONSECURE)
            #define GPIOTE_IRQ_GROUP       0
            #define GRTC_IRQ_GROUP         1 
        #else
            #define GPIOTE_IRQ_GROUP       1
            #define GRTC_IRQ_GROUP         2
        #endif
    #endif

    #define GPIOTE20_CH_NUM GPIOTE20_GPIOTE_NCHANNELS_SIZE
    #define GPIOTE30_CH_NUM GPIOTE30_GPIOTE_NCHANNELS_SIZE

    #define GPIOTE_CH_NUM   8
    #define GPIOTE20_AVAILABLE_GPIO_PORTS 0x2UL
    #define GPIOTE30_AVAILABLE_GPIO_PORTS 0x1UL
    #define GPIOTE_FEATURE_SET_PRESENT
    #define GPIOTE_FEATURE_CLR_PRESENT
    #define GPIOTE_PORT_NUM GPIOTE_EVENTS_PORT_MaxCount

    #define DPPI_PRESENT DPPIC_PRESENT

    #define DPPIC00_CH_NUM DPPIC00_CH_NUM_SIZE
    #define DPPIC10_CH_NUM DPPIC10_CH_NUM_SIZE
    #define DPPIC20_CH_NUM DPPIC20_CH_NUM_SIZE
    #define DPPIC30_CH_NUM DPPIC30_CH_NUM_SIZE
    
    #define DPPIC00_GROUP_NUM DPPIC00_GROUP_NUM_SIZE
    #define DPPIC10_GROUP_NUM DPPIC10_GROUP_NUM_SIZE
    #define DPPIC20_GROUP_NUM DPPIC20_GROUP_NUM_SIZE
    #define DPPIC30_GROUP_NUM DPPIC30_GROUP_NUM_SIZE

    #define P0_PIN_NUM P0_PIN_NUM_SIZE
    #define P1_PIN_NUM P1_PIN_NUM_SIZE
    #define P2_PIN_NUM P2_PIN_NUM_SIZE
    #define P3_PIN_NUM P3_PIN_NUM_SIZE
    #define P4_PIN_NUM P4_PIN_NUM_SIZE

    #define NRF_AUXPLL NRF_AUDIOPLL

    typedef enum
    {
        NRF_APB_INDEX_MCU   = 1,
        NRF_APB_INDEX_RADIO = 2,
        NRF_APB_INDEX_PERI  = 3,
        NRF_APB_INDEX_LP    = 4
    } nrf_apb_index_t;

#endif

#endif // NRF7120_ENGA_INTERIM_H__
