PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
SRSS_Type Struct Reference

## Description

SRSS Core Registers (SRSS)

## Data Fields
__IM uint32_t | RESERVED [64]
__IOM uint32_t | CLK_DSI_SELECT [16]
__IOM uint32_t | CLK_OUTPUT_FAST
__IOM uint32_t | CLK_OUTPUT_SLOW
__IOM uint32_t | CLK_CAL_CNT1
__IM uint32_t | CLK_CAL_CNT2
__IM uint32_t | RESERVED1 [44]
__IOM uint32_t | SRSS_INTR
__IOM uint32_t | SRSS_INTR_SET
__IOM uint32_t | SRSS_INTR_MASK
__IM uint32_t | SRSS_INTR_MASKED
__IM uint32_t | RESERVED2 [60]
__IOM uint32_t | SRSS_AINTR
__IOM uint32_t | SRSS_AINTR_SET
__IOM uint32_t | SRSS_AINTR_MASK
__IM uint32_t | SRSS_AINTR_MASKED
__IM uint32_t | RESERVED3 [12]
__IM uint32_t | PWR_LVD_STATUS
__IM uint32_t | RESERVED4 [48]
__IOM uint32_t | BOOT_DLM_CTL
__IOM uint32_t | BOOT_DLM_CTL2
__IOM uint32_t | BOOT_DLM_STATUS
__IOM uint32_t | RES_SOFT_CTL
__IM uint32_t | RESERVED5
__IOM uint32_t | BOOT_STATUS
__IM uint32_t | RESERVED6 [5]
__IOM uint32_t | BOOT_ENTRY
__IM uint32_t | RESERVED7 [3]
__IM uint32_t | DECODED_LCS_DATA
__IM uint32_t | RESERVED8 [239]
__IOM uint32_t | PWR_HIB_DATA [32]
__IM uint32_t | RESERVED9 [8]
__IOM uint32_t | PWR_HIB_WAKE_CTL
__IOM uint32_t | PWR_HIB_WAKE_CTL2
__IM uint32_t | RESERVED10
__IOM uint32_t | PWR_HIB_WAKE_CAUSE
__IM uint32_t | RESERVED11 [25]
__IOM uint32_t | TST_XRES_SECURE
__IM uint32_t | RESERVED12 [442]
__IM uint32_t | PWR_CTL
__IOM uint32_t | PWR_CTL2
__IOM uint32_t | PWR_HIBERNATE
__IM uint32_t | RESERVED13 [5]
__IOM uint32_t | PWR_LVD_CTL
__IM uint32_t | RESERVED14 [119]
__IOM uint32_t | CLK_PATH_SELECT [16]
__IOM uint32_t | CLK_ROOT_SELECT [16]
__IOM uint32_t | CLK_DIRECT_SELECT [16]
__IM uint32_t | RESERVED15 [16]
__IOM uint32_t | CLK_SELECT
__IOM uint32_t | CLK_MF_SELECT
__IM uint32_t | RESERVED16 [2]
__IOM uint32_t | CLK_ALTHF_CTL [2]
__IM uint32_t | RESERVED17 [2]
__IOM uint32_t | CLK_ECO_PRESCALE
__IM uint32_t | RESERVED18 [7]
__IOM uint32_t | CLK_IMO_CONFIG
__IOM uint32_t | CLK_IHO_CONFIG
__IM uint32_t | RESERVED19 [6]
CLK_ECO_Type | CLK_ECO_STRUCT
__IOM uint32_t | CLK_PILO_CONFIG
__IM uint32_t | CLK_PILO_STATUS
__IM uint32_t | RESERVED20 [2]
__IOM uint32_t | CLK_ILO_CONFIG
__IOM uint32_t | CLK_TRIM_ILO_CTL
__IM uint32_t | RESERVED21 [2]
__IOM uint32_t | CLK_WCO_CONFIG
__IM uint32_t | CLK_WCO_STATUS
__IM uint32_t | RESERVED22 [26]
CSV_HF_Type | CSV_HF_STRUCT
__IOM uint32_t | CSV_REF_SEL
__IM uint32_t | RESERVED23 [3]
CSV_REF_Type | CSV_REF_STRUCT
__IOM uint32_t | CSV_LF_REF_SEL
__IM uint32_t | RESERVED24 [3]
CSV_LF_Type | CSV_LF_STRUCT
__IOM uint32_t | CSV_PILO_REF_SEL
__IM uint32_t | RESERVED25 [3]
CSV_PILO_Type | CSV_PILO
__IM uint32_t | RESERVED26 [40]
CLK_DPLL_LP_Type | CLK_DPLL_LP [15]
__IM uint32_t | RESERVED27 [8]
CLK_DPLL_HP_Type | CLK_DPLL_HP [15]
__IM uint32_t | RESERVED28 [4]
__IOM uint32_t | RES_CAUSE
__IOM uint32_t | RES_CAUSE2
__IM uint32_t | RESERVED29 [3]
__OM uint32_t | RES_PXRES_CTL
__IM uint32_t | RESERVED30 [7]
__IOM uint32_t | RES_CAUSE_EXTEND
__IM uint32_t | RESERVED31 [2]
__IOM uint32_t | PWR_CBUCK_CTL
__IOM uint32_t | PWR_CBUCK_CTL2
__IM uint32_t | RESERVED32
__IOM uint32_t | PWR_CBUCK_DPSLP_CTL
__IM uint32_t | PWR_CBUCK_STATUS
__IOM uint32_t | PWR_RETLDO_CTL
__IOM uint32_t | PWR_SRAMLDO_CTL
__IM uint32_t | RESERVED33
__IOM uint32_t | PWR_MISCLDO_CTL
__IM uint32_t | RESERVED34 [311]
__IOM uint32_t | PWR_TRIM_PMU_CTL0
__IM uint32_t | RESERVED35 [963]
__IOM uint32_t | CLK_TRIM_ECO_CTL
__IM uint32_t | RESERVED36 [119]
CLK_TRIM_DPLL_LP_Type | CLK_TRIM_DPLL_LP [15]
__IM uint32_t | RESERVED37 [776]
RAM_TRIM_Type | RAM_TRIM_STRUCT
__IM uint32_t | RESERVED38 [8176]
__IOM uint32_t | WDT_CTL
__IOM uint32_t | WDT_CNT
__IOM uint32_t | WDT_MATCH
__IOM uint32_t | WDT_MATCH2
__IM uint32_t | RESERVED39 [60]
WDT_Type | WDT [4]
__IM uint32_t | RESERVED40 [832]
MCWDT_STRUCT_Type | MCWDT_STRUCT [4]
__IM uint32_t | RESERVED41 [960]
MCWDT_Type | MCWDT [4]

## Field Documentation

## ◆ RESERVED

__IM uint32_t SRSS_Type::RESERVED[64]

## ◆ CLK_DSI_SELECT

__IOM uint32_t SRSS_Type::CLK_DSI_SELECT[16]

0x00000100 Clock DSI Select Register

## ◆ CLK_OUTPUT_FAST

__IOM uint32_t SRSS_Type::CLK_OUTPUT_FAST

0x00000140 Fast Clock Output Select Register

## ◆ CLK_OUTPUT_SLOW

__IOM uint32_t SRSS_Type::CLK_OUTPUT_SLOW

0x00000144 Slow Clock Output Select Register

## ◆ CLK_CAL_CNT1

__IOM uint32_t SRSS_Type::CLK_CAL_CNT1

0x00000148 Clock Calibration Counter 1

## ◆ CLK_CAL_CNT2

__IM uint32_t SRSS_Type::CLK_CAL_CNT2

0x0000014C Clock Calibration Counter 2

## ◆ RESERVED1

__IM uint32_t SRSS_Type::RESERVED1[44]

## ◆ SRSS_INTR

__IOM uint32_t SRSS_Type::SRSS_INTR

0x00000200 SRSS Interrupt Register

## ◆ SRSS_INTR_SET

__IOM uint32_t SRSS_Type::SRSS_INTR_SET

0x00000204 SRSS Interrupt Set Register

## ◆ SRSS_INTR_MASK

__IOM uint32_t SRSS_Type::SRSS_INTR_MASK

0x00000208 SRSS Interrupt Mask Register

## ◆ SRSS_INTR_MASKED

__IM uint32_t SRSS_Type::SRSS_INTR_MASKED

0x0000020C SRSS Interrupt Masked Register

## ◆ RESERVED2

__IM uint32_t SRSS_Type::RESERVED2[60]

## ◆ SRSS_AINTR

__IOM uint32_t SRSS_Type::SRSS_AINTR

0x00000300 SRSS Additional Interrupt Register

## ◆ SRSS_AINTR_SET

__IOM uint32_t SRSS_Type::SRSS_AINTR_SET

0x00000304 SRSS Additional Interrupt Set Register

## ◆ SRSS_AINTR_MASK

__IOM uint32_t SRSS_Type::SRSS_AINTR_MASK

0x00000308 SRSS Additional Interrupt Mask Register

## ◆ SRSS_AINTR_MASKED

__IM uint32_t SRSS_Type::SRSS_AINTR_MASKED

0x0000030C SRSS Additional Interrupt Masked Register

## ◆ RESERVED3

__IM uint32_t SRSS_Type::RESERVED3[12]

## ◆ PWR_LVD_STATUS

__IM uint32_t SRSS_Type::PWR_LVD_STATUS

0x00000340 High Voltage / Low Voltage Detector (HVLVD) Status Register

## ◆ RESERVED4

__IM uint32_t SRSS_Type::RESERVED4[48]

## ◆ BOOT_DLM_CTL

__IOM uint32_t SRSS_Type::BOOT_DLM_CTL

0x00000404 Debug Control Register

## ◆ BOOT_DLM_CTL2

__IOM uint32_t SRSS_Type::BOOT_DLM_CTL2

0x00000408 Debug Control Register 2

## ◆ BOOT_DLM_STATUS

__IOM uint32_t SRSS_Type::BOOT_DLM_STATUS

0x0000040C Debug Status Register

## ◆ RES_SOFT_CTL

__IOM uint32_t SRSS_Type::RES_SOFT_CTL

0x00000410 Soft Reset Trigger Register

## ◆ RESERVED5

__IM uint32_t SRSS_Type::RESERVED5

## ◆ BOOT_STATUS

__IOM uint32_t SRSS_Type::BOOT_STATUS

0x00000418 Boot Execution Status Register

## ◆ RESERVED6

__IM uint32_t SRSS_Type::RESERVED6[5]

## ◆ BOOT_ENTRY

__IOM uint32_t SRSS_Type::BOOT_ENTRY

0x00000430 Warm Boot Entry Address

## ◆ RESERVED7

__IM uint32_t SRSS_Type::RESERVED7[3]

## ◆ DECODED_LCS_DATA

__IM uint32_t SRSS_Type::DECODED_LCS_DATA

0x00000440 Decoded Life Cycle Stage Data Register

## ◆ RESERVED8

__IM uint32_t SRSS_Type::RESERVED8[239]

## ◆ PWR_HIB_DATA

__IOM uint32_t SRSS_Type::PWR_HIB_DATA[32]

0x00000800 Hibernate Data Register

## ◆ RESERVED9

__IM uint32_t SRSS_Type::RESERVED9[8]

## ◆ PWR_HIB_WAKE_CTL

__IOM uint32_t SRSS_Type::PWR_HIB_WAKE_CTL

0x000008A0 Hibernate Wakeup Mask Register

## ◆ PWR_HIB_WAKE_CTL2

__IOM uint32_t SRSS_Type::PWR_HIB_WAKE_CTL2

0x000008A4 Hibernate Wakeup Polarity Register

## ◆ RESERVED10

__IM uint32_t SRSS_Type::RESERVED10

## ◆ PWR_HIB_WAKE_CAUSE

__IOM uint32_t SRSS_Type::PWR_HIB_WAKE_CAUSE

0x000008AC Hibernate Wakeup Cause Register

## ◆ RESERVED11

__IM uint32_t SRSS_Type::RESERVED11[25]

## ◆ TST_XRES_SECURE

__IOM uint32_t SRSS_Type::TST_XRES_SECURE

0x00000914 SECURE TEST and FIRMWARE TEST Key control register

## ◆ RESERVED12

__IM uint32_t SRSS_Type::RESERVED12[442]

## ◆ PWR_CTL

__IM uint32_t SRSS_Type::PWR_CTL

0x00001000 Power Mode Control

## ◆ PWR_CTL2

__IOM uint32_t SRSS_Type::PWR_CTL2

0x00001004 Power Mode Control 2

## ◆ PWR_HIBERNATE

__IOM uint32_t SRSS_Type::PWR_HIBERNATE

0x00001008 HIBERNATE Mode Register

## ◆ RESERVED13

__IM uint32_t SRSS_Type::RESERVED13[5]

## ◆ PWR_LVD_CTL

__IOM uint32_t SRSS_Type::PWR_LVD_CTL

0x00001020 High Voltage / Low Voltage Detector (HVLVD) Configuration Register

## ◆ RESERVED14

__IM uint32_t SRSS_Type::RESERVED14[119]

## ◆ CLK_PATH_SELECT

__IOM uint32_t SRSS_Type::CLK_PATH_SELECT[16]

0x00001200 Clock Path Select Register

## ◆ CLK_ROOT_SELECT

__IOM uint32_t SRSS_Type::CLK_ROOT_SELECT[16]

0x00001240 Clock Root Select Register

## ◆ CLK_DIRECT_SELECT

__IOM uint32_t SRSS_Type::CLK_DIRECT_SELECT[16]

0x00001280 Clock Root Direct Select Register

## ◆ RESERVED15

__IM uint32_t SRSS_Type::RESERVED15[16]

## ◆ CLK_SELECT

__IOM uint32_t SRSS_Type::CLK_SELECT

0x00001300 Clock selection register

## ◆ CLK_MF_SELECT

__IOM uint32_t SRSS_Type::CLK_MF_SELECT

0x00001304 Medium Frequency Clock Select Register

## ◆ RESERVED16

__IM uint32_t SRSS_Type::RESERVED16[2]

## ◆ CLK_ALTHF_CTL

__IOM uint32_t SRSS_Type::CLK_ALTHF_CTL[2]

0x00001310 Alternate High Frequency Clock Control Register

## ◆ RESERVED17

__IM uint32_t SRSS_Type::RESERVED17[2]

## ◆ CLK_ECO_PRESCALE

__IOM uint32_t SRSS_Type::CLK_ECO_PRESCALE

0x00001320 ECO Prescaler Configuration Register

## ◆ RESERVED18

__IM uint32_t SRSS_Type::RESERVED18[7]

## ◆ CLK_IMO_CONFIG

__IOM uint32_t SRSS_Type::CLK_IMO_CONFIG

0x00001340 IMO Configuration

## ◆ CLK_IHO_CONFIG

__IOM uint32_t SRSS_Type::CLK_IHO_CONFIG

0x00001344 IHO Configuration Register

## ◆ RESERVED19

__IM uint32_t SRSS_Type::RESERVED19[6]

## ◆ CLK_ECO_STRUCT

CLK_ECO_Type SRSS_Type::CLK_ECO_STRUCT

0x00001360 ECO Configuration

## ◆ CLK_PILO_CONFIG

__IOM uint32_t SRSS_Type::CLK_PILO_CONFIG

0x00001370 Precision ILO Configuration Register

## ◆ CLK_PILO_STATUS

__IM uint32_t SRSS_Type::CLK_PILO_STATUS

0x00001374 Precision ILO Status Register

## ◆ RESERVED20

__IM uint32_t SRSS_Type::RESERVED20[2]

## ◆ CLK_ILO_CONFIG

__IOM uint32_t SRSS_Type::CLK_ILO_CONFIG

0x00001380 ILO Configuration

## ◆ CLK_TRIM_ILO_CTL

__IOM uint32_t SRSS_Type::CLK_TRIM_ILO_CTL

0x00001384 ILO Trim Register

## ◆ RESERVED21

__IM uint32_t SRSS_Type::RESERVED21[2]

## ◆ CLK_WCO_CONFIG

__IOM uint32_t SRSS_Type::CLK_WCO_CONFIG

0x00001390 WCO Configuration Register

## ◆ CLK_WCO_STATUS

__IM uint32_t SRSS_Type::CLK_WCO_STATUS

0x00001394 WCO Status Register

## ◆ RESERVED22

__IM uint32_t SRSS_Type::RESERVED22[26]

## ◆ CSV_HF_STRUCT

CSV_HF_Type SRSS_Type::CSV_HF_STRUCT

0x00001400 Clock Supervisor (CSV) registers for Root clocks

## ◆ CSV_REF_SEL

__IOM uint32_t SRSS_Type::CSV_REF_SEL

0x00001500 Select CSV Reference clock for Active domain

## ◆ RESERVED23

__IM uint32_t SRSS_Type::RESERVED23[3]

## ◆ CSV_REF_STRUCT

CSV_REF_Type SRSS_Type::CSV_REF_STRUCT

0x00001510 CSV registers for the CSV Reference clock

## ◆ CSV_LF_REF_SEL

__IOM uint32_t SRSS_Type::CSV_LF_REF_SEL

0x00001520 Select CSV Reference clock for LF clock

## ◆ RESERVED24

__IM uint32_t SRSS_Type::RESERVED24[3]

## ◆ CSV_LF_STRUCT

CSV_LF_Type SRSS_Type::CSV_LF_STRUCT

0x00001530 CSV registers for LF clock

## ◆ CSV_PILO_REF_SEL

__IOM uint32_t SRSS_Type::CSV_PILO_REF_SEL

0x00001540 Select CSV Reference clock for PILO clock

## ◆ RESERVED25

__IM uint32_t SRSS_Type::RESERVED25[3]

## ◆ CSV_PILO

CSV_PILO_Type SRSS_Type::CSV_PILO

0x00001550 CSV registers for PILO clock

## ◆ RESERVED26

__IM uint32_t SRSS_Type::RESERVED26[40]

## ◆ CLK_DPLL_LP

CLK_DPLL_LP_Type SRSS_Type::CLK_DPLL_LP[15]

0x00001600 DPLL LP Configuration Register

## ◆ RESERVED27

__IM uint32_t SRSS_Type::RESERVED27[8]

## ◆ CLK_DPLL_HP

CLK_DPLL_HP_Type SRSS_Type::CLK_DPLL_HP[15]

0x00001800 DPLL HP Configuration Register

## ◆ RESERVED28

__IM uint32_t SRSS_Type::RESERVED28[4]

## ◆ RES_CAUSE

__IOM uint32_t SRSS_Type::RES_CAUSE

0x00001BD0 Reset Cause Observation Register

## ◆ RES_CAUSE2

__IOM uint32_t SRSS_Type::RES_CAUSE2

0x00001BD4 Reset Cause Observation Register 2

## ◆ RESERVED29

__IM uint32_t SRSS_Type::RESERVED29[3]

## ◆ RES_PXRES_CTL

__OM uint32_t SRSS_Type::RES_PXRES_CTL

0x00001BE4 Programmable XRES Control Register

## ◆ RESERVED30

__IM uint32_t SRSS_Type::RESERVED30[7]

## ◆ RES_CAUSE_EXTEND

__IOM uint32_t SRSS_Type::RES_CAUSE_EXTEND

0x00001C04 Extended Reset Cause Observation Register

## ◆ RESERVED31

__IM uint32_t SRSS_Type::RESERVED31[2]

## ◆ PWR_CBUCK_CTL

__IOM uint32_t SRSS_Type::PWR_CBUCK_CTL

0x00001C10 Core Buck Control Register

## ◆ PWR_CBUCK_CTL2

__IOM uint32_t SRSS_Type::PWR_CBUCK_CTL2

0x00001C14 Core Buck Control Register 2

## ◆ RESERVED32

__IM uint32_t SRSS_Type::RESERVED32

## ◆ PWR_CBUCK_DPSLP_CTL

__IOM uint32_t SRSS_Type::PWR_CBUCK_DPSLP_CTL

0x00001C1C Core Buck Deepsleep Control Register

## ◆ PWR_CBUCK_STATUS

__IM uint32_t SRSS_Type::PWR_CBUCK_STATUS

0x00001C20 Core Buck Status Register

## ◆ PWR_RETLDO_CTL

__IOM uint32_t SRSS_Type::PWR_RETLDO_CTL

0x00001C24 RETLDO Control Register

## ◆ PWR_SRAMLDO_CTL

__IOM uint32_t SRSS_Type::PWR_SRAMLDO_CTL

0x00001C28 SRAMLDO Control Register

## ◆ RESERVED33

__IM uint32_t SRSS_Type::RESERVED33

## ◆ PWR_MISCLDO_CTL

__IOM uint32_t SRSS_Type::PWR_MISCLDO_CTL

0x00001C30 MISCLDO Control Register

## ◆ RESERVED34

__IM uint32_t SRSS_Type::RESERVED34[311]

## ◆ PWR_TRIM_PMU_CTL0

__IOM uint32_t SRSS_Type::PWR_TRIM_PMU_CTL0

0x00002110 PMU Trim Register 0

## ◆ RESERVED35

__IM uint32_t SRSS_Type::RESERVED35[963]

## ◆ CLK_TRIM_ECO_CTL

__IOM uint32_t SRSS_Type::CLK_TRIM_ECO_CTL

0x00003020 ECO Trim Register

## ◆ RESERVED36

__IM uint32_t SRSS_Type::RESERVED36[119]

## ◆ CLK_TRIM_DPLL_LP

CLK_TRIM_DPLL_LP_Type SRSS_Type::CLK_TRIM_DPLL_LP[15]

0x00003200 DPLL LP Trims

## ◆ RESERVED37

__IM uint32_t SRSS_Type::RESERVED37[776]

## ◆ RAM_TRIM_STRUCT

RAM_TRIM_Type SRSS_Type::RAM_TRIM_STRUCT

0x00004000 SRAM Trim registers

## ◆ RESERVED38

__IM uint32_t SRSS_Type::RESERVED38[8176]

## ◆ WDT_CTL

__IOM uint32_t SRSS_Type::WDT_CTL

0x0000C000 Watchdog Counter Control Register (Type A)

## ◆ WDT_CNT

__IOM uint32_t SRSS_Type::WDT_CNT

0x0000C004 Watchdog Counter Count Register (Type A)

## ◆ WDT_MATCH

__IOM uint32_t SRSS_Type::WDT_MATCH

0x0000C008 Watchdog Counter Match Register (Type A)

## ◆ WDT_MATCH2

__IOM uint32_t SRSS_Type::WDT_MATCH2

0x0000C00C Watchdog Counter Match Register 2 (Type A)

## ◆ RESERVED39

__IM uint32_t SRSS_Type::RESERVED39[60]

## ◆ WDT

WDT_Type SRSS_Type::WDT[4]

0x0000C100 Watchdog Timer (Type B)

## ◆ RESERVED40

__IM uint32_t SRSS_Type::RESERVED40[832]

## ◆ MCWDT_STRUCT

MCWDT_STRUCT_Type SRSS_Type::MCWDT_STRUCT[4]

0x0000D000 Multi-Counter Watchdog Timer (Type A)

## ◆ RESERVED41

__IM uint32_t SRSS_Type::RESERVED41[960]

## ◆ MCWDT

MCWDT_Type SRSS_Type::MCWDT[4]

0x0000E000 Multi-Counter Watchdog Timer (Type B)