PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Enumerations
Enumerated Types
PDL API Reference » AUTONOMOUS ANALOG (Autonomous Analog Block) » CT DAC (Continuous Time Digital to Analog Converter)

## General Description

## Enumerations
enum | cy_en_autanalog_dac_topo_cfg_t { CY_AUTANALOG_DAC_TOPO_DIRECT = 0UL , CY_AUTANALOG_DAC_TOPO_DIRECT_WITH_TRACK_CAP = 1UL , CY_AUTANALOG_DAC_TOPO_DIRECT_WITH_TRACK_HOLD_CAP = 2UL , CY_AUTANALOG_DAC_TOPO_BUFFERED_INTERNAL = 3UL , CY_AUTANALOG_DAC_TOPO_BUFFERED_EXTERNAL = 4UL }
| Defines the connection topology for the DAC, for more details, refer to the device Architecture Technical Reference Manual. More...
enum | cy_en_autanalog_dac_vref_sel_t { CY_AUTANALOG_DAC_VREF_MUX_OUT = 0UL , CY_AUTANALOG_DAC_VREF_VDDA = 1UL }
| Defines the source of the reference voltage for the DAC, for more details, refer to the device Architecture Technical Reference Manual. More...
enum | cy_en_autanalog_dac_ref_buf_pwr_t { CY_AUTANALOG_DAC_REF_BUF_PWR_OFF = 0UL , CY_AUTANALOG_DAC_REF_BUF_PWR_ULTRA_LOW = 1UL , CY_AUTANALOG_DAC_REF_BUF_PWR_ULTRA_LOW_RAIL = 2UL , CY_AUTANALOG_DAC_REF_BUF_PWR_LOW_RAIL = 4UL , CY_AUTANALOG_DAC_REF_BUF_PWR_MEDIUM_RAIL = 6UL , CY_AUTANALOG_DAC_REF_BUF_PWR_HIGH = 7UL , CY_AUTANALOG_DAC_REF_BUF_PWR_HIGH_RAIL = 8UL , CY_AUTANALOG_DAC_REF_BUF_PWR_ULTRA_HIGH_RAIL = 10UL }
| Defines Power mode for the reference buffer. More...
enum | cy_en_autanalog_dac_out_buf_pwr_t { CY_AUTANALOG_DAC_OUT_BUF_PWR_OFF = 0UL , CY_AUTANALOG_DAC_OUT_BUF_PWR_ULTRA_LOW = 1UL , CY_AUTANALOG_DAC_OUT_BUF_PWR_ULTRA_LOW_RAIL = 2UL , CY_AUTANALOG_DAC_OUT_BUF_PWR_LOW_RAIL = 4UL , CY_AUTANALOG_DAC_OUT_BUF_PWR_MEDIUM_RAIL = 6UL , CY_AUTANALOG_DAC_OUT_BUF_PWR_HIGH_RAIL = 8UL , CY_AUTANALOG_DAC_OUT_BUF_PWR_ULTRA_HIGH_RAIL = 10UL }
| Defines Power mode for the output buffer. More...
enum | cy_en_autanalog_dac_vref_mux_t { CY_AUTANALOG_DAC_VREF_MUX_VBGR = 0UL , CY_AUTANALOG_DAC_VREF_MUX_CTB0_OA0 = 1UL , CY_AUTANALOG_DAC_VREF_MUX_CTB0_OA1 = 2UL , CY_AUTANALOG_DAC_VREF_MUX_CTB1_OA0 = 3UL , CY_AUTANALOG_DAC_VREF_MUX_CTB1_OA1 = 4UL , CY_AUTANALOG_DAC_VREF_MUX_PRB_OUT0 = 6UL , CY_AUTANALOG_DAC_VREF_MUX_PRB_OUT1 = 7UL }
| Defines the multiplexed reference voltage to be used for the DAC, for more details, refer to the device Architecture Technical Reference Manual. More...
enum | cy_en_autanalog_dac_oper_mode_t { CY_AUTANALOG_DAC_LUT_OS_ONE_QUAD = 0UL , CY_AUTANALOG_DAC_LUT_OS_TWO_QUAD = 1UL , CY_AUTANALOG_DAC_LUT_OS_FOUR_QUAD = 2UL , CY_AUTANALOG_DAC_LUT_CONT_ONE_QUAD = 3UL , CY_AUTANALOG_DAC_LUT_CONT_TWO_QUAD = 4UL , CY_AUTANALOG_DAC_LUT_CONT_FOUR_QUAD = 5UL , CY_AUTANALOG_DAC_WAVEFORM_MODE_ADDR = 6UL , CY_AUTANALOG_DAC_WAVEFORM_MODE_DATA = 7UL }
| Defines the operating mode of the DAC, refer to Operating Mode. More...
enum | cy_en_autanalog_dac_step_sel_t { CY_AUTANALOG_DAC_STEP_SEL_DISABLED = 0UL , CY_AUTANALOG_DAC_STEP_SEL_0 = 1UL , CY_AUTANALOG_DAC_STEP_SEL_1 = 2UL , CY_AUTANALOG_DAC_STEP_SEL_2 = 3UL }
| The step selector for the DAC, defines the selected step movement in the LUT. More...
enum | cy_en_autanalog_dac_stat_sel_t { CY_AUTANALOG_DAC_STATUS_SEL_DISABLED = 0UL , CY_AUTANALOG_DAC_STATUS_SEL_0 = 1UL , CY_AUTANALOG_DAC_STATUS_SEL_1 = 2UL , CY_AUTANALOG_DAC_STATUS_SEL_2 = 3UL }
| The DAC range status selector, defines the selected range conditions for the DAC output value. More...
enum | cy_en_autanalog_dac_out_drive_mode_t { CY_AUTANALOG_DAC_OUT_DRIVE_MODE_EN = 0UL , CY_AUTANALOG_DAC_OUT_DRIVE_MODE_HIZ = 1UL , CY_AUTANALOG_DAC_OUT_DRIVE_MODE_VREF = 2UL }
| Defines the drive mode for the DAC output, for more details, refer to the device Architecture Technical Reference Manual. More...
enum | cy_en_autanalog_dac_limit_t { CY_AUTANALOG_DAC_CH_LIMIT_BELOW = 0UL , CY_AUTANALOG_DAC_CH_LIMIT_INSIDE = 1UL , CY_AUTANALOG_DAC_CH_LIMIT_ABOVE = 2UL , CY_AUTANALOG_DAC_CH_LIMIT_OUTSIDE = 3UL }
| Defines the range detection conditions for the DAC output, refer to cy_stc_autanalog_dac_ch_limit_t. More...
enum | cy_en_autanalog_stt_dac_dir_t { CY_AUTANALOG_DAC_DIRECTION_DISABLED = 0UL , CY_AUTANALOG_DAC_DIRECTION_FORWARD = 1UL , CY_AUTANALOG_DAC_DIRECTION_REVERSE = 2UL }
| Defines the direction of movement in the LUT or the increment/decrement of the DAC value using the State Transition table, refer to cy_stc_autanalog_stt_dac_t. More...

## Enumeration Type Documentation

## ◆ cy_en_autanalog_dac_topo_cfg_t

enum cy_en_autanalog_dac_topo_cfg_t

Defines the connection topology for the DAC, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_TOPO_DIRECT | The DAC drives the output directly.
CY_AUTANALOG_DAC_TOPO_DIRECT_WITH_TRACK_CAP | The DAC drives the output directly with a Ctrack capacitor at the output.
CY_AUTANALOG_DAC_TOPO_DIRECT_WITH_TRACK_HOLD_CAP | The DAC drives output directly with Ctrack and Chold capacitors at the output.
CY_AUTANALOG_DAC_TOPO_BUFFERED_INTERNAL | The output of the DAC is buffered (for internal connections only)
CY_AUTANALOG_DAC_TOPO_BUFFERED_EXTERNAL | The output of the DAC is buffered for internal or external connections.

## ◆ cy_en_autanalog_dac_vref_sel_t

enum cy_en_autanalog_dac_vref_sel_t

Defines the source of the reference voltage for the DAC, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_VREF_MUX_OUT | The DAC reference is driven by the reference multiplexer, see cy_en_autanalog_dac_vref_mux_t. This option requires that cy_stc_autanalog_dac_sta_t::refBuffPwr be set to a value other than OFF
CY_AUTANALOG_DAC_VREF_VDDA | The DAC reference is driven directly from the Vdda. As this path does not use the DAC reference buffer, cy_stc_autanalog_dac_sta_t::refBuffPwr should be set to OFF

## ◆ cy_en_autanalog_dac_ref_buf_pwr_t

enum cy_en_autanalog_dac_ref_buf_pwr_t

Defines Power mode for the reference buffer.

Each power setting consumes different levels of the current and supports a different input range and gain bandwidth. The charge pump is used to increase the input range to the rails.
For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_REF_BUF_PWR_OFF | The power mode for the buffer is OFF, the buffer is disabled.
CY_AUTANALOG_DAC_REF_BUF_PWR_ULTRA_LOW | The power mode for the buffer is ULTRA LOW, the charge pump is OFF, the buffer quiescent current is 15uA, the gain bandwidth is 30kHz;.
CY_AUTANALOG_DAC_REF_BUF_PWR_ULTRA_LOW_RAIL | The power mode for the buffer is ULTRA LOW, the charge pump is ON, the buffer quiescent current is 35uA, the gain bandwidth is 30kHz;.
CY_AUTANALOG_DAC_REF_BUF_PWR_LOW_RAIL | The power mode for the buffer is LOW, the charge pump is ON, the buffer quiescent current is 150uA, the gain bandwidth is 350kHz;.
CY_AUTANALOG_DAC_REF_BUF_PWR_MEDIUM_RAIL | The power mode for the buffer is MEDIUM, the charge pump is ON, the buffer quiescent current is 200uA, the gain bandwidth is 700kHz;.
CY_AUTANALOG_DAC_REF_BUF_PWR_HIGH | The power mode for the buffer is HIGH, the charge pump is OFF, the buffer quiescent current is 400uA, the gain bandwidth is 1.75MHz;. Note This is the recommended power mode for the DAC reference buffer when the DAC reference is 0.9V or less.
CY_AUTANALOG_DAC_REF_BUF_PWR_HIGH_RAIL | The power mode for the buffer is HIGH, the charge pump is ON, the buffer quiescent current is 600uA, the gain bandwidth is 1.75MHz;.
CY_AUTANALOG_DAC_REF_BUF_PWR_ULTRA_HIGH_RAIL | The power mode for the buffer is ULTRA HIGH, the charge pump is ON, the buffer quiescent current is 800uA, the gain bandwidth is 2.8MHz;.

## ◆ cy_en_autanalog_dac_out_buf_pwr_t

enum cy_en_autanalog_dac_out_buf_pwr_t

Defines Power mode for the output buffer.

Each power setting consumes different levels of the current and supports a different input range and gain bandwidth. The charge pump is used to increase the input range to the rails.
For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_OUT_BUF_PWR_OFF | The power mode for the buffer is OFF, the buffer is disabled.
CY_AUTANALOG_DAC_OUT_BUF_PWR_ULTRA_LOW | The power mode for the buffer is ULTRA LOW, the charge pump is OFF, the buffer quiescent current is 15uA, the output drive capability is 10uA. If cy_stc_autanalog_dac_sta_t::outBuffPwr is INTERNAL the gain bandwidth is 30kHz; If cy_stc_autanalog_dac_sta_t::outBuffPwr is EXTERNAL the gain bandwidth is 100kHz;
CY_AUTANALOG_DAC_OUT_BUF_PWR_ULTRA_LOW_RAIL | The power mode for the buffer is ULTRA LOW, the charge pump is ON, the buffer quiescent current is 35uA, the output drive capability is 10uA. If cy_stc_autanalog_dac_sta_t::outBuffPwr is INTERNAL the gain bandwidth is 30kHz; If cy_stc_autanalog_dac_sta_t::outBuffPwr is EXTERNAL the gain bandwidth is 100kHz;
CY_AUTANALOG_DAC_OUT_BUF_PWR_LOW_RAIL | The power mode for the buffer is LOW, the charge pump is ON, the buffer quiescent current is 150uA, the output drive capability is 100uA. If cy_stc_autanalog_dac_sta_t::outBuffPwr is INTERNAL the gain bandwidth is 350kHz; If cy_stc_autanalog_dac_sta_t::outBuffPwr is EXTERNAL the gain bandwidth is 1.2MHz;
CY_AUTANALOG_DAC_OUT_BUF_PWR_MEDIUM_RAIL | The power mode for the buffer is MEDIUM, the charge pump is ON, the buffer quiescent current is 200uA, the output drive capability is 1mA. If cy_stc_autanalog_dac_sta_t::outBuffPwr is INTERNAL the gain bandwidth is 700kHz; If cy_stc_autanalog_dac_sta_t::outBuffPwr is EXTERNAL the gain bandwidth is 2.4MHz;
CY_AUTANALOG_DAC_OUT_BUF_PWR_HIGH_RAIL | The power mode for the buffer is HIGH, the charge pump is ON, the buffer quiescent current is 600uA, the output drive capability is 1mA. If cy_stc_autanalog_dac_sta_t::outBuffPwr is INTERNAL the gain bandwidth is 1.75MHz; If cy_stc_autanalog_dac_sta_t::outBuffPwr is EXTERNAL the gain bandwidth is 6MHz;
CY_AUTANALOG_DAC_OUT_BUF_PWR_ULTRA_HIGH_RAIL | The power mode for the buffer is ULTRA HIGH, the charge pump is ON, the buffer quiescent current is 800uA, the output drive capability is 10mA. If cy_stc_autanalog_dac_sta_t::outBuffPwr is INTERNAL the gain bandwidth is 2.8MHz; If cy_stc_autanalog_dac_sta_t::outBuffPwr is EXTERNAL the gain bandwidth is 7.5MHz;

## ◆ cy_en_autanalog_dac_vref_mux_t

enum cy_en_autanalog_dac_vref_mux_t

Defines the multiplexed reference voltage to be used for the DAC, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_VREF_MUX_VBGR | The DAC reference is VBGR.
CY_AUTANALOG_DAC_VREF_MUX_CTB0_OA0 | The DAC reference is driven by the Opamp0 output in the CTB0.
CY_AUTANALOG_DAC_VREF_MUX_CTB0_OA1 | The DAC reference is driven by the Opamp1 output in the CTB0.
CY_AUTANALOG_DAC_VREF_MUX_CTB1_OA0 | The DAC reference is driven by the Opamp0 output in the CTB1.
CY_AUTANALOG_DAC_VREF_MUX_CTB1_OA1 | The DAC reference is driven by the Opamp1 output in the CTB1.
CY_AUTANALOG_DAC_VREF_MUX_PRB_OUT0 | The DAC reference is Vref0 from the PRB0.
CY_AUTANALOG_DAC_VREF_MUX_PRB_OUT1 | The DAC reference is Vref1 from the PRB1.

## ◆ cy_en_autanalog_dac_oper_mode_t

enum cy_en_autanalog_dac_oper_mode_t

Defines the operating mode of the DAC, refer to Operating Mode.

For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_LUT_OS_ONE_QUAD | The LUT mode is One Shot One Quadrant.
CY_AUTANALOG_DAC_LUT_OS_TWO_QUAD | The LUT mode is One Shot Two Quadrant.
CY_AUTANALOG_DAC_LUT_OS_FOUR_QUAD | The LUT mode is One Shot Four Quadrant.
CY_AUTANALOG_DAC_LUT_CONT_ONE_QUAD | The LUT mode is Continuous One Quadrant.
CY_AUTANALOG_DAC_LUT_CONT_TWO_QUAD | The LUT mode is Continuous Two Quadrant.
CY_AUTANALOG_DAC_LUT_CONT_FOUR_QUAD | The LUT mode is Continuous Four Quadrant.
CY_AUTANALOG_DAC_WAVEFORM_MODE_ADDR | The LUT operates in Address mode.
CY_AUTANALOG_DAC_WAVEFORM_MODE_DATA | The LUT operates in Data mode.

## ◆ cy_en_autanalog_dac_step_sel_t

enum cy_en_autanalog_dac_step_sel_t

The step selector for the DAC, defines the selected step movement in the LUT.

For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_STEP_SEL_DISABLED | The selector is not used, the step value is 1 by default.
CY_AUTANALOG_DAC_STEP_SEL_0 | The step value stored in the array cy_stc_autanalog_dac_sta_t::stepVal at index zero is used.
CY_AUTANALOG_DAC_STEP_SEL_1 | The step value stored in the array cy_stc_autanalog_dac_sta_t::stepVal at index one is used.
CY_AUTANALOG_DAC_STEP_SEL_2 | The step value stored in the array cy_stc_autanalog_dac_sta_t::stepVal at index two is used.

## ◆ cy_en_autanalog_dac_stat_sel_t

enum cy_en_autanalog_dac_stat_sel_t

The DAC range status selector, defines the selected range conditions for the DAC output value.

For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_STATUS_SEL_DISABLED | The selector is not used, the DAC output is not validated for compliance with the range conditions.
CY_AUTANALOG_DAC_STATUS_SEL_0 | The DAC output range stored in the array cy_stc_autanalog_dac_sta_t::chLimitCfg at index zero is used for validation.
CY_AUTANALOG_DAC_STATUS_SEL_1 | The DAC output range stored in the array cy_stc_autanalog_dac_sta_t::chLimitCfg at index one is used for validation.
CY_AUTANALOG_DAC_STATUS_SEL_2 | The DAC output range stored in the array cy_stc_autanalog_dac_sta_t::chLimitCfg at index two is used for validation.

## ◆ cy_en_autanalog_dac_out_drive_mode_t

enum cy_en_autanalog_dac_out_drive_mode_t

Defines the drive mode for the DAC output, for more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_OUT_DRIVE_MODE_EN | The DAC output is enabled (outputs appropriate value)
CY_AUTANALOG_DAC_OUT_DRIVE_MODE_HIZ | The DAC output is disabled (output is tri-state)
CY_AUTANALOG_DAC_OUT_DRIVE_MODE_VREF | The DAC output is disabled (output is Vssa or Vref, depends on parameter cy_stc_autanalog_dac_sta_t::bottomSel)

## ◆ cy_en_autanalog_dac_limit_t

enum cy_en_autanalog_dac_limit_t

Defines the range detection conditions for the DAC output, refer to cy_stc_autanalog_dac_ch_limit_t.

For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_CH_LIMIT_BELOW | The DAC value must satisfy the following: Value < cy_stc_autanalog_dac_ch_limit_t::low.
CY_AUTANALOG_DAC_CH_LIMIT_INSIDE | The DAC value must satisfy the following: (cy_stc_autanalog_dac_ch_limit_t::low <= Value) AND (Value < cy_stc_autanalog_dac_ch_limit_t::high)
CY_AUTANALOG_DAC_CH_LIMIT_ABOVE | The DAC value must satisfy the following: Value > cy_stc_autanalog_dac_ch_limit_t::high.
CY_AUTANALOG_DAC_CH_LIMIT_OUTSIDE | The DAC value must satisfy the following: (Value < cy_stc_autanalog_dac_ch_limit_t::low) OR (Value >= cy_stc_autanalog_dac_ch_limit_t::high)

## ◆ cy_en_autanalog_stt_dac_dir_t

enum cy_en_autanalog_stt_dac_dir_t

Defines the direction of movement in the LUT or the increment/decrement of the DAC value using the State Transition table, refer to cy_stc_autanalog_stt_dac_t.

For more details, refer to the device Architecture Technical Reference Manual.

Enumerator
CY_AUTANALOG_DAC_DIRECTION_DISABLED | Direction is NOT selected.
CY_AUTANALOG_DAC_DIRECTION_FORWARD | Forward/Increment.
CY_AUTANALOG_DAC_DIRECTION_REVERSE | Backward/Decrement.