PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

API Reference
Clock Path Source
PDL API Reference » SysClk (System Clock)

## General Description

Clock paths are a series of multiplexers that allow a source clock to drive multiple clocking resources down the chain.

These paths are used for active domain clocks that are not operational during chip Deep Sleep, hibernate and off modes. Illustrated below is a diagram of the clock paths for the PSoC 63 series, showing the first three clock paths. The source clocks for these paths are highlighted in the red box.

- IMO: 8 MHz Internal Main Oscillator (Default)
- EXTCLK: External clock (signal brought in through dedicated pins)
- ECO: External Crystal Oscillator (requires external crystal on dedicated pins)
- ALTHF: Select on-chip signals (e.g. group_ble_clk)
- Digital Signal (DSI): Digital signal from a UDB source

Some clock paths such as path 0 and path 1 have additional resources that can be utilized to provide a higher frequency clock. For example, path 0 source clock can be used as the reference clock for the FLL and path 1 source clock can be used as the reference clock for the PLL.

Note
  The PDL driver cannot configure a clock path to use Digital Signal Interconnect (DSI) outputs as sources. This must be done through DSI configuration tool such as PSoC Creator.

## API Reference
| Functions
| Enumerated Types