PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
SDHC_CORE_Type Struct Reference

## Description

MMIO for Synopsys Mobile Storage Host Controller IP (SDHC_CORE)

## Data Fields
__IOM uint32_t | SDMASA_R
__IOM uint16_t | BLOCKSIZE_R
__IOM uint16_t | BLOCKCOUNT_R
__IOM uint32_t | ARGUMENT_R
__IOM uint16_t | XFER_MODE_R
__IOM uint16_t | CMD_R
__IM uint32_t | RESP01_R
__IM uint32_t | RESP23_R
__IM uint32_t | RESP45_R
__IM uint32_t | RESP67_R
__IOM uint32_t | BUF_DATA_R
__IM uint32_t | PSTATE_REG
__IOM uint8_t | HOST_CTRL1_R
__IOM uint8_t | PWR_CTRL_R
__IOM uint8_t | BGAP_CTRL_R
__IOM uint8_t | WUP_CTRL_R
__IOM uint16_t | CLK_CTRL_R
__IOM uint8_t | TOUT_CTRL_R
__IOM uint8_t | SW_RST_R
__IOM uint16_t | NORMAL_INT_STAT_R
__IOM uint16_t | ERROR_INT_STAT_R
__IOM uint16_t | NORMAL_INT_STAT_EN_R
__IOM uint16_t | ERROR_INT_STAT_EN_R
__IOM uint16_t | NORMAL_INT_SIGNAL_EN_R
__IOM uint16_t | ERROR_INT_SIGNAL_EN_R
__IM uint16_t | AUTO_CMD_STAT_R
__IOM uint16_t | HOST_CTRL2_R
__IM uint32_t | CAPABILITIES1_R
__IM uint32_t | CAPABILITIES2_R
__IM uint32_t | CURR_CAPABILITIES1_R
__IM uint32_t | CURR_CAPABILITIES2_R
__OM uint16_t | FORCE_AUTO_CMD_STAT_R
__IOM uint16_t | FORCE_ERROR_INT_STAT_R
__IM uint8_t | ADMA_ERR_STAT_R
__IM uint8_t | RESERVED [3]
__IOM uint32_t | ADMA_SA_LOW_R
__IM uint32_t | RESERVED1 [7]
__IOM uint32_t | ADMA_ID_LOW_R
__IM uint16_t | RESERVED2 [65]
__IM uint16_t | HOST_CNTRL_VERS_R
__IM uint32_t | RESERVED3 [32]
__IM uint32_t | CQVER
__IM uint32_t | CQCAP
__IOM uint32_t | CQCFG
__IOM uint32_t | CQCTL
__IOM uint32_t | CQIS
__IOM uint32_t | CQISE
__IOM uint32_t | CQISGE
__IOM uint32_t | CQIC
__IOM uint32_t | CQTDLBA
__IM uint32_t | RESERVED4
__IOM uint32_t | CQTDBR
__IOM uint32_t | CQTCN
__IM uint32_t | CQDQS
__IM uint32_t | CQDPT
__IOM uint32_t | CQTCLR
__IM uint32_t | RESERVED5
__IOM uint32_t | CQSSC1
__IOM uint32_t | CQSSC2
__IM uint32_t | CQCRDCT
__IM uint32_t | RESERVED6
__IOM uint32_t | CQRMEM
__IM uint32_t | CQTERRI
__IM uint32_t | CQCRI
__IM uint32_t | CQCRA
__IM uint32_t | RESERVED7 [200]
__IM uint32_t | MSHC_VER_ID_R
__IM uint32_t | MSHC_VER_TYPE_R
__IOM uint8_t | MSHC_CTRL_R
__IM uint8_t | RESERVED8 [7]
__IOM uint8_t | MBIU_CTRL_R
__IM uint8_t | RESERVED9 [27]
__IOM uint16_t | EMMC_CTRL_R
__IOM uint16_t | BOOT_CTRL_R
__IM uint32_t | GP_IN_R
__IOM uint32_t | GP_OUT_R
__IM uint32_t | RESERVED10 [690]

## Field Documentation

## ◆ SDMASA_R

__IOM uint32_t SDHC_CORE_Type::SDMASA_R

0x00000000 SDMA System Address register

## ◆ BLOCKSIZE_R

__IOM uint16_t SDHC_CORE_Type::BLOCKSIZE_R

0x00000004 Block Size register

## ◆ BLOCKCOUNT_R

__IOM uint16_t SDHC_CORE_Type::BLOCKCOUNT_R

0x00000006 16-bit Block Count register

## ◆ ARGUMENT_R

__IOM uint32_t SDHC_CORE_Type::ARGUMENT_R

0x00000008 Argument register

## ◆ XFER_MODE_R

__IOM uint16_t SDHC_CORE_Type::XFER_MODE_R

0x0000000C Transfer Mode register

## ◆ CMD_R

__IOM uint16_t SDHC_CORE_Type::CMD_R

0x0000000E Command register

## ◆ RESP01_R

__IM uint32_t SDHC_CORE_Type::RESP01_R

0x00000010 Response Register 0/1

## ◆ RESP23_R

__IM uint32_t SDHC_CORE_Type::RESP23_R

0x00000014 Response Register 2/3

## ◆ RESP45_R

__IM uint32_t SDHC_CORE_Type::RESP45_R

0x00000018 Response Register 4/5

## ◆ RESP67_R

__IM uint32_t SDHC_CORE_Type::RESP67_R

0x0000001C Response Register 6/7

## ◆ BUF_DATA_R

__IOM uint32_t SDHC_CORE_Type::BUF_DATA_R

0x00000020 Buffer Data Port Register

## ◆ PSTATE_REG

__IM uint32_t SDHC_CORE_Type::PSTATE_REG

0x00000024 Present State Register

## ◆ HOST_CTRL1_R

__IOM uint8_t SDHC_CORE_Type::HOST_CTRL1_R

0x00000028 Host Control 1 Register

## ◆ PWR_CTRL_R

__IOM uint8_t SDHC_CORE_Type::PWR_CTRL_R

0x00000029 Power Control Register

## ◆ BGAP_CTRL_R

__IOM uint8_t SDHC_CORE_Type::BGAP_CTRL_R

0x0000002A Block Gap Control Register

## ◆ WUP_CTRL_R

__IOM uint8_t SDHC_CORE_Type::WUP_CTRL_R

0x0000002B Wakeup Control Register

## ◆ CLK_CTRL_R

__IOM uint16_t SDHC_CORE_Type::CLK_CTRL_R

0x0000002C Clock Control Register

## ◆ TOUT_CTRL_R

__IOM uint8_t SDHC_CORE_Type::TOUT_CTRL_R

0x0000002E Timeout Control Register

## ◆ SW_RST_R

__IOM uint8_t SDHC_CORE_Type::SW_RST_R

0x0000002F Software Reset Register

## ◆ NORMAL_INT_STAT_R

__IOM uint16_t SDHC_CORE_Type::NORMAL_INT_STAT_R

0x00000030 Normal Interrupt Status Register

## ◆ ERROR_INT_STAT_R

__IOM uint16_t SDHC_CORE_Type::ERROR_INT_STAT_R

0x00000032 Error Interrupt Status Register

## ◆ NORMAL_INT_STAT_EN_R

__IOM uint16_t SDHC_CORE_Type::NORMAL_INT_STAT_EN_R

0x00000034 Normal Interrupt Status Enable Register

## ◆ ERROR_INT_STAT_EN_R

__IOM uint16_t SDHC_CORE_Type::ERROR_INT_STAT_EN_R

0x00000036 Error Interrupt Status Enable Register

## ◆ NORMAL_INT_SIGNAL_EN_R

__IOM uint16_t SDHC_CORE_Type::NORMAL_INT_SIGNAL_EN_R

0x00000038 Normal Interrupt Signal Enable Register

## ◆ ERROR_INT_SIGNAL_EN_R

__IOM uint16_t SDHC_CORE_Type::ERROR_INT_SIGNAL_EN_R

0x0000003A Error Interrupt Signal Enable Register

## ◆ AUTO_CMD_STAT_R

__IM uint16_t SDHC_CORE_Type::AUTO_CMD_STAT_R

0x0000003C Auto CMD Status Register

## ◆ HOST_CTRL2_R

__IOM uint16_t SDHC_CORE_Type::HOST_CTRL2_R

0x0000003E Host Control 2 Register

## ◆ CAPABILITIES1_R

__IM uint32_t SDHC_CORE_Type::CAPABILITIES1_R

0x00000040 Capabilities 1 Register - 0 to 31

## ◆ CAPABILITIES2_R

__IM uint32_t SDHC_CORE_Type::CAPABILITIES2_R

0x00000044 Capabilities Register - 32 to 63

## ◆ CURR_CAPABILITIES1_R

__IM uint32_t SDHC_CORE_Type::CURR_CAPABILITIES1_R

0x00000048 Current Capabilities Register - 0 to 31

## ◆ CURR_CAPABILITIES2_R

__IM uint32_t SDHC_CORE_Type::CURR_CAPABILITIES2_R

0x0000004C Maximum Current Capabilities Register - 32 to 63

## ◆ FORCE_AUTO_CMD_STAT_R

__OM uint16_t SDHC_CORE_Type::FORCE_AUTO_CMD_STAT_R

0x00000050 Force Event Register for Auto CMD Error Status register

## ◆ FORCE_ERROR_INT_STAT_R

__IOM uint16_t SDHC_CORE_Type::FORCE_ERROR_INT_STAT_R

0x00000052 Force Event Register for Error Interrupt Status

## ◆ ADMA_ERR_STAT_R

__IM uint8_t SDHC_CORE_Type::ADMA_ERR_STAT_R

0x00000054 ADMA Error Status Register

## ◆ RESERVED

__IM uint8_t SDHC_CORE_Type::RESERVED[3]

## ◆ ADMA_SA_LOW_R

__IOM uint32_t SDHC_CORE_Type::ADMA_SA_LOW_R

0x00000058 ADMA System Address Register - Low

## ◆ RESERVED1

__IM uint32_t SDHC_CORE_Type::RESERVED1[7]

## ◆ ADMA_ID_LOW_R

__IOM uint32_t SDHC_CORE_Type::ADMA_ID_LOW_R

0x00000078 ADMA3 Integrated Descriptor Address Register - Low

## ◆ RESERVED2

__IM uint16_t SDHC_CORE_Type::RESERVED2[65]

## ◆ HOST_CNTRL_VERS_R

__IM uint16_t SDHC_CORE_Type::HOST_CNTRL_VERS_R

0x000000FE Host Controller Version

## ◆ RESERVED3

__IM uint32_t SDHC_CORE_Type::RESERVED3[32]

## ◆ CQVER

__IM uint32_t SDHC_CORE_Type::CQVER

0x00000180 Command Queuing Version register

## ◆ CQCAP

__IM uint32_t SDHC_CORE_Type::CQCAP

0x00000184 Command Queuing Capabilities register

## ◆ CQCFG

__IOM uint32_t SDHC_CORE_Type::CQCFG

0x00000188 Command Queuing Configuration register

## ◆ CQCTL

__IOM uint32_t SDHC_CORE_Type::CQCTL

0x0000018C Command Queuing Control register

## ◆ CQIS

__IOM uint32_t SDHC_CORE_Type::CQIS

0x00000190 Command Queuing Interrupt Status register

## ◆ CQISE

__IOM uint32_t SDHC_CORE_Type::CQISE

0x00000194 Command Queuing Interrupt Status Enable register

## ◆ CQISGE

__IOM uint32_t SDHC_CORE_Type::CQISGE

0x00000198 Command Queuing Interrupt signal enable register

## ◆ CQIC

__IOM uint32_t SDHC_CORE_Type::CQIC

0x0000019C Command Queuing Interrupt Coalescing register

## ◆ CQTDLBA

__IOM uint32_t SDHC_CORE_Type::CQTDLBA

0x000001A0 Command Queuing Task Descriptor List Base Address register

## ◆ RESERVED4

__IM uint32_t SDHC_CORE_Type::RESERVED4

## ◆ CQTDBR

__IOM uint32_t SDHC_CORE_Type::CQTDBR

0x000001A8 Command Queuing DoorBell register

## ◆ CQTCN

__IOM uint32_t SDHC_CORE_Type::CQTCN

0x000001AC Command Queuing TaskClear Notification register

## ◆ CQDQS

__IM uint32_t SDHC_CORE_Type::CQDQS

0x000001B0 Device queue status register

## ◆ CQDPT

__IM uint32_t SDHC_CORE_Type::CQDPT

0x000001B4 Device pending tasks register

## ◆ CQTCLR

__IOM uint32_t SDHC_CORE_Type::CQTCLR

0x000001B8 Command Queuing DoorBell register

## ◆ RESERVED5

__IM uint32_t SDHC_CORE_Type::RESERVED5

## ◆ CQSSC1

__IOM uint32_t SDHC_CORE_Type::CQSSC1

0x000001C0 CQ Send Status Configuration 1 register

## ◆ CQSSC2

__IOM uint32_t SDHC_CORE_Type::CQSSC2

0x000001C4 CQ Send Status Configuration 2 register

## ◆ CQCRDCT

__IM uint32_t SDHC_CORE_Type::CQCRDCT

0x000001C8 Command response for direct command register

## ◆ RESERVED6

__IM uint32_t SDHC_CORE_Type::RESERVED6

## ◆ CQRMEM

__IOM uint32_t SDHC_CORE_Type::CQRMEM

0x000001D0 Command response mode error mask register

## ◆ CQTERRI

__IM uint32_t SDHC_CORE_Type::CQTERRI

0x000001D4 CQ Task Error Information register

## ◆ CQCRI

__IM uint32_t SDHC_CORE_Type::CQCRI

0x000001D8 CQ Command response index

## ◆ CQCRA

__IM uint32_t SDHC_CORE_Type::CQCRA

0x000001DC CQ Command response argument register

## ◆ RESERVED7

__IM uint32_t SDHC_CORE_Type::RESERVED7[200]

## ◆ MSHC_VER_ID_R

__IM uint32_t SDHC_CORE_Type::MSHC_VER_ID_R

0x00000500 MSHC version

## ◆ MSHC_VER_TYPE_R

__IM uint32_t SDHC_CORE_Type::MSHC_VER_TYPE_R

0x00000504 MSHC version type

## ◆ MSHC_CTRL_R

__IOM uint8_t SDHC_CORE_Type::MSHC_CTRL_R

0x00000508 MSHC Control register

## ◆ RESERVED8

__IM uint8_t SDHC_CORE_Type::RESERVED8[7]

## ◆ MBIU_CTRL_R

__IOM uint8_t SDHC_CORE_Type::MBIU_CTRL_R

0x00000510 MBIU Control register

## ◆ RESERVED9

__IM uint8_t SDHC_CORE_Type::RESERVED9[27]

## ◆ EMMC_CTRL_R

__IOM uint16_t SDHC_CORE_Type::EMMC_CTRL_R

0x0000052C eMMC Control register

## ◆ BOOT_CTRL_R

__IOM uint16_t SDHC_CORE_Type::BOOT_CTRL_R

0x0000052E eMMC Boot Control register

## ◆ GP_IN_R

__IM uint32_t SDHC_CORE_Type::GP_IN_R

0x00000530 General Purpose Input register

## ◆ GP_OUT_R

__IOM uint32_t SDHC_CORE_Type::GP_OUT_R

0x00000534 General Purpose Output register

## ◆ RESERVED10

__IM uint32_t SDHC_CORE_Type::RESERVED10[690]