PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

API Reference
Shift Register (TCPWM)
PDL API Reference » TCPWM (Timer Counter PWM)

## General Description

Driver API for Shift Register.

The functions and other declarations used in this part of the driver are in cy_tcpwm_shiftreg.h. You can also include cy_pdl.h to get access to all functions and declarations in the PDL.

Shift Register functionality shifts the counter value to the right. A shift register is used to apply a signal delay function which can be used eg: in detecting frequency shift keying (FSK) signals. A shift register is also used in parallel-in to serial-out data conversion and serial-in to parallel-out data conversion.

Features:

- 16- or 32-bit Counter
- 2 compare (CC0/CC1) registers with double buffer.
- Programmable Counter taps through PERIOD_BUFF register.
- Line output generated from a XOR combination of all enabled counter taps (bit position) defined by PERIOD_BUFF.
- Programmable Compare Register. Compare value can be swapped with a buffered compare value on comparison event.
- Interrupt on Comparison match events (CC0_MATCH/CC1_MATCH).
- Start, Reload, Stop, Shift, and Serial-in Inputs.
- Comparison match and Line Outputs.
- Line output can be output with invert polarity.

Note
  Shift Register mode is available only in TCPWM Version 2

# Configuration Considerations

The Shift Register configuration can be divided to number of sequential steps listed below:

- Configure Shift Register
- Assign and Configure Pins
- Assign Clock Divider
- Enable Shift Register
- Start Shift Register

## Configure Shift Register

To configure Shift Register, provide the configuration parameters in the cy_stc_tcpwm_shiftreg_config_t structure. The configuration structure can be modified through software, but if the configurator in ModusToolbox is used then the configuration structure will be updated with the users inputs. To initialize the driver, call Cy_TCPWM_ShiftReg_Init function providing a pointer to the populated cy_stc_tcpwm_shiftreg_config_t structure.

/* Scenario: Initialize the first (index = 0) of TCPWM 0 block
* as Shift Register with configuration settings
*/
cy_stc_tcpwm_shiftreg_config_t shiftreg_config =
{
/* .clockPrescaler = */CY_TCPWM_SHIFTREG_PRESCALER_DIVBY_1,
/* .tapsEnabled = */0x80000000UL,
/* .compare0 = */16384UL,
/* .compareBuf0 = */16384UL,
/* .enableCompare0Swap = */false,
/* .compare1 = */16384UL,
/* .compareBuf1 = */16384UL,
/* .enableCompare1Swap = */false,
/* .interruptSources = */CY_TCPWM_INT_ON_CC0, /* Interrupt will rise on CC0 Match*/
/* .invertShiftRegOut = */CY_TCPWM_SHIFTREG_INVERT_DISABLE, /* Not inverted */
/* .invertShiftRegOutN = */CY_TCPWM_SHIFTREG_INVERT_DISABLE, /* Not inverted */
/* .reloadInputMode = */CY_TCPWM_INPUT_LEVEL, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
/* .reloadInput = */CY_TCPWM_INPUT_0,
/* .startInputMode = */CY_TCPWM_INPUT_LEVEL, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
/* .startInput = */CY_TCPWM_INPUT_0,
/* .killInputMode = */CY_TCPWM_INPUT_LEVEL, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
/* .killInput = */CY_TCPWM_INPUT_0,
/* .shiftInputMode = */CY_TCPWM_INPUT_LEVEL, /* Set this input to LEVEL and 1 (high logic level) */
/* .shiftInput = */CY_TCPWM_INPUT_1, /* Shift Register will run forever */
/* .serialInputMode = */CY_TCPWM_INPUT_LEVEL, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
/* .serialInput = */CY_TCPWM_INPUT_0,
/* .shiftRegOnDisable = */CY_TCPWM_SHIFTREG_OUTPUT_HIGHZ, /* Default High impedance mode*/
/* .trigger0Event = */CY_TCPWM_CNT_TRIGGER_ON_DISABLED, /* Disable output trigger0 event generation*/
/* .trigger1Event = */CY_TCPWM_CNT_TRIGGER_ON_DISABLED, /* Disable output trigger1 event generation*/
};
#define MY_TCPWM_SHIFTREG_NUM (0UL)
if (CY_TCPWM_SUCCESS != Cy_TCPWM_ShiftReg_Init(TCPWM0, MY_TCPWM_SHIFTREG_NUM, &shiftreg_config))
{
/* Handle possible errors */
}
cy_stc_tcpwm_shiftreg_config_t
Shift Register configuration structure.
Definition: cy_tcpwm_shiftreg.h:121
CY_TCPWM_SUCCESS
@ CY_TCPWM_SUCCESS
Successful.
Definition: cy_tcpwm.h:402
Cy_TCPWM_ShiftReg_Init
cy_en_tcpwm_status_t Cy_TCPWM_ShiftReg_Init(TCPWM_Type const *base, uint32_t cntNum, cy_stc_tcpwm_shiftreg_config_t const *config)
Initializes the counter in the TCPWM block for the Shift Register operation.
Definition: cy_tcpwm_shiftreg.c:55
CY_TCPWM_INPUT_LEVEL
#define CY_TCPWM_INPUT_LEVEL
The event is triggered on each edge of the TCPWM clock if the input is high.
Definition: cy_tcpwm.h:272
CY_TCPWM_INPUT_1
#define CY_TCPWM_INPUT_1
Input is tied to logic 1.
Definition: cy_tcpwm.h:229
CY_TCPWM_INPUT_0
#define CY_TCPWM_INPUT_0
Input is tied to logic 0.
Definition: cy_tcpwm.h:228
CY_TCPWM_INT_ON_CC0
#define CY_TCPWM_INT_ON_CC0
Interrupt on Compare 0/Capture 0(CC0)
Definition: cy_tcpwm.h:307
CY_TCPWM_CNT_TRIGGER_ON_DISABLED
#define CY_TCPWM_CNT_TRIGGER_ON_DISABLED
Output trigger disabled.
Definition: cy_tcpwm.h:297
CY_TCPWM_SHIFTREG_PRESCALER_DIVBY_1
#define CY_TCPWM_SHIFTREG_PRESCALER_DIVBY_1
Divide by 1.
Definition: cy_tcpwm_shiftreg.h:166
CY_TCPWM_SHIFTREG_INVERT_DISABLE
#define CY_TCPWM_SHIFTREG_INVERT_DISABLE
Do not invert the output mode.
Definition: cy_tcpwm_shiftreg.h:189
CY_TCPWM_SHIFTREG_OUTPUT_HIGHZ
#define CY_TCPWM_SHIFTREG_OUTPUT_HIGHZ
Shift Register output (default) high impedance.
Definition: cy_tcpwm_shiftreg.h:197

## Assign and Configure Pins

The dedicated TCPWM pins can be used. The HSIOM register must be configured to connect the block to the pins. Use the GPIO (General Purpose Input Output) driver API to do that.

/* Scenario:
* Configure P0[4] as Shift Register Line Output.
* Configure P0[5] as Shift Register Line Compliment Output.
*/
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 4UL, CY_GPIO_DM_STRONG_IN_OFF, 0UL, P0_4_TCPWM0_LINE2);
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 5UL, CY_GPIO_DM_STRONG_IN_OFF, 0UL, P0_5_TCPWM0_LINE_COMPL2);
CY_GPIO_DM_STRONG_IN_OFF
#define CY_GPIO_DM_STRONG_IN_OFF
Strong Drive.
Definition: cy_gpio.h:514
Cy_GPIO_Pin_FastInit
void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type *base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom)
Initialize the most common configuration settings for all pin types.
Definition: cy_gpio.c:419

## Assign Clock Divider

The clock source must be connected for proper operation. Any of the peripheral clock dividers could be used. Use the SysClk (System Clock) driver API to do that.

## Enable Shift Register

Shift Register has to be enabled before starting

/* Scenario: Enable Shift Register */
#define MY_TCPWM_SHIFTREG_NUM (0UL)
Cy_TCPWM_ShiftReg_Enable(TCPWM0, MY_TCPWM_SHIFTREG_NUM);
Cy_TCPWM_ShiftReg_Enable
__STATIC_INLINE void Cy_TCPWM_ShiftReg_Enable(TCPWM_Type *base, uint32_t cntNum)
Enables the counter in the TCPWM block for the Shift Register operation.
Definition: cy_tcpwm_shiftreg.h:273

## Start Shift Register

To start Shift Register operation Cy_TCPWM_TriggerStart_Single API can be used.

/* Scenario: Use software trigger to start Shift Register operation */
#define MY_TCPWM_SHIFTREG_NUM (0UL)
Cy_TCPWM_TriggerStart_Single(TCPWM0, MY_TCPWM_SHIFTREG_NUM);
Cy_TCPWM_TriggerStart_Single
__STATIC_INLINE void Cy_TCPWM_TriggerStart_Single(TCPWM_Type *base, uint32_t cntNum)
Triggers a software start on the selected TCPWM.
Definition: cy_tcpwm.h:891

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