PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

API Reference
GPIO (General Purpose Input Output)
PDL API Reference

## General Description

The GPIO driver provides an API to configure and access device Input/Output pins.

The functions and other declarations used in this driver are in cy_gpio.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and their variants.

Initialization can be performed either at the port level or by configuring the individual pins. For efficient use of code space, port configuration should be used in the field. Refer to the product device header files for the list of supported ports and pins.

A port is represented by GPIO_PRT_Type and a pin is represented by a number 0 to 7.

- Single pin configuration is performed by using Cy_GPIO_Pin_FastInit (provide specific values) or Cy_GPIO_Pin_Init (provide a filled cy_stc_gpio_pin_config_t structure).
- An entire port can be configured using Cy_GPIO_Port_Init. Provide a filled cy_stc_gpio_prt_config_t structure. The values in the structure are bitfields representing the desired value for each pin in the port.
- Pin configuration and management is based on the port address and pin number. Cy_GPIO_PortToAddr function can optionally be used to calculate the port address from the port number at run-time.
- Each I/O is individually configurable to one of eight drive modes represented by drivemode of cy_stc_gpio_pin_config_t structure.

Once the pin/port initialization is complete, each pin can be accessed by specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API functions.

# Configuration Considerations

1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection. This allows the pin to connect to signal sources/sinks throughout the device, as defined by the pin HSIOM selection options (en_hsiom_sel_t).
2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW control digital pin only) at Power-On-Reset(POR).
3. Some API functions perform read-modify-write operations on shared port registers. These functions are not thread safe and care must be taken when called by the application.
4. Digital input buffer provides a high-impedance buffer for the external digital input. The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripheral. Enabling the input buffer provides possibility to read the pin state via the CPU. If pin is connected to an analog signal, the input buffer should be disabled to avoid crowbar currents. For more information refer to device TRM and the device datasheet.

Multiple pins on a port can be updated using direct port register writes with an appropriate port mask. An example is shown below, highlighting the different ways of configuring Port 1 pins using:

- Initialize a Pin using cy_stc_gpio_pin_config_t structure
  cy_stc_gpio_pin_config_t pinConfig = {
  /*.outVal =*/ 1UL, /* Output = High */
  /*.driveMode =*/ CY_GPIO_DM_STRONG, /* Resistive pull-up, input buffer on */
  /*.hsiom =*/ P0_0_GPIO, /* Software controlled pin */
  /*.intEdge =*/ CY_GPIO_INTR_RISING, /* Rising edge interrupt */
  /*.intMask =*/ 1UL, /* Enable port interrupt for this pin */
  /*.vtrip =*/ CY_GPIO_VTRIP_CMOS, /* CMOS voltage trip */
  /*.slewRate =*/ CY_GPIO_SLEW_FAST, /* Fast slew rate */
  /*.driveSel =*/ CY_GPIO_DRIVE_FULL, /* Full drive strength */
  /*.vregEn =*/ 0UL, /* SIO-specific setting - ignored */
  /*.ibufMode =*/ 0UL, /* SIO-specific setting - ignored */
  /*.vtripSel =*/ 0UL, /* SIO-specific setting - ignored */
  /*.vrefSel =*/ 0UL, /* SIO-specific setting - ignored */
  /*.vohSel =*/ 0UL, /* SIO-specific setting - ignored */
  /*.nonSec =*/ 0UL, /* Secure attribute */
  /*.pullUpRes =*/ 0UL /* Pull-up resistor configuration */
  };
  /* Initialize pin P0.0 */
  if(CY_GPIO_SUCCESS != Cy_GPIO_Pin_Init(P0_0_PORT, P0_0_NUM, &pinConfig))
  {
  /* Insert error handling */
  }
  cy_stc_gpio_pin_config_t
  This structure is used to initialize a single GPIO pin.
  Definition: cy_gpio.h:230
  CY_GPIO_DM_STRONG
  #define CY_GPIO_DM_STRONG
  Strong Drive.
  Definition: cy_gpio.h:522
  CY_GPIO_DRIVE_FULL
  #define CY_GPIO_DRIVE_FULL
  Full drive strength: Max drive current.
  Definition: cy_gpio.h:563
  CY_GPIO_SUCCESS
  @ CY_GPIO_SUCCESS
  Returned successful.
  Definition: cy_gpio.h:157
  Cy_GPIO_Pin_Init
  cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config)
  Initializes all pin configuration settings for the specified pin.
  Definition: cy_gpio.c:79
  CY_GPIO_INTR_RISING
  #define CY_GPIO_INTR_RISING
  Rising-Edge interrupt.
  Definition: cy_gpio.h:577
  CY_GPIO_SLEW_FAST
  #define CY_GPIO_SLEW_FAST
  Fast slew rate.
  Definition: cy_gpio.h:544
  CY_GPIO_VTRIP_CMOS
  #define CY_GPIO_VTRIP_CMOS
  Input buffer compatible with CMOS and I2C interfaces.
  Definition: cy_gpio.h:534
- Initialize entire port using cy_stc_gpio_prt_config_t structure
  /* Scenario: Initialize GPIO port 0:
  * - 3 pin as input with resistive pull-up and rising edge interrupt;
  * - 5 pin as output in a strong drive mode with initial state high. */
  #define PIN_INPUT_NUM 3u
  #define PIN_OUTPUT_NUM 5u
  #define PIN_HIGH 1u
  #define INTR_ENABLE 1u
  #define INTR_CFG_LEN 2u
  #define PIN_DM_CFG_LEN 4u
  cy_stc_gpio_prt_config_t port0_Config = {
  /*.out =*/ (PIN_HIGH << PIN_OUTPUT_NUM), /* PX.5 output value = 1 */
  /*.intrMask =*/ (INTR_ENABLE << PIN_INPUT_NUM), /* PX.3 interrupt enabled */
  /*.intrCfg =*/ (CY_GPIO_INTR_RISING << (PIN_INPUT_NUM * INTR_CFG_LEN)), /* PX.3 rising edge interrupt */
  /*.cfg =*/ ((CY_GPIO_DM_PULLUP << (PIN_INPUT_NUM * PIN_DM_CFG_LEN)) | /* PX.3 resistive pull-up */
  (CY_GPIO_DM_STRONG << (PIN_OUTPUT_NUM * PIN_DM_CFG_LEN))), /* PX.5 strong drive */
  /*.cfgIn =*/ 0x00000000u, /* PX[7:0] CMOS trip (default value)*/
  /*.cfgOut =*/ 0x00000000u, /* PX[7:0] Fast slew rate, full drive strength (default value) */
  /*.cfgSIO =*/ 0x00000000u, /* PX[7:0] ignored (default value) */
  /*.sel0Active =*/ 0x00000000u, /* PX[3:0] Use GPIO HSIOM (default value) */
  /*.sel1Active =*/ 0x00000000u, /* PX[7:4] Use GPIO HSIOM (default value) */
  /*.cfgSlew =*/ 0x00000000u, /* PX[3:0] Slew rate control (default value) */
  /*.cfgDriveSel0 =*/ 0x00000000u, /* PX[3:0] Drive strength selection (default value) */
  /*.cfgDriveSel1 =*/ 0x00000000u, /* PX[7:4] Drive strength selection (default value) */
  /*.nonSecMask =*/ 0x00000000u, /* PX[7:0] Non-secure mask (default value) */
  /*.cfgRes =*/ 0x00000000u, /* PX[7:0] Pull-up resistor configuration for port pins (default value) */
  /*.cfgOut3 =*/ 0x00000000u, /* PX[7:0] Pin extra drive mode (default value) */
  };
  /* Initialize GPIO port 0 */
  if(CY_GPIO_SUCCESS != Cy_GPIO_Port_Init(GPIO_PRT0, &port0_Config))
  {
  /* Insert error handling */
  }
  cy_stc_gpio_prt_config_t
  This structure is used to initialize a port of GPIO pins.
  Definition: cy_gpio.h:206
  CY_GPIO_DM_PULLUP
  #define CY_GPIO_DM_PULLUP
  Resistive Pull-Up.
  Definition: cy_gpio.h:518
  Cy_GPIO_Port_Init
  cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type *base, const cy_stc_gpio_prt_config_t *config)
  Initialize a complete port of pins from a single init structure.
  Definition: cy_gpio.c:254
- Port output data register
- Port output data set register
- Port output data clear register

GPIO_PRT_Type* portAddr;
uint8_t value;
/* Set the port address */
portAddr = GPIO_PRT1;
/* Set the drive mode to STRONG for pins P1[0], P1[2] and P1[3] (other pins in this port are HIGHZ) */
CY_SET_REG32(&portAddr->CFG, CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE0_Pos |
CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE2_Pos |
CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE3_Pos );
/* Set the pins P1[0], P1[2] and P1[3] to high and other pins in this port to low */
CY_SET_REG32(&portAddr->OUT, GPIO_PRT_OUT_OUT0_Msk |
GPIO_PRT_OUT_OUT2_Msk |
GPIO_PRT_OUT_OUT3_Msk);
/* Set the pins P1[2] and P1[3] to low (other pins in this port are unchanged) */
CY_SET_REG32(&portAddr->OUT_CLR, GPIO_PRT_OUT_CLR_OUT2_Msk |
GPIO_PRT_OUT_CLR_OUT3_Msk);
/* Set the pin P1[3] to high again (other pins in this port are unchanged) */
CY_SET_REG32(&portAddr->OUT_SET, GPIO_PRT_OUT_SET_OUT3_Msk);
/* Read the port data (value should be 0b00001001) */
value = CY_GET_REG32(&portAddr->OUT);
/* Set pin P1[3] to low (other pins are not impacted) */
CY_SET_REG32(&portAddr->OUT, _CLR_SET_FLD32U(portAddr->OUT, GPIO_PRT_OUT_OUT3, 0u));
/* Set pin P1[2] to high (other pins are not impacted) */
CY_SET_REG32(&portAddr->OUT, _CLR_SET_FLD32U(portAddr->OUT, GPIO_PRT_OUT_OUT2, 1u));
CY_GPIO_DM_STRONG_IN_OFF
#define CY_GPIO_DM_STRONG_IN_OFF
Strong Drive.
Definition: cy_gpio.h:514
GPIO_PRT_Type
GPIO port registers (GPIO_PRT)
Definition: cyip_gpio.h:39
GPIO_PRT_Type::OUT_SET
__IOM uint32_t OUT_SET
Definition: cyip_gpio.h:42
GPIO_PRT_Type::OUT_CLR
__IOM uint32_t OUT_CLR
Definition: cyip_gpio.h:41
GPIO_PRT_Type::CFG
__IOM uint32_t CFG
Definition: cyip_gpio.h:51
GPIO_PRT_Type::OUT
__IOM uint32_t OUT
Definition: cyip_gpio.h:40

# More Information

Refer to the technical reference manual (TRM) and the device datasheet.

## API Reference
| Macros
| Functions
| Data Structures
| Enumerated Types