PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Structures
Data Structures
PDL API Reference » TDM/I2S (Time Division Multiplexing/Inter-IC Sound)

## General Description

## Data Structures
struct | cy_stc_tdm_config_tx_t
| TDM Initialization configuration. More...
struct | cy_stc_tdm_config_rx_t
| cy_stc_tdm_config_rx_t More...
struct | cy_stc_tdm_config_t
| cy_stc_tdm_config_t More...

## Data Structure Documentation

## ◆ cy_stc_tdm_config_tx_t

struct cy_stc_tdm_config_tx_t

Data Fields
bool | enable | Enables/Disables TDM TX.
cy_en_tdm_device_cfg_t | masterMode | Master mode/Slave mode configuration. cy_en_tdm_device_cfg_t
cy_en_tdm_ws_t | wordSize | TX word length. Channel size must be greater or equal to the word size.
cy_en_tdm_format_t | format | TX data format, cy_en_tdm_format_t.
uint16_t | clkDiv | Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock. Only for Master Mode
cy_en_tdm_clock_sel_t | clkSel | Interface clock "clk_if" selection, cy_en_tdm_clock_sel_t.
cy_en_tdm_sckpolarity_t | sckPolarity | TX clock polarity, 0: as is and 1: inverted cy_en_tdm_sckpolarity_t.
cy_en_tdm_fsyncpolarity_t | fsyncPolarity | Synchronization polarity:0:as is 1:inverted. cy_en_tdm_fsyncpolarity_t
cy_en_tdm_fsyncformat_t | fsyncFormat | Channel synchronization pulse format cy_en_tdm_fsyncformat_t.
uint8_t | channelNum | Number of channels in the frame: 1 to 32 channels supported. In I2S mode number of channels should be 2.
uint8_t | channelSize | Channel Size. Channel size must be greater or equal to the word size.
uint8_t | fifoTriggerLevel | Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated.
uint32_t | chEn | Channels enabled: channel i is controlled by bit chEn[i]. For example : In I2S mode for 2 channels the chEn will be 0x3
uint32_t | signalInput | Controls routing to the TX slave signaling inputs (FSYNC/SCK): '0': TX slave signaling independent from RX signaling : '1': TX slave signaling inputs driven by RX Slave: '2': TX slave signaling inputs driven by RX Master:
bool | i2sMode | IF set to 1 the IP is configured for I2S mode else for TDM mode

## ◆ cy_stc_tdm_config_rx_t

struct cy_stc_tdm_config_rx_t

Data Fields
bool | enable | Enables/Disables TDM RX.
cy_en_tdm_device_cfg_t | masterMode | Master mode/Slave mode configuration. cy_en_tdm_device_cfg_t
cy_en_tdm_ws_t | wordSize | RX word length. Channel size must be greater or equal to the word size.
cy_en_tdm_word_extend_cfg_t | signExtend | Word extension cy_en_tdm_word_extend_cfg_t.
cy_en_tdm_format_t | format | RX data format, cy_en_tdm_format_t.
uint16_t | clkDiv | Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock. Only for Master Mode
cy_en_tdm_clock_sel_t | clkSel | Interface clock "clk_if" selection, cy_en_tdm_clock_sel_t.
cy_en_tdm_sckpolarity_t | sckPolarity | RX clock polarity, 0: as is and 1: inverted cy_en_tdm_sckpolarity_t.
cy_en_tdm_fsyncpolarity_t | fsyncPolarity | Channel synchronization polarity:'false':used "as is". 'true': inverted.
bool | lateSample | Interface late sample delay. Slave configuration: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_in "true": Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_in" (half a cycle delay). Master configuration: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_out". "true": Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_out" (half a cycle delay). RISING = 0 FALLING = 1
cy_en_tdm_fsyncformat_t | fsyncFormat | Channel synchronization pulse format cy_en_tdm_fsyncformat_t.
uint8_t | channelNum | Number of channels in the frame: 1 to 32 channels supported. In I2S mode number of channels should be 2.
uint8_t | channelSize | Channel Size. Channel size must be greater or equal to the word size.
uint32_t | chEn | Channels enabled: channel i is controlled by bit chEn[i]. For example : In I2S mode for 2 channels the chEn will be 0x3
uint8_t | fifoTriggerLevel | Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated.
uint32_t | signalInput | Controls routing to the RX slave signaling inputs (FSYNC/SCK): '0': RX slave signaling independent from TX signaling : '1': RX slave signaling inputs driven by TX Slave: '2': RX slave signaling inputs driven by TX Master:
bool | i2sMode | IF set to 1 the IP is configured for I2S mode else for TDM mode

## ◆ cy_stc_tdm_config_t

struct cy_stc_tdm_config_t

Data Fields
cy_stc_tdm_config_tx_t * | tx_config | TDM Initialization configuration for TX.
cy_stc_tdm_config_rx_t * | rx_config | TDM Initialization configuration for RX.