/***************************************************************************//**
* MXNNLITE_2_0 IP definitions
*
********************************************************************************
* \copyright
* (c) (2016-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#ifndef _CYIP_MXNNLITE_2_0_V2_H_
#define _CYIP_MXNNLITE_2_0_V2_H_

#include "cyip_headers.h"

/*******************************************************************************
*                                 MXNNLITE_2_0
*******************************************************************************/

#define MXNNLITE_2_0_SECTION_SIZE               0x00001000UL

/**
  * \brief MXNNLITE_2_0
  */
typedef struct {
   __IM uint32_t RESERVED;
  __IOM uint32_t WEIGHTSTREAMERBASEADDR;        /*!< 0x00000004  */
  __IOM uint32_t WEIGHTSTREAMEROFFSET;          /*!< 0x00000008  */
  __IOM uint32_t WEIGHTSTREAMERKERNELCHANNELTIMESHEIGHTTIMESWIDTH; /*!< 0x0000000C  */
  __IOM uint32_t ACTIVATIONSTREAMERCHANNEL;     /*!< 0x00000010  */
  __IOM uint32_t ACTIVATIONSTREAMERBASEADDR;    /*!< 0x00000014  */
  __IOM uint32_t ACTIVATIONSTREAMEROFFSET;      /*!< 0x00000018  */
  __IOM uint32_t ACTIVATIONSTREAMERKERNELCHANNELTIMESWIDTH; /*!< 0x0000001C  */
  __IOM uint32_t ACTIVATIONSTREAMERKERNELHEIGHT; /*!< 0x00000020  */
  __IOM uint32_t ACTIVATIONSTREAMERREPEATS;     /*!< 0x00000024  */
  __IOM uint32_t ACTIVATIONSTREAMERSTARTCOL;    /*!< 0x00000028  */
  __IOM uint32_t ACTIVATIONSTREAMERSTARTROW;    /*!< 0x0000002C  */
  __IOM uint32_t ACTIVATIONSTREAMERCHANNELTIMESWIDTH; /*!< 0x00000030  */
  __IOM uint32_t ACTIVATIONSTREAMERHEIGHT;      /*!< 0x00000034  */
  __IOM uint32_t ACTIVATIONSTREAMERPADDING;     /*!< 0x00000038  */
  __IOM uint32_t ACTIVATIONSTREAMERSPARSITYMAPBASEADDR; /*!< 0x0000003C  */
  __IOM uint32_t OUTSTREAMERBASEADDR;           /*!< 0x00000040  */
  __IOM uint32_t OUTSTREAMEROUTPUTOFFSET;       /*!< 0x00000044  */
  __IOM uint32_t OUTSTREAMERCLIPPING;           /*!< 0x00000048  */
  __IOM uint32_t INTERPOLATIONLUTDATA0;         /*!< 0x0000004C  */
  __IOM uint32_t INTERPOLATIONLUTDATA1;         /*!< 0x00000050  */
  __IOM uint32_t BIASBASEADDR;                  /*!< 0x00000054  */
  __IOM uint32_t SCALINGFACTORBASEADDR;         /*!< 0x00000058  */
  __IOM uint32_t NONZEROWEIGHTSPOINTER;         /*!< 0x0000005C Memory address, which stores the number of the non-zero weights */
  __IOM uint32_t INPUTRESCALINGFACTOR;          /*!< 0x00000060 Floating point value (IEEE-754 single precision) which scales
                                                                the activation/weight input */
  __IOM uint32_t OUTPUTCHANNELS;                /*!< 0x00000064 Unsigned number of output channels for depthwise operations */
  __IOM uint32_t OUTPUTWIDTH;                   /*!< 0x00000068 Output width for one layer */
  __IOM uint32_t OUTPUTHEIGHT;                  /*!< 0x0000006C Output height for one layer */
  __IOM uint32_t STRIDE;                        /*!< 0x00000070 Stride control register */
  __IOM uint32_t NNLAYER_CTL;                   /*!< 0x00000074 Configure layer pattern, activation functions, activation size,
                                                                and weight size (only for DSP algorithms) */
  __IOM uint32_t INTR;                          /*!< 0x00000078 Interrupt cause and clear register */
  __IOM uint32_t INTR_MASK;                     /*!< 0x0000007C Interrupt mask register. A co-located interrupt cause bit will
                                                                only cause an interrupt when its mask bit is 1 */
  __IOM uint32_t TRIG_MASK;                     /*!< 0x00000080 Trigger mask register. Calculation done for one layer triggers
                                                                DataWire when its mask bit is 1 */
  __IOM uint32_t CMD;                           /*!< 0x00000084 Command register */
  __IOM uint32_t INTR_SET;                      /*!< 0x00000088 Set INTR_XXX register by software for debug purpose */
   __IM uint32_t INTR_MASKED;                   /*!< 0x0000008C Virtual register for generating the interrupt signal to MCU. It
                                                                is the logical AND of the INTR_XXX and INTR_MASK_XXX register */
   __IM uint32_t STATUS;                        /*!< 0x00000090 Status register */
} MXNNLITE_2_0_Type;                            /*!< Size = 148 (0x94) */


/* MXNNLITE_2_0.WEIGHTSTREAMERBASEADDR */
#define MXNNLITE_2_0_WEIGHTSTREAMERBASEADDR_WEIGHTSTREAMERBASEADDR_Pos 0UL
#define MXNNLITE_2_0_WEIGHTSTREAMERBASEADDR_WEIGHTSTREAMERBASEADDR_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.WEIGHTSTREAMEROFFSET */
#define MXNNLITE_2_0_WEIGHTSTREAMEROFFSET_WEIGHTSTREAMEROFFSET_Pos 0UL
#define MXNNLITE_2_0_WEIGHTSTREAMEROFFSET_WEIGHTSTREAMEROFFSET_Msk 0x1FFFFUL
/* MXNNLITE_2_0.WEIGHTSTREAMERKERNELCHANNELTIMESHEIGHTTIMESWIDTH */
#define MXNNLITE_2_0_WEIGHTSTREAMERKERNELCHANNELTIMESHEIGHTTIMESWIDTH_WEIGHTSTREAMERKERNELCHANNELTIMESHEIGHTTIMESWIDTH_Pos 0UL
#define MXNNLITE_2_0_WEIGHTSTREAMERKERNELCHANNELTIMESHEIGHTTIMESWIDTH_WEIGHTSTREAMERKERNELCHANNELTIMESHEIGHTTIMESWIDTH_Msk 0x3FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERCHANNEL */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERCHANNEL_ACTIVATIONSTREAMERCHANNEL_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERCHANNEL_ACTIVATIONSTREAMERCHANNEL_Msk 0x1FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERBASEADDR */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERBASEADDR_ACTIVATIONSTREAMERBASEADDR_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERBASEADDR_ACTIVATIONSTREAMERBASEADDR_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMEROFFSET */
#define MXNNLITE_2_0_ACTIVATIONSTREAMEROFFSET_ACTIVATIONSTREAMEROFFSET_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMEROFFSET_ACTIVATIONSTREAMEROFFSET_Msk 0x1FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERKERNELCHANNELTIMESWIDTH */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERKERNELCHANNELTIMESWIDTH_ACTIVATIONSTREAMERKERNELCHANNELTIMESWIDTH_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERKERNELCHANNELTIMESWIDTH_ACTIVATIONSTREAMERKERNELCHANNELTIMESWIDTH_Msk 0x3FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERKERNELHEIGHT */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERKERNELHEIGHT_ACTIVATIONSTREAMERKERNELHEIGHT_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERKERNELHEIGHT_ACTIVATIONSTREAMERKERNELHEIGHT_Msk 0x1FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERREPEATS */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERREPEATS_ACTIVATIONSTREAMERREPEATS_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERREPEATS_ACTIVATIONSTREAMERREPEATS_Msk 0x3FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERSTARTCOL */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERSTARTCOL_ACTIVATIONSTREAMERSTARTCOL_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERSTARTCOL_ACTIVATIONSTREAMERSTARTCOL_Msk 0x3FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERSTARTROW */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERSTARTROW_ACTIVATIONSTREAMERSTARTROW_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERSTARTROW_ACTIVATIONSTREAMERSTARTROW_Msk 0x3FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERCHANNELTIMESWIDTH */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERCHANNELTIMESWIDTH_ACTIVATIONSTREAMERCHANNELTIMESWIDTH_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERCHANNELTIMESWIDTH_ACTIVATIONSTREAMERCHANNELTIMESWIDTH_Msk 0x1FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERHEIGHT */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERHEIGHT_ACTIVATIONSTREAMERHEIGHT_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERHEIGHT_ACTIVATIONSTREAMERHEIGHT_Msk 0x1FFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERPADDING */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERPADDING_ACTIVATIONSTREAMERPADVALUE_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERPADDING_ACTIVATIONSTREAMERPADVALUE_Msk 0xFFFFUL
/* MXNNLITE_2_0.ACTIVATIONSTREAMERSPARSITYMAPBASEADDR */
#define MXNNLITE_2_0_ACTIVATIONSTREAMERSPARSITYMAPBASEADDR_ACTIVATIONSTREAMERSPARSITYMAPBASEADDR_Pos 0UL
#define MXNNLITE_2_0_ACTIVATIONSTREAMERSPARSITYMAPBASEADDR_ACTIVATIONSTREAMERSPARSITYMAPBASEADDR_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.OUTSTREAMERBASEADDR */
#define MXNNLITE_2_0_OUTSTREAMERBASEADDR_OUTSTREAMERBASEADDR_Pos 0UL
#define MXNNLITE_2_0_OUTSTREAMERBASEADDR_OUTSTREAMERBASEADDR_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.OUTSTREAMEROUTPUTOFFSET */
#define MXNNLITE_2_0_OUTSTREAMEROUTPUTOFFSET_OUTSTREAMEROUTPUTOFFSET_Pos 0UL
#define MXNNLITE_2_0_OUTSTREAMEROUTPUTOFFSET_OUTSTREAMEROUTPUTOFFSET_Msk 0x1FFFFUL
/* MXNNLITE_2_0.OUTSTREAMERCLIPPING */
#define MXNNLITE_2_0_OUTSTREAMERCLIPPING_OUTSTREAMERCLIPPINGVALUEMIN_Pos 0UL
#define MXNNLITE_2_0_OUTSTREAMERCLIPPING_OUTSTREAMERCLIPPINGVALUEMIN_Msk 0xFFFFUL
#define MXNNLITE_2_0_OUTSTREAMERCLIPPING_OUTSTREAMERCLIPPINGVALUEMAX_Pos 16UL
#define MXNNLITE_2_0_OUTSTREAMERCLIPPING_OUTSTREAMERCLIPPINGVALUEMAX_Msk 0xFFFF0000UL
/* MXNNLITE_2_0.INTERPOLATIONLUTDATA0 */
#define MXNNLITE_2_0_INTERPOLATIONLUTDATA0_INTERPOLATIONLUTDATA0_Pos 0UL
#define MXNNLITE_2_0_INTERPOLATIONLUTDATA0_INTERPOLATIONLUTDATA0_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.INTERPOLATIONLUTDATA1 */
#define MXNNLITE_2_0_INTERPOLATIONLUTDATA1_INTERPOLATIONLUTDATA1_Pos 0UL
#define MXNNLITE_2_0_INTERPOLATIONLUTDATA1_INTERPOLATIONLUTDATA1_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.BIASBASEADDR */
#define MXNNLITE_2_0_BIASBASEADDR_BIASBASEADDR_Pos 0UL
#define MXNNLITE_2_0_BIASBASEADDR_BIASBASEADDR_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.SCALINGFACTORBASEADDR */
#define MXNNLITE_2_0_SCALINGFACTORBASEADDR_SCALINGFACTORBASEADDR_Pos 0UL
#define MXNNLITE_2_0_SCALINGFACTORBASEADDR_SCALINGFACTORBASEADDR_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.NONZEROWEIGHTSPOINTER */
#define MXNNLITE_2_0_NONZEROWEIGHTSPOINTER_NONZEROWEIGHTSPOINTER_Pos 0UL
#define MXNNLITE_2_0_NONZEROWEIGHTSPOINTER_NONZEROWEIGHTSPOINTER_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.INPUTRESCALINGFACTOR */
#define MXNNLITE_2_0_INPUTRESCALINGFACTOR_INPUTRESCALINGFACTOR_Pos 0UL
#define MXNNLITE_2_0_INPUTRESCALINGFACTOR_INPUTRESCALINGFACTOR_Msk 0xFFFFFFFFUL
/* MXNNLITE_2_0.OUTPUTCHANNELS */
#define MXNNLITE_2_0_OUTPUTCHANNELS_OUTPUTCHANNELS_Pos 0UL
#define MXNNLITE_2_0_OUTPUTCHANNELS_OUTPUTCHANNELS_Msk 0x1FFFFUL
/* MXNNLITE_2_0.OUTPUTWIDTH */
#define MXNNLITE_2_0_OUTPUTWIDTH_OUTPUTWIDTH_Pos 0UL
#define MXNNLITE_2_0_OUTPUTWIDTH_OUTPUTWIDTH_Msk 0x1FFFFUL
/* MXNNLITE_2_0.OUTPUTHEIGHT */
#define MXNNLITE_2_0_OUTPUTHEIGHT_OUTPUTHEIGHT_Pos 0UL
#define MXNNLITE_2_0_OUTPUTHEIGHT_OUTPUTHEIGHT_Msk 0x1FFFFUL
/* MXNNLITE_2_0.STRIDE */
#define MXNNLITE_2_0_STRIDE_STRIDECHANNELTIMESCOLUMN_Pos 0UL
#define MXNNLITE_2_0_STRIDE_STRIDECHANNELTIMESCOLUMN_Msk 0xFFFFUL
#define MXNNLITE_2_0_STRIDE_STRIDEROW_Pos       16UL
#define MXNNLITE_2_0_STRIDE_STRIDEROW_Msk       0xFF0000UL
/* MXNNLITE_2_0.NNLAYER_CTL */
#define MXNNLITE_2_0_NNLAYER_CTL_INPUT_RESCALE_Pos 0UL
#define MXNNLITE_2_0_NNLAYER_CTL_INPUT_RESCALE_Msk 0x3UL
#define MXNNLITE_2_0_NNLAYER_CTL_OPTYPE_Pos     7UL
#define MXNNLITE_2_0_NNLAYER_CTL_OPTYPE_Msk     0x780UL
#define MXNNLITE_2_0_NNLAYER_CTL_ACTTYPE_Pos    11UL
#define MXNNLITE_2_0_NNLAYER_CTL_ACTTYPE_Msk    0x3800UL
#define MXNNLITE_2_0_NNLAYER_CTL_FETCH_MODE_Pos 14UL
#define MXNNLITE_2_0_NNLAYER_CTL_FETCH_MODE_Msk 0xC000UL
#define MXNNLITE_2_0_NNLAYER_CTL_REPEAT_WEIGHTS_Pos 16UL
#define MXNNLITE_2_0_NNLAYER_CTL_REPEAT_WEIGHTS_Msk 0x10000UL
#define MXNNLITE_2_0_NNLAYER_CTL_SCALEFACTOR_CTL_Pos 17UL
#define MXNNLITE_2_0_NNLAYER_CTL_SCALEFACTOR_CTL_Msk 0x60000UL
#define MXNNLITE_2_0_NNLAYER_CTL_INPUT_SIZE_CTL_Pos 19UL
#define MXNNLITE_2_0_NNLAYER_CTL_INPUT_SIZE_CTL_Msk 0x80000UL
#define MXNNLITE_2_0_NNLAYER_CTL_OUTPUT_SIZE_CTL_Pos 20UL
#define MXNNLITE_2_0_NNLAYER_CTL_OUTPUT_SIZE_CTL_Msk 0x300000UL
#define MXNNLITE_2_0_NNLAYER_CTL_WEIGHT_SIZE_CTL_Pos 22UL
#define MXNNLITE_2_0_NNLAYER_CTL_WEIGHT_SIZE_CTL_Msk 0x400000UL
#define MXNNLITE_2_0_NNLAYER_CTL_BIAS_EN_Pos    23UL
#define MXNNLITE_2_0_NNLAYER_CTL_BIAS_EN_Msk    0x800000UL
#define MXNNLITE_2_0_NNLAYER_CTL_SPARSE_EN_Pos  24UL
#define MXNNLITE_2_0_NNLAYER_CTL_SPARSE_EN_Msk  0x1000000UL
#define MXNNLITE_2_0_NNLAYER_CTL_CHUNK_EN_Pos   25UL
#define MXNNLITE_2_0_NNLAYER_CTL_CHUNK_EN_Msk   0x2000000UL
#define MXNNLITE_2_0_NNLAYER_CTL_FFT_EN_Pos     26UL
#define MXNNLITE_2_0_NNLAYER_CTL_FFT_EN_Msk     0x4000000UL
#define MXNNLITE_2_0_NNLAYER_CTL_WPREFETCH_LEN_Pos 27UL
#define MXNNLITE_2_0_NNLAYER_CTL_WPREFETCH_LEN_Msk 0x18000000UL
/* MXNNLITE_2_0.INTR */
#define MXNNLITE_2_0_INTR_INTR_DONE_Pos         0UL
#define MXNNLITE_2_0_INTR_INTR_DONE_Msk         0x1UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_SPARSITY_Pos 1UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_SPARSITY_Msk 0x2UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_ACTIVATIONSTREAMER_Pos 2UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_ACTIVATIONSTREAMER_Msk 0x4UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_WEIGHTSTREAMER_Pos 3UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_WEIGHTSTREAMER_Msk 0x8UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_BIASSTREAMER_Pos 4UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_BIASSTREAMER_Msk 0x10UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_OUTPUTSTREAMER_Pos 5UL
#define MXNNLITE_2_0_INTR_INTR_MEM_ERR_OUTPUTSTREAMER_Msk 0x20UL
#define MXNNLITE_2_0_INTR_INTR_ACCUMULATION_SATURATION_Pos 6UL
#define MXNNLITE_2_0_INTR_INTR_ACCUMULATION_SATURATION_Msk 0x40UL
#define MXNNLITE_2_0_INTR_INTR_INPUT_PRESCALE_SATURATION_Pos 7UL
#define MXNNLITE_2_0_INTR_INTR_INPUT_PRESCALE_SATURATION_Msk 0x80UL
#define MXNNLITE_2_0_INTR_INTR_OUTPUT_PRESCALE_SATURATION_Pos 8UL
#define MXNNLITE_2_0_INTR_INTR_OUTPUT_PRESCALE_SATURATION_Msk 0x100UL
#define MXNNLITE_2_0_INTR_INTR_OUTPUT_POSTSCALE_SATURATION_Pos 9UL
#define MXNNLITE_2_0_INTR_INTR_OUTPUT_POSTSCALE_SATURATION_Msk 0x200UL
/* MXNNLITE_2_0.INTR_MASK */
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_DONE_Pos 0UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_DONE_Msk 0x1UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_SPARSITY_Pos 1UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_SPARSITY_Msk 0x2UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_ACTIVATIONSTREAMER_Pos 2UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_ACTIVATIONSTREAMER_Msk 0x4UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_WEIGHTSTREAMER_Pos 3UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_WEIGHTSTREAMER_Msk 0x8UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_BIASSTREAMER_Pos 4UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_BIASSTREAMER_Msk 0x10UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_OUTPUTSTREAMER_Pos 5UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_MEM_ERR_OUTPUTSTREAMER_Msk 0x20UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_ACCUMULATION_SATURATION_Pos 6UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_ACCUMULATION_SATURATION_Msk 0x40UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_INPUT_PRESCALE_SATURATION_Pos 7UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_INPUT_PRESCALE_SATURATION_Msk 0x80UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_OUTPUT_PRESCALE_SATURATION_Pos 8UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_OUTPUT_PRESCALE_SATURATION_Msk 0x100UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_OUTPUT_POSTSCALE_SATURATION_Pos 9UL
#define MXNNLITE_2_0_INTR_MASK_INTR_MASK_OUTPUT_POSTSCALE_SATURATION_Msk 0x200UL
/* MXNNLITE_2_0.TRIG_MASK */
#define MXNNLITE_2_0_TRIG_MASK_TRIG_MASK_DONE_Pos 0UL
#define MXNNLITE_2_0_TRIG_MASK_TRIG_MASK_DONE_Msk 0x1UL
/* MXNNLITE_2_0.CMD */
#define MXNNLITE_2_0_CMD_START_CMD_Pos          0UL
#define MXNNLITE_2_0_CMD_START_CMD_Msk          0x1UL
#define MXNNLITE_2_0_CMD_ABORT_CMD_Pos          1UL
#define MXNNLITE_2_0_CMD_ABORT_CMD_Msk          0x2UL
/* MXNNLITE_2_0.INTR_SET */
#define MXNNLITE_2_0_INTR_SET_INTR_SET_DONE_Pos 0UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_DONE_Msk 0x1UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_SPARSITY_Pos 1UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_SPARSITY_Msk 0x2UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_ACTIVATIONSTREAMER_Pos 2UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_ACTIVATIONSTREAMER_Msk 0x4UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_WEIGHTSTREAMER_Pos 3UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_WEIGHTSTREAMER_Msk 0x8UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_BIASSTREAMER_Pos 4UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_BIASSTREAMER_Msk 0x10UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_OUTPUTSTREAMER_Pos 5UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_MEM_ERR_OUTPUTSTREAMER_Msk 0x20UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_ACCUMULATION_SATURATION_Pos 6UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_ACCUMULATION_SATURATION_Msk 0x40UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_INPUT_PRESCALE_SATURATION_Pos 7UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_INPUT_PRESCALE_SATURATION_Msk 0x80UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_OUTPUT_PRESCALE_SATURATION_Pos 8UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_OUTPUT_PRESCALE_SATURATION_Msk 0x100UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_OUTPUT_POSTSCALE_SATURATION_Pos 9UL
#define MXNNLITE_2_0_INTR_SET_INTR_SET_OUTPUT_POSTSCALE_SATURATION_Msk 0x200UL
/* MXNNLITE_2_0.INTR_MASKED */
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_DONE_Pos 0UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_DONE_Msk 0x1UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_SPARSITY_Pos 1UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_SPARSITY_Msk 0x2UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_ACTIVATIONSTREAMER_Pos 2UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_ACTIVATIONSTREAMER_Msk 0x4UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_WEIGHTSTREAMER_Pos 3UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_WEIGHTSTREAMER_Msk 0x8UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_BIASSTREAMER_Pos 4UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_BIASSTREAMER_Msk 0x10UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_OUTPUTSTREAMER_Pos 5UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_MEM_ERR_OUTPUTSTREAMER_Msk 0x20UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_ACCUMULATION_SATURATION_Pos 6UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_ACCUMULATION_SATURATION_Msk 0x40UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_INPUT_PRESCALE_SATURATION_Pos 7UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_INPUT_PRESCALE_SATURATION_Msk 0x80UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_OUTPUT_PRESCALE_SATURATION_Pos 8UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_OUTPUT_PRESCALE_SATURATION_Msk 0x100UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_OUTPUT_POSTSCALE_SATURATION_Pos 9UL
#define MXNNLITE_2_0_INTR_MASKED_INTR_MASKED_OUTPUT_POSTSCALE_SATURATION_Msk 0x200UL
/* MXNNLITE_2_0.STATUS */
#define MXNNLITE_2_0_STATUS_BUSY_STATUS_Pos     0UL
#define MXNNLITE_2_0_STATUS_BUSY_STATUS_Msk     0x1UL
#define MXNNLITE_2_0_STATUS_ACTIVATIONSTREAMERDONE_Pos 1UL
#define MXNNLITE_2_0_STATUS_ACTIVATIONSTREAMERDONE_Msk 0x2UL


#endif /* _CYIP_MXNNLITE_2_0_V2_H_ */


/* [] END OF FILE */
