PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
mtb_hal_memoryspi_configurator_t Struct Reference

## Description

MemorySPI configurator struct.

This struct allows a configurator to provide block configuration information to the HAL. Because configurator-generated configurations are platform specific, the contents of this struct is subject to change between platforms and/or HAL releases.

## Data Fields
SMIF_Type * | base
| Base address for the SMIF.
const cy_stc_smif_config_t * | config
| PDL-level SMIF configuration.
uint32_t | instNumber
| SMIF instance number.
cy_stc_smif_context_t | context
| SMIF context for PDL use.
const mtb_hal_clock_t * | clock
| Default clock to use.
bool | csel [4]
| Used stus of each chip select.
uint8_t | irqs
| Bit representation of currently not supported interrupts: Bit 5 : Memory Mode Alignment Error Bit 4 : RX Data FIFO Underflow Bit 3 : TX Command FIFO Overflow Bit 2 : TX Data FIFO Overflow Bit 1 : RX FIFO Level Trigger Bit 0 : TX FIFO Level Trigger.
uint8_t | dmas
| Bit representation of DMA triggers activation indicators: Bit 1 : RX Trigger Output activated in configurator Bit 0 : TX Trigger Output activated in configurator.

## Field Documentation

## ◆ base

SMIF_Type* mtb_hal_memoryspi_configurator_t::base

Base address for the SMIF.

## ◆ config

const cy_stc_smif_config_t* mtb_hal_memoryspi_configurator_t::config

PDL-level SMIF configuration.

## ◆ instNumber

uint32_t mtb_hal_memoryspi_configurator_t::instNumber

SMIF instance number.

## ◆ context

cy_stc_smif_context_t mtb_hal_memoryspi_configurator_t::context

SMIF context for PDL use.

## ◆ clock

const mtb_hal_clock_t* mtb_hal_memoryspi_configurator_t::clock

Default clock to use.

## ◆ csel

bool mtb_hal_memoryspi_configurator_t::csel[4]

Used stus of each chip select.

## ◆ irqs

uint8_t mtb_hal_memoryspi_configurator_t::irqs

Bit representation of currently not supported interrupts: Bit 5 : Memory Mode Alignment Error Bit 4 : RX Data FIFO Underflow Bit 3 : TX Command FIFO Overflow Bit 2 : TX Data FIFO Overflow Bit 1 : RX FIFO Level Trigger Bit 0 : TX FIFO Level Trigger.

## ◆ dmas

uint8_t mtb_hal_memoryspi_configurator_t::dmas

Bit representation of DMA triggers activation indicators: Bit 1 : RX Trigger Output activated in configurator Bit 0 : TX Trigger Output activated in configurator.