PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Enumerations
Enumerated Types
PDL API Reference » MS_CTL (Master Security Controller)

## General Description

## Enumerations
enum | cy_en_ms_ctl_status_t { CY_MS_CTL_SUCCESS = 0x00U , CY_MS_CTL_BAD_PARAM = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x01U , CY_MS_CTL_INVALID_STATE = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x02U , CY_MS_CTL_FAILURE = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x03U , CY_MS_CTL_UNAVAILABLE = CY_MS_CTL_ID | CY_PDL_STATUS_ERROR | 0x04U }
| MSC API return status. More...
enum | en_ms_ctl_master_t { CY_MS_CTL_ID_CM33_0 = 0 , CY_MS_CTL_ID_CM33_1 = 1 , CY_MS_CTL_ID_DMAC0_MS = 2 , CY_MS_CTL_ID_DMAC1_MS = 3 , CY_MS_CTL_ID_DW0_MS = 4 , CY_MS_CTL_ID_DW1_MS = 5 , CY_MS_CTL_ID_CODE_MS_0 = 6 , CY_MS_CTL_ID_SYS_MS_0 = 7 , CY_MS_CTL_ID_SYS_MS_1 = 8 , CY_MS_CTL_ID_EXP_SYSCPUSS_MS_0 = 9 , CY_MS_CTL_ID_EXP_SYSCPUSS_MS_1 = 10 , CY_MS_CTL_ID_EXP_SYSCPUSS_MS_2 = 11 , CY_MS_CTL_ID_EXP_SYSCPUSS_MS_3 = 12 , CY_MS_CTL_ID_EXP_APPCPUSS_MS_0 = 13 , CY_MS_CTL_ID_EXP_APPCPUSS_MS_1 = 14 , CY_MS_CTL_ID_EXP_APPCPUSS_MS_2 = 15 , CY_MS_CTL_ID_EXP_APPCPUSS_MS_3 = 16 , CY_MS_CTL_ID_SYS_MS_0_NVM = 17 , CY_MS_CTL_ID_SYS_MS_1_NVM = 18 , CY_MS_CTL_ID_CM55_MS_0 = 19 , CY_MS_CTL_ID_CM55_MS_1 = 20 , CY_MS_CTL_ID_CM55_MS_2 = 21 , CY_MS_CTL_ID_CM55_MS_3 = 22 , CY_MS_CTL_ID_AXIDMAC0_MS = 23 , CY_MS_CTL_ID_AXIDMAC1_MS = 24 , CY_MS_CTL_ID_U55AXI0_MS = 25 , CY_MS_CTL_ID_U55AXI1_MS = 26 , CY_MS_CTL_ID_AXI_SYS_MS2 = 27 , CY_MS_CTL_ID_AXI_SYS_MS3 = 28 , CY_MS_CTL_ID_BISR_MS = 29 , CY_MS_CTL_ID_RESERVED = 30 , CY_MS_CTL_ID_TC_MS = 31 }
| Bus masters. More...
enum | en_ms_ctl_master_sc_acg_t { CODE_MS0_MSC = 0 , SYS_MS0_MSC = 1 , SYS_MS1_MSC = 2 , EXP_MS_MSC = 3 , DMAC0_MSC = 4 , DMAC1_MSC = 5 }
| Bus masters security controller and Access Control Group (ACG) config.
enum | en_ms_ctl_master_sc_acg_v1_t { APP_SYS_MS0_MSC = 0 , APP_SYS_MS1_MSC = 1 , APP_AXIDMAC0_MSC = 2 , APP_AXIDMAC1_MSC = 3 , APP_AXI_MS0_MSC = 4 , APP_AXI_MS1_MSC = 5 , APP_AXI_MS2_MSC = 6 , APP_AXI_MS3_MSC = 7 , APP_EXP_MS0_MSC = 8 , APP_EXP_MS1_MSC = 9 , APP_EXP_MS2_MSC = 10 , APP_EXP_MS3_MSC = 11 }
| Bus masters security controller and Access Control Group (ACG) config.
enum | cy_en_ms_ctl_cfg_gate_resp_t { CY_MS_CTL_GATE_RESP_WAITED_TRFR = 0 , CY_MS_CTL_GATE_RESP_ERR = 1 }
| Response type when ACG blocks incoming transfers. More...
enum | cy_en_ms_ctl_sec_resp_t { CY_MS_CTL_SEC_RESP_RAZ_WI = 0 , CY_MS_CTL_SEC_RESP_ERR = 1 }
| Response type when MSC blocks transfers. More...
enum | cy_en_ms_ctl_pcmask_t { CY_MS_CTL_PCMASK0 = 0x0001U , CY_MS_CTL_PCMASK1 = 0x0002U , CY_MS_CTL_PCMASK2 = 0x0004U , CY_MS_CTL_PCMASK3 = 0x0008U , CY_MS_CTL_PCMASK4 = 0x0010U , CY_MS_CTL_PCMASK5 = 0x0020U , CY_MS_CTL_PCMASK6 = 0x0040U , CY_MS_CTL_PCMASK7 = 0x0080U , CY_MS_CTL_PCMASK8 = 0x0100U , CY_MS_CTL_PCMASK9 = 0x0200U , CY_MS_CTL_PCMASK10 = 0x0400U , CY_MS_CTL_PCMASK11 = 0x0800U , CY_MS_CTL_PCMASK12 = 0x1000U , CY_MS_CTL_PCMASK13 = 0x2000U , CY_MS_CTL_PCMASK14 = 0x4000U , CY_MS_CTL_PCMASK15 = 0x8000U }
| Protection context mask (PC_MASK) More...

## Enumeration Type Documentation

## ◆ cy_en_ms_ctl_status_t

enum cy_en_ms_ctl_status_t

MSC API return status.

Enumerator
CY_MS_CTL_SUCCESS | Returned successful.
CY_MS_CTL_BAD_PARAM | Bad parameter was passed.
CY_MS_CTL_INVALID_STATE | The operation is not setup.
CY_MS_CTL_FAILURE | The resource is locked.
CY_MS_CTL_UNAVAILABLE | The resource is unavailable.

## ◆ en_ms_ctl_master_t

enum en_ms_ctl_master_t

Bus masters.

Enumerator
CY_MS_CTL_ID_CM33_0 | Cortex M33 CPU-0.
CY_MS_CTL_ID_CM33_1 | Cortex M33 CPU-1.
CY_MS_CTL_ID_DMAC0_MS | AHBDMA 0 controller.
CY_MS_CTL_ID_DMAC1_MS | AHBDMA 1 controller.
CY_MS_CTL_ID_DW0_MS | DataWire 0.
CY_MS_CTL_ID_DW1_MS | DataWire 1.
CY_MS_CTL_ID_CODE_MS_0 | External 128-bit AHB5 CODE master-0.
CY_MS_CTL_ID_SYS_MS_0 | External 32-bit AHB5 SYS interconnect master-0.
CY_MS_CTL_ID_SYS_MS_1 | External 32-bit AHB5 SYS interconnect master-1.
CY_MS_CTL_ID_EXP_SYSCPUSS_MS_0 | External 32-bit AHB5 EXP interconnect master-0.
CY_MS_CTL_ID_EXP_SYSCPUSS_MS_1 | External 32-bit AHB5 EXP interconnect master-1.
CY_MS_CTL_ID_EXP_SYSCPUSS_MS_2 | External 32-bit AHB5 EXP interconnect master-2.
CY_MS_CTL_ID_EXP_SYSCPUSS_MS_3 | External 32-bit AHB5 EXP interconnect master-3.
CY_MS_CTL_ID_EXP_APPCPUSS_MS_0 | External 32-bit AHB5 EXP interconnect master-4.
CY_MS_CTL_ID_EXP_APPCPUSS_MS_1 | External 32-bit AHB5 EXP interconnect master-5.
CY_MS_CTL_ID_EXP_APPCPUSS_MS_2 | External 32-bit AHB5 EXP interconnect master-6.
CY_MS_CTL_ID_EXP_APPCPUSS_MS_3 | External 32-bit AHB5 EXP interconnect master-7.
CY_MS_CTL_ID_SYS_MS_0_NVM | External 32-bit AHB5 SYS NVM interconnect master-0.
CY_MS_CTL_ID_SYS_MS_1_NVM | External 32-bit AHB5 SYS NVM interconnect master-1.
CY_MS_CTL_ID_CM55_MS_0 | Cortex M55 CPU-0.
CY_MS_CTL_ID_CM55_MS_1 | Cortex M55 CPU-1.
CY_MS_CTL_ID_CM55_MS_2 | Cortex M55 CPU-2.
CY_MS_CTL_ID_CM55_MS_3 | Cortex M55 CPU-3.
CY_MS_CTL_ID_AXIDMAC0_MS | AXIDMA 0 controller.
CY_MS_CTL_ID_AXIDMAC1_MS | AXIDMA 1 controller.
CY_MS_CTL_ID_U55AXI0_MS | AXI_SYS_MS_0.
CY_MS_CTL_ID_U55AXI1_MS | AXI_SYS_MS_1.
CY_MS_CTL_ID_AXI_SYS_MS2 | AXI_SYS_MS_2.
CY_MS_CTL_ID_AXI_SYS_MS3 | AXI_SYS_MS_3.
CY_MS_CTL_ID_BISR_MS | BISR_MS.
CY_MS_CTL_ID_RESERVED | Reserved.
CY_MS_CTL_ID_TC_MS | Test Controller.

## ◆ cy_en_ms_ctl_cfg_gate_resp_t

enum cy_en_ms_ctl_cfg_gate_resp_t

Response type when ACG blocks incoming transfers.

Enumerator
CY_MS_CTL_GATE_RESP_WAITED_TRFR | Waited transfer.
CY_MS_CTL_GATE_RESP_ERR | Error response.

## ◆ cy_en_ms_ctl_sec_resp_t

enum cy_en_ms_ctl_sec_resp_t

Response type when MSC blocks transfers.

Enumerator
CY_MS_CTL_SEC_RESP_RAZ_WI | Read as zero and write ignored.
CY_MS_CTL_SEC_RESP_ERR | Error response.

## ◆ cy_en_ms_ctl_pcmask_t

enum cy_en_ms_ctl_pcmask_t

Protection context mask (PC_MASK)

Enumerator
CY_MS_CTL_PCMASK0 | Mask to allow PC = 0.
CY_MS_CTL_PCMASK1 | Mask to allow PC = 1.
CY_MS_CTL_PCMASK2 | Mask to allow PC = 2.
CY_MS_CTL_PCMASK3 | Mask to allow PC = 3.
CY_MS_CTL_PCMASK4 | Mask to allow PC = 4.
CY_MS_CTL_PCMASK5 | Mask to allow PC = 5.
CY_MS_CTL_PCMASK6 | Mask to allow PC = 6.
CY_MS_CTL_PCMASK7 | Mask to allow PC = 7.
CY_MS_CTL_PCMASK8 | Mask to allow PC = 8.
CY_MS_CTL_PCMASK9 | Mask to allow PC = 9.
CY_MS_CTL_PCMASK10 | Mask to allow PC = 10.
CY_MS_CTL_PCMASK11 | Mask to allow PC = 11.
CY_MS_CTL_PCMASK12 | Mask to allow PC = 12.
CY_MS_CTL_PCMASK13 | Mask to allow PC = 13.
CY_MS_CTL_PCMASK14 | Mask to allow PC = 14.
CY_MS_CTL_PCMASK15 | Mask to allow PC = 15.