PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Structures
Data Structures
PDL API Reference » AUTONOMOUS ANALOG (Autonomous Analog Block) » CT DAC (Continuous Time Digital to Analog Converter)

## General Description

## Data Structures
struct | cy_stc_autanalog_dac_ch_t
| The configuration structure of the DAC channel. More...
struct | cy_stc_autanalog_dac_ch_limit_t
| The channel range detection configuration structure. More...
struct | cy_stc_autanalog_dac_waveform_t
| The configuration structure of the waveform. More...
struct | cy_stc_autanalog_dac_sta_t
| Defines the static configuration structure, see Static Configuration. More...
struct | cy_stc_autanalog_dac_t
| The configuration structure to set up the entire DAC. More...
struct | cy_stc_autanalog_stt_dac_t
| The DAC section in the State Transition Table state. More...

## Data Structure Documentation

## ◆ cy_stc_autanalog_dac_ch_t

struct cy_stc_autanalog_dac_ch_t

Data Fields
uint16_t | startAddr | Start address of the waveform in the LUT. When the DAC is triggered (refer to cy_stc_autanalog_stt_dac_t), it outputs the value at START_ADDR. The START_ADDR is word (16 bits) aligned and the value ranges from 0 to 511
uint16_t | endAddr | End address of the waveform in the LUT. The end address must be greater than or equal to the start address (START_ADDR). The END_ADDR is word (16 bit) aligned and the value ranges from 0 to 511
cy_en_autanalog_dac_oper_mode_t | operMode | The DAC operating mode, for more details, refer to Operating Mode.
bool | sampleAndHold | Enables Sample and Hold functionality for the DAC, for more details, refer to Sample and Hold.
cy_en_autanalog_dac_step_sel_t | stepSel | The step selector for the DAC.
cy_en_autanalog_dac_stat_sel_t | statSel | The status selector for the DAC output range.

## ◆ cy_stc_autanalog_dac_ch_limit_t

struct cy_stc_autanalog_dac_ch_limit_t

Data Fields
cy_en_autanalog_dac_limit_t | cond | Range detection condition.
int16_t | low | Low threshold for range detection.
int16_t | high | High threshold for range detection.

## ◆ cy_stc_autanalog_dac_waveform_t

struct cy_stc_autanalog_dac_waveform_t

Data Fields
uint16_t | numSamples | The number of samples in the waveform.
const int16_t * | waveformData | The pointer to the waveform data.
bool | isDriveModeArray | Indicates that all samples in the waveform array have the same drive mode configuration.
cy_en_autanalog_dac_out_drive_mode_t * | driveMode | The pointer to the drive mode configurations.

## ◆ cy_stc_autanalog_dac_sta_t

struct cy_stc_autanalog_dac_sta_t

Data Fields
uint16_t | lpDivDac | The Low Power clock divider, actual divide value is DIV_VAL + 1, valid range is 1..1024. For more details, refer to Clocking chapter
cy_en_autanalog_dac_topo_cfg_t | topology | The DAC topology, for more details, refer to Topology chapter.
cy_en_autanalog_dac_vref_sel_t | vrefSel | The DAC source of the Vref, for more details, refer to Reference Voltage chapter.
bool | deGlitch | Enables the DAC de-glitch functionality, for more details, refer to De-glitch chapter. FALSE - disabled; TRUE - enabled;
bool | bottomSel | The selector for the connecting the bottom end of the R-2R resistors ladder, for more details, refer to Output Drive Control chapter. FALSE - connect to Vssa; TRUE - connect to Vref;
bool | disabledMode | The selector for the DAC output value when the output is disabled, for more details, refer to Output Drive Control chapter. FALSE - tri-state output; TRUE - output Vssa or Vref, depends on the setting in the cy_stc_autanalog_dac_sta_t::bottomSel field;
cy_en_autanalog_dac_ref_buf_pwr_t | refBuffPwr | The power mode of the reference voltage buffer, for more details, refer to Topology chapter.
cy_en_autanalog_dac_out_buf_pwr_t | outBuffPwr | The power mode of the output voltage buffer, for more details, refer to Topology chapter.
bool | sign | Output data as a unsigned/signed value, for more details, refer to Signed/Unsigned Input chapter. FALSE - unsigned 12-bit number; TRUE - virtual signed 12-bits number;
cy_en_autanalog_dac_vref_mux_t | vrefMux | Multiplexed reference voltage, for more details, refer to Reference Voltage.
uint8_t | sampleTime | The sample time selection for the cy_stc_autanalog_dac_ch_t::sampleAndHold. Actual value is SAMPLE_TIME + 1, range 1..256 Note The sample time is measured in terms of the number of clock cycles.
uint8_t | stepVal[CY_AUTANALOG_DAC_STEP_VAL_NUM] | The DAC step value. Actual step value is STEP_VAL + 1. for more details, refer to Operating Mode chapter
uint8_t | deGlitchTime | The DAC de-glitch time, for more details, refer to De-glitch Actual value is DEGLITCH_CNT + 1, range 1..256. Note The sample time is measured in terms of the number of clock cycles.
cy_stc_autanalog_dac_ch_t * | chCfg[CY_AUTANALOG_DAC_CH_CFG_NUM] | The array of pointers to the configuration structures for the DAC channels, a NULL element means that the channel structure is not configured.
cy_stc_autanalog_dac_ch_limit_t * | chLimitCfg[CY_AUTANALOG_DAC_CH_RANGE_NUM] | The array of pointers to the configuration structures for the DAC output range detection, a NULL element means that the range detection is not configured.

## ◆ cy_stc_autanalog_dac_t

struct cy_stc_autanalog_dac_t

Data Fields
cy_stc_autanalog_dac_sta_t * | dacStaCfg | The pointer to a static part of the DAC configuration.
cy_stc_autanalog_dac_waveform_t * | waveform | The pointer to a waveform part of the DAC configuration.

## ◆ cy_stc_autanalog_stt_dac_t

struct cy_stc_autanalog_stt_dac_t

Data Fields
bool | unlock | DAC Unlock . FALSE - Locked: Data from fields enable, trigger, channel and direction of this structure are NOT taken into account in the corresponding state of STT; TRUE - Unlocked: Data from fields enable, trigger, channel and direction of this structure are used in the STT corresponding state;
bool | enable | Enables the DAC.
bool | trigger | This field initiates the DAC operation per selected channel.
uint8_t | channel | The DAC channel selector, refer to cy_stc_autanalog_dac_sta_t::chCfg.
cy_en_autanalog_stt_dac_dir_t | direction | Defines the direction of movement in the LUT or the increment/decrement of the DAC value.