/*

Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this
   list of conditions and the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright
   notice, this list of conditions and the following disclaimer in the
   documentation and/or other materials provided with the distribution.

3. Neither the name of Nordic Semiconductor ASA nor the names of its
   contributors may be used to endorse or promote products derived from this
   software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

*/

#ifndef NRF54L10_TYPES_H
#define NRF54L10_TYPES_H

#ifdef __cplusplus
    extern "C" {
#endif

#include <stdint.h>
#include "compiler_abstraction.h"


/* ============================================ Include required type specifiers ============================================= */

#ifndef __I
  #ifdef __cplusplus
    #define __I     volatile                         /*!< Defines 'read only' permissions                                      */
  #else
    #define __I     volatile const                   /*!< Defines 'read only' permissions                                      */
  #endif
#endif
#ifndef __O
  #define __O     volatile                           /*!< Defines 'write only' permissions                                     */
#endif
#ifndef __IO
  #define __IO    volatile                           /*!< Defines 'read / write' permissions                                   */
#endif

/* The following defines should be used for structure members */
#ifndef __IM
  #define __IM     volatile const                    /*!< Defines 'read only' structure member permissions                     */
#endif
#ifndef __OM
  #define __OM     volatile                          /*!< Defines 'write only' structure member permissions                    */
#endif
#ifndef __IOM
  #define __IOM    volatile                          /*!< Defines 'read / write' structure member permissions                  */
#endif

/* ======================================================= Domain IDs ======================================================== */
/**
  * @brief (unspecified)
  */
typedef enum {
  NRF_DOMAIN_NONE                            = 0,    /*!< No domain                                                            */
} NRF_DOMAINID_Type;

/* ====================================================== Processor IDs ====================================================== */
/**
  * @brief (unspecified)
  */
typedef enum {
  NRF_PROCESSOR_CM33                         = 1,    /*!< (unspecified)                                                        */
  NRF_PROCESSOR_VPR                          = 2,    /*!< (unspecified)                                                        */
} NRF_PROCESSORID_Type;

/* ======================================================== Owner IDs ======================================================== */
/**
  * @brief (unspecified)
  */
typedef enum {
  NRF_OWNER_NONE                             = 0,    /*!< Used to denote that ownership is not enforced                        */
  NRF_OWNER_APPLICATION                      = 1,    /*!< Application Core                                                     */
  NRF_OWNER_KMU                              = 2,    /*!< KMU Accesses                                                         */
} NRF_OWNERID_Type;


/* ========================================= Start of section using anonymous unions ========================================= */

#include "compiler_abstraction.h"

#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Unsupported compiler type
#endif

/* =========================================================================================================================== */
/* ================                                    Peripherals Section                                    ================ */
/* =========================================================================================================================== */


/* =========================================================================================================================== */
/* ================                                            AAR                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ====================================================== Struct AAR_IN ====================================================== */
/**
  * @brief IN [AAR_IN] IN EasyDMA channel
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Input pointer                                         */
} NRF_AAR_IN_Type;                                   /*!< Size = 4 (0x004)                                                     */

/* AAR_IN_PTR: Input pointer */
  #define AAR_IN_PTR_ResetValue (0x00000000UL)       /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Points to a job list containing AAR data structure */
  #define AAR_IN_PTR_PTR_Pos (0UL)                   /*!< Position of PTR field.                                               */
  #define AAR_IN_PTR_PTR_Msk (0xFFFFFFFFUL << AAR_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                  */



/* ===================================================== Struct AAR_OUT ====================================================== */
/**
  * @brief OUT [AAR_OUT] OUT EasyDMA channel
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Output pointer                                        */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Number of bytes transferred in the last transaction   */
} NRF_AAR_OUT_Type;                                  /*!< Size = 8 (0x008)                                                     */

/* AAR_OUT_PTR: Output pointer */
  #define AAR_OUT_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Output pointer */
  #define AAR_OUT_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
  #define AAR_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << AAR_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */


/* AAR_OUT_AMOUNT: Number of bytes transferred in the last transaction */
  #define AAR_OUT_AMOUNT_ResetValue (0x00000000UL)   /*!< Reset value of AMOUNT register.                                      */

/* AMOUNT @Bits 0..7 : Number of bytes written to memory after triggering the START task. */
  #define AAR_OUT_AMOUNT_AMOUNT_Pos (0UL)            /*!< Position of AMOUNT field.                                            */
  #define AAR_OUT_AMOUNT_AMOUNT_Msk (0xFFUL << AAR_OUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                       */
  #define AAR_OUT_AMOUNT_AMOUNT_Min (0x01UL)         /*!< Min value of AMOUNT field.                                           */
  #define AAR_OUT_AMOUNT_AMOUNT_Max (0xFFUL)         /*!< Max size of AMOUNT field.                                            */


/* ======================================================= Struct AAR ======================================================== */
/**
  * @brief Accelerated Address Resolver
  */
  typedef struct {                                   /*!< AAR Structure                                                        */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified in
                                                                         the IRK data structure*/
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop resolving addresses                              */
    __IM uint32_t RESERVED[30];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED1[30];
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000100) Address resolution procedure complete or ended due to
                                                                         an error*/
    __IOM uint32_t EVENTS_RESOLVED;                  /*!< (@ 0x00000104) Address resolved                                      */
    __IOM uint32_t EVENTS_NOTRESOLVED;               /*!< (@ 0x00000108) Address not resolved                                  */
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x0000010C) Operation aborted because of a STOP task or due to an
                                                                         error This event does not generate an interrupt*/
    __IM uint32_t RESERVED2[28];
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000180) Publish configuration for event END                   */
    __IOM uint32_t PUBLISH_RESOLVED;                 /*!< (@ 0x00000184) Publish configuration for event RESOLVED              */
    __IOM uint32_t PUBLISH_NOTRESOLVED;              /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED           */
    __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x0000018C) Publish configuration for event ERROR                 */
    __IM uint32_t RESERVED3[93];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED4[62];
    __IM uint32_t ERRORSTATUS;                       /*!< (@ 0x00000404) Error status                                          */
    __IM uint32_t RESERVED5[62];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable AAR                                            */
    __IM uint32_t RESERVED6;
    __IOM uint32_t MAXRESOLVED;                      /*!< (@ 0x00000508) Maximum number of IRKs to resolve                     */
    __IM uint32_t RESERVED7[9];
    __IOM NRF_AAR_IN_Type IN;                        /*!< (@ 0x00000530) IN EasyDMA channel                                    */
    __IM uint32_t RESERVED8;
    __IOM NRF_AAR_OUT_Type OUT;                      /*!< (@ 0x00000538) OUT EasyDMA channel                                   */
  } NRF_AAR_Type;                                    /*!< Size = 1344 (0x540)                                                  */

/* AAR_TASKS_START: Start resolving addresses based on IRKs specified in the IRK data structure */
  #define AAR_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
  #define AAR_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
  #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
  #define AAR_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
  #define AAR_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
  #define AAR_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */


/* AAR_TASKS_STOP: Stop resolving addresses */
  #define AAR_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop resolving addresses */
  #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
  #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
  #define AAR_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
  #define AAR_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
  #define AAR_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* AAR_SUBSCRIBE_START: Subscribe configuration for task START */
  #define AAR_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define AAR_SUBSCRIBE_START_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define AAR_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define AAR_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
  #define AAR_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define AAR_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define AAR_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define AAR_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* AAR_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define AAR_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define AAR_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define AAR_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
  #define AAR_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define AAR_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define AAR_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
  #define AAR_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */


/* AAR_EVENTS_END: Address resolution procedure complete or ended due to an error */
  #define AAR_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : Address resolution procedure complete or ended due to an error */
  #define AAR_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
  #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
  #define AAR_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
  #define AAR_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
  #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
  #define AAR_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */


/* AAR_EVENTS_RESOLVED: Address resolved */
  #define AAR_EVENTS_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESOLVED register.                          */

/* EVENTS_RESOLVED @Bit 0 : Address resolved */
  #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field.                                */
  #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of
                                                                            EVENTS_RESOLVED field.*/
  #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESOLVED field.                  */
  #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESOLVED field.                  */
  #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (0x1UL) /*!< Event generated                                           */


/* AAR_EVENTS_NOTRESOLVED: Address not resolved */
  #define AAR_EVENTS_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NOTRESOLVED register.                    */

/* EVENTS_NOTRESOLVED @Bit 0 : Address not resolved */
  #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field.                       */
  #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask
                                                                            of EVENTS_NOTRESOLVED field.*/
  #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_NOTRESOLVED field.         */
  #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_NOTRESOLVED field.         */
  #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (0x1UL) /*!< Event generated                                     */


/* AAR_EVENTS_ERROR: Operation aborted because of a STOP task or due to an error This event does not generate an interrupt */
  #define AAR_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                                */

/* EVENTS_ERROR @Bit 0 : Operation aborted because of a STOP task or due to an error This event does not generate an interrupt */
  #define AAR_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)    /*!< Position of EVENTS_ERROR field.                                      */
  #define AAR_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << AAR_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.  */
  #define AAR_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL)  /*!< Min enumerator value of EVENTS_ERROR field.                          */
  #define AAR_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL)  /*!< Max enumerator value of EVENTS_ERROR field.                          */
  #define AAR_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define AAR_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                 */


/* AAR_PUBLISH_END: Publish configuration for event END */
  #define AAR_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define AAR_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
  #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
  #define AAR_PUBLISH_END_CHIDX_Min (0x00UL)         /*!< Min value of CHIDX field.                                            */
  #define AAR_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define AAR_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
  #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
  #define AAR_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
  #define AAR_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
  #define AAR_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
  #define AAR_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */


/* AAR_PUBLISH_RESOLVED: Publish configuration for event RESOLVED */
  #define AAR_PUBLISH_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESOLVED register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event RESOLVED will publish to */
  #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define AAR_PUBLISH_RESOLVED_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define AAR_PUBLISH_RESOLVED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field.                        */
  #define AAR_PUBLISH_RESOLVED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define AAR_PUBLISH_RESOLVED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define AAR_PUBLISH_RESOLVED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define AAR_PUBLISH_RESOLVED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* AAR_PUBLISH_NOTRESOLVED: Publish configuration for event NOTRESOLVED */
  #define AAR_PUBLISH_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NOTRESOLVED register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that event NOTRESOLVED will publish to */
  #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field.                  */
  #define AAR_PUBLISH_NOTRESOLVED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define AAR_PUBLISH_NOTRESOLVED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* AAR_PUBLISH_ERROR: Publish configuration for event ERROR */
  #define AAR_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
  #define AAR_PUBLISH_ERROR_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define AAR_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << AAR_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define AAR_PUBLISH_ERROR_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define AAR_PUBLISH_ERROR_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define AAR_PUBLISH_ERROR_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define AAR_PUBLISH_ERROR_EN_Msk (0x1UL << AAR_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                              */
  #define AAR_PUBLISH_ERROR_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define AAR_PUBLISH_ERROR_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define AAR_PUBLISH_ERROR_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define AAR_PUBLISH_ERROR_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* AAR_INTENSET: Enable interrupt */
  #define AAR_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* END @Bit 0 : Write '1' to enable interrupt for event END */
  #define AAR_INTENSET_END_Pos (0UL)                 /*!< Position of END field.                                               */
  #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
  #define AAR_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define AAR_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define AAR_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
  #define AAR_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define AAR_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* RESOLVED @Bit 1 : Write '1' to enable interrupt for event RESOLVED */
  #define AAR_INTENSET_RESOLVED_Pos (1UL)            /*!< Position of RESOLVED field.                                          */
  #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field.                      */
  #define AAR_INTENSET_RESOLVED_Min (0x0UL)          /*!< Min enumerator value of RESOLVED field.                              */
  #define AAR_INTENSET_RESOLVED_Max (0x1UL)          /*!< Max enumerator value of RESOLVED field.                              */
  #define AAR_INTENSET_RESOLVED_Set (0x1UL)          /*!< Enable                                                               */
  #define AAR_INTENSET_RESOLVED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define AAR_INTENSET_RESOLVED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* NOTRESOLVED @Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
  #define AAR_INTENSET_NOTRESOLVED_Pos (2UL)         /*!< Position of NOTRESOLVED field.                                       */
  #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field.             */
  #define AAR_INTENSET_NOTRESOLVED_Min (0x0UL)       /*!< Min enumerator value of NOTRESOLVED field.                           */
  #define AAR_INTENSET_NOTRESOLVED_Max (0x1UL)       /*!< Max enumerator value of NOTRESOLVED field.                           */
  #define AAR_INTENSET_NOTRESOLVED_Set (0x1UL)       /*!< Enable                                                               */
  #define AAR_INTENSET_NOTRESOLVED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define AAR_INTENSET_NOTRESOLVED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ERROR @Bit 3 : Write '1' to enable interrupt for event ERROR */
  #define AAR_INTENSET_ERROR_Pos (3UL)               /*!< Position of ERROR field.                                             */
  #define AAR_INTENSET_ERROR_Msk (0x1UL << AAR_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
  #define AAR_INTENSET_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
  #define AAR_INTENSET_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
  #define AAR_INTENSET_ERROR_Set (0x1UL)             /*!< Enable                                                               */
  #define AAR_INTENSET_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define AAR_INTENSET_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */


/* AAR_INTENCLR: Disable interrupt */
  #define AAR_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* END @Bit 0 : Write '1' to disable interrupt for event END */
  #define AAR_INTENCLR_END_Pos (0UL)                 /*!< Position of END field.                                               */
  #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
  #define AAR_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define AAR_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define AAR_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
  #define AAR_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define AAR_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* RESOLVED @Bit 1 : Write '1' to disable interrupt for event RESOLVED */
  #define AAR_INTENCLR_RESOLVED_Pos (1UL)            /*!< Position of RESOLVED field.                                          */
  #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field.                      */
  #define AAR_INTENCLR_RESOLVED_Min (0x0UL)          /*!< Min enumerator value of RESOLVED field.                              */
  #define AAR_INTENCLR_RESOLVED_Max (0x1UL)          /*!< Max enumerator value of RESOLVED field.                              */
  #define AAR_INTENCLR_RESOLVED_Clear (0x1UL)        /*!< Disable                                                              */
  #define AAR_INTENCLR_RESOLVED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define AAR_INTENCLR_RESOLVED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* NOTRESOLVED @Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
  #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL)         /*!< Position of NOTRESOLVED field.                                       */
  #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field.             */
  #define AAR_INTENCLR_NOTRESOLVED_Min (0x0UL)       /*!< Min enumerator value of NOTRESOLVED field.                           */
  #define AAR_INTENCLR_NOTRESOLVED_Max (0x1UL)       /*!< Max enumerator value of NOTRESOLVED field.                           */
  #define AAR_INTENCLR_NOTRESOLVED_Clear (0x1UL)     /*!< Disable                                                              */
  #define AAR_INTENCLR_NOTRESOLVED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define AAR_INTENCLR_NOTRESOLVED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ERROR @Bit 3 : Write '1' to disable interrupt for event ERROR */
  #define AAR_INTENCLR_ERROR_Pos (3UL)               /*!< Position of ERROR field.                                             */
  #define AAR_INTENCLR_ERROR_Msk (0x1UL << AAR_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
  #define AAR_INTENCLR_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
  #define AAR_INTENCLR_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
  #define AAR_INTENCLR_ERROR_Clear (0x1UL)           /*!< Disable                                                              */
  #define AAR_INTENCLR_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define AAR_INTENCLR_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */


/* AAR_ERRORSTATUS: Error status */
  #define AAR_ERRORSTATUS_ResetValue (0x00000000UL)  /*!< Reset value of ERRORSTATUS register.                                 */

/* ERRORSTATUS @Bits 0..2 : Error status when the ERROR event is generated */
  #define AAR_ERRORSTATUS_ERRORSTATUS_Pos (0UL)      /*!< Position of ERRORSTATUS field.                                       */
  #define AAR_ERRORSTATUS_ERRORSTATUS_Msk (0x7UL << AAR_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field.       */
  #define AAR_ERRORSTATUS_ERRORSTATUS_Min (0x0UL)    /*!< Min enumerator value of ERRORSTATUS field.                           */
  #define AAR_ERRORSTATUS_ERRORSTATUS_Max (0x4UL)    /*!< Max enumerator value of ERRORSTATUS field.                           */
  #define AAR_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred                                             */
  #define AAR_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before data structure was read.     */
  #define AAR_ERRORSTATUS_ERRORSTATUS_DmaError (0x4UL) /*!< Bus error during DMA access.                                       */


/* AAR_ENABLE: Enable AAR */
  #define AAR_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..1 : Enable or disable AAR */
  #define AAR_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
  #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
  #define AAR_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
  #define AAR_ENABLE_ENABLE_Max (0x3UL)              /*!< Max enumerator value of ENABLE field.                                */
  #define AAR_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
  #define AAR_ENABLE_ENABLE_Enabled (0x3UL)          /*!< Enable                                                               */


/* AAR_MAXRESOLVED: Maximum number of IRKs to resolve */
  #define AAR_MAXRESOLVED_ResetValue (0x00000001UL)  /*!< Reset value of MAXRESOLVED register.                                 */

/* MAXRESOLVED @Bits 0..11 : The maximum number of IRKs to resolve */
  #define AAR_MAXRESOLVED_MAXRESOLVED_Pos (0UL)      /*!< Position of MAXRESOLVED field.                                       */
  #define AAR_MAXRESOLVED_MAXRESOLVED_Msk (0xFFFUL << AAR_MAXRESOLVED_MAXRESOLVED_Pos) /*!< Bit mask of MAXRESOLVED field.     */
  #define AAR_MAXRESOLVED_MAXRESOLVED_Min (0x001UL)  /*!< Min value of MAXRESOLVED field.                                      */
  #define AAR_MAXRESOLVED_MAXRESOLVED_Max (0xFFFUL)  /*!< Max size of MAXRESOLVED field.                                       */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           CACHE                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================= Struct CACHE_PROFILING ================================================== */
/**
  * @brief PROFILING [CACHE_PROFILING] (unspecified)
  */
typedef struct {
  __IOM uint32_t  ENABLE;                            /*!< (@ 0x00000000) Enable the profiling counters.                        */
  __OM  uint32_t  CLEAR;                             /*!< (@ 0x00000004) Clear the profiling counters.                         */
  __IM  uint32_t  HIT;                               /*!< (@ 0x00000008) The cache hit counter for cache region.               */
  __IM  uint32_t  MISS;                              /*!< (@ 0x0000000C) The cache miss counter for cache region.              */
  __IM  uint32_t  LMISS;                             /*!< (@ 0x00000010) The cache line miss counter for cache region.         */
  __IM  uint32_t  READS;                             /*!< (@ 0x00000014) Number of reads for cache region.                     */
  __IM  uint32_t  WRITES;                            /*!< (@ 0x00000018) Number of writes for cache region.                    */
} NRF_CACHE_PROFILING_Type;                          /*!< Size = 28 (0x01C)                                                    */

/* CACHE_PROFILING_ENABLE: Enable the profiling counters. */
  #define CACHE_PROFILING_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register.                                */

/* ENABLE @Bit 0 : Enable the profiling counters */
  #define CACHE_PROFILING_ENABLE_ENABLE_Pos (0UL)    /*!< Position of ENABLE field.                                            */
  #define CACHE_PROFILING_ENABLE_ENABLE_Msk (0x1UL << CACHE_PROFILING_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.        */
  #define CACHE_PROFILING_ENABLE_ENABLE_Min (0x0UL)  /*!< Min enumerator value of ENABLE field.                                */
  #define CACHE_PROFILING_ENABLE_ENABLE_Max (0x1UL)  /*!< Max enumerator value of ENABLE field.                                */
  #define CACHE_PROFILING_ENABLE_ENABLE_Disable (0x0UL) /*!< Disable profiling                                                 */
  #define CACHE_PROFILING_ENABLE_ENABLE_Enable (0x1UL) /*!< Enable profiling                                                   */


/* CACHE_PROFILING_CLEAR: Clear the profiling counters. */
  #define CACHE_PROFILING_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of CLEAR register.                                  */

/* CLEAR @Bit 0 : Clearing the profiling counters */
  #define CACHE_PROFILING_CLEAR_CLEAR_Pos (0UL)      /*!< Position of CLEAR field.                                             */
  #define CACHE_PROFILING_CLEAR_CLEAR_Msk (0x1UL << CACHE_PROFILING_CLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field.             */
  #define CACHE_PROFILING_CLEAR_CLEAR_Min (0x1UL)    /*!< Min enumerator value of CLEAR field.                                 */
  #define CACHE_PROFILING_CLEAR_CLEAR_Max (0x1UL)    /*!< Max enumerator value of CLEAR field.                                 */
  #define CACHE_PROFILING_CLEAR_CLEAR_Clear (0x1UL)  /*!< Clear the profiling counters                                         */


/* CACHE_PROFILING_HIT: The cache hit counter for cache region. */
  #define CACHE_PROFILING_HIT_ResetValue (0x00000000UL) /*!< Reset value of HIT register.                                      */

/* HITS @Bits 0..31 : Number of cache hits */
  #define CACHE_PROFILING_HIT_HITS_Pos (0UL)         /*!< Position of HITS field.                                              */
  #define CACHE_PROFILING_HIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_HIT_HITS_Pos) /*!< Bit mask of HITS field.             */


/* CACHE_PROFILING_MISS: The cache miss counter for cache region. */
  #define CACHE_PROFILING_MISS_ResetValue (0x00000000UL) /*!< Reset value of MISS register.                                    */

/* MISSES @Bits 0..31 : Number of cache misses */
  #define CACHE_PROFILING_MISS_MISSES_Pos (0UL)      /*!< Position of MISSES field.                                            */
  #define CACHE_PROFILING_MISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_MISS_MISSES_Pos) /*!< Bit mask of MISSES field.     */


/* CACHE_PROFILING_LMISS: The cache line miss counter for cache region. */
  #define CACHE_PROFILING_LMISS_ResetValue (0x00000000UL) /*!< Reset value of LMISS register.                                  */

/* LMISSES @Bits 0..31 : Number of cache line misses */
  #define CACHE_PROFILING_LMISS_LMISSES_Pos (0UL)    /*!< Position of LMISSES field.                                           */
  #define CACHE_PROFILING_LMISS_LMISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_LMISS_LMISSES_Pos) /*!< Bit mask of LMISSES field.*/


/* CACHE_PROFILING_READS: Number of reads for cache region. */
  #define CACHE_PROFILING_READS_ResetValue (0x00000000UL) /*!< Reset value of READS register.                                  */

/* READS @Bits 0..31 : Number of reads for cache region. */
  #define CACHE_PROFILING_READS_READS_Pos (0UL)      /*!< Position of READS field.                                             */
  #define CACHE_PROFILING_READS_READS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_READS_READS_Pos) /*!< Bit mask of READS field.      */


/* CACHE_PROFILING_WRITES: Number of writes for cache region. */
  #define CACHE_PROFILING_WRITES_ResetValue (0x00000000UL) /*!< Reset value of WRITES register.                                */

/* WRITES @Bits 0..31 : Number of writes for cache region. */
  #define CACHE_PROFILING_WRITES_WRITES_Pos (0UL)    /*!< Position of WRITES field.                                            */
  #define CACHE_PROFILING_WRITES_WRITES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_WRITES_WRITES_Pos) /*!< Bit mask of WRITES field. */


/* ====================================================== Struct CACHE ======================================================= */
/**
  * @brief Cache
  */
  typedef struct {                                   /*!< CACHE Structure                                                      */
    __IM uint32_t RESERVED[2];
    __OM uint32_t TASKS_INVALIDATECACHE;             /*!< (@ 0x00000008) Invalidate the cache.                                 */
    __IM uint32_t RESERVED1[2];
    __OM uint32_t TASKS_INVALIDATELINE;              /*!< (@ 0x00000014) Invalidate the line.                                  */
    __IM uint32_t RESERVED2[2];
    __OM uint32_t TASKS_ERASE;                       /*!< (@ 0x00000020) Erase the cache.                                      */
    __IM uint32_t RESERVED3[247];
    __IM uint32_t STATUS;                            /*!< (@ 0x00000400) Status of the cache activities.                       */
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000404) Enable cache.                                         */
    __IM uint32_t RESERVED4[2];
    __IOM uint32_t LINEADDR;                         /*!< (@ 0x00000410) Memory address covered by the line to be maintained.  */
    __IOM NRF_CACHE_PROFILING_Type PROFILING;        /*!< (@ 0x00000414) (unspecified)                                         */
    __IOM uint32_t DEBUGLOCK;                        /*!< (@ 0x00000430) Lock debug mode.                                      */
    __IOM uint32_t WRITELOCK;                        /*!< (@ 0x00000434) Lock cache updates.                                   */
  } NRF_CACHE_Type;                                  /*!< Size = 1080 (0x438)                                                  */

/* CACHE_TASKS_INVALIDATECACHE: Invalidate the cache. */
  #define CACHE_TASKS_INVALIDATECACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATECACHE register.            */

/* TASKS_INVALIDATECACHE @Bit 0 : Invalidate the cache. */
  #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos (0UL) /*!< Position of TASKS_INVALIDATECACHE field.            */
  #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Msk (0x1UL << CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos)
                                                                            /*!< Bit mask of TASKS_INVALIDATECACHE field.*/
  #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATECACHE
                                                                            field.*/
  #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATECACHE
                                                                            field.*/
  #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Trigger (0x1UL) /*!< Trigger task                                  */


/* CACHE_TASKS_INVALIDATELINE: Invalidate the line. */
  #define CACHE_TASKS_INVALIDATELINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATELINE register.              */

/* TASKS_INVALIDATELINE @Bit 0 : Invalidate the line. */
  #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos (0UL) /*!< Position of TASKS_INVALIDATELINE field.               */
  #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Msk (0x1UL << CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos)
                                                                            /*!< Bit mask of TASKS_INVALIDATELINE field.*/
  #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATELINE field. */
  #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATELINE field. */
  #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Trigger (0x1UL) /*!< Trigger task                                    */


/* CACHE_TASKS_ERASE: Erase the cache. */
  #define CACHE_TASKS_ERASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ERASE register.                                */

/* TASKS_ERASE @Bit 0 : Erase the cache. */
  #define CACHE_TASKS_ERASE_TASKS_ERASE_Pos (0UL)    /*!< Position of TASKS_ERASE field.                                       */
  #define CACHE_TASKS_ERASE_TASKS_ERASE_Msk (0x1UL << CACHE_TASKS_ERASE_TASKS_ERASE_Pos) /*!< Bit mask of TASKS_ERASE field.   */
  #define CACHE_TASKS_ERASE_TASKS_ERASE_Min (0x1UL)  /*!< Min enumerator value of TASKS_ERASE field.                           */
  #define CACHE_TASKS_ERASE_TASKS_ERASE_Max (0x1UL)  /*!< Max enumerator value of TASKS_ERASE field.                           */
  #define CACHE_TASKS_ERASE_TASKS_ERASE_Trigger (0x1UL) /*!< Trigger task                                                      */


/* CACHE_STATUS: Status of the cache activities. */
  #define CACHE_STATUS_ResetValue (0x00000000UL)     /*!< Reset value of STATUS register.                                      */

/* READY @Bit 0 : Ready status. */
  #define CACHE_STATUS_READY_Pos (0UL)               /*!< Position of READY field.                                             */
  #define CACHE_STATUS_READY_Msk (0x1UL << CACHE_STATUS_READY_Pos) /*!< Bit mask of READY field.                               */
  #define CACHE_STATUS_READY_Min (0x0UL)             /*!< Min enumerator value of READY field.                                 */
  #define CACHE_STATUS_READY_Max (0x1UL)             /*!< Max enumerator value of READY field.                                 */
  #define CACHE_STATUS_READY_Ready (0x0UL)           /*!< Activity is done and ready for the next activity.                    */
  #define CACHE_STATUS_READY_Busy (0x1UL)            /*!< Activity is in progress.                                             */


/* CACHE_ENABLE: Enable cache. */
  #define CACHE_ENABLE_ResetValue (0x00000000UL)     /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bit 0 : Enable cache */
  #define CACHE_ENABLE_ENABLE_Pos (0UL)              /*!< Position of ENABLE field.                                            */
  #define CACHE_ENABLE_ENABLE_Msk (0x1UL << CACHE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                            */
  #define CACHE_ENABLE_ENABLE_Min (0x0UL)            /*!< Min enumerator value of ENABLE field.                                */
  #define CACHE_ENABLE_ENABLE_Max (0x1UL)            /*!< Max enumerator value of ENABLE field.                                */
  #define CACHE_ENABLE_ENABLE_Disabled (0x0UL)       /*!< Disable cache                                                        */
  #define CACHE_ENABLE_ENABLE_Enabled (0x1UL)        /*!< Enable cache                                                         */


/* CACHE_LINEADDR: Memory address covered by the line to be maintained. */
  #define CACHE_LINEADDR_ResetValue (0x00000000UL)   /*!< Reset value of LINEADDR register.                                    */

/* ADDR @Bits 0..31 : Address. */
  #define CACHE_LINEADDR_ADDR_Pos (0UL)              /*!< Position of ADDR field.                                              */
  #define CACHE_LINEADDR_ADDR_Msk (0xFFFFFFFFUL << CACHE_LINEADDR_ADDR_Pos) /*!< Bit mask of ADDR field.                       */


/* CACHE_DEBUGLOCK: Lock debug mode. */
  #define CACHE_DEBUGLOCK_ResetValue (0x00000000UL)  /*!< Reset value of DEBUGLOCK register.                                   */

/* DEBUGLOCK @Bit 0 : Lock debug mode */
  #define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL)        /*!< Position of DEBUGLOCK field.                                         */
  #define CACHE_DEBUGLOCK_DEBUGLOCK_Msk (0x1UL << CACHE_DEBUGLOCK_DEBUGLOCK_Pos) /*!< Bit mask of DEBUGLOCK field.             */
  #define CACHE_DEBUGLOCK_DEBUGLOCK_Min (0x0UL)      /*!< Min enumerator value of DEBUGLOCK field.                             */
  #define CACHE_DEBUGLOCK_DEBUGLOCK_Max (0x1UL)      /*!< Max enumerator value of DEBUGLOCK field.                             */
  #define CACHE_DEBUGLOCK_DEBUGLOCK_Unlocked (0x0UL) /*!< Debug mode unlocked                                                  */
  #define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (0x1UL)   /*!< Debug mode locked. Ignores any other value written.                  */


/* CACHE_WRITELOCK: Lock cache updates. */
  #define CACHE_WRITELOCK_ResetValue (0x00000000UL)  /*!< Reset value of WRITELOCK register.                                   */

/* WRITELOCK @Bit 0 : Lock cache updates */
  #define CACHE_WRITELOCK_WRITELOCK_Pos (0UL)        /*!< Position of WRITELOCK field.                                         */
  #define CACHE_WRITELOCK_WRITELOCK_Msk (0x1UL << CACHE_WRITELOCK_WRITELOCK_Pos) /*!< Bit mask of WRITELOCK field.             */
  #define CACHE_WRITELOCK_WRITELOCK_Min (0x0UL)      /*!< Min enumerator value of WRITELOCK field.                             */
  #define CACHE_WRITELOCK_WRITELOCK_Max (0x1UL)      /*!< Max enumerator value of WRITELOCK field.                             */
  #define CACHE_WRITELOCK_WRITELOCK_Unlocked (0x0UL) /*!< Cache updates unlocked                                               */
  #define CACHE_WRITELOCK_WRITELOCK_Locked (0x1UL)   /*!< Cache updates locked                                                 */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                         CACHEDATA                                         ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* =============================================== Struct CACHEDATA_SET_WAY_DU =============================================== */
/**
  * @brief DU [CACHEDATA_SET_WAY_DU] (unspecified)
  */
typedef struct {
  __IOM uint32_t  DATA[2];                           /*!< (@ 0x00000000) Cache data bits for DATA[q] in DU[p] (DataUnit) of
                                                                         SET[n], WAY[o].*/
} NRF_CACHEDATA_SET_WAY_DU_Type;                     /*!< Size = 8 (0x008)                                                     */
  #define CACHEDATA_SET_WAY_DU_MaxCount (4UL)        /*!< Size of DU[4] array.                                                 */
  #define CACHEDATA_SET_WAY_DU_MaxIndex (3UL)        /*!< Max index of DU[4] array.                                            */
  #define CACHEDATA_SET_WAY_DU_MinIndex (0UL)        /*!< Min index of DU[4] array.                                            */

/* CACHEDATA_SET_WAY_DU_DATA: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. */
  #define CACHEDATA_SET_WAY_DU_DATA_MaxCount (2UL)   /*!< Max size of DATA[2] array.                                           */
  #define CACHEDATA_SET_WAY_DU_DATA_MaxIndex (1UL)   /*!< Max index of DATA[2] array.                                          */
  #define CACHEDATA_SET_WAY_DU_DATA_MinIndex (0UL)   /*!< Min index of DATA[2] array.                                          */
  #define CACHEDATA_SET_WAY_DU_DATA_ResetValue (0x00000000UL) /*!< Reset value of DATA[2] register.                            */

/* Data @Bits 0..31 : Data */
  #define CACHEDATA_SET_WAY_DU_DATA_Data_Pos (0UL)   /*!< Position of Data field.                                              */
  #define CACHEDATA_SET_WAY_DU_DATA_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DU_DATA_Data_Pos) /*!< Bit mask of Data field. */



/* ================================================ Struct CACHEDATA_SET_WAY ================================================= */
/**
  * @brief WAY [CACHEDATA_SET_WAY] (unspecified)
  */
typedef struct {
  __IOM NRF_CACHEDATA_SET_WAY_DU_Type DU[4];         /*!< (@ 0x00000000) (unspecified)                                         */
} NRF_CACHEDATA_SET_WAY_Type;                        /*!< Size = 32 (0x020)                                                    */
  #define CACHEDATA_SET_WAY_MaxCount (2UL)           /*!< Size of WAY[2] array.                                                */
  #define CACHEDATA_SET_WAY_MaxIndex (1UL)           /*!< Max index of WAY[2] array.                                           */
  #define CACHEDATA_SET_WAY_MinIndex (0UL)           /*!< Min index of WAY[2] array.                                           */


/* ================================================== Struct CACHEDATA_SET =================================================== */
/**
  * @brief SET [CACHEDATA_SET] (unspecified)
  */
typedef struct {
  __IOM NRF_CACHEDATA_SET_WAY_Type WAY[2];           /*!< (@ 0x00000000) (unspecified)                                         */
} NRF_CACHEDATA_SET_Type;                            /*!< Size = 64 (0x040)                                                    */
  #define CACHEDATA_SET_MaxCount (128UL)             /*!< Size of SET[128] array.                                              */
  #define CACHEDATA_SET_MaxIndex (127UL)             /*!< Max index of SET[128] array.                                         */
  #define CACHEDATA_SET_MinIndex (0UL)               /*!< Min index of SET[128] array.                                         */

/* ==================================================== Struct CACHEDATA ===================================================== */
/**
  * @brief CACHEDATA
  */
  typedef struct {                                   /*!< CACHEDATA Structure                                                  */
    __IOM NRF_CACHEDATA_SET_Type SET[128];           /*!< (@ 0x00000000) (unspecified)                                         */
  } NRF_CACHEDATA_Type;                              /*!< Size = 8192 (0x2000)                                                 */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                         CACHEINFO                                         ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct CACHEINFO_SET_WAY ================================================= */
/**
  * @brief WAY [CACHEINFO_SET_WAY] (unspecified)
  */
typedef struct {
  __IOM uint32_t  INFO;                              /*!< (@ 0x00000000) Cache information for SET[n], WAY[o].                 */
} NRF_CACHEINFO_SET_WAY_Type;                        /*!< Size = 4 (0x004)                                                     */
  #define CACHEINFO_SET_WAY_MaxCount (2UL)           /*!< Size of WAY[2] array.                                                */
  #define CACHEINFO_SET_WAY_MaxIndex (1UL)           /*!< Max index of WAY[2] array.                                           */
  #define CACHEINFO_SET_WAY_MinIndex (0UL)           /*!< Min index of WAY[2] array.                                           */

/* CACHEINFO_SET_WAY_INFO: Cache information for SET[n], WAY[o]. */
  #define CACHEINFO_SET_WAY_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register.                                  */

/* TAG @Bits 0..19 : Cache tag. */
  #define CACHEINFO_SET_WAY_INFO_TAG_Pos (0UL)       /*!< Position of TAG field.                                               */
  #define CACHEINFO_SET_WAY_INFO_TAG_Msk (0xFFFFFUL << CACHEINFO_SET_WAY_INFO_TAG_Pos) /*!< Bit mask of TAG field.             */

/* DUV0 @Bit 24 : Data unit valid info. */
  #define CACHEINFO_SET_WAY_INFO_DUV0_Pos (24UL)     /*!< Position of DUV0 field.                                              */
  #define CACHEINFO_SET_WAY_INFO_DUV0_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV0_Pos) /*!< Bit mask of DUV0 field.              */
  #define CACHEINFO_SET_WAY_INFO_DUV0_Min (0x0UL)    /*!< Min enumerator value of DUV0 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV0_Max (0x1UL)    /*!< Max enumerator value of DUV0 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV0_Invalid (0x0UL) /*!< Invalid data unit                                                   */
  #define CACHEINFO_SET_WAY_INFO_DUV0_Valid (0x1UL)  /*!< Valid data unit                                                      */

/* DUV1 @Bit 25 : Data unit valid info. */
  #define CACHEINFO_SET_WAY_INFO_DUV1_Pos (25UL)     /*!< Position of DUV1 field.                                              */
  #define CACHEINFO_SET_WAY_INFO_DUV1_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV1_Pos) /*!< Bit mask of DUV1 field.              */
  #define CACHEINFO_SET_WAY_INFO_DUV1_Min (0x0UL)    /*!< Min enumerator value of DUV1 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV1_Max (0x1UL)    /*!< Max enumerator value of DUV1 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV1_Invalid (0x0UL) /*!< Invalid data unit                                                   */
  #define CACHEINFO_SET_WAY_INFO_DUV1_Valid (0x1UL)  /*!< Valid data unit                                                      */

/* DUV2 @Bit 26 : Data unit valid info. */
  #define CACHEINFO_SET_WAY_INFO_DUV2_Pos (26UL)     /*!< Position of DUV2 field.                                              */
  #define CACHEINFO_SET_WAY_INFO_DUV2_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV2_Pos) /*!< Bit mask of DUV2 field.              */
  #define CACHEINFO_SET_WAY_INFO_DUV2_Min (0x0UL)    /*!< Min enumerator value of DUV2 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV2_Max (0x1UL)    /*!< Max enumerator value of DUV2 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV2_Invalid (0x0UL) /*!< Invalid data unit                                                   */
  #define CACHEINFO_SET_WAY_INFO_DUV2_Valid (0x1UL)  /*!< Valid data unit                                                      */

/* DUV3 @Bit 27 : Data unit valid info. */
  #define CACHEINFO_SET_WAY_INFO_DUV3_Pos (27UL)     /*!< Position of DUV3 field.                                              */
  #define CACHEINFO_SET_WAY_INFO_DUV3_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_DUV3_Pos) /*!< Bit mask of DUV3 field.              */
  #define CACHEINFO_SET_WAY_INFO_DUV3_Min (0x0UL)    /*!< Min enumerator value of DUV3 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV3_Max (0x1UL)    /*!< Max enumerator value of DUV3 field.                                  */
  #define CACHEINFO_SET_WAY_INFO_DUV3_Invalid (0x0UL) /*!< Invalid data unit                                                   */
  #define CACHEINFO_SET_WAY_INFO_DUV3_Valid (0x1UL)  /*!< Valid data unit                                                      */

/* V @Bit 30 : Line valid bit. */
  #define CACHEINFO_SET_WAY_INFO_V_Pos (30UL)        /*!< Position of V field.                                                 */
  #define CACHEINFO_SET_WAY_INFO_V_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_V_Pos) /*!< Bit mask of V field.                       */
  #define CACHEINFO_SET_WAY_INFO_V_Min (0x0UL)       /*!< Min enumerator value of V field.                                     */
  #define CACHEINFO_SET_WAY_INFO_V_Max (0x1UL)       /*!< Max enumerator value of V field.                                     */
  #define CACHEINFO_SET_WAY_INFO_V_Invalid (0x0UL)   /*!< Invalid cache line                                                   */
  #define CACHEINFO_SET_WAY_INFO_V_Valid (0x1UL)     /*!< Valid cache line                                                     */

/* MRU @Bit 31 : Most recently used way. */
  #define CACHEINFO_SET_WAY_INFO_MRU_Pos (31UL)      /*!< Position of MRU field.                                               */
  #define CACHEINFO_SET_WAY_INFO_MRU_Msk (0x1UL << CACHEINFO_SET_WAY_INFO_MRU_Pos) /*!< Bit mask of MRU field.                 */
  #define CACHEINFO_SET_WAY_INFO_MRU_Min (0x0UL)     /*!< Min enumerator value of MRU field.                                   */
  #define CACHEINFO_SET_WAY_INFO_MRU_Max (0x1UL)     /*!< Max enumerator value of MRU field.                                   */
  #define CACHEINFO_SET_WAY_INFO_MRU_Way0 (0x0UL)    /*!< Way0 was most recently used                                          */
  #define CACHEINFO_SET_WAY_INFO_MRU_Way1 (0x1UL)    /*!< Way1 was most recently used                                          */



/* ================================================== Struct CACHEINFO_SET =================================================== */
/**
  * @brief SET [CACHEINFO_SET] (unspecified)
  */
typedef struct {
  __IOM NRF_CACHEINFO_SET_WAY_Type WAY[2];           /*!< (@ 0x00000000) (unspecified)                                         */
} NRF_CACHEINFO_SET_Type;                            /*!< Size = 8 (0x008)                                                     */
  #define CACHEINFO_SET_MaxCount (128UL)             /*!< Size of SET[128] array.                                              */
  #define CACHEINFO_SET_MaxIndex (127UL)             /*!< Max index of SET[128] array.                                         */
  #define CACHEINFO_SET_MinIndex (0UL)               /*!< Min index of SET[128] array.                                         */

/* ==================================================== Struct CACHEINFO ===================================================== */
/**
  * @brief CACHEINFO
  */
  typedef struct {                                   /*!< CACHEINFO Structure                                                  */
    __IOM NRF_CACHEINFO_SET_Type SET[128];           /*!< (@ 0x00000000) (unspecified)                                         */
  } NRF_CACHEINFO_Type;                              /*!< Size = 1024 (0x400)                                                  */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            CCM                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ===================================================== Struct CCM_KEY ====================================================== */
/**
  * @brief KEY [CCM_KEY] (unspecified)
  */
typedef struct {
  __OM  uint32_t  VALUE[4];                          /*!< (@ 0x00000000) 128-bit AES key                                       */
} NRF_CCM_KEY_Type;                                  /*!< Size = 16 (0x010)                                                    */

/* CCM_KEY_VALUE: 128-bit AES key */
  #define CCM_KEY_VALUE_MaxCount (4UL)               /*!< Max size of VALUE[4] array.                                          */
  #define CCM_KEY_VALUE_MaxIndex (3UL)               /*!< Max index of VALUE[4] array.                                         */
  #define CCM_KEY_VALUE_MinIndex (0UL)               /*!< Min index of VALUE[4] array.                                         */
  #define CCM_KEY_VALUE_ResetValue (0x00000000UL)    /*!< Reset value of VALUE[4] register.                                    */

/* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(i+1))-1 : (32*i) */
  #define CCM_KEY_VALUE_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
  #define CCM_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field.                      */



/* ==================================================== Struct CCM_NONCE ===================================================== */
/**
  * @brief NONCE [CCM_NONCE] (unspecified)
  */
typedef struct {
  __IOM uint32_t  VALUE[4];                          /*!< (@ 0x00000000) 13-byte NONCE vector Only the lower 13 bytes are used */
} NRF_CCM_NONCE_Type;                                /*!< Size = 16 (0x010)                                                    */

/* CCM_NONCE_VALUE: 13-byte NONCE vector Only the lower 13 bytes are used */
  #define CCM_NONCE_VALUE_MaxCount (4UL)             /*!< Max size of VALUE[4] array.                                          */
  #define CCM_NONCE_VALUE_MaxIndex (3UL)             /*!< Max index of VALUE[4] array.                                         */
  #define CCM_NONCE_VALUE_MinIndex (0UL)             /*!< Min index of VALUE[4] array.                                         */
  #define CCM_NONCE_VALUE_ResetValue (0x00000000UL)  /*!< Reset value of VALUE[4] register.                                    */

/* VALUE @Bits 0..31 : NONCE value, bits (32*(n+1))-1 : (32*n) */
  #define CCM_NONCE_VALUE_VALUE_Pos (0UL)            /*!< Position of VALUE field.                                             */
  #define CCM_NONCE_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_NONCE_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field.                  */



/* ====================================================== Struct CCM_IN ====================================================== */
/**
  * @brief IN [CCM_IN] IN EasyDMA channel
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Input pointer Points to a job list containing
                                                                         unencrypted CCM data structure in Encryption mode
                                                                         Points to a job list containing encrypted CCM data
                                                                         structure in Decryption mode*/
} NRF_CCM_IN_Type;                                   /*!< Size = 4 (0x004)                                                     */

/* CCM_IN_PTR: Input pointer Points to a job list containing unencrypted CCM data structure in Encryption mode Points to a job
                list containing encrypted CCM data structure in Decryption mode */

  #define CCM_IN_PTR_ResetValue (0x00000000UL)       /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Input pointer */
  #define CCM_IN_PTR_PTR_Pos (0UL)                   /*!< Position of PTR field.                                               */
  #define CCM_IN_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                  */



/* ===================================================== Struct CCM_OUT ====================================================== */
/**
  * @brief OUT [CCM_OUT] OUT EasyDMA channel
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Output pointer Points to a job list containing
                                                                         encrypted CCM data structure in Encryption mode Points
                                                                         to a job list containing decrypted CCM data structure
                                                                         in Decryption mode*/
} NRF_CCM_OUT_Type;                                  /*!< Size = 4 (0x004)                                                     */

/* CCM_OUT_PTR: Output pointer Points to a job list containing encrypted CCM data structure in Encryption mode Points to a job
                 list containing decrypted CCM data structure in Decryption mode */

  #define CCM_OUT_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Output pointer */
  #define CCM_OUT_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
  #define CCM_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */


/* ======================================================= Struct CCM ======================================================== */
/**
  * @brief AES CCM Mode Encryption
  */
  typedef struct {                                   /*!< CCM Structure                                                        */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start encryption/decryption. This operation will stop
                                                                         by itself when completed.*/
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop encryption/decryption                            */
    __OM uint32_t TASKS_RATEOVERRIDE;                /*!< (@ 0x00000008) Override DATARATE setting in MODE register with the
                                                                         contents of the RATEOVERRIDE register for any ongoing
                                                                         encryption/decryption*/
    __IM uint32_t RESERVED[29];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_RATEOVERRIDE;           /*!< (@ 0x00000088) Subscribe configuration for task RATEOVERRIDE         */
    __IM uint32_t RESERVED1[30];
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000104) Encrypt/decrypt complete or ended because of an error */
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000108) CCM error event                                       */
    __IM uint32_t RESERVED2[30];
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000184) Publish configuration for event END                   */
    __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x00000188) Publish configuration for event ERROR                 */
    __IM uint32_t RESERVED3[94];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED4[61];
    __IM uint32_t MACSTATUS;                         /*!< (@ 0x00000400) MAC check result                                      */
    __IM uint32_t ERRORSTATUS;                       /*!< (@ 0x00000404) Error status                                          */
    __IM uint32_t RESERVED5[62];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable                                                */
    __IOM uint32_t MODE;                             /*!< (@ 0x00000504) Operation mode                                        */
    __IM uint32_t RESERVED6[2];
    __IOM NRF_CCM_KEY_Type KEY;                      /*!< (@ 0x00000510) (unspecified)                                         */
    __IOM NRF_CCM_NONCE_Type NONCE;                  /*!< (@ 0x00000520) (unspecified)                                         */
    __IOM NRF_CCM_IN_Type IN;                        /*!< (@ 0x00000530) IN EasyDMA channel                                    */
    __IM uint32_t RESERVED7;
    __IOM NRF_CCM_OUT_Type OUT;                      /*!< (@ 0x00000538) OUT EasyDMA channel                                   */
    __IM uint32_t RESERVED8[2];
    __IOM uint32_t RATEOVERRIDE;                     /*!< (@ 0x00000544) Data rate override setting.                           */
    __IOM uint32_t ADATAMASK;                        /*!< (@ 0x00000548) CCM adata mask.                                       */
  } NRF_CCM_Type;                                    /*!< Size = 1356 (0x54C)                                                  */

/* CCM_TASKS_START: Start encryption/decryption. This operation will stop by itself when completed. */
  #define CCM_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
  #define CCM_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
  #define CCM_TASKS_START_TASKS_START_Msk (0x1UL << CCM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
  #define CCM_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
  #define CCM_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
  #define CCM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */


/* CCM_TASKS_STOP: Stop encryption/decryption */
  #define CCM_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop encryption/decryption */
  #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
  #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
  #define CCM_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
  #define CCM_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
  #define CCM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* CCM_TASKS_RATEOVERRIDE: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any
                            ongoing encryption/decryption */

  #define CCM_TASKS_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RATEOVERRIDE register.                    */

/* TASKS_RATEOVERRIDE @Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any
                               ongoing encryption/decryption */

  #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field.                       */
  #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask
                                                                            of TASKS_RATEOVERRIDE field.*/
  #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Min (0x1UL) /*!< Min enumerator value of TASKS_RATEOVERRIDE field.         */
  #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Max (0x1UL) /*!< Max enumerator value of TASKS_RATEOVERRIDE field.         */
  #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (0x1UL) /*!< Trigger task                                          */


/* CCM_SUBSCRIBE_START: Subscribe configuration for task START */
  #define CCM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define CCM_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define CCM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define CCM_SUBSCRIBE_START_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define CCM_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CCM_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define CCM_SUBSCRIBE_START_EN_Msk (0x1UL << CCM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
  #define CCM_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define CCM_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define CCM_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define CCM_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* CCM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define CCM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define CCM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define CCM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
  #define CCM_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define CCM_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define CCM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
  #define CCM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */


/* CCM_SUBSCRIBE_RATEOVERRIDE: Subscribe configuration for task RATEOVERRIDE */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RATEOVERRIDE register.            */

/* CHIDX @Bits 0..7 : DPPI channel that task RATEOVERRIDE will subscribe to */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field.            */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0x0UL) /*!< Disable subscription                                             */
  #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (0x1UL) /*!< Enable subscription                                               */


/* CCM_EVENTS_END: Encrypt/decrypt complete or ended because of an error */
  #define CCM_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : Encrypt/decrypt complete or ended because of an error */
  #define CCM_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
  #define CCM_EVENTS_END_EVENTS_END_Msk (0x1UL << CCM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
  #define CCM_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
  #define CCM_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
  #define CCM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
  #define CCM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */


/* CCM_EVENTS_ERROR: CCM error event */
  #define CCM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                                */

/* EVENTS_ERROR @Bit 0 : CCM error event */
  #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)    /*!< Position of EVENTS_ERROR field.                                      */
  #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.  */
  #define CCM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL)  /*!< Min enumerator value of EVENTS_ERROR field.                          */
  #define CCM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL)  /*!< Max enumerator value of EVENTS_ERROR field.                          */
  #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                 */


/* CCM_PUBLISH_END: Publish configuration for event END */
  #define CCM_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define CCM_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
  #define CCM_PUBLISH_END_CHIDX_Msk (0xFFUL << CCM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
  #define CCM_PUBLISH_END_CHIDX_Min (0x00UL)         /*!< Min value of CHIDX field.                                            */
  #define CCM_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CCM_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
  #define CCM_PUBLISH_END_EN_Msk (0x1UL << CCM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
  #define CCM_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
  #define CCM_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
  #define CCM_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
  #define CCM_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */


/* CCM_PUBLISH_ERROR: Publish configuration for event ERROR */
  #define CCM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
  #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define CCM_PUBLISH_ERROR_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define CCM_PUBLISH_ERROR_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CCM_PUBLISH_ERROR_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                              */
  #define CCM_PUBLISH_ERROR_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define CCM_PUBLISH_ERROR_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define CCM_PUBLISH_ERROR_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define CCM_PUBLISH_ERROR_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* CCM_INTENSET: Enable interrupt */
  #define CCM_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* END @Bit 1 : Write '1' to enable interrupt for event END */
  #define CCM_INTENSET_END_Pos (1UL)                 /*!< Position of END field.                                               */
  #define CCM_INTENSET_END_Msk (0x1UL << CCM_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
  #define CCM_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define CCM_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define CCM_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
  #define CCM_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define CCM_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* ERROR @Bit 2 : Write '1' to enable interrupt for event ERROR */
  #define CCM_INTENSET_ERROR_Pos (2UL)               /*!< Position of ERROR field.                                             */
  #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
  #define CCM_INTENSET_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
  #define CCM_INTENSET_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
  #define CCM_INTENSET_ERROR_Set (0x1UL)             /*!< Enable                                                               */
  #define CCM_INTENSET_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define CCM_INTENSET_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */


/* CCM_INTENCLR: Disable interrupt */
  #define CCM_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* END @Bit 1 : Write '1' to disable interrupt for event END */
  #define CCM_INTENCLR_END_Pos (1UL)                 /*!< Position of END field.                                               */
  #define CCM_INTENCLR_END_Msk (0x1UL << CCM_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
  #define CCM_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define CCM_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define CCM_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
  #define CCM_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define CCM_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* ERROR @Bit 2 : Write '1' to disable interrupt for event ERROR */
  #define CCM_INTENCLR_ERROR_Pos (2UL)               /*!< Position of ERROR field.                                             */
  #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
  #define CCM_INTENCLR_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
  #define CCM_INTENCLR_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
  #define CCM_INTENCLR_ERROR_Clear (0x1UL)           /*!< Disable                                                              */
  #define CCM_INTENCLR_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define CCM_INTENCLR_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */


/* CCM_MACSTATUS: MAC check result */
  #define CCM_MACSTATUS_ResetValue (0x00000000UL)    /*!< Reset value of MACSTATUS register.                                   */

/* MACSTATUS @Bit 0 : The result of the MAC check performed during the previous decryption operation */
  #define CCM_MACSTATUS_MACSTATUS_Pos (0UL)          /*!< Position of MACSTATUS field.                                         */
  #define CCM_MACSTATUS_MACSTATUS_Msk (0x1UL << CCM_MACSTATUS_MACSTATUS_Pos) /*!< Bit mask of MACSTATUS field.                 */
  #define CCM_MACSTATUS_MACSTATUS_Min (0x0UL)        /*!< Min enumerator value of MACSTATUS field.                             */
  #define CCM_MACSTATUS_MACSTATUS_Max (0x1UL)        /*!< Max enumerator value of MACSTATUS field.                             */
  #define CCM_MACSTATUS_MACSTATUS_CheckFailed (0x0UL) /*!< MAC check failed                                                    */
  #define CCM_MACSTATUS_MACSTATUS_CheckPassed (0x1UL) /*!< MAC check passed                                                    */


/* CCM_ERRORSTATUS: Error status */
  #define CCM_ERRORSTATUS_ResetValue (0x00000000UL)  /*!< Reset value of ERRORSTATUS register.                                 */

/* ERRORSTATUS @Bits 0..2 : Error status when the ERROR event is generated */
  #define CCM_ERRORSTATUS_ERRORSTATUS_Pos (0UL)      /*!< Position of ERRORSTATUS field.                                       */
  #define CCM_ERRORSTATUS_ERRORSTATUS_Msk (0x7UL << CCM_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field.       */
  #define CCM_ERRORSTATUS_ERRORSTATUS_Min (0x0UL)    /*!< Min enumerator value of ERRORSTATUS field.                           */
  #define CCM_ERRORSTATUS_ERRORSTATUS_Max (0x4UL)    /*!< Max enumerator value of ERRORSTATUS field.                           */
  #define CCM_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred                                             */
  #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before CCM data structure was read. */
  #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd (0x2UL) /*!< End of OUTPTR job list before CCM data structure was
                                                                      read.*/
  #define CCM_ERRORSTATUS_ERRORSTATUS_EncryptionTooSlow (0x3UL) /*!< Encryption of the unencrypted CCM data structure did not
                                                                     complete in time.*/
  #define CCM_ERRORSTATUS_ERRORSTATUS_DmaError (0x4UL) /*!< Bus error during DMA access.                                       */


/* CCM_ENABLE: Enable */
  #define CCM_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..1 : Enable or disable CCM */
  #define CCM_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
  #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
  #define CCM_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
  #define CCM_ENABLE_ENABLE_Max (0x2UL)              /*!< Max enumerator value of ENABLE field.                                */
  #define CCM_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
  #define CCM_ENABLE_ENABLE_Enabled (0x2UL)          /*!< Enable                                                               */


/* CCM_MODE: Operation mode */
  #define CCM_MODE_ResetValue (0x00000001UL)         /*!< Reset value of MODE register.                                        */

/* MODE @Bits 0..1 : The mode of operation to be used. The settings in this register apply when the CRYPT task is triggered. */
  #define CCM_MODE_MODE_Pos (0UL)                    /*!< Position of MODE field.                                              */
  #define CCM_MODE_MODE_Msk (0x3UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                          */
  #define CCM_MODE_MODE_Min (0x0UL)                  /*!< Min enumerator value of MODE field.                                  */
  #define CCM_MODE_MODE_Max (0x2UL)                  /*!< Max enumerator value of MODE field.                                  */
  #define CCM_MODE_MODE_Encryption (0x0UL)           /*!< AES CCM packet encryption mode                                       */
  #define CCM_MODE_MODE_Decryption (0x1UL)           /*!< This mode will run CCM decryption in the speed of the DATARATE field.*/
  #define CCM_MODE_MODE_FastDecryption (0x2UL)       /*!< AES CCM decryption mode.                                             */

/* PROTOCOL @Bits 8..9 : Protocol and packet format selection */
  #define CCM_MODE_PROTOCOL_Pos (8UL)                /*!< Position of PROTOCOL field.                                          */
  #define CCM_MODE_PROTOCOL_Msk (0x3UL << CCM_MODE_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field.                              */
  #define CCM_MODE_PROTOCOL_Min (0x0UL)              /*!< Min enumerator value of PROTOCOL field.                              */
  #define CCM_MODE_PROTOCOL_Max (0x1UL)              /*!< Max enumerator value of PROTOCOL field.                              */
  #define CCM_MODE_PROTOCOL_Ble (0x0UL)              /*!< Bluetooth Low Energy packet format                                   */
  #define CCM_MODE_PROTOCOL_Ieee802154 (0x1UL)       /*!< 802.15.4 packet format                                               */

/* DATARATE @Bits 16..18 : Radio data rate that the CCM shall run synchronous with */
  #define CCM_MODE_DATARATE_Pos (16UL)               /*!< Position of DATARATE field.                                          */
  #define CCM_MODE_DATARATE_Msk (0x7UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field.                              */
  #define CCM_MODE_DATARATE_Min (0x0UL)              /*!< Min enumerator value of DATARATE field.                              */
  #define CCM_MODE_DATARATE_Max (0x5UL)              /*!< Max enumerator value of DATARATE field.                              */
  #define CCM_MODE_DATARATE_125Kbit (0x0UL)          /*!< 125 Kbps                                                             */
  #define CCM_MODE_DATARATE_250Kbit (0x1UL)          /*!< 250 Kbps                                                             */
  #define CCM_MODE_DATARATE_500Kbit (0x2UL)          /*!< 500 Kbps                                                             */
  #define CCM_MODE_DATARATE_1Mbit (0x3UL)            /*!< 1 Mbps                                                               */
  #define CCM_MODE_DATARATE_2Mbit (0x4UL)            /*!< 2 Mbps                                                               */
  #define CCM_MODE_DATARATE_4Mbit (0x5UL)            /*!< 4 Mbps                                                               */

/* MACLEN @Bits 24..26 : CCM MAC length (bytes) */
  #define CCM_MODE_MACLEN_Pos (24UL)                 /*!< Position of MACLEN field.                                            */
  #define CCM_MODE_MACLEN_Msk (0x7UL << CCM_MODE_MACLEN_Pos) /*!< Bit mask of MACLEN field.                                    */
  #define CCM_MODE_MACLEN_Min (0x0UL)                /*!< Min enumerator value of MACLEN field.                                */
  #define CCM_MODE_MACLEN_Max (0x7UL)                /*!< Max enumerator value of MACLEN field.                                */
  #define CCM_MODE_MACLEN_M0 (0x0UL)                 /*!< M = 0 This is a special case for CCM* where encryption is required but
                                                          not authentication*/
  #define CCM_MODE_MACLEN_M4 (0x1UL)                 /*!< M = 4                                                                */
  #define CCM_MODE_MACLEN_M6 (0x2UL)                 /*!< M = 6                                                                */
  #define CCM_MODE_MACLEN_M8 (0x3UL)                 /*!< M = 8                                                                */
  #define CCM_MODE_MACLEN_M10 (0x4UL)                /*!< M = 10                                                               */
  #define CCM_MODE_MACLEN_M12 (0x5UL)                /*!< M = 12                                                               */
  #define CCM_MODE_MACLEN_M14 (0x6UL)                /*!< M = 14                                                               */
  #define CCM_MODE_MACLEN_M16 (0x7UL)                /*!< M = 16                                                               */


/* CCM_RATEOVERRIDE: Data rate override setting. */
  #define CCM_RATEOVERRIDE_ResetValue (0x00000002UL) /*!< Reset value of RATEOVERRIDE register.                                */

/* RATEOVERRIDE @Bits 0..2 : Data rate override setting. */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL)    /*!< Position of RATEOVERRIDE field.                                      */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x7UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field.  */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_Min (0x0UL)  /*!< Min enumerator value of RATEOVERRIDE field.                          */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_Max (0x5UL)  /*!< Max enumerator value of RATEOVERRIDE field.                          */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbit (0x0UL) /*!< 125 Kbps                                                          */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbit (0x2UL) /*!< 500 Kbps                                                          */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0x3UL) /*!< 1 Mbps                                                              */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (0x4UL) /*!< 2 Mbps                                                              */
  #define CCM_RATEOVERRIDE_RATEOVERRIDE_4Mbit (0x5UL) /*!< 4 Mbps                                                              */


/* CCM_ADATAMASK: CCM adata mask. */
  #define CCM_ADATAMASK_ResetValue (0x000000E3UL)    /*!< Reset value of ADATAMASK register.                                   */

/* ADATAMASK @Bits 0..7 : CCM adata mask. */
  #define CCM_ADATAMASK_ADATAMASK_Pos (0UL)          /*!< Position of ADATAMASK field.                                         */
  #define CCM_ADATAMASK_ADATAMASK_Msk (0xFFUL << CCM_ADATAMASK_ADATAMASK_Pos) /*!< Bit mask of ADATAMASK field.                */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           CLIC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ==================================================== Struct CLIC_CLIC ===================================================== */
/**
  * @brief CLIC [CLIC_CLIC] (unspecified)
  */
typedef struct {
  __IM  uint32_t  CLICCFG;                           /*!< (@ 0x00000000) CLIC configuration.                                   */
  __IM  uint32_t  CLICINFO;                          /*!< (@ 0x00000004) CLIC information.                                     */
  __IM  uint32_t  RESERVED[1022];
  __IOM uint32_t  CLICINT[271];                      /*!< (@ 0x00001000) Interrupt control register for IRQ number [n].        */
} NRF_CLIC_CLIC_Type;                                /*!< Size = 5180 (0x143C)                                                 */

/* CLIC_CLIC_CLICCFG: CLIC configuration. */
  #define CLIC_CLIC_CLICCFG_ResetValue (0x00000011UL) /*!< Reset value of CLICCFG register.                                    */

/* NVBITS @Bit 0 : Selective interrupt hardware vectoring. */
  #define CLIC_CLIC_CLICCFG_NVBITS_Pos (0UL)         /*!< Position of NVBITS field.                                            */
  #define CLIC_CLIC_CLICCFG_NVBITS_Msk (0x1UL << CLIC_CLIC_CLICCFG_NVBITS_Pos) /*!< Bit mask of NVBITS field.                  */
  #define CLIC_CLIC_CLICCFG_NVBITS_Min (0x1UL)       /*!< Min enumerator value of NVBITS field.                                */
  #define CLIC_CLIC_CLICCFG_NVBITS_Max (0x1UL)       /*!< Max enumerator value of NVBITS field.                                */
  #define CLIC_CLIC_CLICCFG_NVBITS_Implemented (0x1UL) /*!< Selective interrupt hardware vectoring is implemented              */

/* NLBITS @Bits 1..4 : Interrupt level encoding. */
  #define CLIC_CLIC_CLICCFG_NLBITS_Pos (1UL)         /*!< Position of NLBITS field.                                            */
  #define CLIC_CLIC_CLICCFG_NLBITS_Msk (0xFUL << CLIC_CLIC_CLICCFG_NLBITS_Pos) /*!< Bit mask of NLBITS field.                  */
  #define CLIC_CLIC_CLICCFG_NLBITS_Min (0x8UL)       /*!< Min enumerator value of NLBITS field.                                */
  #define CLIC_CLIC_CLICCFG_NLBITS_Max (0x8UL)       /*!< Max enumerator value of NLBITS field.                                */
  #define CLIC_CLIC_CLICCFG_NLBITS_Eight (0x8UL)     /*!< 8 bits = interrupt levels encoded in eight bits                      */

/* NMBITS @Bits 5..6 : Interrupt privilege mode. */
  #define CLIC_CLIC_CLICCFG_NMBITS_Pos (5UL)         /*!< Position of NMBITS field.                                            */
  #define CLIC_CLIC_CLICCFG_NMBITS_Msk (0x3UL << CLIC_CLIC_CLICCFG_NMBITS_Pos) /*!< Bit mask of NMBITS field.                  */
  #define CLIC_CLIC_CLICCFG_NMBITS_Min (0x0UL)       /*!< Min enumerator value of NMBITS field.                                */
  #define CLIC_CLIC_CLICCFG_NMBITS_Max (0x0UL)       /*!< Max enumerator value of NMBITS field.                                */
  #define CLIC_CLIC_CLICCFG_NMBITS_ModeM (0x0UL)     /*!< All interrupts are M-mode only                                       */


/* CLIC_CLIC_CLICINFO: CLIC information. */
  #define CLIC_CLIC_CLICINFO_ResetValue (0x00401FFFUL) /*!< Reset value of CLICINFO register.                                  */

/* NUMINTERRUPTS @Bits 0..12 : Maximum number of interrupts supported. */
  #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos (0UL) /*!< Position of NUMINTERRUPTS field.                                     */
  #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Msk (0x1FFFUL << CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos) /*!< Bit mask of NUMINTERRUPTS
                                                                            field.*/

/* VERSION @Bits 13..20 : Version */
  #define CLIC_CLIC_CLICINFO_VERSION_Pos (13UL)      /*!< Position of VERSION field.                                           */
  #define CLIC_CLIC_CLICINFO_VERSION_Msk (0xFFUL << CLIC_CLIC_CLICINFO_VERSION_Pos) /*!< Bit mask of VERSION field.            */

/* NUMTRIGGER @Bits 25..30 : Number of maximum interrupt triggers supported */
  #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos (25UL)   /*!< Position of NUMTRIGGER field.                                        */
  #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Msk (0x3FUL << CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos) /*!< Bit mask of NUMTRIGGER field.   */


/* CLIC_CLIC_CLICINT: Interrupt control register for IRQ number [n]. */
  #define CLIC_CLIC_CLICINT_MaxCount (271UL)         /*!< Max size of CLICINT[271] array.                                      */
  #define CLIC_CLIC_CLICINT_MaxIndex (270UL)         /*!< Max index of CLICINT[271] array.                                     */
  #define CLIC_CLIC_CLICINT_MinIndex (0UL)           /*!< Min index of CLICINT[271] array.                                     */
  #define CLIC_CLIC_CLICINT_ResetValue (0x3FC30000UL) /*!< Reset value of CLICINT[271] register.                               */

/* IP @Bit 0 : Interrupt Pending bit. */
  #define CLIC_CLIC_CLICINT_IP_Pos (0UL)             /*!< Position of IP field.                                                */
  #define CLIC_CLIC_CLICINT_IP_Msk (0x1UL << CLIC_CLIC_CLICINT_IP_Pos) /*!< Bit mask of IP field.                              */
  #define CLIC_CLIC_CLICINT_IP_Min (0x0UL)           /*!< Min enumerator value of IP field.                                    */
  #define CLIC_CLIC_CLICINT_IP_Max (0x1UL)           /*!< Max enumerator value of IP field.                                    */
  #define CLIC_CLIC_CLICINT_IP_NotPending (0x0UL)    /*!< Interrupt not pending                                                */
  #define CLIC_CLIC_CLICINT_IP_Pending (0x1UL)       /*!< Interrupt pending                                                    */

/* READ1 @Bits 1..7 : Read as 0, write ignored. */
  #define CLIC_CLIC_CLICINT_READ1_Pos (1UL)          /*!< Position of READ1 field.                                             */
  #define CLIC_CLIC_CLICINT_READ1_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ1_Pos) /*!< Bit mask of READ1 field.                    */

/* IE @Bit 8 : Interrupt enable bit. */
  #define CLIC_CLIC_CLICINT_IE_Pos (8UL)             /*!< Position of IE field.                                                */
  #define CLIC_CLIC_CLICINT_IE_Msk (0x1UL << CLIC_CLIC_CLICINT_IE_Pos) /*!< Bit mask of IE field.                              */
  #define CLIC_CLIC_CLICINT_IE_Min (0x0UL)           /*!< Min enumerator value of IE field.                                    */
  #define CLIC_CLIC_CLICINT_IE_Max (0x1UL)           /*!< Max enumerator value of IE field.                                    */
  #define CLIC_CLIC_CLICINT_IE_Disabled (0x0UL)      /*!< Interrupt disabled                                                   */
  #define CLIC_CLIC_CLICINT_IE_Enabled (0x1UL)       /*!< Interrupt enabled                                                    */

/* READ2 @Bits 9..15 : Read as 0, write ignored. */
  #define CLIC_CLIC_CLICINT_READ2_Pos (9UL)          /*!< Position of READ2 field.                                             */
  #define CLIC_CLIC_CLICINT_READ2_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ2_Pos) /*!< Bit mask of READ2 field.                    */

/* SHV @Bit 16 : Selective Hardware Vectoring. */
  #define CLIC_CLIC_CLICINT_SHV_Pos (16UL)           /*!< Position of SHV field.                                               */
  #define CLIC_CLIC_CLICINT_SHV_Msk (0x1UL << CLIC_CLIC_CLICINT_SHV_Pos) /*!< Bit mask of SHV field.                           */
  #define CLIC_CLIC_CLICINT_SHV_Min (0x1UL)          /*!< Min enumerator value of SHV field.                                   */
  #define CLIC_CLIC_CLICINT_SHV_Max (0x1UL)          /*!< Max enumerator value of SHV field.                                   */
  #define CLIC_CLIC_CLICINT_SHV_Vectored (0x1UL)     /*!< Hardware vectored                                                    */

/* TRIG @Bits 17..18 : Trigger type and polarity for each interrupt input. */
  #define CLIC_CLIC_CLICINT_TRIG_Pos (17UL)          /*!< Position of TRIG field.                                              */
  #define CLIC_CLIC_CLICINT_TRIG_Msk (0x3UL << CLIC_CLIC_CLICINT_TRIG_Pos) /*!< Bit mask of TRIG field.                        */
  #define CLIC_CLIC_CLICINT_TRIG_Min (0x1UL)         /*!< Min enumerator value of TRIG field.                                  */
  #define CLIC_CLIC_CLICINT_TRIG_Max (0x1UL)         /*!< Max enumerator value of TRIG field.                                  */
  #define CLIC_CLIC_CLICINT_TRIG_EdgeTriggered (0x1UL) /*!< Interrupts are edge-triggered                                      */

/* MODE @Bits 22..23 : Privilege mode. */
  #define CLIC_CLIC_CLICINT_MODE_Pos (22UL)          /*!< Position of MODE field.                                              */
  #define CLIC_CLIC_CLICINT_MODE_Msk (0x3UL << CLIC_CLIC_CLICINT_MODE_Pos) /*!< Bit mask of MODE field.                        */
  #define CLIC_CLIC_CLICINT_MODE_Min (0x3UL)         /*!< Min enumerator value of MODE field.                                  */
  #define CLIC_CLIC_CLICINT_MODE_Max (0x3UL)         /*!< Max enumerator value of MODE field.                                  */
  #define CLIC_CLIC_CLICINT_MODE_MachineMode (0x3UL) /*!< Machine mode                                                         */

/* PRIORITY @Bits 24..31 : Interrupt priority level */
  #define CLIC_CLIC_CLICINT_PRIORITY_Pos (24UL)      /*!< Position of PRIORITY field.                                          */
  #define CLIC_CLIC_CLICINT_PRIORITY_Msk (0xFFUL << CLIC_CLIC_CLICINT_PRIORITY_Pos) /*!< Bit mask of PRIORITY field.           */
  #define CLIC_CLIC_CLICINT_PRIORITY_Min (0x3FUL)    /*!< Min enumerator value of PRIORITY field.                              */
  #define CLIC_CLIC_CLICINT_PRIORITY_Max (0xFFUL)    /*!< Max enumerator value of PRIORITY field.                              */
  #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL0 (0x3FUL) /*!< Priority level 0                                                 */
  #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL1 (0x7FUL) /*!< Priority level 1                                                 */
  #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL2 (0xBFUL) /*!< Priority level 2                                                 */
  #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL3 (0xFFUL) /*!< Priority level 3                                                 */


/* ======================================================= Struct CLIC ======================================================= */
/**
  * @brief VPR CLIC registers
  */
  typedef struct {                                   /*!< CLIC Structure                                                       */
    __IOM NRF_CLIC_CLIC_Type CLIC;                   /*!< (@ 0x00000000) (unspecified)                                         */
  } NRF_CLIC_Type;                                   /*!< Size = 5180 (0x143C)                                                 */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           CLOCK                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ===================================================== Struct CLOCK_XO ===================================================== */
/**
  * @brief XO [CLOCK_XO] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __IM  uint32_t  RUN;                               /*!< (@ 0x00000008) Indicates that XOSTART task was triggered             */
  __IM  uint32_t  STAT;                              /*!< (@ 0x0000000C) XO status                                             */
} NRF_CLOCK_XO_Type;                                 /*!< Size = 16 (0x010)                                                    */

/* CLOCK_XO_RUN: Indicates that XOSTART task was triggered */
  #define CLOCK_XO_RUN_ResetValue (0x00000000UL)     /*!< Reset value of RUN register.                                         */

/* STATUS @Bit 0 : XOSTART task triggered or not */
  #define CLOCK_XO_RUN_STATUS_Pos (0UL)              /*!< Position of STATUS field.                                            */
  #define CLOCK_XO_RUN_STATUS_Msk (0x1UL << CLOCK_XO_RUN_STATUS_Pos) /*!< Bit mask of STATUS field.                            */
  #define CLOCK_XO_RUN_STATUS_Min (0x0UL)            /*!< Min enumerator value of STATUS field.                                */
  #define CLOCK_XO_RUN_STATUS_Max (0x1UL)            /*!< Max enumerator value of STATUS field.                                */
  #define CLOCK_XO_RUN_STATUS_NotTriggered (0x0UL)   /*!< Task not triggered                                                   */
  #define CLOCK_XO_RUN_STATUS_Triggered (0x1UL)      /*!< Task triggered                                                       */


/* CLOCK_XO_STAT: XO status */
  #define CLOCK_XO_STAT_ResetValue (0x00000000UL)    /*!< Reset value of STAT register.                                        */

/* STATE @Bit 16 : XO state (Running between START task and STOPPED event) */
  #define CLOCK_XO_STAT_STATE_Pos (16UL)             /*!< Position of STATE field.                                             */
  #define CLOCK_XO_STAT_STATE_Msk (0x1UL << CLOCK_XO_STAT_STATE_Pos) /*!< Bit mask of STATE field.                             */
  #define CLOCK_XO_STAT_STATE_Min (0x0UL)            /*!< Min enumerator value of STATE field.                                 */
  #define CLOCK_XO_STAT_STATE_Max (0x1UL)            /*!< Max enumerator value of STATE field.                                 */
  #define CLOCK_XO_STAT_STATE_NotRunning (0x0UL)     /*!< XO is not running                                                    */
  #define CLOCK_XO_STAT_STATE_Running (0x1UL)        /*!< XO is running                                                        */



/* ==================================================== Struct CLOCK_PLL ===================================================== */
/**
  * @brief PLL [CLOCK_PLL] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __IM  uint32_t  RUN;                               /*!< (@ 0x00000008) Indicates that PLLSTART task was triggered            */
  __IM  uint32_t  STAT;                              /*!< (@ 0x0000000C) Which PLL settings were selected when triggering START
                                                                         task*/
} NRF_CLOCK_PLL_Type;                                /*!< Size = 16 (0x010)                                                    */

/* CLOCK_PLL_RUN: Indicates that PLLSTART task was triggered */
  #define CLOCK_PLL_RUN_ResetValue (0x00000000UL)    /*!< Reset value of RUN register.                                         */

/* STATUS @Bit 0 : PLLSTART task triggered or not */
  #define CLOCK_PLL_RUN_STATUS_Pos (0UL)             /*!< Position of STATUS field.                                            */
  #define CLOCK_PLL_RUN_STATUS_Msk (0x1UL << CLOCK_PLL_RUN_STATUS_Pos) /*!< Bit mask of STATUS field.                          */
  #define CLOCK_PLL_RUN_STATUS_Min (0x0UL)           /*!< Min enumerator value of STATUS field.                                */
  #define CLOCK_PLL_RUN_STATUS_Max (0x1UL)           /*!< Max enumerator value of STATUS field.                                */
  #define CLOCK_PLL_RUN_STATUS_NotTriggered (0x0UL)  /*!< Task not triggered                                                   */
  #define CLOCK_PLL_RUN_STATUS_Triggered (0x1UL)     /*!< Task triggered                                                       */


/* CLOCK_PLL_STAT: Which PLL settings were selected when triggering START task */
  #define CLOCK_PLL_STAT_ResetValue (0x00000000UL)   /*!< Reset value of STAT register.                                        */

/* STATE @Bit 16 : PLL state (Running between START task and STOPPED event) */
  #define CLOCK_PLL_STAT_STATE_Pos (16UL)            /*!< Position of STATE field.                                             */
  #define CLOCK_PLL_STAT_STATE_Msk (0x1UL << CLOCK_PLL_STAT_STATE_Pos) /*!< Bit mask of STATE field.                           */
  #define CLOCK_PLL_STAT_STATE_Min (0x0UL)           /*!< Min enumerator value of STATE field.                                 */
  #define CLOCK_PLL_STAT_STATE_Max (0x1UL)           /*!< Max enumerator value of STATE field.                                 */
  #define CLOCK_PLL_STAT_STATE_NotRunning (0x0UL)    /*!< PLL is not running                                                   */
  #define CLOCK_PLL_STAT_STATE_Running (0x1UL)       /*!< PLL is running                                                       */



/* =================================================== Struct CLOCK_LFCLK ==================================================== */
/**
  * @brief LFCLK [CLOCK_LFCLK] (unspecified)
  */
typedef struct {
  __IOM uint32_t  SRC;                               /*!< (@ 0x00000000) Clock source for LFCLK                                */
  __IM  uint32_t  RESERVED;
  __IM  uint32_t  RUN;                               /*!< (@ 0x00000008) Indicates that LFCLKSTART task was triggered          */
  __IM  uint32_t  STAT;                              /*!< (@ 0x0000000C) Copy of LFCLK.SRCCOPY register, set when LFCLKSTARTED
                                                                         event is triggered.*/
  __IOM uint32_t  SRCCOPY;                           /*!< (@ 0x00000010) Copy of LFCLK.SRC register, set when LFCLKSTART task is
                                                                         triggered*/
} NRF_CLOCK_LFCLK_Type;                              /*!< Size = 20 (0x014)                                                    */

/* CLOCK_LFCLK_SRC: Clock source for LFCLK */
  #define CLOCK_LFCLK_SRC_ResetValue (0x00000000UL)  /*!< Reset value of SRC register.                                         */

/* SRC @Bits 0..1 : Select which LFCLK source is started by the LFCLKSTART task */
  #define CLOCK_LFCLK_SRC_SRC_Pos (0UL)              /*!< Position of SRC field.                                               */
  #define CLOCK_LFCLK_SRC_SRC_Msk (0x3UL << CLOCK_LFCLK_SRC_SRC_Pos) /*!< Bit mask of SRC field.                               */
  #define CLOCK_LFCLK_SRC_SRC_Min (0x0UL)            /*!< Min enumerator value of SRC field.                                   */
  #define CLOCK_LFCLK_SRC_SRC_Max (0x2UL)            /*!< Max enumerator value of SRC field.                                   */
  #define CLOCK_LFCLK_SRC_SRC_LFRC (0x0UL)           /*!< 32.768 kHz RC oscillator                                             */
  #define CLOCK_LFCLK_SRC_SRC_LFXO (0x1UL)           /*!< 32.768 kHz crystal oscillator                                        */
  #define CLOCK_LFCLK_SRC_SRC_LFSYNT (0x2UL)         /*!< 32.768 kHz synthesized from HFCLK                                    */


/* CLOCK_LFCLK_RUN: Indicates that LFCLKSTART task was triggered */
  #define CLOCK_LFCLK_RUN_ResetValue (0x00000000UL)  /*!< Reset value of RUN register.                                         */

/* STATUS @Bit 0 : LFCLKSTART task triggered or not */
  #define CLOCK_LFCLK_RUN_STATUS_Pos (0UL)           /*!< Position of STATUS field.                                            */
  #define CLOCK_LFCLK_RUN_STATUS_Msk (0x1UL << CLOCK_LFCLK_RUN_STATUS_Pos) /*!< Bit mask of STATUS field.                      */
  #define CLOCK_LFCLK_RUN_STATUS_Min (0x0UL)         /*!< Min enumerator value of STATUS field.                                */
  #define CLOCK_LFCLK_RUN_STATUS_Max (0x1UL)         /*!< Max enumerator value of STATUS field.                                */
  #define CLOCK_LFCLK_RUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered                                                  */
  #define CLOCK_LFCLK_RUN_STATUS_Triggered (0x1UL)   /*!< Task triggered                                                       */


/* CLOCK_LFCLK_STAT: Copy of LFCLK.SRCCOPY register, set when LFCLKSTARTED event is triggered. */
  #define CLOCK_LFCLK_STAT_ResetValue (0x00000000UL) /*!< Reset value of STAT register.                                        */

/* SRC @Bits 0..1 : Value of LFCLK.SRCCOPY register when LFCLKSTARTED event was triggered */
  #define CLOCK_LFCLK_STAT_SRC_Pos (0UL)             /*!< Position of SRC field.                                               */
  #define CLOCK_LFCLK_STAT_SRC_Msk (0x3UL << CLOCK_LFCLK_STAT_SRC_Pos) /*!< Bit mask of SRC field.                             */
  #define CLOCK_LFCLK_STAT_SRC_Min (0x0UL)           /*!< Min enumerator value of SRC field.                                   */
  #define CLOCK_LFCLK_STAT_SRC_Max (0x2UL)           /*!< Max enumerator value of SRC field.                                   */
  #define CLOCK_LFCLK_STAT_SRC_LFRC (0x0UL)          /*!< 32.768 kHz RC oscillator                                             */
  #define CLOCK_LFCLK_STAT_SRC_LFXO (0x1UL)          /*!< 32.768 kHz crystal oscillator                                        */
  #define CLOCK_LFCLK_STAT_SRC_LFSYNT (0x2UL)        /*!< 32.768 kHz synthesized from HFCLK                                    */

/* ALWAYSRUNNING @Bit 4 : ALWAYSRUN activated */
  #define CLOCK_LFCLK_STAT_ALWAYSRUNNING_Pos (4UL)   /*!< Position of ALWAYSRUNNING field.                                     */
  #define CLOCK_LFCLK_STAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLK_STAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING
                                                                            field.*/
  #define CLOCK_LFCLK_STAT_ALWAYSRUNNING_Min (0x0UL) /*!< Min enumerator value of ALWAYSRUNNING field.                         */
  #define CLOCK_LFCLK_STAT_ALWAYSRUNNING_Max (0x1UL) /*!< Max enumerator value of ALWAYSRUNNING field.                         */
  #define CLOCK_LFCLK_STAT_ALWAYSRUNNING_NotRunning (0x0UL) /*!< Automatic clock control enabled                               */
  #define CLOCK_LFCLK_STAT_ALWAYSRUNNING_Running (0x1UL) /*!< Oscillator is always running                                     */

/* STATE @Bit 16 : LFCLK state (Running between START task and STOPPED event) */
  #define CLOCK_LFCLK_STAT_STATE_Pos (16UL)          /*!< Position of STATE field.                                             */
  #define CLOCK_LFCLK_STAT_STATE_Msk (0x1UL << CLOCK_LFCLK_STAT_STATE_Pos) /*!< Bit mask of STATE field.                       */
  #define CLOCK_LFCLK_STAT_STATE_Min (0x0UL)         /*!< Min enumerator value of STATE field.                                 */
  #define CLOCK_LFCLK_STAT_STATE_Max (0x1UL)         /*!< Max enumerator value of STATE field.                                 */
  #define CLOCK_LFCLK_STAT_STATE_NotRunning (0x0UL)  /*!< LFCLK not running                                                    */
  #define CLOCK_LFCLK_STAT_STATE_Running (0x1UL)     /*!< LFCLK running                                                        */


/* CLOCK_LFCLK_SRCCOPY: Copy of LFCLK.SRC register, set when LFCLKSTART task is triggered */
  #define CLOCK_LFCLK_SRCCOPY_ResetValue (0x00000000UL) /*!< Reset value of SRCCOPY register.                                  */

/* SRC @Bits 0..1 : Value of LFCLK.SRC register when LFCLKSTART task was triggered */
  #define CLOCK_LFCLK_SRCCOPY_SRC_Pos (0UL)          /*!< Position of SRC field.                                               */
  #define CLOCK_LFCLK_SRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLK_SRCCOPY_SRC_Pos) /*!< Bit mask of SRC field.                       */
  #define CLOCK_LFCLK_SRCCOPY_SRC_Min (0x0UL)        /*!< Min enumerator value of SRC field.                                   */
  #define CLOCK_LFCLK_SRCCOPY_SRC_Max (0x2UL)        /*!< Max enumerator value of SRC field.                                   */
  #define CLOCK_LFCLK_SRCCOPY_SRC_LFRC (0x0UL)       /*!< 32.768 kHz RC oscillator                                             */
  #define CLOCK_LFCLK_SRCCOPY_SRC_LFXO (0x1UL)       /*!< 32.768 kHz crystal oscillator                                        */
  #define CLOCK_LFCLK_SRCCOPY_SRC_LFSYNT (0x2UL)     /*!< 32.768 kHz synthesized from HFCLK                                    */


/* ====================================================== Struct CLOCK ======================================================= */
/**
  * @brief Clock management
  */
  typedef struct {                                   /*!< CLOCK Structure                                                      */
    __OM uint32_t TASKS_XOSTART;                     /*!< (@ 0x00000000) Start crystal oscillator (HFXO)                       */
    __OM uint32_t TASKS_XOSTOP;                      /*!< (@ 0x00000004) Stop crystal oscillator (HFXO)                        */
    __OM uint32_t TASKS_PLLSTART;                    /*!< (@ 0x00000008) Start PLL and keep it running, regardless of the
                                                                         automatic clock requests*/
    __OM uint32_t TASKS_PLLSTOP;                     /*!< (@ 0x0000000C) Stop PLL                                              */
    __OM uint32_t TASKS_LFCLKSTART;                  /*!< (@ 0x00000010) Start LFCLK source as selected in LFCLK.SRC           */
    __OM uint32_t TASKS_LFCLKSTOP;                   /*!< (@ 0x00000014) Stop LFCLK source                                     */
    __OM uint32_t TASKS_CAL;                         /*!< (@ 0x00000018) Start calibration of LFRC oscillator                  */
    __OM uint32_t TASKS_XOTUNE;                      /*!< (@ 0x0000001C) Request tuning for HFXO                               */
    __OM uint32_t TASKS_XOTUNEABORT;                 /*!< (@ 0x00000020) Abort tuning for HFXO                                 */
    __IM uint32_t RESERVED[23];
    __IOM uint32_t SUBSCRIBE_XOSTART;                /*!< (@ 0x00000080) Subscribe configuration for task XOSTART              */
    __IOM uint32_t SUBSCRIBE_XOSTOP;                 /*!< (@ 0x00000084) Subscribe configuration for task XOSTOP               */
    __IOM uint32_t SUBSCRIBE_PLLSTART;               /*!< (@ 0x00000088) Subscribe configuration for task PLLSTART             */
    __IOM uint32_t SUBSCRIBE_PLLSTOP;                /*!< (@ 0x0000008C) Subscribe configuration for task PLLSTOP              */
    __IOM uint32_t SUBSCRIBE_LFCLKSTART;             /*!< (@ 0x00000090) Subscribe configuration for task LFCLKSTART           */
    __IOM uint32_t SUBSCRIBE_LFCLKSTOP;              /*!< (@ 0x00000094) Subscribe configuration for task LFCLKSTOP            */
    __IOM uint32_t SUBSCRIBE_CAL;                    /*!< (@ 0x00000098) Subscribe configuration for task CAL                  */
    __IM uint32_t RESERVED1[25];
    __IOM uint32_t EVENTS_XOSTARTED;                 /*!< (@ 0x00000100) Crystal oscillator has started                        */
    __IOM uint32_t EVENTS_PLLSTARTED;                /*!< (@ 0x00000104) PLL started                                           */
    __IOM uint32_t EVENTS_LFCLKSTARTED;              /*!< (@ 0x00000108) LFCLK source started                                  */
    __IOM uint32_t EVENTS_DONE;                      /*!< (@ 0x0000010C) Calibration of LFRC oscillator complete event         */
    __IOM uint32_t EVENTS_XOTUNED;                   /*!< (@ 0x00000110) HFXO tuning is done. XOTUNED is generated after
                                                                         TASKS_XOSTART or after TASKS_XOTUNE has completed*/
    __IOM uint32_t EVENTS_XOTUNEERROR;               /*!< (@ 0x00000114) HFXO quality issue detected, XOTUNE is needed         */
    __IOM uint32_t EVENTS_XOTUNEFAILED;              /*!< (@ 0x00000118) HFXO tuning could not be completed                    */
    __IM uint32_t RESERVED2[121];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED3[60];
    __IOM NRF_CLOCK_XO_Type XO;                      /*!< (@ 0x00000400) (unspecified)                                         */
    __IM uint32_t RESERVED4[4];
    __IOM NRF_CLOCK_PLL_Type PLL;                    /*!< (@ 0x00000420) (unspecified)                                         */
    __IM uint32_t RESERVED5[4];
    __IOM NRF_CLOCK_LFCLK_Type LFCLK;                /*!< (@ 0x00000440) (unspecified)                                         */
  } NRF_CLOCK_Type;                                  /*!< Size = 1108 (0x454)                                                  */

/* CLOCK_TASKS_XOSTART: Start crystal oscillator (HFXO) */
  #define CLOCK_TASKS_XOSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOSTART register.                            */

/* TASKS_XOSTART @Bit 0 : Start crystal oscillator (HFXO) */
  #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Pos (0UL) /*!< Position of TASKS_XOSTART field.                                    */
  #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Msk (0x1UL << CLOCK_TASKS_XOSTART_TASKS_XOSTART_Pos) /*!< Bit mask of TASKS_XOSTART
                                                                            field.*/
  #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_XOSTART field.                      */
  #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_XOSTART field.                      */
  #define CLOCK_TASKS_XOSTART_TASKS_XOSTART_Trigger (0x1UL) /*!< Trigger task                                                  */


/* CLOCK_TASKS_XOSTOP: Stop crystal oscillator (HFXO) */
  #define CLOCK_TASKS_XOSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOSTOP register.                              */

/* TASKS_XOSTOP @Bit 0 : Stop crystal oscillator (HFXO) */
  #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Pos (0UL)  /*!< Position of TASKS_XOSTOP field.                                      */
  #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Msk (0x1UL << CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Pos) /*!< Bit mask of TASKS_XOSTOP
                                                                            field.*/
  #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_XOSTOP field.                         */
  #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_XOSTOP field.                         */
  #define CLOCK_TASKS_XOSTOP_TASKS_XOSTOP_Trigger (0x1UL) /*!< Trigger task                                                    */


/* CLOCK_TASKS_PLLSTART: Start PLL and keep it running, regardless of the automatic clock requests */
  #define CLOCK_TASKS_PLLSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PLLSTART register.                          */

/* TASKS_PLLSTART @Bit 0 : Start PLL and keep it running, regardless of the automatic clock requests */
  #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Pos (0UL) /*!< Position of TASKS_PLLSTART field.                                 */
  #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Msk (0x1UL << CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Pos) /*!< Bit mask of
                                                                            TASKS_PLLSTART field.*/
  #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_PLLSTART field.                   */
  #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_PLLSTART field.                   */
  #define CLOCK_TASKS_PLLSTART_TASKS_PLLSTART_Trigger (0x1UL) /*!< Trigger task                                                */


/* CLOCK_TASKS_PLLSTOP: Stop PLL */
  #define CLOCK_TASKS_PLLSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PLLSTOP register.                            */

/* TASKS_PLLSTOP @Bit 0 : Stop PLL */
  #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Pos (0UL) /*!< Position of TASKS_PLLSTOP field.                                    */
  #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Msk (0x1UL << CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Pos) /*!< Bit mask of TASKS_PLLSTOP
                                                                            field.*/
  #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_PLLSTOP field.                      */
  #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_PLLSTOP field.                      */
  #define CLOCK_TASKS_PLLSTOP_TASKS_PLLSTOP_Trigger (0x1UL) /*!< Trigger task                                                  */


/* CLOCK_TASKS_LFCLKSTART: Start LFCLK source as selected in LFCLK.SRC */
  #define CLOCK_TASKS_LFCLKSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_LFCLKSTART register.                      */

/* TASKS_LFCLKSTART @Bit 0 : Start LFCLK source as selected in LFCLK.SRC */
  #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field.                           */
  #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of
                                                                            TASKS_LFCLKSTART field.*/
  #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_LFCLKSTART field.             */
  #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_LFCLKSTART field.             */
  #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (0x1UL) /*!< Trigger task                                            */


/* CLOCK_TASKS_LFCLKSTOP: Stop LFCLK source */
  #define CLOCK_TASKS_LFCLKSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_LFCLKSTOP register.                        */

/* TASKS_LFCLKSTOP @Bit 0 : Stop LFCLK source */
  #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field.                              */
  #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of
                                                                            TASKS_LFCLKSTOP field.*/
  #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_LFCLKSTOP field.                */
  #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_LFCLKSTOP field.                */
  #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (0x1UL) /*!< Trigger task                                              */


/* CLOCK_TASKS_CAL: Start calibration of LFRC oscillator */
  #define CLOCK_TASKS_CAL_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_CAL register.                                   */

/* TASKS_CAL @Bit 0 : Start calibration of LFRC oscillator */
  #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL)        /*!< Position of TASKS_CAL field.                                         */
  #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field.             */
  #define CLOCK_TASKS_CAL_TASKS_CAL_Min (0x1UL)      /*!< Min enumerator value of TASKS_CAL field.                             */
  #define CLOCK_TASKS_CAL_TASKS_CAL_Max (0x1UL)      /*!< Max enumerator value of TASKS_CAL field.                             */
  #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* CLOCK_TASKS_XOTUNE: Request tuning for HFXO */
  #define CLOCK_TASKS_XOTUNE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOTUNE register.                              */

/* TASKS_XOTUNE @Bit 0 : Request tuning for HFXO */
  #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Pos (0UL)  /*!< Position of TASKS_XOTUNE field.                                      */
  #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Msk (0x1UL << CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Pos) /*!< Bit mask of TASKS_XOTUNE
                                                                            field.*/
  #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Min (0x1UL) /*!< Min enumerator value of TASKS_XOTUNE field.                         */
  #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Max (0x1UL) /*!< Max enumerator value of TASKS_XOTUNE field.                         */
  #define CLOCK_TASKS_XOTUNE_TASKS_XOTUNE_Trigger (0x1UL) /*!< Trigger task                                                    */


/* CLOCK_TASKS_XOTUNEABORT: Abort tuning for HFXO */
  #define CLOCK_TASKS_XOTUNEABORT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_XOTUNEABORT register.                    */

/* TASKS_XOTUNEABORT @Bit 0 : Abort tuning for HFXO */
  #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Pos (0UL) /*!< Position of TASKS_XOTUNEABORT field.                        */
  #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Msk (0x1UL << CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Pos) /*!< Bit mask
                                                                            of TASKS_XOTUNEABORT field.*/
  #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Min (0x1UL) /*!< Min enumerator value of TASKS_XOTUNEABORT field.          */
  #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Max (0x1UL) /*!< Max enumerator value of TASKS_XOTUNEABORT field.          */
  #define CLOCK_TASKS_XOTUNEABORT_TASKS_XOTUNEABORT_Trigger (0x1UL) /*!< Trigger task                                          */


/* CLOCK_SUBSCRIBE_XOSTART: Subscribe configuration for task XOSTART */
  #define CLOCK_SUBSCRIBE_XOSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XOSTART register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task XOSTART will subscribe to */
  #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define CLOCK_SUBSCRIBE_XOSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CLOCK_SUBSCRIBE_XOSTART_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define CLOCK_SUBSCRIBE_XOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XOSTART_EN_Pos) /*!< Bit mask of EN field.                  */
  #define CLOCK_SUBSCRIBE_XOSTART_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_XOSTART_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_XOSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define CLOCK_SUBSCRIBE_XOSTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* CLOCK_SUBSCRIBE_XOSTOP: Subscribe configuration for task XOSTOP */
  #define CLOCK_SUBSCRIBE_XOSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_XOSTOP register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that task XOSTOP will subscribe to */
  #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define CLOCK_SUBSCRIBE_XOSTOP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CLOCK_SUBSCRIBE_XOSTOP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define CLOCK_SUBSCRIBE_XOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_XOSTOP_EN_Pos) /*!< Bit mask of EN field.                    */
  #define CLOCK_SUBSCRIBE_XOSTOP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_XOSTOP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_XOSTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define CLOCK_SUBSCRIBE_XOSTOP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* CLOCK_SUBSCRIBE_PLLSTART: Subscribe configuration for task PLLSTART */
  #define CLOCK_SUBSCRIBE_PLLSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PLLSTART register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that task PLLSTART will subscribe to */
  #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define CLOCK_SUBSCRIBE_PLLSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define CLOCK_SUBSCRIBE_PLLSTART_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define CLOCK_SUBSCRIBE_PLLSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_PLLSTART_EN_Pos) /*!< Bit mask of EN field.                */
  #define CLOCK_SUBSCRIBE_PLLSTART_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_PLLSTART_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_PLLSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
  #define CLOCK_SUBSCRIBE_PLLSTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */


/* CLOCK_SUBSCRIBE_PLLSTOP: Subscribe configuration for task PLLSTOP */
  #define CLOCK_SUBSCRIBE_PLLSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PLLSTOP register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task PLLSTOP will subscribe to */
  #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define CLOCK_SUBSCRIBE_PLLSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_PLLSTOP_EN_Pos) /*!< Bit mask of EN field.                  */
  #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define CLOCK_SUBSCRIBE_PLLSTOP_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* CLOCK_SUBSCRIBE_LFCLKSTART: Subscribe configuration for task LFCLKSTART */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_LFCLKSTART register.              */

/* CHIDX @Bits 0..7 : DPPI channel that task LFCLKSTART will subscribe to */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field.            */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                             */
  #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription                                               */


/* CLOCK_SUBSCRIBE_LFCLKSTOP: Subscribe configuration for task LFCLKSTOP */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_LFCLKSTOP register.                */

/* CHIDX @Bits 0..7 : DPPI channel that task LFCLKSTOP will subscribe to */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field.              */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                              */
  #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription                                                */


/* CLOCK_SUBSCRIBE_CAL: Subscribe configuration for task CAL */
  #define CLOCK_SUBSCRIBE_CAL_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAL register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task CAL will subscribe to */
  #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define CLOCK_SUBSCRIBE_CAL_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define CLOCK_SUBSCRIBE_CAL_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field.                          */
  #define CLOCK_SUBSCRIBE_CAL_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_CAL_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* CLOCK_EVENTS_XOSTARTED: Crystal oscillator has started */
  #define CLOCK_EVENTS_XOSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOSTARTED register.                      */

/* EVENTS_XOSTARTED @Bit 0 : Crystal oscillator has started */
  #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Pos (0UL) /*!< Position of EVENTS_XOSTARTED field.                           */
  #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Msk (0x1UL << CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Pos) /*!< Bit mask of
                                                                            EVENTS_XOSTARTED field.*/
  #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOSTARTED field.             */
  #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOSTARTED field.             */
  #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define CLOCK_EVENTS_XOSTARTED_EVENTS_XOSTARTED_Generated (0x1UL) /*!< Event generated                                       */


/* CLOCK_EVENTS_PLLSTARTED: PLL started */
  #define CLOCK_EVENTS_PLLSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PLLSTARTED register.                    */

/* EVENTS_PLLSTARTED @Bit 0 : PLL started */
  #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Pos (0UL) /*!< Position of EVENTS_PLLSTARTED field.                        */
  #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Msk (0x1UL << CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Pos) /*!< Bit mask
                                                                            of EVENTS_PLLSTARTED field.*/
  #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PLLSTARTED field.          */
  #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PLLSTARTED field.          */
  #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define CLOCK_EVENTS_PLLSTARTED_EVENTS_PLLSTARTED_Generated (0x1UL) /*!< Event generated                                     */


/* CLOCK_EVENTS_LFCLKSTARTED: LFCLK source started */
  #define CLOCK_EVENTS_LFCLKSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LFCLKSTARTED register.                */

/* EVENTS_LFCLKSTARTED @Bit 0 : LFCLK source started */
  #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field.                  */
  #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!<
                                                                            Bit mask of EVENTS_LFCLKSTARTED field.*/
  #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_LFCLKSTARTED field.    */
  #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_LFCLKSTARTED field.    */
  #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated                          */
  #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (0x1UL) /*!< Event generated                                 */


/* CLOCK_EVENTS_DONE: Calibration of LFRC oscillator complete event */
  #define CLOCK_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register.                                */

/* EVENTS_DONE @Bit 0 : Calibration of LFRC oscillator complete event */
  #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL)    /*!< Position of EVENTS_DONE field.                                       */
  #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field.   */
  #define CLOCK_EVENTS_DONE_EVENTS_DONE_Min (0x0UL)  /*!< Min enumerator value of EVENTS_DONE field.                           */
  #define CLOCK_EVENTS_DONE_EVENTS_DONE_Max (0x1UL)  /*!< Max enumerator value of EVENTS_DONE field.                           */
  #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated                                                 */


/* CLOCK_EVENTS_XOTUNED: HFXO tuning is done. XOTUNED is generated after TASKS_XOSTART or after TASKS_XOTUNE has completed */
  #define CLOCK_EVENTS_XOTUNED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOTUNED register.                          */

/* EVENTS_XOTUNED @Bit 0 : HFXO tuning is done. XOTUNED is generated after TASKS_XOSTART or after TASKS_XOTUNE has completed */
  #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Pos (0UL) /*!< Position of EVENTS_XOTUNED field.                                 */
  #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Msk (0x1UL << CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Pos) /*!< Bit mask of
                                                                            EVENTS_XOTUNED field.*/
  #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOTUNED field.                   */
  #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOTUNED field.                   */
  #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define CLOCK_EVENTS_XOTUNED_EVENTS_XOTUNED_Generated (0x1UL) /*!< Event generated                                           */


/* CLOCK_EVENTS_XOTUNEERROR: HFXO quality issue detected, XOTUNE is needed */
  #define CLOCK_EVENTS_XOTUNEERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOTUNEERROR register.                  */

/* EVENTS_XOTUNEERROR @Bit 0 : HFXO quality issue detected, XOTUNE is needed */
  #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Pos (0UL) /*!< Position of EVENTS_XOTUNEERROR field.                     */
  #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Msk (0x1UL << CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Pos) /*!< Bit
                                                                            mask of EVENTS_XOTUNEERROR field.*/
  #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOTUNEERROR field.       */
  #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOTUNEERROR field.       */
  #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_NotGenerated (0x0UL) /*!< Event not generated                            */
  #define CLOCK_EVENTS_XOTUNEERROR_EVENTS_XOTUNEERROR_Generated (0x1UL) /*!< Event generated                                   */


/* CLOCK_EVENTS_XOTUNEFAILED: HFXO tuning could not be completed */
  #define CLOCK_EVENTS_XOTUNEFAILED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XOTUNEFAILED register.                */

/* EVENTS_XOTUNEFAILED @Bit 0 : HFXO tuning could not be completed */
  #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Pos (0UL) /*!< Position of EVENTS_XOTUNEFAILED field.                  */
  #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Msk (0x1UL << CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Pos) /*!<
                                                                            Bit mask of EVENTS_XOTUNEFAILED field.*/
  #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Min (0x0UL) /*!< Min enumerator value of EVENTS_XOTUNEFAILED field.    */
  #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Max (0x1UL) /*!< Max enumerator value of EVENTS_XOTUNEFAILED field.    */
  #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_NotGenerated (0x0UL) /*!< Event not generated                          */
  #define CLOCK_EVENTS_XOTUNEFAILED_EVENTS_XOTUNEFAILED_Generated (0x1UL) /*!< Event generated                                 */


/* CLOCK_INTEN: Enable or disable interrupt */
  #define CLOCK_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */

/* XOSTARTED @Bit 0 : Enable or disable interrupt for event XOSTARTED */
  #define CLOCK_INTEN_XOSTARTED_Pos (0UL)            /*!< Position of XOSTARTED field.                                         */
  #define CLOCK_INTEN_XOSTARTED_Msk (0x1UL << CLOCK_INTEN_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field.                     */
  #define CLOCK_INTEN_XOSTARTED_Min (0x0UL)          /*!< Min enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTEN_XOSTARTED_Max (0x1UL)          /*!< Max enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTEN_XOSTARTED_Disabled (0x0UL)     /*!< Disable                                                              */
  #define CLOCK_INTEN_XOSTARTED_Enabled (0x1UL)      /*!< Enable                                                               */

/* PLLSTARTED @Bit 1 : Enable or disable interrupt for event PLLSTARTED */
  #define CLOCK_INTEN_PLLSTARTED_Pos (1UL)           /*!< Position of PLLSTARTED field.                                        */
  #define CLOCK_INTEN_PLLSTARTED_Msk (0x1UL << CLOCK_INTEN_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field.                  */
  #define CLOCK_INTEN_PLLSTARTED_Min (0x0UL)         /*!< Min enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTEN_PLLSTARTED_Max (0x1UL)         /*!< Max enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTEN_PLLSTARTED_Disabled (0x0UL)    /*!< Disable                                                              */
  #define CLOCK_INTEN_PLLSTARTED_Enabled (0x1UL)     /*!< Enable                                                               */

/* LFCLKSTARTED @Bit 2 : Enable or disable interrupt for event LFCLKSTARTED */
  #define CLOCK_INTEN_LFCLKSTARTED_Pos (2UL)         /*!< Position of LFCLKSTARTED field.                                      */
  #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field.            */
  #define CLOCK_INTEN_LFCLKSTARTED_Min (0x0UL)       /*!< Min enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTEN_LFCLKSTARTED_Max (0x1UL)       /*!< Max enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0x0UL)  /*!< Disable                                                              */
  #define CLOCK_INTEN_LFCLKSTARTED_Enabled (0x1UL)   /*!< Enable                                                               */

/* DONE @Bit 3 : Enable or disable interrupt for event DONE */
  #define CLOCK_INTEN_DONE_Pos (3UL)                 /*!< Position of DONE field.                                              */
  #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field.                                    */
  #define CLOCK_INTEN_DONE_Min (0x0UL)               /*!< Min enumerator value of DONE field.                                  */
  #define CLOCK_INTEN_DONE_Max (0x1UL)               /*!< Max enumerator value of DONE field.                                  */
  #define CLOCK_INTEN_DONE_Disabled (0x0UL)          /*!< Disable                                                              */
  #define CLOCK_INTEN_DONE_Enabled (0x1UL)           /*!< Enable                                                               */

/* XOTUNED @Bit 4 : Enable or disable interrupt for event XOTUNED */
  #define CLOCK_INTEN_XOTUNED_Pos (4UL)              /*!< Position of XOTUNED field.                                           */
  #define CLOCK_INTEN_XOTUNED_Msk (0x1UL << CLOCK_INTEN_XOTUNED_Pos) /*!< Bit mask of XOTUNED field.                           */
  #define CLOCK_INTEN_XOTUNED_Min (0x0UL)            /*!< Min enumerator value of XOTUNED field.                               */
  #define CLOCK_INTEN_XOTUNED_Max (0x1UL)            /*!< Max enumerator value of XOTUNED field.                               */
  #define CLOCK_INTEN_XOTUNED_Disabled (0x0UL)       /*!< Disable                                                              */
  #define CLOCK_INTEN_XOTUNED_Enabled (0x1UL)        /*!< Enable                                                               */

/* XOTUNEERROR @Bit 5 : Enable or disable interrupt for event XOTUNEERROR */
  #define CLOCK_INTEN_XOTUNEERROR_Pos (5UL)          /*!< Position of XOTUNEERROR field.                                       */
  #define CLOCK_INTEN_XOTUNEERROR_Msk (0x1UL << CLOCK_INTEN_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field.               */
  #define CLOCK_INTEN_XOTUNEERROR_Min (0x0UL)        /*!< Min enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTEN_XOTUNEERROR_Max (0x1UL)        /*!< Max enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTEN_XOTUNEERROR_Disabled (0x0UL)   /*!< Disable                                                              */
  #define CLOCK_INTEN_XOTUNEERROR_Enabled (0x1UL)    /*!< Enable                                                               */

/* XOTUNEFAILED @Bit 6 : Enable or disable interrupt for event XOTUNEFAILED */
  #define CLOCK_INTEN_XOTUNEFAILED_Pos (6UL)         /*!< Position of XOTUNEFAILED field.                                      */
  #define CLOCK_INTEN_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTEN_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field.            */
  #define CLOCK_INTEN_XOTUNEFAILED_Min (0x0UL)       /*!< Min enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTEN_XOTUNEFAILED_Max (0x1UL)       /*!< Max enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTEN_XOTUNEFAILED_Disabled (0x0UL)  /*!< Disable                                                              */
  #define CLOCK_INTEN_XOTUNEFAILED_Enabled (0x1UL)   /*!< Enable                                                               */


/* CLOCK_INTENSET: Enable interrupt */
  #define CLOCK_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */

/* XOSTARTED @Bit 0 : Write '1' to enable interrupt for event XOSTARTED */
  #define CLOCK_INTENSET_XOSTARTED_Pos (0UL)         /*!< Position of XOSTARTED field.                                         */
  #define CLOCK_INTENSET_XOSTARTED_Msk (0x1UL << CLOCK_INTENSET_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field.               */
  #define CLOCK_INTENSET_XOSTARTED_Min (0x0UL)       /*!< Min enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTENSET_XOSTARTED_Max (0x1UL)       /*!< Max enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTENSET_XOSTARTED_Set (0x1UL)       /*!< Enable                                                               */
  #define CLOCK_INTENSET_XOSTARTED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define CLOCK_INTENSET_XOSTARTED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* PLLSTARTED @Bit 1 : Write '1' to enable interrupt for event PLLSTARTED */
  #define CLOCK_INTENSET_PLLSTARTED_Pos (1UL)        /*!< Position of PLLSTARTED field.                                        */
  #define CLOCK_INTENSET_PLLSTARTED_Msk (0x1UL << CLOCK_INTENSET_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field.            */
  #define CLOCK_INTENSET_PLLSTARTED_Min (0x0UL)      /*!< Min enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTENSET_PLLSTARTED_Max (0x1UL)      /*!< Max enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTENSET_PLLSTARTED_Set (0x1UL)      /*!< Enable                                                               */
  #define CLOCK_INTENSET_PLLSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define CLOCK_INTENSET_PLLSTARTED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* LFCLKSTARTED @Bit 2 : Write '1' to enable interrupt for event LFCLKSTARTED */
  #define CLOCK_INTENSET_LFCLKSTARTED_Pos (2UL)      /*!< Position of LFCLKSTARTED field.                                      */
  #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field.      */
  #define CLOCK_INTENSET_LFCLKSTARTED_Min (0x0UL)    /*!< Min enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTENSET_LFCLKSTARTED_Max (0x1UL)    /*!< Max enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTENSET_LFCLKSTARTED_Set (0x1UL)    /*!< Enable                                                               */
  #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DONE @Bit 3 : Write '1' to enable interrupt for event DONE */
  #define CLOCK_INTENSET_DONE_Pos (3UL)              /*!< Position of DONE field.                                              */
  #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field.                              */
  #define CLOCK_INTENSET_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
  #define CLOCK_INTENSET_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
  #define CLOCK_INTENSET_DONE_Set (0x1UL)            /*!< Enable                                                               */
  #define CLOCK_INTENSET_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define CLOCK_INTENSET_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* XOTUNED @Bit 4 : Write '1' to enable interrupt for event XOTUNED */
  #define CLOCK_INTENSET_XOTUNED_Pos (4UL)           /*!< Position of XOTUNED field.                                           */
  #define CLOCK_INTENSET_XOTUNED_Msk (0x1UL << CLOCK_INTENSET_XOTUNED_Pos) /*!< Bit mask of XOTUNED field.                     */
  #define CLOCK_INTENSET_XOTUNED_Min (0x0UL)         /*!< Min enumerator value of XOTUNED field.                               */
  #define CLOCK_INTENSET_XOTUNED_Max (0x1UL)         /*!< Max enumerator value of XOTUNED field.                               */
  #define CLOCK_INTENSET_XOTUNED_Set (0x1UL)         /*!< Enable                                                               */
  #define CLOCK_INTENSET_XOTUNED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define CLOCK_INTENSET_XOTUNED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* XOTUNEERROR @Bit 5 : Write '1' to enable interrupt for event XOTUNEERROR */
  #define CLOCK_INTENSET_XOTUNEERROR_Pos (5UL)       /*!< Position of XOTUNEERROR field.                                       */
  #define CLOCK_INTENSET_XOTUNEERROR_Msk (0x1UL << CLOCK_INTENSET_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field.         */
  #define CLOCK_INTENSET_XOTUNEERROR_Min (0x0UL)     /*!< Min enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTENSET_XOTUNEERROR_Max (0x1UL)     /*!< Max enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTENSET_XOTUNEERROR_Set (0x1UL)     /*!< Enable                                                               */
  #define CLOCK_INTENSET_XOTUNEERROR_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define CLOCK_INTENSET_XOTUNEERROR_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* XOTUNEFAILED @Bit 6 : Write '1' to enable interrupt for event XOTUNEFAILED */
  #define CLOCK_INTENSET_XOTUNEFAILED_Pos (6UL)      /*!< Position of XOTUNEFAILED field.                                      */
  #define CLOCK_INTENSET_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTENSET_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field.      */
  #define CLOCK_INTENSET_XOTUNEFAILED_Min (0x0UL)    /*!< Min enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTENSET_XOTUNEFAILED_Max (0x1UL)    /*!< Max enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTENSET_XOTUNEFAILED_Set (0x1UL)    /*!< Enable                                                               */
  #define CLOCK_INTENSET_XOTUNEFAILED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define CLOCK_INTENSET_XOTUNEFAILED_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* CLOCK_INTENCLR: Disable interrupt */
  #define CLOCK_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */

/* XOSTARTED @Bit 0 : Write '1' to disable interrupt for event XOSTARTED */
  #define CLOCK_INTENCLR_XOSTARTED_Pos (0UL)         /*!< Position of XOSTARTED field.                                         */
  #define CLOCK_INTENCLR_XOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field.               */
  #define CLOCK_INTENCLR_XOSTARTED_Min (0x0UL)       /*!< Min enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTENCLR_XOSTARTED_Max (0x1UL)       /*!< Max enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTENCLR_XOSTARTED_Clear (0x1UL)     /*!< Disable                                                              */
  #define CLOCK_INTENCLR_XOSTARTED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define CLOCK_INTENCLR_XOSTARTED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* PLLSTARTED @Bit 1 : Write '1' to disable interrupt for event PLLSTARTED */
  #define CLOCK_INTENCLR_PLLSTARTED_Pos (1UL)        /*!< Position of PLLSTARTED field.                                        */
  #define CLOCK_INTENCLR_PLLSTARTED_Msk (0x1UL << CLOCK_INTENCLR_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field.            */
  #define CLOCK_INTENCLR_PLLSTARTED_Min (0x0UL)      /*!< Min enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTENCLR_PLLSTARTED_Max (0x1UL)      /*!< Max enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTENCLR_PLLSTARTED_Clear (0x1UL)    /*!< Disable                                                              */
  #define CLOCK_INTENCLR_PLLSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define CLOCK_INTENCLR_PLLSTARTED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* LFCLKSTARTED @Bit 2 : Write '1' to disable interrupt for event LFCLKSTARTED */
  #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (2UL)      /*!< Position of LFCLKSTARTED field.                                      */
  #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field.      */
  #define CLOCK_INTENCLR_LFCLKSTARTED_Min (0x0UL)    /*!< Min enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTENCLR_LFCLKSTARTED_Max (0x1UL)    /*!< Max enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (0x1UL)  /*!< Disable                                                              */
  #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DONE @Bit 3 : Write '1' to disable interrupt for event DONE */
  #define CLOCK_INTENCLR_DONE_Pos (3UL)              /*!< Position of DONE field.                                              */
  #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field.                              */
  #define CLOCK_INTENCLR_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
  #define CLOCK_INTENCLR_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
  #define CLOCK_INTENCLR_DONE_Clear (0x1UL)          /*!< Disable                                                              */
  #define CLOCK_INTENCLR_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define CLOCK_INTENCLR_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* XOTUNED @Bit 4 : Write '1' to disable interrupt for event XOTUNED */
  #define CLOCK_INTENCLR_XOTUNED_Pos (4UL)           /*!< Position of XOTUNED field.                                           */
  #define CLOCK_INTENCLR_XOTUNED_Msk (0x1UL << CLOCK_INTENCLR_XOTUNED_Pos) /*!< Bit mask of XOTUNED field.                     */
  #define CLOCK_INTENCLR_XOTUNED_Min (0x0UL)         /*!< Min enumerator value of XOTUNED field.                               */
  #define CLOCK_INTENCLR_XOTUNED_Max (0x1UL)         /*!< Max enumerator value of XOTUNED field.                               */
  #define CLOCK_INTENCLR_XOTUNED_Clear (0x1UL)       /*!< Disable                                                              */
  #define CLOCK_INTENCLR_XOTUNED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define CLOCK_INTENCLR_XOTUNED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* XOTUNEERROR @Bit 5 : Write '1' to disable interrupt for event XOTUNEERROR */
  #define CLOCK_INTENCLR_XOTUNEERROR_Pos (5UL)       /*!< Position of XOTUNEERROR field.                                       */
  #define CLOCK_INTENCLR_XOTUNEERROR_Msk (0x1UL << CLOCK_INTENCLR_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field.         */
  #define CLOCK_INTENCLR_XOTUNEERROR_Min (0x0UL)     /*!< Min enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTENCLR_XOTUNEERROR_Max (0x1UL)     /*!< Max enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTENCLR_XOTUNEERROR_Clear (0x1UL)   /*!< Disable                                                              */
  #define CLOCK_INTENCLR_XOTUNEERROR_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define CLOCK_INTENCLR_XOTUNEERROR_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* XOTUNEFAILED @Bit 6 : Write '1' to disable interrupt for event XOTUNEFAILED */
  #define CLOCK_INTENCLR_XOTUNEFAILED_Pos (6UL)      /*!< Position of XOTUNEFAILED field.                                      */
  #define CLOCK_INTENCLR_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTENCLR_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field.      */
  #define CLOCK_INTENCLR_XOTUNEFAILED_Min (0x0UL)    /*!< Min enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTENCLR_XOTUNEFAILED_Max (0x1UL)    /*!< Max enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTENCLR_XOTUNEFAILED_Clear (0x1UL)  /*!< Disable                                                              */
  #define CLOCK_INTENCLR_XOTUNEFAILED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define CLOCK_INTENCLR_XOTUNEFAILED_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* CLOCK_INTPEND: Pending interrupts */
  #define CLOCK_INTPEND_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND register.                                     */

/* XOSTARTED @Bit 0 : Read pending status of interrupt for event XOSTARTED */
  #define CLOCK_INTPEND_XOSTARTED_Pos (0UL)          /*!< Position of XOSTARTED field.                                         */
  #define CLOCK_INTPEND_XOSTARTED_Msk (0x1UL << CLOCK_INTPEND_XOSTARTED_Pos) /*!< Bit mask of XOSTARTED field.                 */
  #define CLOCK_INTPEND_XOSTARTED_Min (0x0UL)        /*!< Min enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTPEND_XOSTARTED_Max (0x1UL)        /*!< Max enumerator value of XOSTARTED field.                             */
  #define CLOCK_INTPEND_XOSTARTED_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define CLOCK_INTPEND_XOSTARTED_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* PLLSTARTED @Bit 1 : Read pending status of interrupt for event PLLSTARTED */
  #define CLOCK_INTPEND_PLLSTARTED_Pos (1UL)         /*!< Position of PLLSTARTED field.                                        */
  #define CLOCK_INTPEND_PLLSTARTED_Msk (0x1UL << CLOCK_INTPEND_PLLSTARTED_Pos) /*!< Bit mask of PLLSTARTED field.              */
  #define CLOCK_INTPEND_PLLSTARTED_Min (0x0UL)       /*!< Min enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTPEND_PLLSTARTED_Max (0x1UL)       /*!< Max enumerator value of PLLSTARTED field.                            */
  #define CLOCK_INTPEND_PLLSTARTED_NotPending (0x0UL) /*!< Read: Not pending                                                   */
  #define CLOCK_INTPEND_PLLSTARTED_Pending (0x1UL)   /*!< Read: Pending                                                        */

/* LFCLKSTARTED @Bit 2 : Read pending status of interrupt for event LFCLKSTARTED */
  #define CLOCK_INTPEND_LFCLKSTARTED_Pos (2UL)       /*!< Position of LFCLKSTARTED field.                                      */
  #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field.        */
  #define CLOCK_INTPEND_LFCLKSTARTED_Min (0x0UL)     /*!< Min enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTPEND_LFCLKSTARTED_Max (0x1UL)     /*!< Max enumerator value of LFCLKSTARTED field.                          */
  #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending                                                 */
  #define CLOCK_INTPEND_LFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending                                                        */

/* DONE @Bit 3 : Read pending status of interrupt for event DONE */
  #define CLOCK_INTPEND_DONE_Pos (3UL)               /*!< Position of DONE field.                                              */
  #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field.                                */
  #define CLOCK_INTPEND_DONE_Min (0x0UL)             /*!< Min enumerator value of DONE field.                                  */
  #define CLOCK_INTPEND_DONE_Max (0x1UL)             /*!< Max enumerator value of DONE field.                                  */
  #define CLOCK_INTPEND_DONE_NotPending (0x0UL)      /*!< Read: Not pending                                                    */
  #define CLOCK_INTPEND_DONE_Pending (0x1UL)         /*!< Read: Pending                                                        */

/* XOTUNED @Bit 4 : Read pending status of interrupt for event XOTUNED */
  #define CLOCK_INTPEND_XOTUNED_Pos (4UL)            /*!< Position of XOTUNED field.                                           */
  #define CLOCK_INTPEND_XOTUNED_Msk (0x1UL << CLOCK_INTPEND_XOTUNED_Pos) /*!< Bit mask of XOTUNED field.                       */
  #define CLOCK_INTPEND_XOTUNED_Min (0x0UL)          /*!< Min enumerator value of XOTUNED field.                               */
  #define CLOCK_INTPEND_XOTUNED_Max (0x1UL)          /*!< Max enumerator value of XOTUNED field.                               */
  #define CLOCK_INTPEND_XOTUNED_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
  #define CLOCK_INTPEND_XOTUNED_Pending (0x1UL)      /*!< Read: Pending                                                        */

/* XOTUNEERROR @Bit 5 : Read pending status of interrupt for event XOTUNEERROR */
  #define CLOCK_INTPEND_XOTUNEERROR_Pos (5UL)        /*!< Position of XOTUNEERROR field.                                       */
  #define CLOCK_INTPEND_XOTUNEERROR_Msk (0x1UL << CLOCK_INTPEND_XOTUNEERROR_Pos) /*!< Bit mask of XOTUNEERROR field.           */
  #define CLOCK_INTPEND_XOTUNEERROR_Min (0x0UL)      /*!< Min enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTPEND_XOTUNEERROR_Max (0x1UL)      /*!< Max enumerator value of XOTUNEERROR field.                           */
  #define CLOCK_INTPEND_XOTUNEERROR_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define CLOCK_INTPEND_XOTUNEERROR_Pending (0x1UL)  /*!< Read: Pending                                                        */

/* XOTUNEFAILED @Bit 6 : Read pending status of interrupt for event XOTUNEFAILED */
  #define CLOCK_INTPEND_XOTUNEFAILED_Pos (6UL)       /*!< Position of XOTUNEFAILED field.                                      */
  #define CLOCK_INTPEND_XOTUNEFAILED_Msk (0x1UL << CLOCK_INTPEND_XOTUNEFAILED_Pos) /*!< Bit mask of XOTUNEFAILED field.        */
  #define CLOCK_INTPEND_XOTUNEFAILED_Min (0x0UL)     /*!< Min enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTPEND_XOTUNEFAILED_Max (0x1UL)     /*!< Max enumerator value of XOTUNEFAILED field.                          */
  #define CLOCK_INTPEND_XOTUNEFAILED_NotPending (0x0UL) /*!< Read: Not pending                                                 */
  #define CLOCK_INTPEND_XOTUNEFAILED_Pending (0x1UL) /*!< Read: Pending                                                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           COMP                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct COMP ======================================================= */
/**
  * @brief Comparator
  */
  typedef struct {                                   /*!< COMP Structure                                                       */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start comparator                                      */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop comparator                                       */
    __OM uint32_t TASKS_SAMPLE;                      /*!< (@ 0x00000008) Sample comparator value. This task requires that COMP
                                                                         has been started by the START Task.*/
    __IM uint32_t RESERVED[29];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_SAMPLE;                 /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE               */
    __IM uint32_t RESERVED1[29];
    __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000100) COMP is ready and output is valid                     */
    __IOM uint32_t EVENTS_DOWN;                      /*!< (@ 0x00000104) Downward crossing                                     */
    __IOM uint32_t EVENTS_UP;                        /*!< (@ 0x00000108) Upward crossing                                       */
    __IOM uint32_t EVENTS_CROSS;                     /*!< (@ 0x0000010C) Downward or upward crossing                           */
    __IM uint32_t RESERVED2[28];
    __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000180) Publish configuration for event READY                 */
    __IOM uint32_t PUBLISH_DOWN;                     /*!< (@ 0x00000184) Publish configuration for event DOWN                  */
    __IOM uint32_t PUBLISH_UP;                       /*!< (@ 0x00000188) Publish configuration for event UP                    */
    __IOM uint32_t PUBLISH_CROSS;                    /*!< (@ 0x0000018C) Publish configuration for event CROSS                 */
    __IM uint32_t RESERVED3[28];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED4[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED5[60];
    __IM uint32_t RESULT;                            /*!< (@ 0x00000400) Compare result                                        */
    __IM uint32_t RESERVED6[63];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) COMP enable                                           */
    __IOM uint32_t PSEL;                             /*!< (@ 0x00000504) Pin select                                            */
    __IOM uint32_t REFSEL;                           /*!< (@ 0x00000508) Reference source select for single-ended mode         */
    __IOM uint32_t EXTREFSEL;                        /*!< (@ 0x0000050C) External reference select                             */
    __IM uint32_t RESERVED7[8];
    __IOM uint32_t TH;                               /*!< (@ 0x00000530) Threshold configuration for hysteresis unit           */
    __IOM uint32_t MODE;                             /*!< (@ 0x00000534) Mode configuration                                    */
    __IOM uint32_t HYST;                             /*!< (@ 0x00000538) Comparator hysteresis enable                          */
    __IOM uint32_t ISOURCE;                          /*!< (@ 0x0000053C) Current source select on analog input                 */
  } NRF_COMP_Type;                                   /*!< Size = 1344 (0x540)                                                  */

/* COMP_TASKS_START: Start comparator */
  #define COMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start comparator */
  #define COMP_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
  #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
  #define COMP_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
  #define COMP_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
  #define COMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */


/* COMP_TASKS_STOP: Stop comparator */
  #define COMP_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop comparator */
  #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
  #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
  #define COMP_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
  #define COMP_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
  #define COMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */


/* COMP_TASKS_SAMPLE: Sample comparator value. This task requires that COMP has been started by the START Task. */
  #define COMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register.                               */

/* TASKS_SAMPLE @Bit 0 : Sample comparator value. This task requires that COMP has been started by the START Task. */
  #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)   /*!< Position of TASKS_SAMPLE field.                                      */
  #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field.*/
  #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field.                          */
  #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field.                          */
  #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task                                                     */


/* COMP_SUBSCRIBE_START: Subscribe configuration for task START */
  #define COMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define COMP_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define COMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define COMP_SUBSCRIBE_START_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define COMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define COMP_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define COMP_SUBSCRIBE_START_EN_Msk (0x1UL << COMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
  #define COMP_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define COMP_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define COMP_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define COMP_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* COMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define COMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define COMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define COMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define COMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define COMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define COMP_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define COMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << COMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
  #define COMP_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define COMP_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define COMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define COMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* COMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */
  #define COMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */
  #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define COMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define COMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << COMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field.                      */
  #define COMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define COMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define COMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define COMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* COMP_EVENTS_READY: COMP is ready and output is valid */
  #define COMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                               */

/* EVENTS_READY @Bit 0 : COMP is ready and output is valid */
  #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL)   /*!< Position of EVENTS_READY field.                                      */
  #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/
  #define COMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                          */
  #define COMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                          */
  #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define COMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                                */


/* COMP_EVENTS_DOWN: Downward crossing */
  #define COMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register.                                 */

/* EVENTS_DOWN @Bit 0 : Downward crossing */
  #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL)     /*!< Position of EVENTS_DOWN field.                                       */
  #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field.     */
  #define COMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL)   /*!< Min enumerator value of EVENTS_DOWN field.                           */
  #define COMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL)   /*!< Max enumerator value of EVENTS_DOWN field.                           */
  #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated                                           */
  #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated                                                  */


/* COMP_EVENTS_UP: Upward crossing */
  #define COMP_EVENTS_UP_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_UP register.                                   */

/* EVENTS_UP @Bit 0 : Upward crossing */
  #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL)         /*!< Position of EVENTS_UP field.                                         */
  #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field.               */
  #define COMP_EVENTS_UP_EVENTS_UP_Min (0x0UL)       /*!< Min enumerator value of EVENTS_UP field.                             */
  #define COMP_EVENTS_UP_EVENTS_UP_Max (0x1UL)       /*!< Max enumerator value of EVENTS_UP field.                             */
  #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated                                               */
  #define COMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated                                                      */


/* COMP_EVENTS_CROSS: Downward or upward crossing */
  #define COMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register.                               */

/* EVENTS_CROSS @Bit 0 : Downward or upward crossing */
  #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL)   /*!< Position of EVENTS_CROSS field.                                      */
  #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field.*/
  #define COMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field.                          */
  #define COMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field.                          */
  #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated                                                */


/* COMP_PUBLISH_READY: Publish configuration for event READY */
  #define COMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define COMP_PUBLISH_READY_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define COMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << COMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define COMP_PUBLISH_READY_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define COMP_PUBLISH_READY_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define COMP_PUBLISH_READY_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define COMP_PUBLISH_READY_EN_Msk (0x1UL << COMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                            */
  #define COMP_PUBLISH_READY_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define COMP_PUBLISH_READY_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define COMP_PUBLISH_READY_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define COMP_PUBLISH_READY_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* COMP_PUBLISH_DOWN: Publish configuration for event DOWN */
  #define COMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register.                               */

/* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */
  #define COMP_PUBLISH_DOWN_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define COMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << COMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define COMP_PUBLISH_DOWN_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define COMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define COMP_PUBLISH_DOWN_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define COMP_PUBLISH_DOWN_EN_Msk (0x1UL << COMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field.                              */
  #define COMP_PUBLISH_DOWN_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define COMP_PUBLISH_DOWN_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define COMP_PUBLISH_DOWN_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define COMP_PUBLISH_DOWN_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* COMP_PUBLISH_UP: Publish configuration for event UP */
  #define COMP_PUBLISH_UP_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_UP register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */
  #define COMP_PUBLISH_UP_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
  #define COMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << COMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
  #define COMP_PUBLISH_UP_CHIDX_Min (0x00UL)         /*!< Min value of CHIDX field.                                            */
  #define COMP_PUBLISH_UP_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define COMP_PUBLISH_UP_EN_Pos (31UL)              /*!< Position of EN field.                                                */
  #define COMP_PUBLISH_UP_EN_Msk (0x1UL << COMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field.                                  */
  #define COMP_PUBLISH_UP_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
  #define COMP_PUBLISH_UP_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
  #define COMP_PUBLISH_UP_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
  #define COMP_PUBLISH_UP_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */


/* COMP_PUBLISH_CROSS: Publish configuration for event CROSS */
  #define COMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */
  #define COMP_PUBLISH_CROSS_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define COMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << COMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define COMP_PUBLISH_CROSS_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define COMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define COMP_PUBLISH_CROSS_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define COMP_PUBLISH_CROSS_EN_Msk (0x1UL << COMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field.                            */
  #define COMP_PUBLISH_CROSS_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define COMP_PUBLISH_CROSS_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define COMP_PUBLISH_CROSS_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define COMP_PUBLISH_CROSS_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* COMP_SHORTS: Shortcuts between local events and tasks */
  #define COMP_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */
  #define COMP_SHORTS_READY_SAMPLE_Pos (0UL)         /*!< Position of READY_SAMPLE field.                                      */
  #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field.            */
  #define COMP_SHORTS_READY_SAMPLE_Min (0x0UL)       /*!< Min enumerator value of READY_SAMPLE field.                          */
  #define COMP_SHORTS_READY_SAMPLE_Max (0x1UL)       /*!< Max enumerator value of READY_SAMPLE field.                          */
  #define COMP_SHORTS_READY_SAMPLE_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
  #define COMP_SHORTS_READY_SAMPLE_Enabled (0x1UL)   /*!< Enable shortcut                                                      */

/* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */
  #define COMP_SHORTS_READY_STOP_Pos (1UL)           /*!< Position of READY_STOP field.                                        */
  #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field.                  */
  #define COMP_SHORTS_READY_STOP_Min (0x0UL)         /*!< Min enumerator value of READY_STOP field.                            */
  #define COMP_SHORTS_READY_STOP_Max (0x1UL)         /*!< Max enumerator value of READY_STOP field.                            */
  #define COMP_SHORTS_READY_STOP_Disabled (0x0UL)    /*!< Disable shortcut                                                     */
  #define COMP_SHORTS_READY_STOP_Enabled (0x1UL)     /*!< Enable shortcut                                                      */

/* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */
  #define COMP_SHORTS_DOWN_STOP_Pos (2UL)            /*!< Position of DOWN_STOP field.                                         */
  #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field.                     */
  #define COMP_SHORTS_DOWN_STOP_Min (0x0UL)          /*!< Min enumerator value of DOWN_STOP field.                             */
  #define COMP_SHORTS_DOWN_STOP_Max (0x1UL)          /*!< Max enumerator value of DOWN_STOP field.                             */
  #define COMP_SHORTS_DOWN_STOP_Disabled (0x0UL)     /*!< Disable shortcut                                                     */
  #define COMP_SHORTS_DOWN_STOP_Enabled (0x1UL)      /*!< Enable shortcut                                                      */

/* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */
  #define COMP_SHORTS_UP_STOP_Pos (3UL)              /*!< Position of UP_STOP field.                                           */
  #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field.                           */
  #define COMP_SHORTS_UP_STOP_Min (0x0UL)            /*!< Min enumerator value of UP_STOP field.                               */
  #define COMP_SHORTS_UP_STOP_Max (0x1UL)            /*!< Max enumerator value of UP_STOP field.                               */
  #define COMP_SHORTS_UP_STOP_Disabled (0x0UL)       /*!< Disable shortcut                                                     */
  #define COMP_SHORTS_UP_STOP_Enabled (0x1UL)        /*!< Enable shortcut                                                      */

/* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */
  #define COMP_SHORTS_CROSS_STOP_Pos (4UL)           /*!< Position of CROSS_STOP field.                                        */
  #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field.                  */
  #define COMP_SHORTS_CROSS_STOP_Min (0x0UL)         /*!< Min enumerator value of CROSS_STOP field.                            */
  #define COMP_SHORTS_CROSS_STOP_Max (0x1UL)         /*!< Max enumerator value of CROSS_STOP field.                            */
  #define COMP_SHORTS_CROSS_STOP_Disabled (0x0UL)    /*!< Disable shortcut                                                     */
  #define COMP_SHORTS_CROSS_STOP_Enabled (0x1UL)     /*!< Enable shortcut                                                      */


/* COMP_INTEN: Enable or disable interrupt */
  #define COMP_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */

/* READY @Bit 0 : Enable or disable interrupt for event READY */
  #define COMP_INTEN_READY_Pos (0UL)                 /*!< Position of READY field.                                             */
  #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field.                                   */
  #define COMP_INTEN_READY_Min (0x0UL)               /*!< Min enumerator value of READY field.                                 */
  #define COMP_INTEN_READY_Max (0x1UL)               /*!< Max enumerator value of READY field.                                 */
  #define COMP_INTEN_READY_Disabled (0x0UL)          /*!< Disable                                                              */
  #define COMP_INTEN_READY_Enabled (0x1UL)           /*!< Enable                                                               */

/* DOWN @Bit 1 : Enable or disable interrupt for event DOWN */
  #define COMP_INTEN_DOWN_Pos (1UL)                  /*!< Position of DOWN field.                                              */
  #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field.                                      */
  #define COMP_INTEN_DOWN_Min (0x0UL)                /*!< Min enumerator value of DOWN field.                                  */
  #define COMP_INTEN_DOWN_Max (0x1UL)                /*!< Max enumerator value of DOWN field.                                  */
  #define COMP_INTEN_DOWN_Disabled (0x0UL)           /*!< Disable                                                              */
  #define COMP_INTEN_DOWN_Enabled (0x1UL)            /*!< Enable                                                               */

/* UP @Bit 2 : Enable or disable interrupt for event UP */
  #define COMP_INTEN_UP_Pos (2UL)                    /*!< Position of UP field.                                                */
  #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field.                                            */
  #define COMP_INTEN_UP_Min (0x0UL)                  /*!< Min enumerator value of UP field.                                    */
  #define COMP_INTEN_UP_Max (0x1UL)                  /*!< Max enumerator value of UP field.                                    */
  #define COMP_INTEN_UP_Disabled (0x0UL)             /*!< Disable                                                              */
  #define COMP_INTEN_UP_Enabled (0x1UL)              /*!< Enable                                                               */

/* CROSS @Bit 3 : Enable or disable interrupt for event CROSS */
  #define COMP_INTEN_CROSS_Pos (3UL)                 /*!< Position of CROSS field.                                             */
  #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field.                                   */
  #define COMP_INTEN_CROSS_Min (0x0UL)               /*!< Min enumerator value of CROSS field.                                 */
  #define COMP_INTEN_CROSS_Max (0x1UL)               /*!< Max enumerator value of CROSS field.                                 */
  #define COMP_INTEN_CROSS_Disabled (0x0UL)          /*!< Disable                                                              */
  #define COMP_INTEN_CROSS_Enabled (0x1UL)           /*!< Enable                                                               */


/* COMP_INTENSET: Enable interrupt */
  #define COMP_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* READY @Bit 0 : Write '1' to enable interrupt for event READY */
  #define COMP_INTENSET_READY_Pos (0UL)              /*!< Position of READY field.                                             */
  #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field.                             */
  #define COMP_INTENSET_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
  #define COMP_INTENSET_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
  #define COMP_INTENSET_READY_Set (0x1UL)            /*!< Enable                                                               */
  #define COMP_INTENSET_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define COMP_INTENSET_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */
  #define COMP_INTENSET_DOWN_Pos (1UL)               /*!< Position of DOWN field.                                              */
  #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field.                                */
  #define COMP_INTENSET_DOWN_Min (0x0UL)             /*!< Min enumerator value of DOWN field.                                  */
  #define COMP_INTENSET_DOWN_Max (0x1UL)             /*!< Max enumerator value of DOWN field.                                  */
  #define COMP_INTENSET_DOWN_Set (0x1UL)             /*!< Enable                                                               */
  #define COMP_INTENSET_DOWN_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define COMP_INTENSET_DOWN_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* UP @Bit 2 : Write '1' to enable interrupt for event UP */
  #define COMP_INTENSET_UP_Pos (2UL)                 /*!< Position of UP field.                                                */
  #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field.                                      */
  #define COMP_INTENSET_UP_Min (0x0UL)               /*!< Min enumerator value of UP field.                                    */
  #define COMP_INTENSET_UP_Max (0x1UL)               /*!< Max enumerator value of UP field.                                    */
  #define COMP_INTENSET_UP_Set (0x1UL)               /*!< Enable                                                               */
  #define COMP_INTENSET_UP_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define COMP_INTENSET_UP_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */
  #define COMP_INTENSET_CROSS_Pos (3UL)              /*!< Position of CROSS field.                                             */
  #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field.                             */
  #define COMP_INTENSET_CROSS_Min (0x0UL)            /*!< Min enumerator value of CROSS field.                                 */
  #define COMP_INTENSET_CROSS_Max (0x1UL)            /*!< Max enumerator value of CROSS field.                                 */
  #define COMP_INTENSET_CROSS_Set (0x1UL)            /*!< Enable                                                               */
  #define COMP_INTENSET_CROSS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define COMP_INTENSET_CROSS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */


/* COMP_INTENCLR: Disable interrupt */
  #define COMP_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* READY @Bit 0 : Write '1' to disable interrupt for event READY */
  #define COMP_INTENCLR_READY_Pos (0UL)              /*!< Position of READY field.                                             */
  #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field.                             */
  #define COMP_INTENCLR_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
  #define COMP_INTENCLR_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
  #define COMP_INTENCLR_READY_Clear (0x1UL)          /*!< Disable                                                              */
  #define COMP_INTENCLR_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define COMP_INTENCLR_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */
  #define COMP_INTENCLR_DOWN_Pos (1UL)               /*!< Position of DOWN field.                                              */
  #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field.                                */
  #define COMP_INTENCLR_DOWN_Min (0x0UL)             /*!< Min enumerator value of DOWN field.                                  */
  #define COMP_INTENCLR_DOWN_Max (0x1UL)             /*!< Max enumerator value of DOWN field.                                  */
  #define COMP_INTENCLR_DOWN_Clear (0x1UL)           /*!< Disable                                                              */
  #define COMP_INTENCLR_DOWN_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define COMP_INTENCLR_DOWN_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* UP @Bit 2 : Write '1' to disable interrupt for event UP */
  #define COMP_INTENCLR_UP_Pos (2UL)                 /*!< Position of UP field.                                                */
  #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field.                                      */
  #define COMP_INTENCLR_UP_Min (0x0UL)               /*!< Min enumerator value of UP field.                                    */
  #define COMP_INTENCLR_UP_Max (0x1UL)               /*!< Max enumerator value of UP field.                                    */
  #define COMP_INTENCLR_UP_Clear (0x1UL)             /*!< Disable                                                              */
  #define COMP_INTENCLR_UP_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define COMP_INTENCLR_UP_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */
  #define COMP_INTENCLR_CROSS_Pos (3UL)              /*!< Position of CROSS field.                                             */
  #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field.                             */
  #define COMP_INTENCLR_CROSS_Min (0x0UL)            /*!< Min enumerator value of CROSS field.                                 */
  #define COMP_INTENCLR_CROSS_Max (0x1UL)            /*!< Max enumerator value of CROSS field.                                 */
  #define COMP_INTENCLR_CROSS_Clear (0x1UL)          /*!< Disable                                                              */
  #define COMP_INTENCLR_CROSS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define COMP_INTENCLR_CROSS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */


/* COMP_INTPEND: Pending interrupts */
  #define COMP_INTPEND_ResetValue (0x00000000UL)     /*!< Reset value of INTPEND register.                                     */

/* READY @Bit 0 : Read pending status of interrupt for event READY */
  #define COMP_INTPEND_READY_Pos (0UL)               /*!< Position of READY field.                                             */
  #define COMP_INTPEND_READY_Msk (0x1UL << COMP_INTPEND_READY_Pos) /*!< Bit mask of READY field.                               */
  #define COMP_INTPEND_READY_Min (0x0UL)             /*!< Min enumerator value of READY field.                                 */
  #define COMP_INTPEND_READY_Max (0x1UL)             /*!< Max enumerator value of READY field.                                 */
  #define COMP_INTPEND_READY_NotPending (0x0UL)      /*!< Read: Not pending                                                    */
  #define COMP_INTPEND_READY_Pending (0x1UL)         /*!< Read: Pending                                                        */

/* DOWN @Bit 1 : Read pending status of interrupt for event DOWN */
  #define COMP_INTPEND_DOWN_Pos (1UL)                /*!< Position of DOWN field.                                              */
  #define COMP_INTPEND_DOWN_Msk (0x1UL << COMP_INTPEND_DOWN_Pos) /*!< Bit mask of DOWN field.                                  */
  #define COMP_INTPEND_DOWN_Min (0x0UL)              /*!< Min enumerator value of DOWN field.                                  */
  #define COMP_INTPEND_DOWN_Max (0x1UL)              /*!< Max enumerator value of DOWN field.                                  */
  #define COMP_INTPEND_DOWN_NotPending (0x0UL)       /*!< Read: Not pending                                                    */
  #define COMP_INTPEND_DOWN_Pending (0x1UL)          /*!< Read: Pending                                                        */

/* UP @Bit 2 : Read pending status of interrupt for event UP */
  #define COMP_INTPEND_UP_Pos (2UL)                  /*!< Position of UP field.                                                */
  #define COMP_INTPEND_UP_Msk (0x1UL << COMP_INTPEND_UP_Pos) /*!< Bit mask of UP field.                                        */
  #define COMP_INTPEND_UP_Min (0x0UL)                /*!< Min enumerator value of UP field.                                    */
  #define COMP_INTPEND_UP_Max (0x1UL)                /*!< Max enumerator value of UP field.                                    */
  #define COMP_INTPEND_UP_NotPending (0x0UL)         /*!< Read: Not pending                                                    */
  #define COMP_INTPEND_UP_Pending (0x1UL)            /*!< Read: Pending                                                        */

/* CROSS @Bit 3 : Read pending status of interrupt for event CROSS */
  #define COMP_INTPEND_CROSS_Pos (3UL)               /*!< Position of CROSS field.                                             */
  #define COMP_INTPEND_CROSS_Msk (0x1UL << COMP_INTPEND_CROSS_Pos) /*!< Bit mask of CROSS field.                               */
  #define COMP_INTPEND_CROSS_Min (0x0UL)             /*!< Min enumerator value of CROSS field.                                 */
  #define COMP_INTPEND_CROSS_Max (0x1UL)             /*!< Max enumerator value of CROSS field.                                 */
  #define COMP_INTPEND_CROSS_NotPending (0x0UL)      /*!< Read: Not pending                                                    */
  #define COMP_INTPEND_CROSS_Pending (0x1UL)         /*!< Read: Pending                                                        */


/* COMP_RESULT: Compare result */
  #define COMP_RESULT_ResetValue (0x00000000UL)      /*!< Reset value of RESULT register.                                      */

/* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */
  #define COMP_RESULT_RESULT_Pos (0UL)               /*!< Position of RESULT field.                                            */
  #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field.                              */
  #define COMP_RESULT_RESULT_Min (0x0UL)             /*!< Min enumerator value of RESULT field.                                */
  #define COMP_RESULT_RESULT_Max (0x1UL)             /*!< Max enumerator value of RESULT field.                                */
  #define COMP_RESULT_RESULT_Below (0x0UL)           /*!< Input voltage is below the threshold (VIN+ < VIN-)                   */
  #define COMP_RESULT_RESULT_Above (0x1UL)           /*!< Input voltage is above the threshold (VIN+ > VIN-)                   */


/* COMP_ENABLE: COMP enable */
  #define COMP_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..1 : Enable or disable COMP */
  #define COMP_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
  #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
  #define COMP_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
  #define COMP_ENABLE_ENABLE_Max (0x2UL)             /*!< Max enumerator value of ENABLE field.                                */
  #define COMP_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable                                                              */
  #define COMP_ENABLE_ENABLE_Enabled (0x2UL)         /*!< Enable                                                               */


/* COMP_PSEL: Pin select */
  #define COMP_PSEL_ResetValue (0x00000000UL)        /*!< Reset value of PSEL register.                                        */

/* PIN @Bits 0..4 : Analog pin select */
  #define COMP_PSEL_PIN_Pos (0UL)                    /*!< Position of PIN field.                                               */
  #define COMP_PSEL_PIN_Msk (0x1FUL << COMP_PSEL_PIN_Pos) /*!< Bit mask of PIN field.                                          */

/* PORT @Bits 8..11 : GPIO Port selection */
  #define COMP_PSEL_PORT_Pos (8UL)                   /*!< Position of PORT field.                                              */
  #define COMP_PSEL_PORT_Msk (0xFUL << COMP_PSEL_PORT_Pos) /*!< Bit mask of PORT field.                                        */


/* COMP_REFSEL: Reference source select for single-ended mode */
  #define COMP_REFSEL_ResetValue (0x00000004UL)      /*!< Reset value of REFSEL register.                                      */

/* REFSEL @Bits 0..2 : Reference select */
  #define COMP_REFSEL_REFSEL_Pos (0UL)               /*!< Position of REFSEL field.                                            */
  #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field.                              */
  #define COMP_REFSEL_REFSEL_Min (0x0UL)             /*!< Min enumerator value of REFSEL field.                                */
  #define COMP_REFSEL_REFSEL_Max (0x5UL)             /*!< Max enumerator value of REFSEL field.                                */
  #define COMP_REFSEL_REFSEL_Int1V2 (0x0UL)          /*!< VREF = internal 1.2 V reference                                      */
  #define COMP_REFSEL_REFSEL_VDD (0x4UL)             /*!< VREF = VDD                                                           */
  #define COMP_REFSEL_REFSEL_ARef (0x5UL)            /*!< VREF = AREF                                                          */


/* COMP_EXTREFSEL: External reference select */
  #define COMP_EXTREFSEL_ResetValue (0x00000000UL)   /*!< Reset value of EXTREFSEL register.                                   */

/* PIN @Bits 0..4 : External analog reference pin select */
  #define COMP_EXTREFSEL_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define COMP_EXTREFSEL_PIN_Msk (0x1FUL << COMP_EXTREFSEL_PIN_Pos) /*!< Bit mask of PIN field.                                */

/* PORT @Bits 8..11 : GPIO Port selection */
  #define COMP_EXTREFSEL_PORT_Pos (8UL)              /*!< Position of PORT field.                                              */
  #define COMP_EXTREFSEL_PORT_Msk (0xFUL << COMP_EXTREFSEL_PORT_Pos) /*!< Bit mask of PORT field.                              */


/* COMP_TH: Threshold configuration for hysteresis unit */
  #define COMP_TH_ResetValue (0x00002020UL)          /*!< Reset value of TH register.                                          */

/* THDOWN @Bits 0..5 : VDOWN = (THDOWN+1)/64*VREF */
  #define COMP_TH_THDOWN_Pos (0UL)                   /*!< Position of THDOWN field.                                            */
  #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field.                                     */
  #define COMP_TH_THDOWN_Min (0x00UL)                /*!< Min value of THDOWN field.                                           */
  #define COMP_TH_THDOWN_Max (0x3FUL)                /*!< Max size of THDOWN field.                                            */

/* THUP @Bits 8..13 : VUP = (THUP+1)/64*VREF */
  #define COMP_TH_THUP_Pos (8UL)                     /*!< Position of THUP field.                                              */
  #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field.                                           */
  #define COMP_TH_THUP_Min (0x00UL)                  /*!< Min value of THUP field.                                             */
  #define COMP_TH_THUP_Max (0x3FUL)                  /*!< Max size of THUP field.                                              */


/* COMP_MODE: Mode configuration */
  #define COMP_MODE_ResetValue (0x00000000UL)        /*!< Reset value of MODE register.                                        */

/* SP @Bits 0..1 : Speed and power modes */
  #define COMP_MODE_SP_Pos (0UL)                     /*!< Position of SP field.                                                */
  #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field.                                              */
  #define COMP_MODE_SP_Min (0x0UL)                   /*!< Min enumerator value of SP field.                                    */
  #define COMP_MODE_SP_Max (0x2UL)                   /*!< Max enumerator value of SP field.                                    */
  #define COMP_MODE_SP_Low (0x0UL)                   /*!< Low-power mode                                                       */
  #define COMP_MODE_SP_Normal (0x1UL)                /*!< Normal mode                                                          */
  #define COMP_MODE_SP_High (0x2UL)                  /*!< High-speed mode                                                      */

/* MAIN @Bit 8 : Main operation modes */
  #define COMP_MODE_MAIN_Pos (8UL)                   /*!< Position of MAIN field.                                              */
  #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field.                                        */
  #define COMP_MODE_MAIN_Min (0x0UL)                 /*!< Min enumerator value of MAIN field.                                  */
  #define COMP_MODE_MAIN_Max (0x1UL)                 /*!< Max enumerator value of MAIN field.                                  */
  #define COMP_MODE_MAIN_SE (0x0UL)                  /*!< Single-ended mode                                                    */
  #define COMP_MODE_MAIN_Diff (0x1UL)                /*!< Differential mode                                                    */


/* COMP_HYST: Comparator hysteresis enable */
  #define COMP_HYST_ResetValue (0x00000000UL)        /*!< Reset value of HYST register.                                        */

/* HYST @Bit 0 : Comparator hysteresis */
  #define COMP_HYST_HYST_Pos (0UL)                   /*!< Position of HYST field.                                              */
  #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field.                                        */
  #define COMP_HYST_HYST_Min (0x0UL)                 /*!< Min enumerator value of HYST field.                                  */
  #define COMP_HYST_HYST_Max (0x1UL)                 /*!< Max enumerator value of HYST field.                                  */
  #define COMP_HYST_HYST_NoHyst (0x0UL)              /*!< Comparator hysteresis disabled                                       */
  #define COMP_HYST_HYST_Hyst40mV (0x1UL)            /*!< Comparator hysteresis enabled                                        */


/* COMP_ISOURCE: Current source select on analog input */
  #define COMP_ISOURCE_ResetValue (0x00000000UL)     /*!< Reset value of ISOURCE register.                                     */

/* ISOURCE @Bits 0..1 : Current source select on analog input */
  #define COMP_ISOURCE_ISOURCE_Pos (0UL)             /*!< Position of ISOURCE field.                                           */
  #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field.                         */
  #define COMP_ISOURCE_ISOURCE_Min (0x0UL)           /*!< Min enumerator value of ISOURCE field.                               */
  #define COMP_ISOURCE_ISOURCE_Max (0x3UL)           /*!< Max enumerator value of ISOURCE field.                               */
  #define COMP_ISOURCE_ISOURCE_Off (0x0UL)           /*!< Current source disabled                                              */
  #define COMP_ISOURCE_ISOURCE_Ien2uA5 (0x1UL)       /*!< Current source enabled (+/- 2.5 uA)                                  */
  #define COMP_ISOURCE_ISOURCE_Ien5uA (0x2UL)        /*!< Current source enabled (+/- 5 uA)                                    */
  #define COMP_ISOURCE_ISOURCE_Ien10uA (0x3UL)       /*!< Current source enabled (+/- 10 uA)                                   */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           CPUC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct CPUC ======================================================= */
/**
  * @brief CPU control
  */
  typedef struct {                                   /*!< CPUC Structure                                                       */
    __IM uint32_t RESERVED[64];
    __IOM uint32_t EVENTS_FPUIOC;                    /*!< (@ 0x00000100) An invalid operation exception has occurred in the
                                                                         FPU.*/
    __IOM uint32_t EVENTS_FPUDZC;                    /*!< (@ 0x00000104) A floating-point divide-by-zero exception has occurred
                                                                         in the FPU.*/
    __IOM uint32_t EVENTS_FPUOFC;                    /*!< (@ 0x00000108) A floating-point overflow exception has occurred in the
                                                                         FPU.*/
    __IOM uint32_t EVENTS_FPUUFC;                    /*!< (@ 0x0000010C) A floating-point underflow exception has occurred in
                                                                         the FPU.*/
    __IOM uint32_t EVENTS_FPUIXC;                    /*!< (@ 0x00000110) A floating-point inexact exception has occurred in the
                                                                         FPU.*/
    __IOM uint32_t EVENTS_FPUIDC;                    /*!< (@ 0x00000114) A floating-point input denormal exception has occurred
                                                                         in the FPU.*/
    __IM uint32_t RESERVED1[122];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED2[125];
    __IOM uint32_t LOCK;                             /*!< (@ 0x00000500) Register to lock the certain parts of the CPU from
                                                                         being modified.*/
    __IM uint32_t CPUID;                             /*!< (@ 0x00000504) The identifier for the CPU in this subsystem.         */
  } NRF_CPUC_Type;                                   /*!< Size = 1288 (0x508)                                                  */

/* CPUC_EVENTS_FPUIOC: An invalid operation exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUIOC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIOC register.                             */

/* EVENTS_FPUIOC @Bit 0 : An invalid operation exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos (0UL) /*!< Position of EVENTS_FPUIOC field.                                     */
  #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Msk (0x1UL << CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos) /*!< Bit mask of EVENTS_FPUIOC
                                                                            field.*/
  #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIOC field.                       */
  #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIOC field.                       */
  #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define CPUC_EVENTS_FPUIOC_EVENTS_FPUIOC_Generated (0x1UL) /*!< Event generated                                              */


/* CPUC_EVENTS_FPUDZC: A floating-point divide-by-zero exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUDZC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUDZC register.                             */

/* EVENTS_FPUDZC @Bit 0 : A floating-point divide-by-zero exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos (0UL) /*!< Position of EVENTS_FPUDZC field.                                     */
  #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Msk (0x1UL << CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos) /*!< Bit mask of EVENTS_FPUDZC
                                                                            field.*/
  #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUDZC field.                       */
  #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUDZC field.                       */
  #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define CPUC_EVENTS_FPUDZC_EVENTS_FPUDZC_Generated (0x1UL) /*!< Event generated                                              */


/* CPUC_EVENTS_FPUOFC: A floating-point overflow exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUOFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUOFC register.                             */

/* EVENTS_FPUOFC @Bit 0 : A floating-point overflow exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos (0UL) /*!< Position of EVENTS_FPUOFC field.                                     */
  #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Msk (0x1UL << CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos) /*!< Bit mask of EVENTS_FPUOFC
                                                                            field.*/
  #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUOFC field.                       */
  #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUOFC field.                       */
  #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define CPUC_EVENTS_FPUOFC_EVENTS_FPUOFC_Generated (0x1UL) /*!< Event generated                                              */


/* CPUC_EVENTS_FPUUFC: A floating-point underflow exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUUFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUUFC register.                             */

/* EVENTS_FPUUFC @Bit 0 : A floating-point underflow exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos (0UL) /*!< Position of EVENTS_FPUUFC field.                                     */
  #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Msk (0x1UL << CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos) /*!< Bit mask of EVENTS_FPUUFC
                                                                            field.*/
  #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUUFC field.                       */
  #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUUFC field.                       */
  #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define CPUC_EVENTS_FPUUFC_EVENTS_FPUUFC_Generated (0x1UL) /*!< Event generated                                              */


/* CPUC_EVENTS_FPUIXC: A floating-point inexact exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUIXC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIXC register.                             */

/* EVENTS_FPUIXC @Bit 0 : A floating-point inexact exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos (0UL) /*!< Position of EVENTS_FPUIXC field.                                     */
  #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Msk (0x1UL << CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos) /*!< Bit mask of EVENTS_FPUIXC
                                                                            field.*/
  #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIXC field.                       */
  #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIXC field.                       */
  #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define CPUC_EVENTS_FPUIXC_EVENTS_FPUIXC_Generated (0x1UL) /*!< Event generated                                              */


/* CPUC_EVENTS_FPUIDC: A floating-point input denormal exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUIDC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIDC register.                             */

/* EVENTS_FPUIDC @Bit 0 : A floating-point input denormal exception has occurred in the FPU. */
  #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos (0UL) /*!< Position of EVENTS_FPUIDC field.                                     */
  #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Msk (0x1UL << CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos) /*!< Bit mask of EVENTS_FPUIDC
                                                                            field.*/
  #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIDC field.                       */
  #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIDC field.                       */
  #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define CPUC_EVENTS_FPUIDC_EVENTS_FPUIDC_Generated (0x1UL) /*!< Event generated                                              */


/* CPUC_INTEN: Enable or disable interrupt */
  #define CPUC_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */

/* FPUIOC @Bit 0 : Enable or disable interrupt for event FPUIOC */
  #define CPUC_INTEN_FPUIOC_Pos (0UL)                /*!< Position of FPUIOC field.                                            */
  #define CPUC_INTEN_FPUIOC_Msk (0x1UL << CPUC_INTEN_FPUIOC_Pos) /*!< Bit mask of FPUIOC field.                                */
  #define CPUC_INTEN_FPUIOC_Min (0x0UL)              /*!< Min enumerator value of FPUIOC field.                                */
  #define CPUC_INTEN_FPUIOC_Max (0x1UL)              /*!< Max enumerator value of FPUIOC field.                                */
  #define CPUC_INTEN_FPUIOC_Disabled (0x0UL)         /*!< Disable                                                              */
  #define CPUC_INTEN_FPUIOC_Enabled (0x1UL)          /*!< Enable                                                               */

/* FPUDZC @Bit 1 : Enable or disable interrupt for event FPUDZC */
  #define CPUC_INTEN_FPUDZC_Pos (1UL)                /*!< Position of FPUDZC field.                                            */
  #define CPUC_INTEN_FPUDZC_Msk (0x1UL << CPUC_INTEN_FPUDZC_Pos) /*!< Bit mask of FPUDZC field.                                */
  #define CPUC_INTEN_FPUDZC_Min (0x0UL)              /*!< Min enumerator value of FPUDZC field.                                */
  #define CPUC_INTEN_FPUDZC_Max (0x1UL)              /*!< Max enumerator value of FPUDZC field.                                */
  #define CPUC_INTEN_FPUDZC_Disabled (0x0UL)         /*!< Disable                                                              */
  #define CPUC_INTEN_FPUDZC_Enabled (0x1UL)          /*!< Enable                                                               */

/* FPUOFC @Bit 2 : Enable or disable interrupt for event FPUOFC */
  #define CPUC_INTEN_FPUOFC_Pos (2UL)                /*!< Position of FPUOFC field.                                            */
  #define CPUC_INTEN_FPUOFC_Msk (0x1UL << CPUC_INTEN_FPUOFC_Pos) /*!< Bit mask of FPUOFC field.                                */
  #define CPUC_INTEN_FPUOFC_Min (0x0UL)              /*!< Min enumerator value of FPUOFC field.                                */
  #define CPUC_INTEN_FPUOFC_Max (0x1UL)              /*!< Max enumerator value of FPUOFC field.                                */
  #define CPUC_INTEN_FPUOFC_Disabled (0x0UL)         /*!< Disable                                                              */
  #define CPUC_INTEN_FPUOFC_Enabled (0x1UL)          /*!< Enable                                                               */

/* FPUUFC @Bit 3 : Enable or disable interrupt for event FPUUFC */
  #define CPUC_INTEN_FPUUFC_Pos (3UL)                /*!< Position of FPUUFC field.                                            */
  #define CPUC_INTEN_FPUUFC_Msk (0x1UL << CPUC_INTEN_FPUUFC_Pos) /*!< Bit mask of FPUUFC field.                                */
  #define CPUC_INTEN_FPUUFC_Min (0x0UL)              /*!< Min enumerator value of FPUUFC field.                                */
  #define CPUC_INTEN_FPUUFC_Max (0x1UL)              /*!< Max enumerator value of FPUUFC field.                                */
  #define CPUC_INTEN_FPUUFC_Disabled (0x0UL)         /*!< Disable                                                              */
  #define CPUC_INTEN_FPUUFC_Enabled (0x1UL)          /*!< Enable                                                               */

/* FPUIXC @Bit 4 : Enable or disable interrupt for event FPUIXC */
  #define CPUC_INTEN_FPUIXC_Pos (4UL)                /*!< Position of FPUIXC field.                                            */
  #define CPUC_INTEN_FPUIXC_Msk (0x1UL << CPUC_INTEN_FPUIXC_Pos) /*!< Bit mask of FPUIXC field.                                */
  #define CPUC_INTEN_FPUIXC_Min (0x0UL)              /*!< Min enumerator value of FPUIXC field.                                */
  #define CPUC_INTEN_FPUIXC_Max (0x1UL)              /*!< Max enumerator value of FPUIXC field.                                */
  #define CPUC_INTEN_FPUIXC_Disabled (0x0UL)         /*!< Disable                                                              */
  #define CPUC_INTEN_FPUIXC_Enabled (0x1UL)          /*!< Enable                                                               */

/* FPUIDC @Bit 5 : Enable or disable interrupt for event FPUIDC */
  #define CPUC_INTEN_FPUIDC_Pos (5UL)                /*!< Position of FPUIDC field.                                            */
  #define CPUC_INTEN_FPUIDC_Msk (0x1UL << CPUC_INTEN_FPUIDC_Pos) /*!< Bit mask of FPUIDC field.                                */
  #define CPUC_INTEN_FPUIDC_Min (0x0UL)              /*!< Min enumerator value of FPUIDC field.                                */
  #define CPUC_INTEN_FPUIDC_Max (0x1UL)              /*!< Max enumerator value of FPUIDC field.                                */
  #define CPUC_INTEN_FPUIDC_Disabled (0x0UL)         /*!< Disable                                                              */
  #define CPUC_INTEN_FPUIDC_Enabled (0x1UL)          /*!< Enable                                                               */


/* CPUC_INTENSET: Enable interrupt */
  #define CPUC_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* FPUIOC @Bit 0 : Write '1' to enable interrupt for event FPUIOC */
  #define CPUC_INTENSET_FPUIOC_Pos (0UL)             /*!< Position of FPUIOC field.                                            */
  #define CPUC_INTENSET_FPUIOC_Msk (0x1UL << CPUC_INTENSET_FPUIOC_Pos) /*!< Bit mask of FPUIOC field.                          */
  #define CPUC_INTENSET_FPUIOC_Min (0x0UL)           /*!< Min enumerator value of FPUIOC field.                                */
  #define CPUC_INTENSET_FPUIOC_Max (0x1UL)           /*!< Max enumerator value of FPUIOC field.                                */
  #define CPUC_INTENSET_FPUIOC_Set (0x1UL)           /*!< Enable                                                               */
  #define CPUC_INTENSET_FPUIOC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENSET_FPUIOC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUDZC @Bit 1 : Write '1' to enable interrupt for event FPUDZC */
  #define CPUC_INTENSET_FPUDZC_Pos (1UL)             /*!< Position of FPUDZC field.                                            */
  #define CPUC_INTENSET_FPUDZC_Msk (0x1UL << CPUC_INTENSET_FPUDZC_Pos) /*!< Bit mask of FPUDZC field.                          */
  #define CPUC_INTENSET_FPUDZC_Min (0x0UL)           /*!< Min enumerator value of FPUDZC field.                                */
  #define CPUC_INTENSET_FPUDZC_Max (0x1UL)           /*!< Max enumerator value of FPUDZC field.                                */
  #define CPUC_INTENSET_FPUDZC_Set (0x1UL)           /*!< Enable                                                               */
  #define CPUC_INTENSET_FPUDZC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENSET_FPUDZC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUOFC @Bit 2 : Write '1' to enable interrupt for event FPUOFC */
  #define CPUC_INTENSET_FPUOFC_Pos (2UL)             /*!< Position of FPUOFC field.                                            */
  #define CPUC_INTENSET_FPUOFC_Msk (0x1UL << CPUC_INTENSET_FPUOFC_Pos) /*!< Bit mask of FPUOFC field.                          */
  #define CPUC_INTENSET_FPUOFC_Min (0x0UL)           /*!< Min enumerator value of FPUOFC field.                                */
  #define CPUC_INTENSET_FPUOFC_Max (0x1UL)           /*!< Max enumerator value of FPUOFC field.                                */
  #define CPUC_INTENSET_FPUOFC_Set (0x1UL)           /*!< Enable                                                               */
  #define CPUC_INTENSET_FPUOFC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENSET_FPUOFC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUUFC @Bit 3 : Write '1' to enable interrupt for event FPUUFC */
  #define CPUC_INTENSET_FPUUFC_Pos (3UL)             /*!< Position of FPUUFC field.                                            */
  #define CPUC_INTENSET_FPUUFC_Msk (0x1UL << CPUC_INTENSET_FPUUFC_Pos) /*!< Bit mask of FPUUFC field.                          */
  #define CPUC_INTENSET_FPUUFC_Min (0x0UL)           /*!< Min enumerator value of FPUUFC field.                                */
  #define CPUC_INTENSET_FPUUFC_Max (0x1UL)           /*!< Max enumerator value of FPUUFC field.                                */
  #define CPUC_INTENSET_FPUUFC_Set (0x1UL)           /*!< Enable                                                               */
  #define CPUC_INTENSET_FPUUFC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENSET_FPUUFC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUIXC @Bit 4 : Write '1' to enable interrupt for event FPUIXC */
  #define CPUC_INTENSET_FPUIXC_Pos (4UL)             /*!< Position of FPUIXC field.                                            */
  #define CPUC_INTENSET_FPUIXC_Msk (0x1UL << CPUC_INTENSET_FPUIXC_Pos) /*!< Bit mask of FPUIXC field.                          */
  #define CPUC_INTENSET_FPUIXC_Min (0x0UL)           /*!< Min enumerator value of FPUIXC field.                                */
  #define CPUC_INTENSET_FPUIXC_Max (0x1UL)           /*!< Max enumerator value of FPUIXC field.                                */
  #define CPUC_INTENSET_FPUIXC_Set (0x1UL)           /*!< Enable                                                               */
  #define CPUC_INTENSET_FPUIXC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENSET_FPUIXC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUIDC @Bit 5 : Write '1' to enable interrupt for event FPUIDC */
  #define CPUC_INTENSET_FPUIDC_Pos (5UL)             /*!< Position of FPUIDC field.                                            */
  #define CPUC_INTENSET_FPUIDC_Msk (0x1UL << CPUC_INTENSET_FPUIDC_Pos) /*!< Bit mask of FPUIDC field.                          */
  #define CPUC_INTENSET_FPUIDC_Min (0x0UL)           /*!< Min enumerator value of FPUIDC field.                                */
  #define CPUC_INTENSET_FPUIDC_Max (0x1UL)           /*!< Max enumerator value of FPUIDC field.                                */
  #define CPUC_INTENSET_FPUIDC_Set (0x1UL)           /*!< Enable                                                               */
  #define CPUC_INTENSET_FPUIDC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENSET_FPUIDC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */


/* CPUC_INTENCLR: Disable interrupt */
  #define CPUC_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* FPUIOC @Bit 0 : Write '1' to disable interrupt for event FPUIOC */
  #define CPUC_INTENCLR_FPUIOC_Pos (0UL)             /*!< Position of FPUIOC field.                                            */
  #define CPUC_INTENCLR_FPUIOC_Msk (0x1UL << CPUC_INTENCLR_FPUIOC_Pos) /*!< Bit mask of FPUIOC field.                          */
  #define CPUC_INTENCLR_FPUIOC_Min (0x0UL)           /*!< Min enumerator value of FPUIOC field.                                */
  #define CPUC_INTENCLR_FPUIOC_Max (0x1UL)           /*!< Max enumerator value of FPUIOC field.                                */
  #define CPUC_INTENCLR_FPUIOC_Clear (0x1UL)         /*!< Disable                                                              */
  #define CPUC_INTENCLR_FPUIOC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENCLR_FPUIOC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUDZC @Bit 1 : Write '1' to disable interrupt for event FPUDZC */
  #define CPUC_INTENCLR_FPUDZC_Pos (1UL)             /*!< Position of FPUDZC field.                                            */
  #define CPUC_INTENCLR_FPUDZC_Msk (0x1UL << CPUC_INTENCLR_FPUDZC_Pos) /*!< Bit mask of FPUDZC field.                          */
  #define CPUC_INTENCLR_FPUDZC_Min (0x0UL)           /*!< Min enumerator value of FPUDZC field.                                */
  #define CPUC_INTENCLR_FPUDZC_Max (0x1UL)           /*!< Max enumerator value of FPUDZC field.                                */
  #define CPUC_INTENCLR_FPUDZC_Clear (0x1UL)         /*!< Disable                                                              */
  #define CPUC_INTENCLR_FPUDZC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENCLR_FPUDZC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUOFC @Bit 2 : Write '1' to disable interrupt for event FPUOFC */
  #define CPUC_INTENCLR_FPUOFC_Pos (2UL)             /*!< Position of FPUOFC field.                                            */
  #define CPUC_INTENCLR_FPUOFC_Msk (0x1UL << CPUC_INTENCLR_FPUOFC_Pos) /*!< Bit mask of FPUOFC field.                          */
  #define CPUC_INTENCLR_FPUOFC_Min (0x0UL)           /*!< Min enumerator value of FPUOFC field.                                */
  #define CPUC_INTENCLR_FPUOFC_Max (0x1UL)           /*!< Max enumerator value of FPUOFC field.                                */
  #define CPUC_INTENCLR_FPUOFC_Clear (0x1UL)         /*!< Disable                                                              */
  #define CPUC_INTENCLR_FPUOFC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENCLR_FPUOFC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUUFC @Bit 3 : Write '1' to disable interrupt for event FPUUFC */
  #define CPUC_INTENCLR_FPUUFC_Pos (3UL)             /*!< Position of FPUUFC field.                                            */
  #define CPUC_INTENCLR_FPUUFC_Msk (0x1UL << CPUC_INTENCLR_FPUUFC_Pos) /*!< Bit mask of FPUUFC field.                          */
  #define CPUC_INTENCLR_FPUUFC_Min (0x0UL)           /*!< Min enumerator value of FPUUFC field.                                */
  #define CPUC_INTENCLR_FPUUFC_Max (0x1UL)           /*!< Max enumerator value of FPUUFC field.                                */
  #define CPUC_INTENCLR_FPUUFC_Clear (0x1UL)         /*!< Disable                                                              */
  #define CPUC_INTENCLR_FPUUFC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENCLR_FPUUFC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUIXC @Bit 4 : Write '1' to disable interrupt for event FPUIXC */
  #define CPUC_INTENCLR_FPUIXC_Pos (4UL)             /*!< Position of FPUIXC field.                                            */
  #define CPUC_INTENCLR_FPUIXC_Msk (0x1UL << CPUC_INTENCLR_FPUIXC_Pos) /*!< Bit mask of FPUIXC field.                          */
  #define CPUC_INTENCLR_FPUIXC_Min (0x0UL)           /*!< Min enumerator value of FPUIXC field.                                */
  #define CPUC_INTENCLR_FPUIXC_Max (0x1UL)           /*!< Max enumerator value of FPUIXC field.                                */
  #define CPUC_INTENCLR_FPUIXC_Clear (0x1UL)         /*!< Disable                                                              */
  #define CPUC_INTENCLR_FPUIXC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENCLR_FPUIXC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* FPUIDC @Bit 5 : Write '1' to disable interrupt for event FPUIDC */
  #define CPUC_INTENCLR_FPUIDC_Pos (5UL)             /*!< Position of FPUIDC field.                                            */
  #define CPUC_INTENCLR_FPUIDC_Msk (0x1UL << CPUC_INTENCLR_FPUIDC_Pos) /*!< Bit mask of FPUIDC field.                          */
  #define CPUC_INTENCLR_FPUIDC_Min (0x0UL)           /*!< Min enumerator value of FPUIDC field.                                */
  #define CPUC_INTENCLR_FPUIDC_Max (0x1UL)           /*!< Max enumerator value of FPUIDC field.                                */
  #define CPUC_INTENCLR_FPUIDC_Clear (0x1UL)         /*!< Disable                                                              */
  #define CPUC_INTENCLR_FPUIDC_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define CPUC_INTENCLR_FPUIDC_Enabled (0x1UL)       /*!< Read: Enabled                                                        */


/* CPUC_LOCK: Register to lock the certain parts of the CPU from being modified. */
  #define CPUC_LOCK_ResetValue (0x00000000UL)        /*!< Reset value of LOCK register.                                        */

/* LOCKVTORAIRCRS @Bit 0 : Locks both the Vector table Offset Register (VTOR) and Application Interrupt and Reset Control
                           Register (AIRCR) for secure mode. */

  #define CPUC_LOCK_LOCKVTORAIRCRS_Pos (0UL)         /*!< Position of LOCKVTORAIRCRS field.                                    */
  #define CPUC_LOCK_LOCKVTORAIRCRS_Msk (0x1UL << CPUC_LOCK_LOCKVTORAIRCRS_Pos) /*!< Bit mask of LOCKVTORAIRCRS field.          */
  #define CPUC_LOCK_LOCKVTORAIRCRS_Min (0x0UL)       /*!< Min enumerator value of LOCKVTORAIRCRS field.                        */
  #define CPUC_LOCK_LOCKVTORAIRCRS_Max (0x1UL)       /*!< Max enumerator value of LOCKVTORAIRCRS field.                        */
  #define CPUC_LOCK_LOCKVTORAIRCRS_NotLocked (0x0UL) /*!< Both VTOR and AIRCR can be changed.                                  */
  #define CPUC_LOCK_LOCKVTORAIRCRS_Locked (0x1UL)    /*!< Prevents changes to both VTOR and AIRCR.                             */

/* LOCKVTORNS @Bit 1 : Locks the Vector table Offset Register (VTOR) for non-secure mode. */
  #define CPUC_LOCK_LOCKVTORNS_Pos (1UL)             /*!< Position of LOCKVTORNS field.                                        */
  #define CPUC_LOCK_LOCKVTORNS_Msk (0x1UL << CPUC_LOCK_LOCKVTORNS_Pos) /*!< Bit mask of LOCKVTORNS field.                      */
  #define CPUC_LOCK_LOCKVTORNS_Min (0x0UL)           /*!< Min enumerator value of LOCKVTORNS field.                            */
  #define CPUC_LOCK_LOCKVTORNS_Max (0x1UL)           /*!< Max enumerator value of LOCKVTORNS field.                            */
  #define CPUC_LOCK_LOCKVTORNS_NotLocked (0x0UL)     /*!< VTOR can be changed.                                                 */
  #define CPUC_LOCK_LOCKVTORNS_Locked (0x1UL)        /*!< Prevents changes to VTOR.                                            */

/* LOCKMPUS @Bit 2 : Locks the Memory Protection Unit (MPU) for secure mode. */
  #define CPUC_LOCK_LOCKMPUS_Pos (2UL)               /*!< Position of LOCKMPUS field.                                          */
  #define CPUC_LOCK_LOCKMPUS_Msk (0x1UL << CPUC_LOCK_LOCKMPUS_Pos) /*!< Bit mask of LOCKMPUS field.                            */
  #define CPUC_LOCK_LOCKMPUS_Min (0x0UL)             /*!< Min enumerator value of LOCKMPUS field.                              */
  #define CPUC_LOCK_LOCKMPUS_Max (0x1UL)             /*!< Max enumerator value of LOCKMPUS field.                              */
  #define CPUC_LOCK_LOCKMPUS_NotLocked (0x0UL)       /*!< MPU registers can be changed.                                        */
  #define CPUC_LOCK_LOCKMPUS_Locked (0x1UL)          /*!< Prevents changes to MPU registers.                                   */

/* LOCKMPUNS @Bit 3 : Locks the Memory Protection Unit (MPU) for non secure mode. */
  #define CPUC_LOCK_LOCKMPUNS_Pos (3UL)              /*!< Position of LOCKMPUNS field.                                         */
  #define CPUC_LOCK_LOCKMPUNS_Msk (0x1UL << CPUC_LOCK_LOCKMPUNS_Pos) /*!< Bit mask of LOCKMPUNS field.                         */
  #define CPUC_LOCK_LOCKMPUNS_Min (0x0UL)            /*!< Min enumerator value of LOCKMPUNS field.                             */
  #define CPUC_LOCK_LOCKMPUNS_Max (0x1UL)            /*!< Max enumerator value of LOCKMPUNS field.                             */
  #define CPUC_LOCK_LOCKMPUNS_NotLocked (0x0UL)      /*!< MPU registers can be changed.                                        */
  #define CPUC_LOCK_LOCKMPUNS_Locked (0x1UL)         /*!< Prevents changes to MPU registers.                                   */

/* LOCKSAU @Bit 4 : Locks the Security Attribution Unit (SAU) */
  #define CPUC_LOCK_LOCKSAU_Pos (4UL)                /*!< Position of LOCKSAU field.                                           */
  #define CPUC_LOCK_LOCKSAU_Msk (0x1UL << CPUC_LOCK_LOCKSAU_Pos) /*!< Bit mask of LOCKSAU field.                               */
  #define CPUC_LOCK_LOCKSAU_Min (0x0UL)              /*!< Min enumerator value of LOCKSAU field.                               */
  #define CPUC_LOCK_LOCKSAU_Max (0x1UL)              /*!< Max enumerator value of LOCKSAU field.                               */
  #define CPUC_LOCK_LOCKSAU_NotLocked (0x0UL)        /*!< SAU registers can be changed.                                        */
  #define CPUC_LOCK_LOCKSAU_Locked (0x1UL)           /*!< Prevents changes to SAU registers.                                   */


/* CPUC_CPUID: The identifier for the CPU in this subsystem. */
  #define CPUC_CPUID_ResetValue (0x00000000UL)       /*!< Reset value of CPUID register.                                       */

/* CPUID @Bits 0..31 : The CPU identifier. */
  #define CPUC_CPUID_CPUID_Pos (0UL)                 /*!< Position of CPUID field.                                             */
  #define CPUC_CPUID_CPUID_Msk (0xFFFFFFFFUL << CPUC_CPUID_CPUID_Pos) /*!< Bit mask of CPUID field.                            */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                          CRACEN                                          ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ====================================================== Struct CRACEN ====================================================== */
/**
  * @brief CRACEN
  */
  typedef struct {                                   /*!< CRACEN Structure                                                     */
    __IM uint32_t RESERVED[64];
    __IOM uint32_t EVENTS_CRYPTOMASTER;              /*!< (@ 0x00000100) Event indicating that interrupt triggered at
                                                                         Cryptomaster*/
    __IOM uint32_t EVENTS_RNG;                       /*!< (@ 0x00000104) Event indicating that interrupt triggered at RNG      */
    __IOM uint32_t EVENTS_PKEIKG;                    /*!< (@ 0x00000108) Event indicating that interrupt triggered at PKE or
                                                                         IKG*/
    __IM uint32_t RESERVED1[125];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED2[60];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000400) Enable CRACEN peripheral modules.                     */
    __IOM uint32_t SEEDVALID;                        /*!< (@ 0x00000404) Marks the SEED register as valid.                     */
    __IM uint32_t RESERVED3[2];
    __OM uint32_t SEED[12];                          /*!< (@ 0x00000410) Seed word [n] for symmetric and asymmetric key
                                                                         generation. This register is only writable from KMU.*/
    __IOM uint32_t SEEDLOCK;                         /*!< (@ 0x00000440) Lock the access to the SEED register.                 */
    __IOM uint32_t PROTECTEDRAMLOCK;                 /*!< (@ 0x00000444) Lock the access to the protected RAM.                 */
  } NRF_CRACEN_Type;                                 /*!< Size = 1096 (0x448)                                                  */

/* CRACEN_EVENTS_CRYPTOMASTER: Event indicating that interrupt triggered at Cryptomaster */
  #define CRACEN_EVENTS_CRYPTOMASTER_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRYPTOMASTER register.               */

/* EVENTS_CRYPTOMASTER @Bit 0 : Event indicating that interrupt triggered at Cryptomaster */
  #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Pos (0UL) /*!< Position of EVENTS_CRYPTOMASTER field.                 */
  #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Msk (0x1UL << CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Pos) /*!<
                                                                            Bit mask of EVENTS_CRYPTOMASTER field.*/
  #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRYPTOMASTER field.   */
  #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRYPTOMASTER field.   */
  #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_NotGenerated (0x0UL) /*!< Event not generated                         */
  #define CRACEN_EVENTS_CRYPTOMASTER_EVENTS_CRYPTOMASTER_Generated (0x1UL) /*!< Event generated                                */


/* CRACEN_EVENTS_RNG: Event indicating that interrupt triggered at RNG */
  #define CRACEN_EVENTS_RNG_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RNG register.                                 */

/* EVENTS_RNG @Bit 0 : Event indicating that interrupt triggered at RNG */
  #define CRACEN_EVENTS_RNG_EVENTS_RNG_Pos (0UL)     /*!< Position of EVENTS_RNG field.                                        */
  #define CRACEN_EVENTS_RNG_EVENTS_RNG_Msk (0x1UL << CRACEN_EVENTS_RNG_EVENTS_RNG_Pos) /*!< Bit mask of EVENTS_RNG field.      */
  #define CRACEN_EVENTS_RNG_EVENTS_RNG_Min (0x0UL)   /*!< Min enumerator value of EVENTS_RNG field.                            */
  #define CRACEN_EVENTS_RNG_EVENTS_RNG_Max (0x1UL)   /*!< Max enumerator value of EVENTS_RNG field.                            */
  #define CRACEN_EVENTS_RNG_EVENTS_RNG_NotGenerated (0x0UL) /*!< Event not generated                                           */
  #define CRACEN_EVENTS_RNG_EVENTS_RNG_Generated (0x1UL) /*!< Event generated                                                  */


/* CRACEN_EVENTS_PKEIKG: Event indicating that interrupt triggered at PKE or IKG */
  #define CRACEN_EVENTS_PKEIKG_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PKEIKG register.                           */

/* EVENTS_PKEIKG @Bit 0 : Event indicating that interrupt triggered at PKE or IKG */
  #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Pos (0UL) /*!< Position of EVENTS_PKEIKG field.                                   */
  #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Msk (0x1UL << CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Pos) /*!< Bit mask of
                                                                            EVENTS_PKEIKG field.*/
  #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Min (0x0UL) /*!< Min enumerator value of EVENTS_PKEIKG field.                     */
  #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Max (0x1UL) /*!< Max enumerator value of EVENTS_PKEIKG field.                     */
  #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define CRACEN_EVENTS_PKEIKG_EVENTS_PKEIKG_Generated (0x1UL) /*!< Event generated                                            */


/* CRACEN_INTEN: Enable or disable interrupt */
  #define CRACEN_INTEN_ResetValue (0x00000000UL)     /*!< Reset value of INTEN register.                                       */

/* CRYPTOMASTER @Bit 0 : Enable or disable interrupt for event CRYPTOMASTER */
  #define CRACEN_INTEN_CRYPTOMASTER_Pos (0UL)        /*!< Position of CRYPTOMASTER field.                                      */
  #define CRACEN_INTEN_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTEN_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field.          */
  #define CRACEN_INTEN_CRYPTOMASTER_Min (0x0UL)      /*!< Min enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTEN_CRYPTOMASTER_Max (0x1UL)      /*!< Max enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTEN_CRYPTOMASTER_Disabled (0x0UL) /*!< Disable                                                              */
  #define CRACEN_INTEN_CRYPTOMASTER_Enabled (0x1UL)  /*!< Enable                                                               */

/* RNG @Bit 1 : Enable or disable interrupt for event RNG */
  #define CRACEN_INTEN_RNG_Pos (1UL)                 /*!< Position of RNG field.                                               */
  #define CRACEN_INTEN_RNG_Msk (0x1UL << CRACEN_INTEN_RNG_Pos) /*!< Bit mask of RNG field.                                     */
  #define CRACEN_INTEN_RNG_Min (0x0UL)               /*!< Min enumerator value of RNG field.                                   */
  #define CRACEN_INTEN_RNG_Max (0x1UL)               /*!< Max enumerator value of RNG field.                                   */
  #define CRACEN_INTEN_RNG_Disabled (0x0UL)          /*!< Disable                                                              */
  #define CRACEN_INTEN_RNG_Enabled (0x1UL)           /*!< Enable                                                               */

/* PKEIKG @Bit 2 : Enable or disable interrupt for event PKEIKG */
  #define CRACEN_INTEN_PKEIKG_Pos (2UL)              /*!< Position of PKEIKG field.                                            */
  #define CRACEN_INTEN_PKEIKG_Msk (0x1UL << CRACEN_INTEN_PKEIKG_Pos) /*!< Bit mask of PKEIKG field.                            */
  #define CRACEN_INTEN_PKEIKG_Min (0x0UL)            /*!< Min enumerator value of PKEIKG field.                                */
  #define CRACEN_INTEN_PKEIKG_Max (0x1UL)            /*!< Max enumerator value of PKEIKG field.                                */
  #define CRACEN_INTEN_PKEIKG_Disabled (0x0UL)       /*!< Disable                                                              */
  #define CRACEN_INTEN_PKEIKG_Enabled (0x1UL)        /*!< Enable                                                               */


/* CRACEN_INTENSET: Enable interrupt */
  #define CRACEN_INTENSET_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET register.                                    */

/* CRYPTOMASTER @Bit 0 : Write '1' to enable interrupt for event CRYPTOMASTER */
  #define CRACEN_INTENSET_CRYPTOMASTER_Pos (0UL)     /*!< Position of CRYPTOMASTER field.                                      */
  #define CRACEN_INTENSET_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTENSET_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field.    */
  #define CRACEN_INTENSET_CRYPTOMASTER_Min (0x0UL)   /*!< Min enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTENSET_CRYPTOMASTER_Max (0x1UL)   /*!< Max enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTENSET_CRYPTOMASTER_Set (0x1UL)   /*!< Enable                                                               */
  #define CRACEN_INTENSET_CRYPTOMASTER_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define CRACEN_INTENSET_CRYPTOMASTER_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* RNG @Bit 1 : Write '1' to enable interrupt for event RNG */
  #define CRACEN_INTENSET_RNG_Pos (1UL)              /*!< Position of RNG field.                                               */
  #define CRACEN_INTENSET_RNG_Msk (0x1UL << CRACEN_INTENSET_RNG_Pos) /*!< Bit mask of RNG field.                               */
  #define CRACEN_INTENSET_RNG_Min (0x0UL)            /*!< Min enumerator value of RNG field.                                   */
  #define CRACEN_INTENSET_RNG_Max (0x1UL)            /*!< Max enumerator value of RNG field.                                   */
  #define CRACEN_INTENSET_RNG_Set (0x1UL)            /*!< Enable                                                               */
  #define CRACEN_INTENSET_RNG_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define CRACEN_INTENSET_RNG_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* PKEIKG @Bit 2 : Write '1' to enable interrupt for event PKEIKG */
  #define CRACEN_INTENSET_PKEIKG_Pos (2UL)           /*!< Position of PKEIKG field.                                            */
  #define CRACEN_INTENSET_PKEIKG_Msk (0x1UL << CRACEN_INTENSET_PKEIKG_Pos) /*!< Bit mask of PKEIKG field.                      */
  #define CRACEN_INTENSET_PKEIKG_Min (0x0UL)         /*!< Min enumerator value of PKEIKG field.                                */
  #define CRACEN_INTENSET_PKEIKG_Max (0x1UL)         /*!< Max enumerator value of PKEIKG field.                                */
  #define CRACEN_INTENSET_PKEIKG_Set (0x1UL)         /*!< Enable                                                               */
  #define CRACEN_INTENSET_PKEIKG_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define CRACEN_INTENSET_PKEIKG_Enabled (0x1UL)     /*!< Read: Enabled                                                        */


/* CRACEN_INTENCLR: Disable interrupt */
  #define CRACEN_INTENCLR_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR register.                                    */

/* CRYPTOMASTER @Bit 0 : Write '1' to disable interrupt for event CRYPTOMASTER */
  #define CRACEN_INTENCLR_CRYPTOMASTER_Pos (0UL)     /*!< Position of CRYPTOMASTER field.                                      */
  #define CRACEN_INTENCLR_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTENCLR_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field.    */
  #define CRACEN_INTENCLR_CRYPTOMASTER_Min (0x0UL)   /*!< Min enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTENCLR_CRYPTOMASTER_Max (0x1UL)   /*!< Max enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTENCLR_CRYPTOMASTER_Clear (0x1UL) /*!< Disable                                                              */
  #define CRACEN_INTENCLR_CRYPTOMASTER_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define CRACEN_INTENCLR_CRYPTOMASTER_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* RNG @Bit 1 : Write '1' to disable interrupt for event RNG */
  #define CRACEN_INTENCLR_RNG_Pos (1UL)              /*!< Position of RNG field.                                               */
  #define CRACEN_INTENCLR_RNG_Msk (0x1UL << CRACEN_INTENCLR_RNG_Pos) /*!< Bit mask of RNG field.                               */
  #define CRACEN_INTENCLR_RNG_Min (0x0UL)            /*!< Min enumerator value of RNG field.                                   */
  #define CRACEN_INTENCLR_RNG_Max (0x1UL)            /*!< Max enumerator value of RNG field.                                   */
  #define CRACEN_INTENCLR_RNG_Clear (0x1UL)          /*!< Disable                                                              */
  #define CRACEN_INTENCLR_RNG_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define CRACEN_INTENCLR_RNG_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* PKEIKG @Bit 2 : Write '1' to disable interrupt for event PKEIKG */
  #define CRACEN_INTENCLR_PKEIKG_Pos (2UL)           /*!< Position of PKEIKG field.                                            */
  #define CRACEN_INTENCLR_PKEIKG_Msk (0x1UL << CRACEN_INTENCLR_PKEIKG_Pos) /*!< Bit mask of PKEIKG field.                      */
  #define CRACEN_INTENCLR_PKEIKG_Min (0x0UL)         /*!< Min enumerator value of PKEIKG field.                                */
  #define CRACEN_INTENCLR_PKEIKG_Max (0x1UL)         /*!< Max enumerator value of PKEIKG field.                                */
  #define CRACEN_INTENCLR_PKEIKG_Clear (0x1UL)       /*!< Disable                                                              */
  #define CRACEN_INTENCLR_PKEIKG_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define CRACEN_INTENCLR_PKEIKG_Enabled (0x1UL)     /*!< Read: Enabled                                                        */


/* CRACEN_INTPEND: Pending interrupts */
  #define CRACEN_INTPEND_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND register.                                     */

/* CRYPTOMASTER @Bit 0 : Read pending status of interrupt for event CRYPTOMASTER */
  #define CRACEN_INTPEND_CRYPTOMASTER_Pos (0UL)      /*!< Position of CRYPTOMASTER field.                                      */
  #define CRACEN_INTPEND_CRYPTOMASTER_Msk (0x1UL << CRACEN_INTPEND_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field.      */
  #define CRACEN_INTPEND_CRYPTOMASTER_Min (0x0UL)    /*!< Min enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTPEND_CRYPTOMASTER_Max (0x1UL)    /*!< Max enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_INTPEND_CRYPTOMASTER_NotPending (0x0UL) /*!< Read: Not pending                                                */
  #define CRACEN_INTPEND_CRYPTOMASTER_Pending (0x1UL) /*!< Read: Pending                                                       */

/* RNG @Bit 1 : Read pending status of interrupt for event RNG */
  #define CRACEN_INTPEND_RNG_Pos (1UL)               /*!< Position of RNG field.                                               */
  #define CRACEN_INTPEND_RNG_Msk (0x1UL << CRACEN_INTPEND_RNG_Pos) /*!< Bit mask of RNG field.                                 */
  #define CRACEN_INTPEND_RNG_Min (0x0UL)             /*!< Min enumerator value of RNG field.                                   */
  #define CRACEN_INTPEND_RNG_Max (0x1UL)             /*!< Max enumerator value of RNG field.                                   */
  #define CRACEN_INTPEND_RNG_NotPending (0x0UL)      /*!< Read: Not pending                                                    */
  #define CRACEN_INTPEND_RNG_Pending (0x1UL)         /*!< Read: Pending                                                        */

/* PKEIKG @Bit 2 : Read pending status of interrupt for event PKEIKG */
  #define CRACEN_INTPEND_PKEIKG_Pos (2UL)            /*!< Position of PKEIKG field.                                            */
  #define CRACEN_INTPEND_PKEIKG_Msk (0x1UL << CRACEN_INTPEND_PKEIKG_Pos) /*!< Bit mask of PKEIKG field.                        */
  #define CRACEN_INTPEND_PKEIKG_Min (0x0UL)          /*!< Min enumerator value of PKEIKG field.                                */
  #define CRACEN_INTPEND_PKEIKG_Max (0x1UL)          /*!< Max enumerator value of PKEIKG field.                                */
  #define CRACEN_INTPEND_PKEIKG_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
  #define CRACEN_INTPEND_PKEIKG_Pending (0x1UL)      /*!< Read: Pending                                                        */


/* CRACEN_ENABLE: Enable CRACEN peripheral modules. */
  #define CRACEN_ENABLE_ResetValue (0x00000000UL)    /*!< Reset value of ENABLE register.                                      */

/* CRYPTOMASTER @Bit 0 : Enable cryptomaster */
  #define CRACEN_ENABLE_CRYPTOMASTER_Pos (0UL)       /*!< Position of CRYPTOMASTER field.                                      */
  #define CRACEN_ENABLE_CRYPTOMASTER_Msk (0x1UL << CRACEN_ENABLE_CRYPTOMASTER_Pos) /*!< Bit mask of CRYPTOMASTER field.        */
  #define CRACEN_ENABLE_CRYPTOMASTER_Min (0x0UL)     /*!< Min enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_ENABLE_CRYPTOMASTER_Max (0x1UL)     /*!< Max enumerator value of CRYPTOMASTER field.                          */
  #define CRACEN_ENABLE_CRYPTOMASTER_Disabled (0x0UL) /*!< Cryptomaster disabled.                                              */
  #define CRACEN_ENABLE_CRYPTOMASTER_Enabled (0x1UL) /*!< Cryptomaster enabled.                                                */

/* RNG @Bit 1 : Enable RNG */
  #define CRACEN_ENABLE_RNG_Pos (1UL)                /*!< Position of RNG field.                                               */
  #define CRACEN_ENABLE_RNG_Msk (0x1UL << CRACEN_ENABLE_RNG_Pos) /*!< Bit mask of RNG field.                                   */
  #define CRACEN_ENABLE_RNG_Min (0x0UL)              /*!< Min enumerator value of RNG field.                                   */
  #define CRACEN_ENABLE_RNG_Max (0x1UL)              /*!< Max enumerator value of RNG field.                                   */
  #define CRACEN_ENABLE_RNG_Disabled (0x0UL)         /*!< RNG disabled.                                                        */
  #define CRACEN_ENABLE_RNG_Enabled (0x1UL)          /*!< RNG enabled.                                                         */

/* PKEIKG @Bit 2 : Enable PKE and IKG */
  #define CRACEN_ENABLE_PKEIKG_Pos (2UL)             /*!< Position of PKEIKG field.                                            */
  #define CRACEN_ENABLE_PKEIKG_Msk (0x1UL << CRACEN_ENABLE_PKEIKG_Pos) /*!< Bit mask of PKEIKG field.                          */
  #define CRACEN_ENABLE_PKEIKG_Min (0x0UL)           /*!< Min enumerator value of PKEIKG field.                                */
  #define CRACEN_ENABLE_PKEIKG_Max (0x1UL)           /*!< Max enumerator value of PKEIKG field.                                */
  #define CRACEN_ENABLE_PKEIKG_Disabled (0x0UL)      /*!< PKE and IKG disabled.                                                */
  #define CRACEN_ENABLE_PKEIKG_Enabled (0x1UL)       /*!< PKE and IKG enabled.                                                 */


/* CRACEN_SEEDVALID: Marks the SEED register as valid. */
  #define CRACEN_SEEDVALID_ResetValue (0x00000000UL) /*!< Reset value of SEEDVALID register.                                   */

/* VALID @Bit 0 : Marks the SEED as valid */
  #define CRACEN_SEEDVALID_VALID_Pos (0UL)           /*!< Position of VALID field.                                             */
  #define CRACEN_SEEDVALID_VALID_Msk (0x1UL << CRACEN_SEEDVALID_VALID_Pos) /*!< Bit mask of VALID field.                       */
  #define CRACEN_SEEDVALID_VALID_Min (0x0UL)         /*!< Min enumerator value of VALID field.                                 */
  #define CRACEN_SEEDVALID_VALID_Max (0x1UL)         /*!< Max enumerator value of VALID field.                                 */
  #define CRACEN_SEEDVALID_VALID_Disabled (0x0UL)    /*!< Valid disabled.                                                      */
  #define CRACEN_SEEDVALID_VALID_Enabled (0x1UL)     /*!< Valid enabled.                                                       */


/* CRACEN_SEED: Seed word [n] for symmetric and asymmetric key generation. This register is only writable from KMU. */
  #define CRACEN_SEED_MaxCount (12UL)                /*!< Max size of SEED[12] array.                                          */
  #define CRACEN_SEED_MaxIndex (11UL)                /*!< Max index of SEED[12] array.                                         */
  #define CRACEN_SEED_MinIndex (0UL)                 /*!< Min index of SEED[12] array.                                         */
  #define CRACEN_SEED_ResetValue (0x00000000UL)      /*!< Reset value of SEED[12] register.                                    */

/* VAL @Bits 0..31 : Seed value */
  #define CRACEN_SEED_VAL_Pos (0UL)                  /*!< Position of VAL field.                                               */
  #define CRACEN_SEED_VAL_Msk (0xFFFFFFFFUL << CRACEN_SEED_VAL_Pos) /*!< Bit mask of VAL field.                                */


/* CRACEN_SEEDLOCK: Lock the access to the SEED register. */
  #define CRACEN_SEEDLOCK_ResetValue (0x00000000UL)  /*!< Reset value of SEEDLOCK register.                                    */

/* ENABLE @Bit 0 : Enable the lock */
  #define CRACEN_SEEDLOCK_ENABLE_Pos (0UL)           /*!< Position of ENABLE field.                                            */
  #define CRACEN_SEEDLOCK_ENABLE_Msk (0x1UL << CRACEN_SEEDLOCK_ENABLE_Pos) /*!< Bit mask of ENABLE field.                      */
  #define CRACEN_SEEDLOCK_ENABLE_Min (0x0UL)         /*!< Min enumerator value of ENABLE field.                                */
  #define CRACEN_SEEDLOCK_ENABLE_Max (0x1UL)         /*!< Max enumerator value of ENABLE field.                                */
  #define CRACEN_SEEDLOCK_ENABLE_Disabled (0x0UL)    /*!< Lock disabled.                                                       */
  #define CRACEN_SEEDLOCK_ENABLE_Enabled (0x1UL)     /*!< Lock enabled.                                                        */


/* CRACEN_PROTECTEDRAMLOCK: Lock the access to the protected RAM. */
  #define CRACEN_PROTECTEDRAMLOCK_ResetValue (0x00000000UL) /*!< Reset value of PROTECTEDRAMLOCK register.                     */

/* ENABLE @Bit 0 : Enable the lock */
  #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Pos (0UL)   /*!< Position of ENABLE field.                                            */
  #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Msk (0x1UL << CRACEN_PROTECTEDRAMLOCK_ENABLE_Pos) /*!< Bit mask of ENABLE field.      */
  #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                                */
  #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                                */
  #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Disabled (0x0UL) /*!< Lock disabled.                                                  */
  #define CRACEN_PROTECTEDRAMLOCK_ENABLE_Enabled (0x1UL) /*!< Lock enabled.                                                    */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                        CRACENCORE                                        ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ============================================= Struct CRACENCORE_CRYPTMSTRDMA ============================================== */
/**
  * @brief CRYPTMSTRDMA [CRACENCORE_CRYPTMSTRDMA] (unspecified)
  */
typedef struct {
  __IOM uint32_t  FETCHADDRLSB;                      /*!< (@ 0x00000000) Fetch Address Least Significant Word                  */
  __IOM uint32_t  FETCHADDRMSB;                      /*!< (@ 0x00000004) Fetch Address Most Significant Word                   */
  __IOM uint32_t  FETCHLEN;                          /*!< (@ 0x00000008) Fetch DMA Length (only used in direct mode)           */
  __IOM uint32_t  FETCHTAG;                          /*!< (@ 0x0000000C) Fetch User Tag (only used in direct mode)             */
  __IOM uint32_t  PUSHADDRLSB;                       /*!< (@ 0x00000010) Push Address Least Significant Word                   */
  __IOM uint32_t  PUSHADDRMSB;                       /*!< (@ 0x00000014) Push Address Most Significant Word                    */
  __IOM uint32_t  PUSHLEN;                           /*!< (@ 0x00000018) Push Length (only used in direct mode)                */
  __IOM uint32_t  INTEN;                             /*!< (@ 0x0000001C) Interrupt Enable mask                                 */
  __IOM uint32_t  INTENSET;                          /*!< (@ 0x00000020) Interrupt Set                                         */
  __IOM uint32_t  INTENCLR;                          /*!< (@ 0x00000024) Interrupt Clear                                       */
  __IOM uint32_t  INTSTATRAW;                        /*!< (@ 0x00000028) Interrupt Status Raw                                  */
  __IOM uint32_t  INTSTAT;                           /*!< (@ 0x0000002C) Interrupt Status                                      */
  __IOM uint32_t  INTSTATCLR;                        /*!< (@ 0x00000030) Interrupt Status Clear                                */
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000034) Cryptomaster configuration                            */
  __IOM uint32_t  START;                             /*!< (@ 0x00000038) Start                                                 */
  __IOM uint32_t  STATUS;                            /*!< (@ 0x0000003C) Status                                                */
} NRF_CRACENCORE_CRYPTMSTRDMA_Type;                  /*!< Size = 64 (0x040)                                                    */

/* CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB: Fetch Address Least Significant Word */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_ResetValue (0x00000000UL) /*!< Reset value of FETCHADDRLSB register.            */

/* FETCHADDRLSB @Bits 0..31 : Address */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_FETCHADDRLSB_Pos (0UL) /*!< Position of FETCHADDRLSB field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_FETCHADDRLSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHADDRLSB_FETCHADDRLSB_Pos)
                                                                            /*!< Bit mask of FETCHADDRLSB field.*/


/* CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB: Fetch Address Most Significant Word */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_ResetValue (0x00000000UL) /*!< Reset value of FETCHADDRMSB register.            */

/* FETCHADDRMSB @Bits 0..31 : (unspecified) */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_FETCHADDRMSB_Pos (0UL) /*!< Position of FETCHADDRMSB field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_FETCHADDRMSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHADDRMSB_FETCHADDRMSB_Pos)
                                                                            /*!< Bit mask of FETCHADDRMSB field.*/


/* CRACENCORE_CRYPTMSTRDMA_FETCHLEN: Fetch DMA Length (only used in direct mode) */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_ResetValue (0x00000000UL) /*!< Reset value of FETCHLEN register.                    */

/* FETCHLEN @Bits 0..27 : Length of data block */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHLEN_Pos (0UL) /*!< Position of FETCHLEN field.                                 */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHLEN_Msk (0xFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHLEN_Pos) /*!< Bit
                                                                            mask of FETCHLEN field.*/

/* FETCHCSTADDR @Bit 28 : Constant address */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHCSTADDR_Pos (28UL) /*!< Position of FETCHCSTADDR field.                        */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHCSTADDR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHCSTADDR_Pos) /*!<
                                                                            Bit mask of FETCHCSTADDR field.*/

/* FETCHREALIGN @Bit 29 : Realign length */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHREALIGN_Pos (29UL) /*!< Position of FETCHREALIGN field.                        */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHREALIGN_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_FETCHLEN_FETCHREALIGN_Pos) /*!<
                                                                            Bit mask of FETCHREALIGN field.*/


/* CRACENCORE_CRYPTMSTRDMA_FETCHTAG: Fetch User Tag (only used in direct mode) */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHTAG_ResetValue (0x00000000UL) /*!< Reset value of FETCHTAG register.                    */

/* FETCHTAG @Bits 0..31 : User tag */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHTAG_FETCHTAG_Pos (0UL) /*!< Position of FETCHTAG field.                                 */
  #define CRACENCORE_CRYPTMSTRDMA_FETCHTAG_FETCHTAG_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_FETCHTAG_FETCHTAG_Pos) /*!< Bit
                                                                            mask of FETCHTAG field.*/


/* CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB: Push Address Least Significant Word */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_ResetValue (0x00000000UL) /*!< Reset value of PUSHADDRLSB register.              */

/* PUSHADDRLSB @Bits 0..31 : Address */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_PUSHADDRLSB_Pos (0UL) /*!< Position of PUSHADDRLSB field.                        */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_PUSHADDRLSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_PUSHADDRLSB_PUSHADDRLSB_Pos)
                                                                            /*!< Bit mask of PUSHADDRLSB field.*/


/* CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB: Push Address Most Significant Word */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_ResetValue (0x00000000UL) /*!< Reset value of PUSHADDRMSB register.              */

/* PUSHADDRMSB @Bits 0..31 : (unspecified) */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_PUSHADDRMSB_Pos (0UL) /*!< Position of PUSHADDRMSB field.                        */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_PUSHADDRMSB_Msk (0xFFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_PUSHADDRMSB_PUSHADDRMSB_Pos)
                                                                            /*!< Bit mask of PUSHADDRMSB field.*/


/* CRACENCORE_CRYPTMSTRDMA_PUSHLEN: Push Length (only used in direct mode) */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_ResetValue (0x00000000UL) /*!< Reset value of PUSHLEN register.                      */

/* PUSHLEN @Bits 0..27 : Length of data block */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHLEN_Pos (0UL) /*!< Position of PUSHLEN field.                                    */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHLEN_Msk (0xFFFFFFFUL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHLEN_Pos) /*!< Bit mask
                                                                            of PUSHLEN field.*/

/* PUSHCSTADDR @Bit 28 : Constant address */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHCSTADDR_Pos (28UL) /*!< Position of PUSHCSTADDR field.                           */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHCSTADDR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHCSTADDR_Pos) /*!< Bit
                                                                            mask of PUSHCSTADDR field.*/

/* PUSHREALIGN @Bit 29 : Realign length */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHREALIGN_Pos (29UL) /*!< Position of PUSHREALIGN field.                           */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHREALIGN_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHREALIGN_Pos) /*!< Bit
                                                                            mask of PUSHREALIGN field.*/

/* PUSHDISCARD @Bit 30 : Discard data */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHDISCARD_Pos (30UL) /*!< Position of PUSHDISCARD field.                           */
  #define CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHDISCARD_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_PUSHLEN_PUSHDISCARD_Pos) /*!< Bit
                                                                            mask of PUSHDISCARD field.*/


/* CRACENCORE_CRYPTMSTRDMA_INTEN: Interrupt Enable mask */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register.                          */

/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field.                      */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERBLOCKEND_Pos) /*!<
                                                                            Bit mask of FETCHERBLOCKEND field.*/

/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field.                        */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERSTOPPED_Pos) /*!< Bit
                                                                            mask of FETCHERSTOPPED field.*/

/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field.                            */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_FETCHERERROR_Pos) /*!< Bit mask
                                                                            of FETCHERERROR field.*/

/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field.                        */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERBLOCKEND_Pos) /*!< Bit
                                                                            mask of PUSHERBLOCKEND field.*/

/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field.                          */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERSTOPPED_Pos) /*!< Bit
                                                                            mask of PUSHERSTOPPED field.*/

/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field.                              */
  #define CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTEN_PUSHERERROR_Pos) /*!< Bit mask
                                                                            of PUSHERERROR field.*/


/* CRACENCORE_CRYPTMSTRDMA_INTENSET: Interrupt Set */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register.                    */

/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field.                   */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of FETCHERBLOCKEND field.*/

/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERSTOPPED_Pos)
                                                                            /*!< Bit mask of FETCHERSTOPPED field.*/

/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field.                         */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_FETCHERERROR_Pos) /*!<
                                                                            Bit mask of FETCHERERROR field.*/

/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of PUSHERBLOCKEND field.*/

/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field.                       */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERSTOPPED_Pos) /*!<
                                                                            Bit mask of PUSHERSTOPPED field.*/

/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field.                           */
  #define CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENSET_PUSHERERROR_Pos) /*!< Bit
                                                                            mask of PUSHERERROR field.*/


/* CRACENCORE_CRYPTMSTRDMA_INTENCLR: Interrupt Clear */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register.                    */

/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field.                   */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of FETCHERBLOCKEND field.*/

/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERSTOPPED_Pos)
                                                                            /*!< Bit mask of FETCHERSTOPPED field.*/

/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field.                         */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_FETCHERERROR_Pos) /*!<
                                                                            Bit mask of FETCHERERROR field.*/

/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of PUSHERBLOCKEND field.*/

/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field.                       */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERSTOPPED_Pos) /*!<
                                                                            Bit mask of PUSHERSTOPPED field.*/

/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field.                           */
  #define CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTENCLR_PUSHERERROR_Pos) /*!< Bit
                                                                            mask of PUSHERERROR field.*/


/* CRACENCORE_CRYPTMSTRDMA_INTSTATRAW: Interrupt Status Raw */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_ResetValue (0x00000000UL) /*!< Reset value of INTSTATRAW register.                */

/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field.                 */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of FETCHERBLOCKEND field.*/

/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field.                   */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERSTOPPED_Pos)
                                                                            /*!< Bit mask of FETCHERSTOPPED field.*/

/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field.                       */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_FETCHERERROR_Pos)
                                                                            /*!< Bit mask of FETCHERERROR field.*/

/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field.                   */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of PUSHERBLOCKEND field.*/

/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERSTOPPED_Pos)
                                                                            /*!< Bit mask of PUSHERSTOPPED field.*/

/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field.                         */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATRAW_PUSHERERROR_Pos) /*!<
                                                                            Bit mask of PUSHERERROR field.*/


/* CRACENCORE_CRYPTMSTRDMA_INTSTAT: Interrupt Status */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_ResetValue (0x00000000UL) /*!< Reset value of INTSTAT register.                      */

/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field.                    */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of FETCHERBLOCKEND field.*/

/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field.                      */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERSTOPPED_Pos) /*!<
                                                                            Bit mask of FETCHERSTOPPED field.*/

/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field.                          */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_FETCHERERROR_Pos) /*!< Bit
                                                                            mask of FETCHERERROR field.*/

/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field.                      */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERBLOCKEND_Pos) /*!<
                                                                            Bit mask of PUSHERBLOCKEND field.*/

/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field.                        */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERSTOPPED_Pos) /*!<
                                                                            Bit mask of PUSHERSTOPPED field.*/

/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field.                            */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTAT_PUSHERERROR_Pos) /*!< Bit
                                                                            mask of PUSHERERROR field.*/


/* CRACENCORE_CRYPTMSTRDMA_INTSTATCLR: Interrupt Status Clear */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_ResetValue (0x00000000UL) /*!< Reset value of INTSTATCLR register.                */

/* FETCHERBLOCKEND @Bit 0 : Fetcher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERBLOCKEND_Pos (0UL) /*!< Position of FETCHERBLOCKEND field.                 */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of FETCHERBLOCKEND field.*/

/* FETCHERSTOPPED @Bit 1 : Fetcher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERSTOPPED_Pos (1UL) /*!< Position of FETCHERSTOPPED field.                   */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERSTOPPED_Pos)
                                                                            /*!< Bit mask of FETCHERSTOPPED field.*/

/* FETCHERERROR @Bit 2 : Bus error during fetcher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERERROR_Pos (2UL) /*!< Position of FETCHERERROR field.                       */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_FETCHERERROR_Pos)
                                                                            /*!< Bit mask of FETCHERERROR field.*/

/* PUSHERBLOCKEND @Bit 3 : Pusher DMA reached the end of a block (if enabled in the descriptor; scatter-gather only) */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERBLOCKEND_Pos (3UL) /*!< Position of PUSHERBLOCKEND field.                   */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERBLOCKEND_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERBLOCKEND_Pos)
                                                                            /*!< Bit mask of PUSHERBLOCKEND field.*/

/* PUSHERSTOPPED @Bit 4 : Pusher DMA reached the end of a block with Stop=1, or end of direct transfer */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERSTOPPED_Pos (4UL) /*!< Position of PUSHERSTOPPED field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERSTOPPED_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERSTOPPED_Pos)
                                                                            /*!< Bit mask of PUSHERSTOPPED field.*/

/* PUSHERERROR @Bit 5 : Bus error during pusher DMA access */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERERROR_Pos (5UL) /*!< Position of PUSHERERROR field.                         */
  #define CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERERROR_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_INTSTATCLR_PUSHERERROR_Pos) /*!<
                                                                            Bit mask of PUSHERERROR field.*/


/* CRACENCORE_CRYPTMSTRDMA_CONFIG: Cryptomaster configuration */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                        */

/* FETCHCTRLINDIRECT @Bit 0 : Fetcher scatter/gather. */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Pos (0UL) /*!< Position of FETCHCTRLINDIRECT field.                 */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Pos)
                                                                            /*!< Bit mask of FETCHCTRLINDIRECT field.*/

/* PUSHCTRLINDIRECT @Bit 1 : Pusher scatter/gather. */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Pos (1UL) /*!< Position of PUSHCTRLINDIRECT field.                   */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Pos)
                                                                            /*!< Bit mask of PUSHCTRLINDIRECT field.*/

/* FETCHSTOP @Bit 2 : Stop fetcher. */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHSTOP_Pos (2UL) /*!< Position of FETCHSTOP field.                                 */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHSTOP_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHSTOP_Pos) /*!< Bit mask of
                                                                            FETCHSTOP field.*/

/* PUSHSTOP @Bit 3 : Stop pusher DMA. */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHSTOP_Pos (3UL) /*!< Position of PUSHSTOP field.                                   */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHSTOP_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHSTOP_Pos) /*!< Bit mask of
                                                                            PUSHSTOP field.*/

/* SOFTRST @Bit 4 : Soft reset the cryptomaster. */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Pos (4UL) /*!< Position of SOFTRST field.                                     */
  #define CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Pos) /*!< Bit mask of
                                                                            SOFTRST field.*/


/* CRACENCORE_CRYPTMSTRDMA_START: Start */
  #define CRACENCORE_CRYPTMSTRDMA_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                          */

/* STARTFETCH @Bit 0 : Writing a '1' starts the fetcher DMA. Writing a '0' has no effect. */
  #define CRACENCORE_CRYPTMSTRDMA_START_STARTFETCH_Pos (0UL) /*!< Position of STARTFETCH field.                                */
  #define CRACENCORE_CRYPTMSTRDMA_START_STARTFETCH_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_START_STARTFETCH_Pos) /*!< Bit mask of
                                                                            STARTFETCH field.*/

/* STARTPUSH @Bit 1 : Writing a '1' starts the pusher DMA. Writing a '0' has no effect. */
  #define CRACENCORE_CRYPTMSTRDMA_START_STARTPUSH_Pos (1UL) /*!< Position of STARTPUSH field.                                  */
  #define CRACENCORE_CRYPTMSTRDMA_START_STARTPUSH_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_START_STARTPUSH_Pos) /*!< Bit mask of
                                                                            STARTPUSH field.*/


/* CRACENCORE_CRYPTMSTRDMA_STATUS: Status */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                        */

/* FETCHBUSY @Bit 0 : This bit is high as long as the fetcher DMA is busy. */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHBUSY_Pos (0UL) /*!< Position of FETCHBUSY field.                                 */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHBUSY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHBUSY_Pos) /*!< Bit mask of
                                                                            FETCHBUSY field.*/

/* PUSHBUSY @Bit 1 : This bit is high as long as the pusher DMA is busy. */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHBUSY_Pos (1UL) /*!< Position of PUSHBUSY field.                                   */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHBUSY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHBUSY_Pos) /*!< Bit mask of
                                                                            PUSHBUSY field.*/

/* FETCHNOTEMPTY @Bit 4 : Not empty flag for fetcher DMA input FIFO */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHNOTEMPTY_Pos (4UL) /*!< Position of FETCHNOTEMPTY field.                         */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHNOTEMPTY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHNOTEMPTY_Pos) /*!< Bit
                                                                            mask of FETCHNOTEMPTY field.*/

/* PUSHWAITINGFIFO @Bit 5 : Pusher DMA Waiting FIFO. This bit is high when the pusher is waiting for more data in output FIFO. */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHWAITINGFIFO_Pos (5UL) /*!< Position of PUSHWAITINGFIFO field.                     */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHWAITINGFIFO_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHWAITINGFIFO_Pos) /*!<
                                                                            Bit mask of PUSHWAITINGFIFO field.*/

/* SOFTRSTBUSY @Bit 6 : This bit is high when the soft reset is on going */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_SOFTRSTBUSY_Pos (6UL) /*!< Position of SOFTRSTBUSY field.                             */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_SOFTRSTBUSY_Msk (0x1UL << CRACENCORE_CRYPTMSTRDMA_STATUS_SOFTRSTBUSY_Pos) /*!< Bit mask
                                                                            of SOFTRSTBUSY field.*/

/* PUSHNBDATA @Bits 16..31 : Amount of data in the pusher DMA output FIFO */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHNBDATA_Pos (16UL) /*!< Position of PUSHNBDATA field.                              */
  #define CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHNBDATA_Msk (0xFFFFUL << CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHNBDATA_Pos) /*!< Bit
                                                                            mask of PUSHNBDATA field.*/



/* ============================================== Struct CRACENCORE_CRYPTMSTRHW ============================================== */
/**
  * @brief CRYPTMSTRHW [CRACENCORE_CRYPTMSTRHW] (unspecified)
  */
typedef struct {
  __IOM uint32_t  INCLIPSHWCFG;                      /*!< (@ 0x00000000) Incuded IPs Hardware configuration                    */
  __IOM uint32_t  BA411EAESHWCFG1;                   /*!< (@ 0x00000004) Generic g_AesModesPoss value.                         */
  __IOM uint32_t  BA411EAESHWCFG2;                   /*!< (@ 0x00000008) Generic g_CtrSize value.                              */
  __IOM uint32_t  BA413HASHHWCFG;                    /*!< (@ 0x0000000C) Generic g_Hash value                                  */
  __IOM uint32_t  BA418SHA3HWCFG;                    /*!< (@ 0x00000010) Generic g_Sha3CtxtEn value.                           */
  __IOM uint32_t  BA419SM4HWCFG;                     /*!< (@ 0x00000014) Generic g_SM4ModesPoss value.                         */
  __IOM uint32_t  BA424ARIAHWCFG;                    /*!< (@ 0x00000018) Generic g_aria_modePoss value.                        */
} NRF_CRACENCORE_CRYPTMSTRHW_Type;                   /*!< Size = 28 (0x01C)                                                    */

/* CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG: Incuded IPs Hardware configuration */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_ResetValue (0x00000771UL) /*!< Reset value of INCLIPSHWCFG register.             */

/* BA411AESINCLUDED @Bit 0 : Generic g_IncludeAES value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA411AESINCLUDED_Pos (0UL) /*!< Position of BA411AESINCLUDED field.              */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA411AESINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA411AESINCLUDED_Pos)
                                                                            /*!< Bit mask of BA411AESINCLUDED field.*/

/* BA415HPAESGCMINCLUDED @Bit 1 : Generic g_IncludeAESGCM value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA415HPAESGCMINCLUDED_Pos (1UL) /*!< Position of BA415HPAESGCMINCLUDED field.    */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA415HPAESGCMINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA415HPAESGCMINCLUDED_Pos)
                                                                            /*!< Bit mask of BA415HPAESGCMINCLUDED field.*/

/* BA416HPAESXTSINCLUDED @Bit 2 : Generic g_IncludeAESXTS value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA416HPAESXTSINCLUDED_Pos (2UL) /*!< Position of BA416HPAESXTSINCLUDED field.    */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA416HPAESXTSINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA416HPAESXTSINCLUDED_Pos)
                                                                            /*!< Bit mask of BA416HPAESXTSINCLUDED field.*/

/* BA412DESINCLUDED @Bit 3 : Generic g_IncludeDES value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA412DESINCLUDED_Pos (3UL) /*!< Position of BA412DESINCLUDED field.              */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA412DESINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA412DESINCLUDED_Pos)
                                                                            /*!< Bit mask of BA412DESINCLUDED field.*/

/* BA413HASHINCLUDED @Bit 4 : Generic g_IncludeHASH value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA413HASHINCLUDED_Pos (4UL) /*!< Position of BA413HASHINCLUDED field.            */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA413HASHINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA413HASHINCLUDED_Pos)
                                                                            /*!< Bit mask of BA413HASHINCLUDED field.*/

/* BA417CHACHAPOLYINCLUDED @Bit 5 : Generic g_IncludeChachaPoly value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA417CHACHAPOLYINCLUDED_Pos (5UL) /*!< Position of BA417CHACHAPOLYINCLUDED field.*/
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA417CHACHAPOLYINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA417CHACHAPOLYINCLUDED_Pos)
                                                                            /*!< Bit mask of BA417CHACHAPOLYINCLUDED field.*/

/* BA418SHA3INCLUDED @Bit 6 : Generic g_IncludeSHA3 value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA418SHA3INCLUDED_Pos (6UL) /*!< Position of BA418SHA3INCLUDED field.            */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA418SHA3INCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA418SHA3INCLUDED_Pos)
                                                                            /*!< Bit mask of BA418SHA3INCLUDED field.*/

/* BA421ZUCINCLUDED @Bit 7 : Generic g_IncludeZUC value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA421ZUCINCLUDED_Pos (7UL) /*!< Position of BA421ZUCINCLUDED field.              */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA421ZUCINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA421ZUCINCLUDED_Pos)
                                                                            /*!< Bit mask of BA421ZUCINCLUDED field.*/

/* BA419SM4INCLUDED @Bit 8 : Generic g_IncludeSM4 value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA419SM4INCLUDED_Pos (8UL) /*!< Position of BA419SM4INCLUDED field.              */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA419SM4INCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA419SM4INCLUDED_Pos)
                                                                            /*!< Bit mask of BA419SM4INCLUDED field.*/

/* BA414EPPKEINCLUDED @Bit 9 : Generic g_IncludePKE value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA414EPPKEINCLUDED_Pos (9UL) /*!< Position of BA414EPPKEINCLUDED field.          */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA414EPPKEINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA414EPPKEINCLUDED_Pos)
                                                                            /*!< Bit mask of BA414EPPKEINCLUDED field.*/

/* BA431NDRNGINCLUDED @Bit 10 : Generic g_IncludeNDRNG value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA431NDRNGINCLUDED_Pos (10UL) /*!< Position of BA431NDRNGINCLUDED field.         */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA431NDRNGINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA431NDRNGINCLUDED_Pos)
                                                                            /*!< Bit mask of BA431NDRNGINCLUDED field.*/

/* BA420HPCHACHAPOLYINCLUDED @Bit 11 : Generic g_IncludeHPChachaPoly value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA420HPCHACHAPOLYINCLUDED_Pos (11UL) /*!< Position of BA420HPCHACHAPOLYINCLUDED
                                                                            field.*/
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA420HPCHACHAPOLYINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA420HPCHACHAPOLYINCLUDED_Pos)
                                                                            /*!< Bit mask of BA420HPCHACHAPOLYINCLUDED field.*/

/* BA423SNOW3GINCLUDED @Bit 12 : Generic g_IncludeSnow3G value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA423SNOW3GINCLUDED_Pos (12UL) /*!< Position of BA423SNOW3GINCLUDED field.       */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA423SNOW3GINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA423SNOW3GINCLUDED_Pos)
                                                                            /*!< Bit mask of BA423SNOW3GINCLUDED field.*/

/* BA422KASUMIINCLUDED @Bit 13 : Generic g_IncludeKasumi value. */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422KASUMIINCLUDED_Pos (13UL) /*!< Position of BA422KASUMIINCLUDED field.       */
  #define CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422KASUMIINCLUDED_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_INCLIPSHWCFG_BA422KASUMIINCLUDED_Pos)
                                                                            /*!< Bit mask of BA422KASUMIINCLUDED field.*/


/* CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1: Generic g_AesModesPoss value. */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_ResetValue (0x070301FFUL) /*!< Reset value of BA411EAESHWCFG1 register.       */

/* BA411EAESHWCFGMODE @Bits 0..8 : Generic g_AesModesPoss value. */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMODE_Pos (0UL) /*!< Position of BA411EAESHWCFGMODE field.       */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMODE_Msk (0x1FFUL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMODE_Pos)
                                                                            /*!< Bit mask of BA411EAESHWCFGMODE field.*/

/* BA411EAESHWCFGCS @Bit 16 : Generic g_CS value. */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGCS_Pos (16UL) /*!< Position of BA411EAESHWCFGCS field.          */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGCS_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGCS_Pos)
                                                                            /*!< Bit mask of BA411EAESHWCFGCS field.*/

/* BA411EAESHWCFGMASKING @Bit 17 : Generic g_UseMasking value. */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMASKING_Pos (17UL) /*!< Position of BA411EAESHWCFGMASKING field.*/
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMASKING_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGMASKING_Pos)
                                                                            /*!< Bit mask of BA411EAESHWCFGMASKING field.*/

/* BA411EAESHWCFGKEYSIZE @Bits 24..26 : Generic g_Keysize value. */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGKEYSIZE_Pos (24UL) /*!< Position of BA411EAESHWCFGKEYSIZE field.*/
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGKEYSIZE_Msk (0x7UL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG1_BA411EAESHWCFGKEYSIZE_Pos)
                                                                            /*!< Bit mask of BA411EAESHWCFGKEYSIZE field.*/


/* CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2: Generic g_CtrSize value. */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_ResetValue (0x00000080UL) /*!< Reset value of BA411EAESHWCFG2 register.       */

/* BA411EAESHWCFG2 @Bits 0..15 : Generic g_CtrSize value. */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_BA411EAESHWCFG2_Pos (0UL) /*!< Position of BA411EAESHWCFG2 field.             */
  #define CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_BA411EAESHWCFG2_Msk (0xFFFFUL << CRACENCORE_CRYPTMSTRHW_BA411EAESHWCFG2_BA411EAESHWCFG2_Pos)
                                                                            /*!< Bit mask of BA411EAESHWCFG2 field.*/


/* CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG: Generic g_Hash value */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_ResetValue (0x0003003FUL) /*!< Reset value of BA413HASHHWCFG register.         */

/* BA413HASHHWCFGMASK @Bits 0..6 : Generic g_HashMaskFunc value. */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGMASK_Pos (0UL) /*!< Position of BA413HASHHWCFGMASK field.        */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGMASK_Msk (0x7FUL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGMASK_Pos)
                                                                            /*!< Bit mask of BA413HASHHWCFGMASK field.*/

/* BA413HASHHWCFGPADDING @Bit 16 : Generic g_HashPadding value. */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGPADDING_Pos (16UL) /*!< Position of BA413HASHHWCFGPADDING field. */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGPADDING_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGPADDING_Pos)
                                                                            /*!< Bit mask of BA413HASHHWCFGPADDING field.*/

/* BA413HASHHWCFGHMAC @Bit 17 : Generic g_HMAC_enabled value. */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGHMAC_Pos (17UL) /*!< Position of BA413HASHHWCFGHMAC field.       */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGHMAC_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGHMAC_Pos)
                                                                            /*!< Bit mask of BA413HASHHWCFGHMAC field.*/

/* BA413HASHHWCFGVERIFYDIGEST @Bit 18 : Generic g_HashVerifyDigest value. */
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGVERIFYDIGEST_Pos (18UL) /*!< Position of
                                                                            BA413HASHHWCFGVERIFYDIGEST field.*/
  #define CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGVERIFYDIGEST_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA413HASHHWCFG_BA413HASHHWCFGVERIFYDIGEST_Pos)
                                                                            /*!< Bit mask of BA413HASHHWCFGVERIFYDIGEST field.*/


/* CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG: Generic g_Sha3CtxtEn value. */
  #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_ResetValue (0x00000001UL) /*!< Reset value of BA418SHA3HWCFG register.         */

/* BA418SHA3HWCFG @Bit 0 : Generic g_Sha3CtxtEn value. */
  #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_BA418SHA3HWCFG_Pos (0UL) /*!< Position of BA418SHA3HWCFG field.                */
  #define CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_BA418SHA3HWCFG_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA418SHA3HWCFG_BA418SHA3HWCFG_Pos)
                                                                            /*!< Bit mask of BA418SHA3HWCFG field.*/


/* CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG: Generic g_SM4ModesPoss value. */
  #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_ResetValue (0x000201FFUL) /*!< Reset value of BA419SM4HWCFG register.           */

/* BA419SM4HWCFG @Bits 0..9 : Generic g_SM4ModesPoss value. */
  #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_BA419SM4HWCFG_Pos (0UL) /*!< Position of BA419SM4HWCFG field.                   */
  #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_BA419SM4HWCFG_Msk (0x3FFUL << CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_BA419SM4HWCFG_Pos)
                                                                            /*!< Bit mask of BA419SM4HWCFG field.*/

/* USEMASKING @Bit 17 : Generic g_sm4UseMasking value. */
  #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_USEMASKING_Pos (17UL) /*!< Position of USEMASKING field.                        */
  #define CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_USEMASKING_Msk (0x1UL << CRACENCORE_CRYPTMSTRHW_BA419SM4HWCFG_USEMASKING_Pos)
                                                                            /*!< Bit mask of USEMASKING field.*/


/* CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG: Generic g_aria_modePoss value. */
  #define CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_ResetValue (0x0000017FUL) /*!< Reset value of BA424ARIAHWCFG register.         */

/* BA424ARIAHWCFG @Bits 0..8 : Generic g_aria_modePoss value. */
  #define CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_BA424ARIAHWCFG_Pos (0UL) /*!< Position of BA424ARIAHWCFG field.                */
  #define CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_BA424ARIAHWCFG_Msk (0x1FFUL << CRACENCORE_CRYPTMSTRHW_BA424ARIAHWCFG_BA424ARIAHWCFG_Pos)
                                                                            /*!< Bit mask of BA424ARIAHWCFG field.*/



/* ============================================== Struct CRACENCORE_RNGCONTROL =============================================== */
/**
  * @brief RNGCONTROL [CRACENCORE_RNGCONTROL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CONTROL;                           /*!< (@ 0x00000000) Control register                                      */
  __IOM uint32_t  FIFOLEVEL;                         /*!< (@ 0x00000004) FIFO level register.                                  */
  __IOM uint32_t  FIFOTHRESHOLD;                     /*!< (@ 0x00000008) FIFO threshold register.                              */
  __IOM uint32_t  FIFODEPTH;                         /*!< (@ 0x0000000C) FIFO depth register.                                  */
  __IOM uint32_t  KEY[4];                            /*!< (@ 0x00000010) Key register.                                         */
  __IOM uint32_t  TESTDATA;                          /*!< (@ 0x00000020) Test data register.                                   */
  __IOM uint32_t  REPEATTHRESHOLD;                   /*!< (@ 0x00000024) Repetition Test Count Cut-Off value.                  */
  __IOM uint32_t  PROPTHRESHOLD;                     /*!< (@ 0x00000028) Adaptive Proportion Test (1024-sample window) Cut-Off
                                                                         value.*/
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000030) Status register.                                      */
  __IOM uint32_t  INITWAITVAL;                       /*!< (@ 0x00000034) Initial wait counter value.                           */
  __IOM uint32_t  DISABLEOSC[2];                     /*!< (@ 0x00000038) Disable oscillator rings #n*32 to #((n+1)*32)-1.      */
  __IOM uint32_t  SWOFFTMRVAL;                       /*!< (@ 0x00000040) Switch off timer value.                               */
  __IOM uint32_t  CLKDIV;                            /*!< (@ 0x00000044) Sample clock divider.                                 */
  __IOM uint32_t  AIS31CONF0;                        /*!< (@ 0x00000048) AIS31 configuration register 0.                       */
  __IOM uint32_t  AIS31CONF1;                        /*!< (@ 0x0000004C) AIS31 configuration register 1.                       */
  __IOM uint32_t  AIS31CONF2;                        /*!< (@ 0x00000050) AIS31 configuration register 2.                       */
  __IOM uint32_t  AIS31STATUS;                       /*!< (@ 0x00000054) AIS31 status register.                                */
  __IOM uint32_t  HWCONFIG;                          /*!< (@ 0x00000058) Hardware configuration register.                      */
  __IM  uint32_t  RESERVED1[9];
  __IM  uint32_t  FIFO[16];                          /*!< (@ 0x00000080) FIFO data                                             */
} NRF_CRACENCORE_RNGCONTROL_Type;                    /*!< Size = 192 (0x0C0)                                                   */

/* CRACENCORE_RNGCONTROL_CONTROL: Control register */
  #define CRACENCORE_RNGCONTROL_CONTROL_ResetValue (0x00040000UL) /*!< Reset value of CONTROL register.                        */

/* ENABLE @Bit 0 : Enable the NDRNG. */
  #define CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                        */
  #define CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_ENABLE_Pos) /*!< Bit mask of ENABLE
                                                                            field.*/

/* LFSREN @Bit 1 : Select between the NDRNG with asynchronous free running oscillators (when 0) and the Pseudo-Random generator
                   with synchronous oscillators for simulation purpose (when 1). */

  #define CRACENCORE_RNGCONTROL_CONTROL_LFSREN_Pos (1UL) /*!< Position of LFSREN field.                                        */
  #define CRACENCORE_RNGCONTROL_CONTROL_LFSREN_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_LFSREN_Pos) /*!< Bit mask of LFSREN
                                                                            field.*/

/* TESTEN @Bit 2 : Select input for conditioning function and continuous tests: */
  #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Pos (2UL) /*!< Position of TESTEN field.                                        */
  #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Pos) /*!< Bit mask of TESTEN
                                                                            field.*/
  #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Min (0x0UL) /*!< Min enumerator value of TESTEN field.                          */
  #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_Max (0x1UL) /*!< Max enumerator value of TESTEN field.                          */
  #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_NORMAL (0x0UL) /*!< Noise source (normal mode).                                 */
  #define CRACENCORE_RNGCONTROL_CONTROL_TESTEN_TEST (0x1UL) /*!< Test data register (test mode).                               */

/* CONDBYPASS @Bit 3 : Conditioning function bypass. */
  #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Pos (3UL) /*!< Position of CONDBYPASS field.                                */
  #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Pos) /*!< Bit mask of
                                                                            CONDBYPASS field.*/
  #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Min (0x0UL) /*!< Min enumerator value of CONDBYPASS field.                  */
  #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_Max (0x1UL) /*!< Max enumerator value of CONDBYPASS field.                  */
  #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_NORMAL (0x0UL) /*!< the conditioning function is used (normal mode).        */
  #define CRACENCORE_RNGCONTROL_CONTROL_CONDBYPASS_BYPASS (0x1UL) /*!< the conditioning function is bypassed (to observe entropy
                                                                       source directly).*/

/* INTENREP @Bit 4 : Interrupt enable for Repetition Count Test failure. */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENREP_Pos (4UL) /*!< Position of INTENREP field.                                    */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENREP_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_INTENREP_Pos) /*!< Bit mask of
                                                                            INTENREP field.*/

/* INTENPROP @Bit 5 : Interrupt enable for Adaptive Proportion Test failure (1024-sample window). */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENPROP_Pos (5UL) /*!< Position of INTENPROP field.                                  */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENPROP_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_INTENPROP_Pos) /*!< Bit mask of
                                                                            INTENPROP field.*/

/* INTENFULL @Bit 7 : Interrupt enable for FIFO full. */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENFULL_Pos (7UL) /*!< Position of INTENFULL field.                                  */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENFULL_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_INTENFULL_Pos) /*!< Bit mask of
                                                                            INTENFULL field.*/

/* SOFTRST @Bit 8 : Software reset: */
  #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Pos (8UL) /*!< Position of SOFTRST field.                                      */
  #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Pos) /*!< Bit mask of
                                                                            SOFTRST field.*/
  #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Min (0x0UL) /*!< Min enumerator value of SOFTRST field.                        */
  #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_Max (0x1UL) /*!< Max enumerator value of SOFTRST field.                        */
  #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_NORMAL (0x0UL) /*!< Normal mode.                                               */
  #define CRACENCORE_RNGCONTROL_CONTROL_SOFTRST_CTEST (0x1UL) /*!< The continuous test, the conditioning function and the FIFO
                                                                   are reset.*/

/* INTENPRE @Bit 9 : Interrupt enable for AIS31 preliminary noise alarm. */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENPRE_Pos (9UL) /*!< Position of INTENPRE field.                                    */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENPRE_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_INTENPRE_Pos) /*!< Bit mask of
                                                                            INTENPRE field.*/

/* INTENALM @Bit 10 : Interrupt enable for AIS31 noise alarm. */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENALM_Pos (10UL) /*!< Position of INTENALM field.                                   */
  #define CRACENCORE_RNGCONTROL_CONTROL_INTENALM_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_INTENALM_Pos) /*!< Bit mask of
                                                                            INTENALM field.*/

/* FORCEACTIVEROS @Bit 11 : Force oscillators to run when FIFO is full. */
  #define CRACENCORE_RNGCONTROL_CONTROL_FORCEACTIVEROS_Pos (11UL) /*!< Position of FORCEACTIVEROS field.                       */
  #define CRACENCORE_RNGCONTROL_CONTROL_FORCEACTIVEROS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_FORCEACTIVEROS_Pos) /*!< Bit
                                                                            mask of FORCEACTIVEROS field.*/

/* HEALTHTESTBYPASS @Bit 12 : Bypass NIST tests such that the results of the start-up and online test do not affect the FSM
                              state. */

  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTBYPASS_Pos (12UL) /*!< Position of HEALTHTESTBYPASS field.                   */
  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTBYPASS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTBYPASS_Pos) /*!<
                                                                            Bit mask of HEALTHTESTBYPASS field.*/

/* AIS31BYPASS @Bit 13 : Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state.
                         */

  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31BYPASS_Pos (13UL) /*!< Position of AIS31BYPASS field.                             */
  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31BYPASS_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_AIS31BYPASS_Pos) /*!< Bit mask
                                                                            of AIS31BYPASS field.*/

/* HEALTHTESTSEL @Bit 14 : Select input to health test module: */
  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTSEL_Pos (14UL) /*!< Position of HEALTHTESTSEL field.                         */
  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTSEL_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTSEL_Pos) /*!< Bit
                                                                            mask of HEALTHTESTSEL field.*/
  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTSEL_Min (0x0UL) /*!< Min enumerator value of HEALTHTESTSEL field.            */
  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTSEL_Max (0x1UL) /*!< Max enumerator value of HEALTHTESTSEL field.            */
  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTSEL_BEFORE (0x0UL) /*!< Before conditioning.                                 */
  #define CRACENCORE_RNGCONTROL_CONTROL_HEALTHTESTSEL_AFTER (0x1UL) /*!< After conditioning.                                   */

/* AIS31TESTSEL @Bit 15 : Select input to the AIS31 test module: */
  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31TESTSEL_Pos (15UL) /*!< Position of AIS31TESTSEL field.                           */
  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31TESTSEL_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_AIS31TESTSEL_Pos) /*!< Bit mask
                                                                            of AIS31TESTSEL field.*/
  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31TESTSEL_Min (0x0UL) /*!< Min enumerator value of AIS31TESTSEL field.              */
  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31TESTSEL_Max (0x1UL) /*!< Max enumerator value of AIS31TESTSEL field.              */
  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31TESTSEL_BEFORE (0x0UL) /*!< Before conditioning.                                  */
  #define CRACENCORE_RNGCONTROL_CONTROL_AIS31TESTSEL_AFTER (0x1UL) /*!< After conditioning.                                    */

/* NB128BITBLOCKS @Bits 16..19 : Number of 128 bit blocks used in AES-CBCMAC post-processing. */
  #define CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Pos (16UL) /*!< Position of NB128BITBLOCKS field.                       */
  #define CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Msk (0xFUL << CRACENCORE_RNGCONTROL_CONTROL_NB128BITBLOCKS_Pos) /*!< Bit
                                                                            mask of NB128BITBLOCKS field.*/

/* FIFOWRITESTARTUP @Bit 20 : Enable write of the samples in the FIFO during start-up. */
  #define CRACENCORE_RNGCONTROL_CONTROL_FIFOWRITESTARTUP_Pos (20UL) /*!< Position of FIFOWRITESTARTUP field.                   */
  #define CRACENCORE_RNGCONTROL_CONTROL_FIFOWRITESTARTUP_Msk (0x1UL << CRACENCORE_RNGCONTROL_CONTROL_FIFOWRITESTARTUP_Pos) /*!<
                                                                            Bit mask of FIFOWRITESTARTUP field.*/


/* CRACENCORE_RNGCONTROL_FIFOLEVEL: FIFO level register. */
  #define CRACENCORE_RNGCONTROL_FIFOLEVEL_ResetValue (0x00000000UL) /*!< Reset value of FIFOLEVEL register.                    */

/* FIFOLEVEL @Bits 0..31 : Number of 32 bits words of random values available in the FIFO. */
  #define CRACENCORE_RNGCONTROL_FIFOLEVEL_FIFOLEVEL_Pos (0UL) /*!< Position of FIFOLEVEL field.                                */
  #define CRACENCORE_RNGCONTROL_FIFOLEVEL_FIFOLEVEL_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_FIFOLEVEL_FIFOLEVEL_Pos) /*!< Bit
                                                                            mask of FIFOLEVEL field.*/


/* CRACENCORE_RNGCONTROL_FIFOTHRESHOLD: FIFO threshold register. */
  #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_ResetValue (0x00000003UL) /*!< Reset value of FIFOTHRESHOLD register.            */

/* FIFOTHRESHOLD @Bits 0..2 : FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number of
                              128bit blocks. */

  #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Pos (0UL) /*!< Position of FIFOTHRESHOLD field.                    */
  #define CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Msk (0x7UL << CRACENCORE_RNGCONTROL_FIFOTHRESHOLD_FIFOTHRESHOLD_Pos)
                                                                            /*!< Bit mask of FIFOTHRESHOLD field.*/


/* CRACENCORE_RNGCONTROL_FIFODEPTH: FIFO depth register. */
  #define CRACENCORE_RNGCONTROL_FIFODEPTH_ResetValue (0x00000010UL) /*!< Reset value of FIFODEPTH register.                    */

/* FIFODEPTH @Bits 0..31 : Maximum number of 32 bits words that can be stored in the FIFO: 2**g_fifodepth. */
  #define CRACENCORE_RNGCONTROL_FIFODEPTH_FIFODEPTH_Pos (0UL) /*!< Position of FIFODEPTH field.                                */
  #define CRACENCORE_RNGCONTROL_FIFODEPTH_FIFODEPTH_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_FIFODEPTH_FIFODEPTH_Pos) /*!< Bit
                                                                            mask of FIFODEPTH field.*/


/* CRACENCORE_RNGCONTROL_KEY: Key register. */
  #define CRACENCORE_RNGCONTROL_KEY_MaxCount (4UL)   /*!< Max size of KEY[4] array.                                            */
  #define CRACENCORE_RNGCONTROL_KEY_MaxIndex (3UL)   /*!< Max index of KEY[4] array.                                           */
  #define CRACENCORE_RNGCONTROL_KEY_MinIndex (0UL)   /*!< Min index of KEY[4] array.                                           */
  #define CRACENCORE_RNGCONTROL_KEY_ResetValue (0x00000000UL) /*!< Reset value of KEY[4] register.                             */

/* KEY @Bits 0..31 : Key register. */
  #define CRACENCORE_RNGCONTROL_KEY_KEY_Pos (0UL)    /*!< Position of KEY field.                                               */
  #define CRACENCORE_RNGCONTROL_KEY_KEY_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_KEY_KEY_Pos) /*!< Bit mask of KEY field.    */


/* CRACENCORE_RNGCONTROL_TESTDATA: Test data register. */
  #define CRACENCORE_RNGCONTROL_TESTDATA_ResetValue (0x00000000UL) /*!< Reset value of TESTDATA register.                      */

/* TESTDATA @Bits 0..31 : Test data register. */
  #define CRACENCORE_RNGCONTROL_TESTDATA_TESTDATA_Pos (0UL) /*!< Position of TESTDATA field.                                   */
  #define CRACENCORE_RNGCONTROL_TESTDATA_TESTDATA_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_TESTDATA_TESTDATA_Pos) /*!< Bit
                                                                            mask of TESTDATA field.*/


/* CRACENCORE_RNGCONTROL_REPEATTHRESHOLD: Repetition Test Count Cut-Off value. */
  #define CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_ResetValue (0x00000029UL) /*!< Reset value of REPEATTHRESHOLD register.        */

/* REPEATTHRESHOLD @Bits 0..5 : Repetition Test Count Cut-Off value. */
  #define CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_REPEATTHRESHOLD_Pos (0UL) /*!< Position of REPEATTHRESHOLD field.              */
  #define CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_REPEATTHRESHOLD_Msk (0x3FUL << CRACENCORE_RNGCONTROL_REPEATTHRESHOLD_REPEATTHRESHOLD_Pos)
                                                                            /*!< Bit mask of REPEATTHRESHOLD field.*/


/* CRACENCORE_RNGCONTROL_PROPTHRESHOLD: Adaptive Proportion Test (1024-sample window) Cut-Off value. */
  #define CRACENCORE_RNGCONTROL_PROPTHRESHOLD_ResetValue (0x00000319UL) /*!< Reset value of PROPTHRESHOLD register.            */

/* PROPTHRESHOLD @Bits 0..9 : Adaptive Proportion Test (1024-sample window) Cut-Off value. */
  #define CRACENCORE_RNGCONTROL_PROPTHRESHOLD_PROPTHRESHOLD_Pos (0UL) /*!< Position of PROPTHRESHOLD field.                    */
  #define CRACENCORE_RNGCONTROL_PROPTHRESHOLD_PROPTHRESHOLD_Msk (0x3FFUL << CRACENCORE_RNGCONTROL_PROPTHRESHOLD_PROPTHRESHOLD_Pos)
                                                                            /*!< Bit mask of PROPTHRESHOLD field.*/


/* CRACENCORE_RNGCONTROL_STATUS: Status register. */
  #define CRACENCORE_RNGCONTROL_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                          */

/* TESTDATABUSY @Bit 0 : High when data written to TestData register is being processed. */
  #define CRACENCORE_RNGCONTROL_STATUS_TESTDATABUSY_Pos (0UL) /*!< Position of TESTDATABUSY field.                             */
  #define CRACENCORE_RNGCONTROL_STATUS_TESTDATABUSY_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_TESTDATABUSY_Pos) /*!< Bit mask
                                                                            of TESTDATABUSY field.*/

/* STATE @Bits 1..3 : State of the control FSM: */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_Pos (1UL) /*!< Position of STATE field.                                           */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_Msk (0x7UL << CRACENCORE_RNGCONTROL_STATUS_STATE_Pos) /*!< Bit mask of STATE
                                                                            field.*/
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field.                             */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_Max (0x5UL) /*!< Max enumerator value of STATE field.                             */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_RESET (0x0UL) /*!< Reset                                                          */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_STARTUP (0x1UL) /*!< Startup                                                      */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_IDLERON (0x2UL) /*!< Idle (Rings On)                                              */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_IDLEROFF (0x3UL) /*!< Idle (Rings Off)                                            */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_FILLFIFO (0x4UL) /*!< Fill FIFO                                                   */
  #define CRACENCORE_RNGCONTROL_STATUS_STATE_ERROR (0x5UL) /*!< Error                                                          */

/* REPFAIL @Bit 4 : NIST-800-90B repetition Count Test interrupt status. */
  #define CRACENCORE_RNGCONTROL_STATUS_REPFAIL_Pos (4UL) /*!< Position of REPFAIL field.                                       */
  #define CRACENCORE_RNGCONTROL_STATUS_REPFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_REPFAIL_Pos) /*!< Bit mask of REPFAIL
                                                                            field.*/

/* PROPFAIL @Bit 5 : NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status. */
  #define CRACENCORE_RNGCONTROL_STATUS_PROPFAIL_Pos (5UL) /*!< Position of PROPFAIL field.                                     */
  #define CRACENCORE_RNGCONTROL_STATUS_PROPFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_PROPFAIL_Pos) /*!< Bit mask of
                                                                            PROPFAIL field.*/

/* FULLINT @Bit 7 : FIFO full status. */
  #define CRACENCORE_RNGCONTROL_STATUS_FULLINT_Pos (7UL) /*!< Position of FULLINT field.                                       */
  #define CRACENCORE_RNGCONTROL_STATUS_FULLINT_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_FULLINT_Pos) /*!< Bit mask of FULLINT
                                                                            field.*/

/* PREINT @Bit 8 : AIS31 preliminary noise alarm interrupt status. */
  #define CRACENCORE_RNGCONTROL_STATUS_PREINT_Pos (8UL) /*!< Position of PREINT field.                                         */
  #define CRACENCORE_RNGCONTROL_STATUS_PREINT_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_PREINT_Pos) /*!< Bit mask of PREINT
                                                                            field.*/

/* ALMINT @Bit 9 : AIS31 noise alarm interrupt status. */
  #define CRACENCORE_RNGCONTROL_STATUS_ALMINT_Pos (9UL) /*!< Position of ALMINT field.                                         */
  #define CRACENCORE_RNGCONTROL_STATUS_ALMINT_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_ALMINT_Pos) /*!< Bit mask of ALMINT
                                                                            field.*/

/* STARTUPFAIL @Bit 10 : Start-up test failure. */
  #define CRACENCORE_RNGCONTROL_STATUS_STARTUPFAIL_Pos (10UL) /*!< Position of STARTUPFAIL field.                              */
  #define CRACENCORE_RNGCONTROL_STATUS_STARTUPFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_STARTUPFAIL_Pos) /*!< Bit mask of
                                                                            STARTUPFAIL field.*/

/* FIFOACCFAIL @Bit 11 : Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel =
                         0). */

  #define CRACENCORE_RNGCONTROL_STATUS_FIFOACCFAIL_Pos (11UL) /*!< Position of FIFOACCFAIL field.                              */
  #define CRACENCORE_RNGCONTROL_STATUS_FIFOACCFAIL_Msk (0x1UL << CRACENCORE_RNGCONTROL_STATUS_FIFOACCFAIL_Pos) /*!< Bit mask of
                                                                            FIFOACCFAIL field.*/


/* CRACENCORE_RNGCONTROL_INITWAITVAL: Initial wait counter value. */
  #define CRACENCORE_RNGCONTROL_INITWAITVAL_ResetValue (0x0000FFFFUL) /*!< Reset value of INITWAITVAL register.                */

/* INITWAITVAL @Bits 0..15 : Number of clock cycles to wait before sampling data from the noise source. */
  #define CRACENCORE_RNGCONTROL_INITWAITVAL_INITWAITVAL_Pos (0UL) /*!< Position of INITWAITVAL field.                          */
  #define CRACENCORE_RNGCONTROL_INITWAITVAL_INITWAITVAL_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_INITWAITVAL_INITWAITVAL_Pos) /*!<
                                                                            Bit mask of INITWAITVAL field.*/


/* CRACENCORE_RNGCONTROL_DISABLEOSC: Disable oscillator rings #n*32 to #((n+1)*32)-1. */
  #define CRACENCORE_RNGCONTROL_DISABLEOSC_MaxCount (2UL) /*!< Max size of DISABLEOSC[2] array.                                */
  #define CRACENCORE_RNGCONTROL_DISABLEOSC_MaxIndex (1UL) /*!< Max index of DISABLEOSC[2] array.                               */
  #define CRACENCORE_RNGCONTROL_DISABLEOSC_MinIndex (0UL) /*!< Min index of DISABLEOSC[2] array.                               */
  #define CRACENCORE_RNGCONTROL_DISABLEOSC_ResetValue (0x00000000UL) /*!< Reset value of DISABLEOSC[2] register.               */

/* DISABLEOSC @Bits 0..31 : Disable oscillator rings #n*32 to #((n+1)*32)-1. */
  #define CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Pos (0UL) /*!< Position of DISABLEOSC field.                             */
  #define CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_DISABLEOSC_DISABLEOSC_Pos) /*!<
                                                                            Bit mask of DISABLEOSC field.*/


/* CRACENCORE_RNGCONTROL_SWOFFTMRVAL: Switch off timer value. */
  #define CRACENCORE_RNGCONTROL_SWOFFTMRVAL_ResetValue (0x0000FFFFUL) /*!< Reset value of SWOFFTMRVAL register.                */

/* SWOFFTMRVAL @Bits 0..15 : Number of clk cycles to wait before stopping the rings after the FIFO is full. */
  #define CRACENCORE_RNGCONTROL_SWOFFTMRVAL_SWOFFTMRVAL_Pos (0UL) /*!< Position of SWOFFTMRVAL field.                          */
  #define CRACENCORE_RNGCONTROL_SWOFFTMRVAL_SWOFFTMRVAL_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_SWOFFTMRVAL_SWOFFTMRVAL_Pos) /*!<
                                                                            Bit mask of SWOFFTMRVAL field.*/


/* CRACENCORE_RNGCONTROL_CLKDIV: Sample clock divider. */
  #define CRACENCORE_RNGCONTROL_CLKDIV_ResetValue (0x00000000UL) /*!< Reset value of CLKDIV register.                          */

/* CLKDIV @Bits 0..7 : Sample clock divider. */
  #define CRACENCORE_RNGCONTROL_CLKDIV_CLKDIV_Pos (0UL) /*!< Position of CLKDIV field.                                         */
  #define CRACENCORE_RNGCONTROL_CLKDIV_CLKDIV_Msk (0xFFUL << CRACENCORE_RNGCONTROL_CLKDIV_CLKDIV_Pos) /*!< Bit mask of CLKDIV
                                                                            field.*/


/* CRACENCORE_RNGCONTROL_AIS31CONF0: AIS31 configuration register 0. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF0_ResetValue (0x43401040UL) /*!< Reset value of AIS31CONF0 register.                  */

/* STARTUPTHRESHOLD @Bits 0..14 : Start-up test threshold. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF0_STARTUPTHRESHOLD_Pos (0UL) /*!< Position of STARTUPTHRESHOLD field.                 */
  #define CRACENCORE_RNGCONTROL_AIS31CONF0_STARTUPTHRESHOLD_Msk (0x7FFFUL << CRACENCORE_RNGCONTROL_AIS31CONF0_STARTUPTHRESHOLD_Pos)
                                                                            /*!< Bit mask of STARTUPTHRESHOLD field.*/

/* ONLINETHRESHOLD @Bits 16..30 : Online threshold. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF0_ONLINETHRESHOLD_Pos (16UL) /*!< Position of ONLINETHRESHOLD field.                  */
  #define CRACENCORE_RNGCONTROL_AIS31CONF0_ONLINETHRESHOLD_Msk (0x7FFFUL << CRACENCORE_RNGCONTROL_AIS31CONF0_ONLINETHRESHOLD_Pos)
                                                                            /*!< Bit mask of ONLINETHRESHOLD field.*/


/* CRACENCORE_RNGCONTROL_AIS31CONF1: AIS31 configuration register 1. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF1_ResetValue (0x03C00680UL) /*!< Reset value of AIS31CONF1 register.                  */

/* ONLINEREPTHRESHOLD @Bits 0..14 : Online repeat threshold. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF1_ONLINEREPTHRESHOLD_Pos (0UL) /*!< Position of ONLINEREPTHRESHOLD field.             */
  #define CRACENCORE_RNGCONTROL_AIS31CONF1_ONLINEREPTHRESHOLD_Msk (0x7FFFUL << CRACENCORE_RNGCONTROL_AIS31CONF1_ONLINEREPTHRESHOLD_Pos)
                                                                            /*!< Bit mask of ONLINEREPTHRESHOLD field.*/

/* HEXPECTEDVALUE @Bits 16..30 : Expected history value. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF1_HEXPECTEDVALUE_Pos (16UL) /*!< Position of HEXPECTEDVALUE field.                    */
  #define CRACENCORE_RNGCONTROL_AIS31CONF1_HEXPECTEDVALUE_Msk (0x7FFFUL << CRACENCORE_RNGCONTROL_AIS31CONF1_HEXPECTEDVALUE_Pos)
                                                                            /*!< Bit mask of HEXPECTEDVALUE field.*/


/* CRACENCORE_RNGCONTROL_AIS31CONF2: AIS31 configuration register 2. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF2_ResetValue (0x04400340UL) /*!< Reset value of AIS31CONF2 register.                  */

/* HMIN @Bits 0..14 : Minimum allowed history value. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF2_HMIN_Pos (0UL) /*!< Position of HMIN field.                                         */
  #define CRACENCORE_RNGCONTROL_AIS31CONF2_HMIN_Msk (0x7FFFUL << CRACENCORE_RNGCONTROL_AIS31CONF2_HMIN_Pos) /*!< Bit mask of
                                                                            HMIN field.*/

/* HMAX @Bits 16..30 : Maximum allowed history value. */
  #define CRACENCORE_RNGCONTROL_AIS31CONF2_HMAX_Pos (16UL) /*!< Position of HMAX field.                                        */
  #define CRACENCORE_RNGCONTROL_AIS31CONF2_HMAX_Msk (0x7FFFUL << CRACENCORE_RNGCONTROL_AIS31CONF2_HMAX_Pos) /*!< Bit mask of
                                                                            HMAX field.*/


/* CRACENCORE_RNGCONTROL_AIS31STATUS: AIS31 status register. */
  #define CRACENCORE_RNGCONTROL_AIS31STATUS_ResetValue (0x00000000UL) /*!< Reset value of AIS31STATUS register.                */

/* NUMPRELIMALARMS @Bits 0..15 : Number of preliminary noise alarms since counter was last cleared. */
  #define CRACENCORE_RNGCONTROL_AIS31STATUS_NUMPRELIMALARMS_Pos (0UL) /*!< Position of NUMPRELIMALARMS field.                  */
  #define CRACENCORE_RNGCONTROL_AIS31STATUS_NUMPRELIMALARMS_Msk (0xFFFFUL << CRACENCORE_RNGCONTROL_AIS31STATUS_NUMPRELIMALARMS_Pos)
                                                                            /*!< Bit mask of NUMPRELIMALARMS field.*/

/* PRELIMNOISEALARMRNG @Bit 16 : Last preliminary noise alarm occurred due to history value out of range. */
  #define CRACENCORE_RNGCONTROL_AIS31STATUS_PRELIMNOISEALARMRNG_Pos (16UL) /*!< Position of PRELIMNOISEALARMRNG field.         */
  #define CRACENCORE_RNGCONTROL_AIS31STATUS_PRELIMNOISEALARMRNG_Msk (0x1UL << CRACENCORE_RNGCONTROL_AIS31STATUS_PRELIMNOISEALARMRNG_Pos)
                                                                            /*!< Bit mask of PRELIMNOISEALARMRNG field.*/

/* PRELIMNOISEALARMREP @Bit 17 : Last preliminary noise alarm occurred due to consecutive high Χ**2. */
  #define CRACENCORE_RNGCONTROL_AIS31STATUS_PRELIMNOISEALARMREP_Pos (17UL) /*!< Position of PRELIMNOISEALARMREP field.         */
  #define CRACENCORE_RNGCONTROL_AIS31STATUS_PRELIMNOISEALARMREP_Msk (0x1UL << CRACENCORE_RNGCONTROL_AIS31STATUS_PRELIMNOISEALARMREP_Pos)
                                                                            /*!< Bit mask of PRELIMNOISEALARMREP field.*/


/* CRACENCORE_RNGCONTROL_HWCONFIG: Hardware configuration register. */
  #define CRACENCORE_RNGCONTROL_HWCONFIG_ResetValue (0x00000337UL) /*!< Reset value of HWCONFIG register.                      */

/* NUMBOFRINGS @Bits 0..7 : Generic g_NumRings value. */
  #define CRACENCORE_RNGCONTROL_HWCONFIG_NUMBOFRINGS_Pos (0UL) /*!< Position of NUMBOFRINGS field.                             */
  #define CRACENCORE_RNGCONTROL_HWCONFIG_NUMBOFRINGS_Msk (0xFFUL << CRACENCORE_RNGCONTROL_HWCONFIG_NUMBOFRINGS_Pos) /*!< Bit
                                                                            mask of NUMBOFRINGS field.*/

/* AIS31 @Bit 8 : Generic g_AIS31 value. */
  #define CRACENCORE_RNGCONTROL_HWCONFIG_AIS31_Pos (8UL) /*!< Position of AIS31 field.                                         */
  #define CRACENCORE_RNGCONTROL_HWCONFIG_AIS31_Msk (0x1UL << CRACENCORE_RNGCONTROL_HWCONFIG_AIS31_Pos) /*!< Bit mask of AIS31
                                                                            field.*/

/* AIS31FULL @Bit 9 : Generic g_AIS31Full value. */
  #define CRACENCORE_RNGCONTROL_HWCONFIG_AIS31FULL_Pos (9UL) /*!< Position of AIS31FULL field.                                 */
  #define CRACENCORE_RNGCONTROL_HWCONFIG_AIS31FULL_Msk (0x1UL << CRACENCORE_RNGCONTROL_HWCONFIG_AIS31FULL_Pos) /*!< Bit mask of
                                                                            AIS31FULL field.*/


/* CRACENCORE_RNGCONTROL_FIFO: FIFO data */
  #define CRACENCORE_RNGCONTROL_FIFO_MaxCount (16UL) /*!< Max size of FIFO[16] array.                                          */
  #define CRACENCORE_RNGCONTROL_FIFO_MaxIndex (15UL) /*!< Max index of FIFO[16] array.                                         */
  #define CRACENCORE_RNGCONTROL_FIFO_MinIndex (0UL)  /*!< Min index of FIFO[16] array.                                         */
  #define CRACENCORE_RNGCONTROL_FIFO_ResetValue (0x00000000UL) /*!< Reset value of FIFO[16] register.                          */

/* DATA @Bits 0..31 : FIFO data */
  #define CRACENCORE_RNGCONTROL_FIFO_DATA_Pos (0UL)  /*!< Position of DATA field.                                              */
  #define CRACENCORE_RNGCONTROL_FIFO_DATA_Msk (0xFFFFFFFFUL << CRACENCORE_RNGCONTROL_FIFO_DATA_Pos) /*!< Bit mask of DATA
                                                                            field.*/



/* ================================================== Struct CRACENCORE_PK =================================================== */
/**
  * @brief PK [CRACENCORE_PK] (unspecified)
  */
typedef struct {
  __IOM uint32_t  POINTERS;                          /*!< (@ 0x00000000) Pointers register.                                    */
  __IOM uint32_t  COMMAND;                           /*!< (@ 0x00000004) Command register.                                     */
  __IOM uint32_t  CONTROL;                           /*!< (@ 0x00000008) Command register.                                     */
  __IOM uint32_t  STATUS;                            /*!< (@ 0x0000000C) Status register.                                      */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  TIMER;                             /*!< (@ 0x00000014) Timer register.                                       */
  __IOM uint32_t  HWCONFIG;                          /*!< (@ 0x00000018) Hardware configuration register.                      */
  __IOM uint32_t  OPSIZE;                            /*!< (@ 0x0000001C) Operand size register.                                */
  __IM  uint32_t  RESERVED1[8];
  __IOM uint32_t  RAMERRORINJECT;                    /*!< (@ 0x00000040) RAM error injection register.                         */
  __IOM uint32_t  RAMERRORSTATUS;                    /*!< (@ 0x00000044) RAM error status register.                            */
} NRF_CRACENCORE_PK_Type;                            /*!< Size = 72 (0x048)                                                    */

/* CRACENCORE_PK_POINTERS: Pointers register. */
  #define CRACENCORE_PK_POINTERS_ResetValue (0x00000000UL) /*!< Reset value of POINTERS register.                              */

/* OPPTRA @Bits 0..3 : When executing primitive arithmetic operations, this pointer defines where operand A is located in memory
                       (location 0x0 to 0xF). */

  #define CRACENCORE_PK_POINTERS_OPPTRA_Pos (0UL)    /*!< Position of OPPTRA field.                                            */
  #define CRACENCORE_PK_POINTERS_OPPTRA_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRA_Pos) /*!< Bit mask of OPPTRA field.        */

/* OPPTRB @Bits 8..11 : When executing primitive arithmetic operations, this pointer defines where operand B is located in
                        memory (location 0x0 to 0xF). */

  #define CRACENCORE_PK_POINTERS_OPPTRB_Pos (8UL)    /*!< Position of OPPTRB field.                                            */
  #define CRACENCORE_PK_POINTERS_OPPTRB_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRB_Pos) /*!< Bit mask of OPPTRB field.        */

/* OPPTRC @Bits 16..19 : When executing primitive arithmetic operations, this pointer defines the location (0x0 to 0xF) where
                         the result will be stored in memory. */

  #define CRACENCORE_PK_POINTERS_OPPTRC_Pos (16UL)   /*!< Position of OPPTRC field.                                            */
  #define CRACENCORE_PK_POINTERS_OPPTRC_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRC_Pos) /*!< Bit mask of OPPTRC field.        */

/* OPPTRN @Bits 24..27 : When executing primitive arithmetic operations, this pointer defines the location where the modulus is
                         located in memory (location 0x0 to 0xF). */

  #define CRACENCORE_PK_POINTERS_OPPTRN_Pos (24UL)   /*!< Position of OPPTRN field.                                            */
  #define CRACENCORE_PK_POINTERS_OPPTRN_Msk (0xFUL << CRACENCORE_PK_POINTERS_OPPTRN_Pos) /*!< Bit mask of OPPTRN field.        */


/* CRACENCORE_PK_COMMAND: Command register. */
  #define CRACENCORE_PK_COMMAND_ResetValue (0x0000000FUL) /*!< Reset value of COMMAND register.                                */

/* OPEADDR @Bits 0..6 : This field defines the operation to be performed. */
  #define CRACENCORE_PK_COMMAND_OPEADDR_Pos (0UL)    /*!< Position of OPEADDR field.                                           */
  #define CRACENCORE_PK_COMMAND_OPEADDR_Msk (0x7FUL << CRACENCORE_PK_COMMAND_OPEADDR_Pos) /*!< Bit mask of OPEADDR field.      */

/* FIELDF @Bit 7 : 0: Field is GF(p) 1: Field is GF(2**m) */
  #define CRACENCORE_PK_COMMAND_FIELDF_Pos (7UL)     /*!< Position of FIELDF field.                                            */
  #define CRACENCORE_PK_COMMAND_FIELDF_Msk (0x1UL << CRACENCORE_PK_COMMAND_FIELDF_Pos) /*!< Bit mask of FIELDF field.          */

/* OPBYTESM1 @Bits 8..17 : This field defines the size (= number of bytes minus one) of the operands for the current operation.
                           */

  #define CRACENCORE_PK_COMMAND_OPBYTESM1_Pos (8UL)  /*!< Position of OPBYTESM1 field.                                         */
  #define CRACENCORE_PK_COMMAND_OPBYTESM1_Msk (0x3FFUL << CRACENCORE_PK_COMMAND_OPBYTESM1_Pos) /*!< Bit mask of OPBYTESM1
                                                                            field.*/

/* RANDMOD @Bit 19 : Enable randomization of modulus (counter-measure). */
  #define CRACENCORE_PK_COMMAND_RANDMOD_Pos (19UL)   /*!< Position of RANDMOD field.                                           */
  #define CRACENCORE_PK_COMMAND_RANDMOD_Msk (0x1UL << CRACENCORE_PK_COMMAND_RANDMOD_Pos) /*!< Bit mask of RANDMOD field.       */

/* SELCURVE @Bits 20..22 : Enable accelerator for specific curve modulus: */
  #define CRACENCORE_PK_COMMAND_SELCURVE_Pos (20UL)  /*!< Position of SELCURVE field.                                          */
  #define CRACENCORE_PK_COMMAND_SELCURVE_Msk (0x7UL << CRACENCORE_PK_COMMAND_SELCURVE_Pos) /*!< Bit mask of SELCURVE field.    */
  #define CRACENCORE_PK_COMMAND_SELCURVE_Min (0x0UL) /*!< Min enumerator value of SELCURVE field.                              */
  #define CRACENCORE_PK_COMMAND_SELCURVE_Max (0x6UL) /*!< Max enumerator value of SELCURVE field.                              */
  #define CRACENCORE_PK_COMMAND_SELCURVE_NOACCEL (0x0UL) /*!< (unspecified)                                                    */
  #define CRACENCORE_PK_COMMAND_SELCURVE_P256 (0x1UL) /*!< (unspecified)                                                       */
  #define CRACENCORE_PK_COMMAND_SELCURVE_P384 (0x2UL) /*!< (unspecified)                                                       */
  #define CRACENCORE_PK_COMMAND_SELCURVE_P521 (0x3UL) /*!< (unspecified)                                                       */
  #define CRACENCORE_PK_COMMAND_SELCURVE_P192 (0x4UL) /*!< (unspecified)                                                       */
  #define CRACENCORE_PK_COMMAND_SELCURVE_CURVE25519 (0x5UL) /*!< (unspecified)                                                 */
  #define CRACENCORE_PK_COMMAND_SELCURVE_ED25519 (0x6UL) /*!< (unspecified)                                                    */

/* RANDKE @Bit 24 : Enable randomization of exponent/scalar (counter-measure). */
  #define CRACENCORE_PK_COMMAND_RANDKE_Pos (24UL)    /*!< Position of RANDKE field.                                            */
  #define CRACENCORE_PK_COMMAND_RANDKE_Msk (0x1UL << CRACENCORE_PK_COMMAND_RANDKE_Pos) /*!< Bit mask of RANDKE field.          */

/* RANDPROJ @Bit 25 : Enable randomization of projective coordinates (counter-measure). */
  #define CRACENCORE_PK_COMMAND_RANDPROJ_Pos (25UL)  /*!< Position of RANDPROJ field.                                          */
  #define CRACENCORE_PK_COMMAND_RANDPROJ_Msk (0x1UL << CRACENCORE_PK_COMMAND_RANDPROJ_Pos) /*!< Bit mask of RANDPROJ field.    */

/* EDWARDS @Bit 26 : Enable Edwards curve. */
  #define CRACENCORE_PK_COMMAND_EDWARDS_Pos (26UL)   /*!< Position of EDWARDS field.                                           */
  #define CRACENCORE_PK_COMMAND_EDWARDS_Msk (0x1UL << CRACENCORE_PK_COMMAND_EDWARDS_Pos) /*!< Bit mask of EDWARDS field.       */

/* SWAPBYTES @Bit 28 : Swap the bytes on AHB interface: */
  #define CRACENCORE_PK_COMMAND_SWAPBYTES_Pos (28UL) /*!< Position of SWAPBYTES field.                                         */
  #define CRACENCORE_PK_COMMAND_SWAPBYTES_Msk (0x1UL << CRACENCORE_PK_COMMAND_SWAPBYTES_Pos) /*!< Bit mask of SWAPBYTES field. */
  #define CRACENCORE_PK_COMMAND_SWAPBYTES_Min (0x0UL) /*!< Min enumerator value of SWAPBYTES field.                            */
  #define CRACENCORE_PK_COMMAND_SWAPBYTES_Max (0x1UL) /*!< Max enumerator value of SWAPBYTES field.                            */
  #define CRACENCORE_PK_COMMAND_SWAPBYTES_NATIVE (0x0UL) /*!< Native format (little endian).                                   */
  #define CRACENCORE_PK_COMMAND_SWAPBYTES_SWAPPED (0x1UL) /*!< Byte swapped (big endian).                                      */

/* FLAGA @Bit 29 : Flag A. */
  #define CRACENCORE_PK_COMMAND_FLAGA_Pos (29UL)     /*!< Position of FLAGA field.                                             */
  #define CRACENCORE_PK_COMMAND_FLAGA_Msk (0x1UL << CRACENCORE_PK_COMMAND_FLAGA_Pos) /*!< Bit mask of FLAGA field.             */

/* FLAGB @Bit 30 : Flag B. */
  #define CRACENCORE_PK_COMMAND_FLAGB_Pos (30UL)     /*!< Position of FLAGB field.                                             */
  #define CRACENCORE_PK_COMMAND_FLAGB_Msk (0x1UL << CRACENCORE_PK_COMMAND_FLAGB_Pos) /*!< Bit mask of FLAGB field.             */

/* CALCR2 @Bit 31 : This bit indicates if the IP has to calculate R**2 mod N for the next operation. */
  #define CRACENCORE_PK_COMMAND_CALCR2_Pos (31UL)    /*!< Position of CALCR2 field.                                            */
  #define CRACENCORE_PK_COMMAND_CALCR2_Msk (0x1UL << CRACENCORE_PK_COMMAND_CALCR2_Pos) /*!< Bit mask of CALCR2 field.          */
  #define CRACENCORE_PK_COMMAND_CALCR2_Min (0x0UL)   /*!< Min enumerator value of CALCR2 field.                                */
  #define CRACENCORE_PK_COMMAND_CALCR2_Max (0x1UL)   /*!< Max enumerator value of CALCR2 field.                                */
  #define CRACENCORE_PK_COMMAND_CALCR2_NRECALCULATE (0x0UL) /*!< don't recalculate R² mod N                                    */
  #define CRACENCORE_PK_COMMAND_CALCR2_RECALCULATE (0x1UL) /*!< re-calculate R² mod N                                          */


/* CRACENCORE_PK_CONTROL: Command register. */
  #define CRACENCORE_PK_CONTROL_ResetValue (0x00000000UL) /*!< Reset value of CONTROL register.                                */

/* START @Bit 0 : Writing a 1 starts the processing. */
  #define CRACENCORE_PK_CONTROL_START_Pos (0UL)      /*!< Position of START field.                                             */
  #define CRACENCORE_PK_CONTROL_START_Msk (0x1UL << CRACENCORE_PK_CONTROL_START_Pos) /*!< Bit mask of START field.             */

/* CLEARIRQ @Bit 1 : Writing a 1 clears the IRQ output. */
  #define CRACENCORE_PK_CONTROL_CLEARIRQ_Pos (1UL)   /*!< Position of CLEARIRQ field.                                          */
  #define CRACENCORE_PK_CONTROL_CLEARIRQ_Msk (0x1UL << CRACENCORE_PK_CONTROL_CLEARIRQ_Pos) /*!< Bit mask of CLEARIRQ field.    */


/* CRACENCORE_PK_STATUS: Status register. */
  #define CRACENCORE_PK_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                                  */

/* ERRORFLAGS @Bits 4..15 : These bits indicate an error condition. */
  #define CRACENCORE_PK_STATUS_ERRORFLAGS_Pos (4UL)  /*!< Position of ERRORFLAGS field.                                        */
  #define CRACENCORE_PK_STATUS_ERRORFLAGS_Msk (0xFFFUL << CRACENCORE_PK_STATUS_ERRORFLAGS_Pos) /*!< Bit mask of ERRORFLAGS
                                                                            field.*/

/* PKBUSY @Bit 16 : This bit reflects the BUSY output value. */
  #define CRACENCORE_PK_STATUS_PKBUSY_Pos (16UL)     /*!< Position of PKBUSY field.                                            */
  #define CRACENCORE_PK_STATUS_PKBUSY_Msk (0x1UL << CRACENCORE_PK_STATUS_PKBUSY_Pos) /*!< Bit mask of PKBUSY field.            */

/* INTRPTSTATUS @Bit 17 : This bit reflects the IRQ output value. */
  #define CRACENCORE_PK_STATUS_INTRPTSTATUS_Pos (17UL) /*!< Position of INTRPTSTATUS field.                                    */
  #define CRACENCORE_PK_STATUS_INTRPTSTATUS_Msk (0x1UL << CRACENCORE_PK_STATUS_INTRPTSTATUS_Pos) /*!< Bit mask of INTRPTSTATUS
                                                                            field.*/

/* FAILPTR @Bits 24..28 : These bits indicate which data location generated the error flag. */
  #define CRACENCORE_PK_STATUS_FAILPTR_Pos (24UL)    /*!< Position of FAILPTR field.                                           */
  #define CRACENCORE_PK_STATUS_FAILPTR_Msk (0x1FUL << CRACENCORE_PK_STATUS_FAILPTR_Pos) /*!< Bit mask of FAILPTR field.        */


/* CRACENCORE_PK_TIMER: Timer register. */
  #define CRACENCORE_PK_TIMER_ResetValue (0x00000000UL) /*!< Reset value of TIMER register.                                    */

/* TIMER @Bits 0..31 : Number of core clock cycles. */
  #define CRACENCORE_PK_TIMER_TIMER_Pos (0UL)        /*!< Position of TIMER field.                                             */
  #define CRACENCORE_PK_TIMER_TIMER_Msk (0xFFFFFFFFUL << CRACENCORE_PK_TIMER_TIMER_Pos) /*!< Bit mask of TIMER field.          */


/* CRACENCORE_PK_HWCONFIG: Hardware configuration register. */
  #define CRACENCORE_PK_HWCONFIG_ResetValue (0x01F72200UL) /*!< Reset value of HWCONFIG register.                              */

/* MAXOPSIZE @Bits 0..11 : Maximum operand size (number of bytes). */
  #define CRACENCORE_PK_HWCONFIG_MAXOPSIZE_Pos (0UL) /*!< Position of MAXOPSIZE field.                                         */
  #define CRACENCORE_PK_HWCONFIG_MAXOPSIZE_Msk (0xFFFUL << CRACENCORE_PK_HWCONFIG_MAXOPSIZE_Pos) /*!< Bit mask of MAXOPSIZE
                                                                            field.*/

/* NBMULT @Bits 12..15 : Number of multipliers: */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_Pos (12UL)   /*!< Position of NBMULT field.                                            */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_Msk (0xFUL << CRACENCORE_PK_HWCONFIG_NBMULT_Pos) /*!< Bit mask of NBMULT field.        */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_Min (0x0UL)  /*!< Min enumerator value of NBMULT field.                                */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_Max (0x8UL)  /*!< Max enumerator value of NBMULT field.                                */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT1 (0x0UL) /*!< 1 multiplier                                                        */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT4 (0x1UL) /*!< 4 multipliers                                                       */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT16 (0x2UL) /*!< 16 multipliers                                                     */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT64 (0x4UL) /*!< 64 multipliers                                                     */
  #define CRACENCORE_PK_HWCONFIG_NBMULT_MULT256 (0x8UL) /*!< 256 multipliers                                                   */

/* PRIMEFIELD @Bit 16 : Support prime field. */
  #define CRACENCORE_PK_HWCONFIG_PRIMEFIELD_Pos (16UL) /*!< Position of PRIMEFIELD field.                                      */
  #define CRACENCORE_PK_HWCONFIG_PRIMEFIELD_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_PRIMEFIELD_Pos) /*!< Bit mask of PRIMEFIELD
                                                                            field.*/

/* BINARYFIELD @Bit 17 : Support binary field. */
  #define CRACENCORE_PK_HWCONFIG_BINARYFIELD_Pos (17UL) /*!< Position of BINARYFIELD field.                                    */
  #define CRACENCORE_PK_HWCONFIG_BINARYFIELD_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_BINARYFIELD_Pos) /*!< Bit mask of BINARYFIELD
                                                                            field.*/

/* ECC @Bit 18 : Support error correction. */
  #define CRACENCORE_PK_HWCONFIG_ECC_Pos (18UL)      /*!< Position of ECC field.                                               */
  #define CRACENCORE_PK_HWCONFIG_ECC_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_ECC_Pos) /*!< Bit mask of ECC field.                 */

/* P256 @Bit 20 : Support ECC P256 acceleration. */
  #define CRACENCORE_PK_HWCONFIG_P256_Pos (20UL)     /*!< Position of P256 field.                                              */
  #define CRACENCORE_PK_HWCONFIG_P256_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P256_Pos) /*!< Bit mask of P256 field.              */

/* P384 @Bit 21 : Support ECC P384 acceleration. */
  #define CRACENCORE_PK_HWCONFIG_P384_Pos (21UL)     /*!< Position of P384 field.                                              */
  #define CRACENCORE_PK_HWCONFIG_P384_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P384_Pos) /*!< Bit mask of P384 field.              */

/* P521 @Bit 22 : Support ECC P521 acceleration. */
  #define CRACENCORE_PK_HWCONFIG_P521_Pos (22UL)     /*!< Position of P521 field.                                              */
  #define CRACENCORE_PK_HWCONFIG_P521_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P521_Pos) /*!< Bit mask of P521 field.              */

/* P192 @Bit 23 : Support ECC P192 acceleration. */
  #define CRACENCORE_PK_HWCONFIG_P192_Pos (23UL)     /*!< Position of P192 field.                                              */
  #define CRACENCORE_PK_HWCONFIG_P192_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_P192_Pos) /*!< Bit mask of P192 field.              */

/* X25519 @Bit 24 : Support Curve25519/Ed25519 acceleration. */
  #define CRACENCORE_PK_HWCONFIG_X25519_Pos (24UL)   /*!< Position of X25519 field.                                            */
  #define CRACENCORE_PK_HWCONFIG_X25519_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_X25519_Pos) /*!< Bit mask of X25519 field.        */

/* AHBMASTER @Bit 25 : Memory access */
  #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Pos (25UL) /*!< Position of AHBMASTER field.                                        */
  #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_AHBMASTER_Pos) /*!< Bit mask of AHBMASTER
                                                                            field.*/
  #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Min (0x0UL) /*!< Min enumerator value of AHBMASTER field.                           */
  #define CRACENCORE_PK_HWCONFIG_AHBMASTER_Max (0x1UL) /*!< Max enumerator value of AHBMASTER field.                           */
  #define CRACENCORE_PK_HWCONFIG_AHBMASTER_SLAVE (0x0UL) /*!< Memory access through AHB Slave and internally in the PKE.       */
  #define CRACENCORE_PK_HWCONFIG_AHBMASTER_MASTER (0x1UL) /*!< Memory access through AHB Master, outside the PKE.              */

/* DISABLESMX @Bit 29 : State of DisableSMx input (high when SM2/SM9 operations are disabled). */
  #define CRACENCORE_PK_HWCONFIG_DISABLESMX_Pos (29UL) /*!< Position of DISABLESMX field.                                      */
  #define CRACENCORE_PK_HWCONFIG_DISABLESMX_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_DISABLESMX_Pos) /*!< Bit mask of DISABLESMX
                                                                            field.*/

/* DISABLECLRMEM @Bit 30 : State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled). */
  #define CRACENCORE_PK_HWCONFIG_DISABLECLRMEM_Pos (30UL) /*!< Position of DISABLECLRMEM field.                                */
  #define CRACENCORE_PK_HWCONFIG_DISABLECLRMEM_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_DISABLECLRMEM_Pos) /*!< Bit mask of
                                                                            DISABLECLRMEM field.*/

/* DISABLECM @Bit 31 : State of DisableCM input (high when counter-measures are disabled). */
  #define CRACENCORE_PK_HWCONFIG_DISABLECM_Pos (31UL) /*!< Position of DISABLECM field.                                        */
  #define CRACENCORE_PK_HWCONFIG_DISABLECM_Msk (0x1UL << CRACENCORE_PK_HWCONFIG_DISABLECM_Pos) /*!< Bit mask of DISABLECM
                                                                            field.*/


/* CRACENCORE_PK_OPSIZE: Operand size register. */
  #define CRACENCORE_PK_OPSIZE_ResetValue (0x00001000UL) /*!< Reset value of OPSIZE register.                                  */

/* OPSIZE @Bits 0..12 : Operand size (number of bytes): This register is used when the memory is accessed via AHB Master */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_Pos (0UL)      /*!< Position of OPSIZE field.                                            */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_Msk (0x1FFFUL << CRACENCORE_PK_OPSIZE_OPSIZE_Pos) /*!< Bit mask of OPSIZE field.         */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_Min (0x100UL)  /*!< Min enumerator value of OPSIZE field.                                */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_Max (0x1000UL) /*!< Max enumerator value of OPSIZE field.                                */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE256 (0x0100UL) /*!< 256 bytes.                                                     */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE521 (0x0209UL) /*!< 521 bytes.                                                     */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE2048 (0x0800UL) /*!< 2048 bytes.                                                   */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE3072 (0x0C00UL) /*!< 3072 bytes.                                                   */
  #define CRACENCORE_PK_OPSIZE_OPSIZE_OPSIZE4096 (0x1000UL) /*!< 4096 bytes.                                                   */


/* CRACENCORE_PK_RAMERRORINJECT: RAM error injection register. */
  #define CRACENCORE_PK_RAMERRORINJECT_ResetValue (0x03FF03FFUL) /*!< Reset value of RAMERRORINJECT register.                  */

/* BITERROR1 @Bits 0..9 : Bit position of first error */
  #define CRACENCORE_PK_RAMERRORINJECT_BITERROR1_Pos (0UL) /*!< Position of BITERROR1 field.                                   */
  #define CRACENCORE_PK_RAMERRORINJECT_BITERROR1_Msk (0x3FFUL << CRACENCORE_PK_RAMERRORINJECT_BITERROR1_Pos) /*!< Bit mask of
                                                                            BITERROR1 field.*/

/* BITERROR2 @Bits 16..25 : Bit position of second error */
  #define CRACENCORE_PK_RAMERRORINJECT_BITERROR2_Pos (16UL) /*!< Position of BITERROR2 field.                                  */
  #define CRACENCORE_PK_RAMERRORINJECT_BITERROR2_Msk (0x3FFUL << CRACENCORE_PK_RAMERRORINJECT_BITERROR2_Pos) /*!< Bit mask of
                                                                            BITERROR2 field.*/


/* CRACENCORE_PK_RAMERRORSTATUS: RAM error status register. */
  #define CRACENCORE_PK_RAMERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RAMERRORSTATUS register.                  */

/* RAMCORRECTION @Bit 0 : This bit indicates that a 1-bit error has been detected and corrected on RAM interface */
  #define CRACENCORE_PK_RAMERRORSTATUS_RAMCORRECTION_Pos (0UL) /*!< Position of RAMCORRECTION field.                           */
  #define CRACENCORE_PK_RAMERRORSTATUS_RAMCORRECTION_Msk (0x1UL << CRACENCORE_PK_RAMERRORSTATUS_RAMCORRECTION_Pos) /*!< Bit mask
                                                                            of RAMCORRECTION field.*/

/* RAMFAILURE @Bit 1 : This bit indicates that an uncorrectable error has been detected on the data RAM interface */
  #define CRACENCORE_PK_RAMERRORSTATUS_RAMFAILURE_Pos (1UL) /*!< Position of RAMFAILURE field.                                 */
  #define CRACENCORE_PK_RAMERRORSTATUS_RAMFAILURE_Msk (0x1UL << CRACENCORE_PK_RAMERRORSTATUS_RAMFAILURE_Pos) /*!< Bit mask of
                                                                            RAMFAILURE field.*/



/* ================================================== Struct CRACENCORE_IKG ================================================== */
/**
  * @brief IKG [CRACENCORE_IKG] (unspecified)
  */
typedef struct {
  __IOM uint32_t  START;                             /*!< (@ 0x00000000) Start register.                                       */
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register.                                      */
  __IOM uint32_t  INITDATA;                          /*!< (@ 0x00000008) InitData register.                                    */
  __IOM uint32_t  NONCE;                             /*!< (@ 0x0000000C) Nonce register.                                       */
  __IOM uint32_t  PERSONALISATIONSTRING;             /*!< (@ 0x00000010) Personalisation String register.                      */
  __IOM uint32_t  RESEEDINTERVALLSB;                 /*!< (@ 0x00000014) Reseed Interval LSB register.                         */
  __IOM uint32_t  RESEEDINTERVALMSB;                 /*!< (@ 0x00000018) Reseed Interval MSB register.                         */
  __IOM uint32_t  PKECONTROL;                        /*!< (@ 0x0000001C) PKE Control register.                                 */
  __IOM uint32_t  PKECOMMAND;                        /*!< (@ 0x00000020) PKE Command register.                                 */
  __IOM uint32_t  PKESTATUS;                         /*!< (@ 0x00000024) PKE Status register.                                  */
  __IOM uint32_t  SOFTRST;                           /*!< (@ 0x00000028) SoftRst register.                                     */
  __IOM uint32_t  HWCONFIG;                          /*!< (@ 0x0000002C) HwConfig register.                                    */
} NRF_CRACENCORE_IKG_Type;                           /*!< Size = 48 (0x030)                                                    */

/* CRACENCORE_IKG_START: Start register. */
  #define CRACENCORE_IKG_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                                   */

/* START @Bit 0 : Start the Isolated Key Generation. */
  #define CRACENCORE_IKG_START_START_Pos (0UL)       /*!< Position of START field.                                             */
  #define CRACENCORE_IKG_START_START_Msk (0x1UL << CRACENCORE_IKG_START_START_Pos) /*!< Bit mask of START field.               */


/* CRACENCORE_IKG_STATUS: Status register. */
  #define CRACENCORE_IKG_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                                 */

/* SEEDERROR @Bit 0 : Seed Error during Isolated Key Generation. */
  #define CRACENCORE_IKG_STATUS_SEEDERROR_Pos (0UL)  /*!< Position of SEEDERROR field.                                         */
  #define CRACENCORE_IKG_STATUS_SEEDERROR_Msk (0x1UL << CRACENCORE_IKG_STATUS_SEEDERROR_Pos) /*!< Bit mask of SEEDERROR field. */

/* ENTROPYERROR @Bit 1 : Entropy Error during Isolated Key Generation. */
  #define CRACENCORE_IKG_STATUS_ENTROPYERROR_Pos (1UL) /*!< Position of ENTROPYERROR field.                                    */
  #define CRACENCORE_IKG_STATUS_ENTROPYERROR_Msk (0x1UL << CRACENCORE_IKG_STATUS_ENTROPYERROR_Pos) /*!< Bit mask of ENTROPYERROR
                                                                            field.*/

/* OKAY @Bit 2 : Isolated Key Generation is okay. */
  #define CRACENCORE_IKG_STATUS_OKAY_Pos (2UL)       /*!< Position of OKAY field.                                              */
  #define CRACENCORE_IKG_STATUS_OKAY_Msk (0x1UL << CRACENCORE_IKG_STATUS_OKAY_Pos) /*!< Bit mask of OKAY field.                */

/* CTRDRBGBUSY @Bit 4 : CTR_DRBG health test is busy (only when g_hw_health_test = true). */
  #define CRACENCORE_IKG_STATUS_CTRDRBGBUSY_Pos (4UL) /*!< Position of CTRDRBGBUSY field.                                      */
  #define CRACENCORE_IKG_STATUS_CTRDRBGBUSY_Msk (0x1UL << CRACENCORE_IKG_STATUS_CTRDRBGBUSY_Pos) /*!< Bit mask of CTRDRBGBUSY
                                                                            field.*/

/* CATASTROPHICERROR @Bit 5 : Catastrophic error during CTR_DRBG health test (only when g_hw_health_test = true). */
  #define CRACENCORE_IKG_STATUS_CATASTROPHICERROR_Pos (5UL) /*!< Position of CATASTROPHICERROR field.                          */
  #define CRACENCORE_IKG_STATUS_CATASTROPHICERROR_Msk (0x1UL << CRACENCORE_IKG_STATUS_CATASTROPHICERROR_Pos) /*!< Bit mask of
                                                                            CATASTROPHICERROR field.*/

/* SYMKEYSTORED @Bit 6 : Symmetric Keys are stored. */
  #define CRACENCORE_IKG_STATUS_SYMKEYSTORED_Pos (6UL) /*!< Position of SYMKEYSTORED field.                                    */
  #define CRACENCORE_IKG_STATUS_SYMKEYSTORED_Msk (0x1UL << CRACENCORE_IKG_STATUS_SYMKEYSTORED_Pos) /*!< Bit mask of SYMKEYSTORED
                                                                            field.*/

/* PRIVKEYSTORED @Bit 7 : Private Keys are stored. */
  #define CRACENCORE_IKG_STATUS_PRIVKEYSTORED_Pos (7UL) /*!< Position of PRIVKEYSTORED field.                                  */
  #define CRACENCORE_IKG_STATUS_PRIVKEYSTORED_Msk (0x1UL << CRACENCORE_IKG_STATUS_PRIVKEYSTORED_Pos) /*!< Bit mask of
                                                                            PRIVKEYSTORED field.*/


/* CRACENCORE_IKG_INITDATA: InitData register. */
  #define CRACENCORE_IKG_INITDATA_ResetValue (0x00000000UL) /*!< Reset value of INITDATA register.                             */

/* INITDATA @Bit 0 : Writing a 1 initialise Nonce and Personalisation_String registers counters, i.e. start writing from the 32
                     LSB. */

  #define CRACENCORE_IKG_INITDATA_INITDATA_Pos (0UL) /*!< Position of INITDATA field.                                          */
  #define CRACENCORE_IKG_INITDATA_INITDATA_Msk (0x1UL << CRACENCORE_IKG_INITDATA_INITDATA_Pos) /*!< Bit mask of INITDATA field.*/


/* CRACENCORE_IKG_NONCE: Nonce register. */
  #define CRACENCORE_IKG_NONCE_ResetValue (0x00000000UL) /*!< Reset value of NONCE register.                                   */

/* NONCE @Bits 0..31 : Nonce (write/read value 32-bit by 32-bit). */
  #define CRACENCORE_IKG_NONCE_NONCE_Pos (0UL)       /*!< Position of NONCE field.                                             */
  #define CRACENCORE_IKG_NONCE_NONCE_Msk (0xFFFFFFFFUL << CRACENCORE_IKG_NONCE_NONCE_Pos) /*!< Bit mask of NONCE field.        */


/* CRACENCORE_IKG_PERSONALISATIONSTRING: Personalisation String register. */
  #define CRACENCORE_IKG_PERSONALISATIONSTRING_ResetValue (0x00000000UL) /*!< Reset value of PERSONALISATIONSTRING register.   */

/* PERSONALISATIONSTRING @Bits 0..31 : Personalisation String (write/read value 32-bit by 32-bit). */
  #define CRACENCORE_IKG_PERSONALISATIONSTRING_PERSONALISATIONSTRING_Pos (0UL) /*!< Position of PERSONALISATIONSTRING field.   */
  #define CRACENCORE_IKG_PERSONALISATIONSTRING_PERSONALISATIONSTRING_Msk (0xFFFFFFFFUL << CRACENCORE_IKG_PERSONALISATIONSTRING_PERSONALISATIONSTRING_Pos)
                                                                            /*!< Bit mask of PERSONALISATIONSTRING field.*/


/* CRACENCORE_IKG_RESEEDINTERVALLSB: Reseed Interval LSB register. */
  #define CRACENCORE_IKG_RESEEDINTERVALLSB_ResetValue (0x80000000UL) /*!< Reset value of RESEEDINTERVALLSB register.           */

/* RESEEDINTERVALLSB @Bits 0..31 : Reseed Interval LSB. */
  #define CRACENCORE_IKG_RESEEDINTERVALLSB_RESEEDINTERVALLSB_Pos (0UL) /*!< Position of RESEEDINTERVALLSB field.               */
  #define CRACENCORE_IKG_RESEEDINTERVALLSB_RESEEDINTERVALLSB_Msk (0xFFFFFFFFUL << CRACENCORE_IKG_RESEEDINTERVALLSB_RESEEDINTERVALLSB_Pos)
                                                                            /*!< Bit mask of RESEEDINTERVALLSB field.*/


/* CRACENCORE_IKG_RESEEDINTERVALMSB: Reseed Interval MSB register. */
  #define CRACENCORE_IKG_RESEEDINTERVALMSB_ResetValue (0x00000000UL) /*!< Reset value of RESEEDINTERVALMSB register.           */

/* RESEEDINTERVALMSB @Bits 0..15 : Reseed Interval MSB. */
  #define CRACENCORE_IKG_RESEEDINTERVALMSB_RESEEDINTERVALMSB_Pos (0UL) /*!< Position of RESEEDINTERVALMSB field.               */
  #define CRACENCORE_IKG_RESEEDINTERVALMSB_RESEEDINTERVALMSB_Msk (0xFFFFUL << CRACENCORE_IKG_RESEEDINTERVALMSB_RESEEDINTERVALMSB_Pos)
                                                                            /*!< Bit mask of RESEEDINTERVALMSB field.*/


/* CRACENCORE_IKG_PKECONTROL: PKE Control register. */
  #define CRACENCORE_IKG_PKECONTROL_ResetValue (0x00000000UL) /*!< Reset value of PKECONTROL register.                         */

/* PKESTART @Bit 0 : Start the PKE operation or trigger for Secure mode exit. */
  #define CRACENCORE_IKG_PKECONTROL_PKESTART_Pos (0UL) /*!< Position of PKESTART field.                                        */
  #define CRACENCORE_IKG_PKECONTROL_PKESTART_Msk (0x1UL << CRACENCORE_IKG_PKECONTROL_PKESTART_Pos) /*!< Bit mask of PKESTART
                                                                            field.*/

/* CLEARIRQ @Bit 1 : Clear the IRQ output. */
  #define CRACENCORE_IKG_PKECONTROL_CLEARIRQ_Pos (1UL) /*!< Position of CLEARIRQ field.                                        */
  #define CRACENCORE_IKG_PKECONTROL_CLEARIRQ_Msk (0x1UL << CRACENCORE_IKG_PKECONTROL_CLEARIRQ_Pos) /*!< Bit mask of CLEARIRQ
                                                                            field.*/


/* CRACENCORE_IKG_PKECOMMAND: PKE Command register. */
  #define CRACENCORE_IKG_PKECOMMAND_ResetValue (0x00000000UL) /*!< Reset value of PKECOMMAND register.                         */

/* SECUREMODE @Bit 0 : Secure mode. */
  #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Pos (0UL) /*!< Position of SECUREMODE field.                                    */
  #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Msk (0x1UL << CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Pos) /*!< Bit mask of
                                                                            SECUREMODE field.*/
  #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Min (0x0UL) /*!< Min enumerator value of SECUREMODE field.                      */
  #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_Max (0x1UL) /*!< Max enumerator value of SECUREMODE field.                      */
  #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_DEACTIVATED (0x0UL) /*!< (unspecified)                                          */
  #define CRACENCORE_IKG_PKECOMMAND_SECUREMODE_ACTIVATED (0x1UL) /*!< (unspecified)                                            */

/* SELECTEDKEY @Bits 4..7 : Select Generated Private Key for PKE operation. */
  #define CRACENCORE_IKG_PKECOMMAND_SELECTEDKEY_Pos (4UL) /*!< Position of SELECTEDKEY field.                                  */
  #define CRACENCORE_IKG_PKECOMMAND_SELECTEDKEY_Msk (0xFUL << CRACENCORE_IKG_PKECOMMAND_SELECTEDKEY_Pos) /*!< Bit mask of
                                                                            SELECTEDKEY field.*/

/* OPSEL @Bits 8..9 : Select PKE operation with Isolated Key */
  #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Pos (8UL)  /*!< Position of OPSEL field.                                             */
  #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Msk (0x3UL << CRACENCORE_IKG_PKECOMMAND_OPSEL_Pos) /*!< Bit mask of OPSEL field.     */
  #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Min (0x0UL) /*!< Min enumerator value of OPSEL field.                                */
  #define CRACENCORE_IKG_PKECOMMAND_OPSEL_Max (0x2UL) /*!< Max enumerator value of OPSEL field.                                */
  #define CRACENCORE_IKG_PKECOMMAND_OPSEL_PUBKEY (0x0UL) /*!< Public Key Generation                                            */
  #define CRACENCORE_IKG_PKECOMMAND_OPSEL_ECDSA (0x1UL) /*!< ECDSA Signature                                                   */
  #define CRACENCORE_IKG_PKECOMMAND_OPSEL_PTMUL (0x2UL) /*!< Point Multiplication                                              */


/* CRACENCORE_IKG_PKESTATUS: PKE Status register. */
  #define CRACENCORE_IKG_PKESTATUS_ResetValue (0x00000000UL) /*!< Reset value of PKESTATUS register.                           */

/* ERROR @Bit 0 : Error because either Private Keys are not stored or the operation is not defined. */
  #define CRACENCORE_IKG_PKESTATUS_ERROR_Pos (0UL)   /*!< Position of ERROR field.                                             */
  #define CRACENCORE_IKG_PKESTATUS_ERROR_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_ERROR_Pos) /*!< Bit mask of ERROR field.       */

/* STARTERROR @Bit 1 : Error because a new operation is started while the previous one is still busy. */
  #define CRACENCORE_IKG_PKESTATUS_STARTERROR_Pos (1UL) /*!< Position of STARTERROR field.                                     */
  #define CRACENCORE_IKG_PKESTATUS_STARTERROR_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_STARTERROR_Pos) /*!< Bit mask of STARTERROR
                                                                            field.*/

/* IKGPKBUSY @Bit 16 : Busy, set when the operation starts and cleared when the operation is finished. */
  #define CRACENCORE_IKG_PKESTATUS_IKGPKBUSY_Pos (16UL) /*!< Position of IKGPKBUSY field.                                      */
  #define CRACENCORE_IKG_PKESTATUS_IKGPKBUSY_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_IKGPKBUSY_Pos) /*!< Bit mask of IKGPKBUSY
                                                                            field.*/

/* IRQSTATUS @Bit 17 : IRQ, set when the operation is finished and cleared when the CPU writes the bit 1 of PKE_Control Register
                       or a new operation is started. */

  #define CRACENCORE_IKG_PKESTATUS_IRQSTATUS_Pos (17UL) /*!< Position of IRQSTATUS field.                                      */
  #define CRACENCORE_IKG_PKESTATUS_IRQSTATUS_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_IRQSTATUS_Pos) /*!< Bit mask of IRQSTATUS
                                                                            field.*/

/* ERASEBUSY @Bit 18 : The PKE Data RAM is being erased. */
  #define CRACENCORE_IKG_PKESTATUS_ERASEBUSY_Pos (18UL) /*!< Position of ERASEBUSY field.                                      */
  #define CRACENCORE_IKG_PKESTATUS_ERASEBUSY_Msk (0x1UL << CRACENCORE_IKG_PKESTATUS_ERASEBUSY_Pos) /*!< Bit mask of ERASEBUSY
                                                                            field.*/


/* CRACENCORE_IKG_SOFTRST: SoftRst register. */
  #define CRACENCORE_IKG_SOFTRST_ResetValue (0x00000000UL) /*!< Reset value of SOFTRST register.                               */

/* SOFTRST @Bit 0 : Software reset: */
  #define CRACENCORE_IKG_SOFTRST_SOFTRST_Pos (0UL)   /*!< Position of SOFTRST field.                                           */
  #define CRACENCORE_IKG_SOFTRST_SOFTRST_Msk (0x1UL << CRACENCORE_IKG_SOFTRST_SOFTRST_Pos) /*!< Bit mask of SOFTRST field.     */
  #define CRACENCORE_IKG_SOFTRST_SOFTRST_Min (0x0UL) /*!< Min enumerator value of SOFTRST field.                               */
  #define CRACENCORE_IKG_SOFTRST_SOFTRST_Max (0x1UL) /*!< Max enumerator value of SOFTRST field.                               */
  #define CRACENCORE_IKG_SOFTRST_SOFTRST_NORMAL (0x0UL) /*!< Normal mode.                                                      */
  #define CRACENCORE_IKG_SOFTRST_SOFTRST_KEY (0x1UL) /*!< The Isolated Key Generation logic and the keys are reset.            */


/* CRACENCORE_IKG_HWCONFIG: HwConfig register. */
  #define CRACENCORE_IKG_HWCONFIG_ResetValue (0xCC4C8312UL) /*!< Reset value of HWCONFIG register.                             */

/* NBSYMKEYS @Bits 0..3 : Number of Symmetric Keys generated. */
  #define CRACENCORE_IKG_HWCONFIG_NBSYMKEYS_Pos (0UL) /*!< Position of NBSYMKEYS field.                                        */
  #define CRACENCORE_IKG_HWCONFIG_NBSYMKEYS_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_NBSYMKEYS_Pos) /*!< Bit mask of NBSYMKEYS
                                                                            field.*/

/* NBPRIVKEYS @Bits 4..7 : Number of Private Keys generated. */
  #define CRACENCORE_IKG_HWCONFIG_NBPRIVKEYS_Pos (4UL) /*!< Position of NBPRIVKEYS field.                                      */
  #define CRACENCORE_IKG_HWCONFIG_NBPRIVKEYS_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_NBPRIVKEYS_Pos) /*!< Bit mask of NBPRIVKEYS
                                                                            field.*/

/* IKGCM @Bit 8 : Countermeasures for IKG operations are implemented when 1. */
  #define CRACENCORE_IKG_HWCONFIG_IKGCM_Pos (8UL)    /*!< Position of IKGCM field.                                             */
  #define CRACENCORE_IKG_HWCONFIG_IKGCM_Msk (0x1UL << CRACENCORE_IKG_HWCONFIG_IKGCM_Pos) /*!< Bit mask of IKGCM field.         */

/* HWHEALTHTEST @Bit 9 : CTR_DRBG health test is implemented when 1. */
  #define CRACENCORE_IKG_HWCONFIG_HWHEALTHTEST_Pos (9UL) /*!< Position of HWHEALTHTEST field.                                  */
  #define CRACENCORE_IKG_HWCONFIG_HWHEALTHTEST_Msk (0x1UL << CRACENCORE_IKG_HWCONFIG_HWHEALTHTEST_Pos) /*!< Bit mask of
                                                                            HWHEALTHTEST field.*/

/* CURVE @Bits 10..11 : ECC curve for IKG (input). */
  #define CRACENCORE_IKG_HWCONFIG_CURVE_Pos (10UL)   /*!< Position of CURVE field.                                             */
  #define CRACENCORE_IKG_HWCONFIG_CURVE_Msk (0x3UL << CRACENCORE_IKG_HWCONFIG_CURVE_Pos) /*!< Bit mask of CURVE field.         */
  #define CRACENCORE_IKG_HWCONFIG_CURVE_Min (0x0UL)  /*!< Min enumerator value of CURVE field.                                 */
  #define CRACENCORE_IKG_HWCONFIG_CURVE_Max (0x2UL)  /*!< Max enumerator value of CURVE field.                                 */
  #define CRACENCORE_IKG_HWCONFIG_CURVE_P256 (0x0UL) /*!< P256.                                                                */
  #define CRACENCORE_IKG_HWCONFIG_CURVE_P384 (0x1UL) /*!< P384.                                                                */
  #define CRACENCORE_IKG_HWCONFIG_CURVE_P521 (0x2UL) /*!< P521.                                                                */

/* DF @Bit 12 : Derivation function is implemented in the CTR_DRBG when 1. */
  #define CRACENCORE_IKG_HWCONFIG_DF_Pos (12UL)      /*!< Position of DF field.                                                */
  #define CRACENCORE_IKG_HWCONFIG_DF_Msk (0x1UL << CRACENCORE_IKG_HWCONFIG_DF_Pos) /*!< Bit mask of DF field.                  */

/* KEYSIZE @Bits 13..15 : AES Key Size support for the AES Core embedded in the CTR_DRBG. */
  #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Pos (13UL) /*!< Position of KEYSIZE field.                                           */
  #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Msk (0x7UL << CRACENCORE_IKG_HWCONFIG_KEYSIZE_Pos) /*!< Bit mask of KEYSIZE field.   */
  #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Min (0x1UL) /*!< Min enumerator value of KEYSIZE field.                              */
  #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_Max (0x4UL) /*!< Max enumerator value of KEYSIZE field.                              */
  #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_AES128 (0x1UL) /*!< supports AES128                                                  */
  #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_AES192 (0x2UL) /*!< supports AES192                                                  */
  #define CRACENCORE_IKG_HWCONFIG_KEYSIZE_AES256 (0x4UL) /*!< supports AES256                                                  */

/* ENTROPYINPUTLENGTH @Bits 16..19 : Value of g_entropy_input_length/32. */
  #define CRACENCORE_IKG_HWCONFIG_ENTROPYINPUTLENGTH_Pos (16UL) /*!< Position of ENTROPYINPUTLENGTH field.                     */
  #define CRACENCORE_IKG_HWCONFIG_ENTROPYINPUTLENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_ENTROPYINPUTLENGTH_Pos) /*!< Bit mask
                                                                            of ENTROPYINPUTLENGTH field.*/

/* NONCELENGTH @Bits 20..23 : Value of g_nonce_length/32. */
  #define CRACENCORE_IKG_HWCONFIG_NONCELENGTH_Pos (20UL) /*!< Position of NONCELENGTH field.                                   */
  #define CRACENCORE_IKG_HWCONFIG_NONCELENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_NONCELENGTH_Pos) /*!< Bit mask of
                                                                            NONCELENGTH field.*/

/* PERSONALIZATIONSTRINGLENGTH @Bits 24..27 : Value of g_personalization_string_length/32. */
  #define CRACENCORE_IKG_HWCONFIG_PERSONALIZATIONSTRINGLENGTH_Pos (24UL) /*!< Position of PERSONALIZATIONSTRINGLENGTH field.   */
  #define CRACENCORE_IKG_HWCONFIG_PERSONALIZATIONSTRINGLENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_PERSONALIZATIONSTRINGLENGTH_Pos)
                                                                            /*!< Bit mask of PERSONALIZATIONSTRINGLENGTH field.*/

/* ADDITIONALINPUTLENGTH @Bits 28..31 : Value of g_additional_input_length/32. */
  #define CRACENCORE_IKG_HWCONFIG_ADDITIONALINPUTLENGTH_Pos (28UL) /*!< Position of ADDITIONALINPUTLENGTH field.               */
  #define CRACENCORE_IKG_HWCONFIG_ADDITIONALINPUTLENGTH_Msk (0xFUL << CRACENCORE_IKG_HWCONFIG_ADDITIONALINPUTLENGTH_Pos) /*!<
                                                                            Bit mask of ADDITIONALINPUTLENGTH field.*/


/* ==================================================== Struct CRACENCORE ==================================================== */
/**
  * @brief CRACENCORE
  */
  typedef struct {                                   /*!< CRACENCORE Structure                                                 */
    __IOM NRF_CRACENCORE_CRYPTMSTRDMA_Type CRYPTMSTRDMA; /*!< (@ 0x00000000) (unspecified)                                     */
    __IM uint32_t RESERVED[240];
    __IOM NRF_CRACENCORE_CRYPTMSTRHW_Type CRYPTMSTRHW; /*!< (@ 0x00000400) (unspecified)                                       */
    __IM uint32_t RESERVED1[761];
    __IOM NRF_CRACENCORE_RNGCONTROL_Type RNGCONTROL; /*!< (@ 0x00001000) (unspecified)                                         */
    __IM uint32_t RESERVED2[976];
    __IOM NRF_CRACENCORE_PK_Type PK;                 /*!< (@ 0x00002000) (unspecified)                                         */
    __IM uint32_t RESERVED3[1006];
    __IOM NRF_CRACENCORE_IKG_Type IKG;               /*!< (@ 0x00003000) (unspecified)                                         */
  } NRF_CRACENCORE_Type;                             /*!< Size = 12336 (0x3030)                                                */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                        CTRLAPPERI                                        ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct CTRLAPPERI_MAILBOX ================================================ */
/**
  * @brief MAILBOX [CTRLAPPERI_MAILBOX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RXDATA;                            /*!< (@ 0x00000000) Data sent from the debugger to the CPU.               */
  __IM  uint32_t  RXSTATUS;                          /*!< (@ 0x00000004) Status to indicate if data sent from the debugger to
                                                                         the CPU has been read.*/
  __IM  uint32_t  RESERVED[30];
  __IOM uint32_t  TXDATA;                            /*!< (@ 0x00000080) Data sent from the CPU to the debugger.               */
  __IM  uint32_t  TXSTATUS;                          /*!< (@ 0x00000084) Status to indicate if data sent from the CPU to the
                                                                         debugger has been read.*/
} NRF_CTRLAPPERI_MAILBOX_Type;                       /*!< Size = 136 (0x088)                                                   */

/* CTRLAPPERI_MAILBOX_RXDATA: Data sent from the debugger to the CPU. */
  #define CTRLAPPERI_MAILBOX_RXDATA_ResetValue (0x00000000UL) /*!< Reset value of RXDATA register.                             */

/* RXDATA @Bits 0..31 : Data received from debugger. */
  #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field.                                            */
  #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA
                                                                            field.*/


/* CTRLAPPERI_MAILBOX_RXSTATUS: Status to indicate if data sent from the debugger to the CPU has been read. */
  #define CTRLAPPERI_MAILBOX_RXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RXSTATUS register.                         */

/* RXSTATUS @Bit 0 : Status of data in register RXDATA. */
  #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field.                                      */
  #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS
                                                                            field.*/
  #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Min (0x0UL) /*!< Min enumerator value of RXSTATUS field.                        */
  #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Max (0x1UL) /*!< Max enumerator value of RXSTATUS field.                        */
  #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data is pending in register RXDATA.               */
  #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data is pending in register RXDATA.                    */


/* CTRLAPPERI_MAILBOX_TXDATA: Data sent from the CPU to the debugger. */
  #define CTRLAPPERI_MAILBOX_TXDATA_ResetValue (0x00000000UL) /*!< Reset value of TXDATA register.                             */

/* TXDATA @Bits 0..31 : Data sent to debugger. */
  #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field.                                            */
  #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA
                                                                            field.*/


/* CTRLAPPERI_MAILBOX_TXSTATUS: Status to indicate if data sent from the CPU to the debugger has been read. */
  #define CTRLAPPERI_MAILBOX_TXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TXSTATUS register.                         */

/* TXSTATUS @Bit 0 : Status of data in register TXDATA. */
  #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field.                                      */
  #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS
                                                                            field.*/
  #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Min (0x0UL) /*!< Min enumerator value of TXSTATUS field.                        */
  #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Max (0x1UL) /*!< Max enumerator value of TXSTATUS field.                        */
  #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data is pending in register TXDATA.               */
  #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data is pending in register TXDATA.                    */



/* ============================================= Struct CTRLAPPERI_ERASEPROTECT ============================================== */
/**
  * @brief ERASEPROTECT [CTRLAPPERI_ERASEPROTECT] (unspecified)
  */
typedef struct {
  __IOM uint32_t  LOCK;                              /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE register
                                                                         from being written until next reset.*/
  __OM  uint32_t  DISABLE;                           /*!< (@ 0x00000004) This register disables the ERASEPROTECT register and
                                                                         performs an ERASEALL operation.*/
} NRF_CTRLAPPERI_ERASEPROTECT_Type;                  /*!< Size = 8 (0x008)                                                     */

/* CTRLAPPERI_ERASEPROTECT_LOCK: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */
  #define CTRLAPPERI_ERASEPROTECT_LOCK_ResetValue (0x00000000UL) /*!< Reset value of LOCK register.                            */

/* LOCK @Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset. */
  #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field.                                             */
  #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field.  */
  #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                               */
  #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                               */
  #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0x0UL) /*!< Register ERASEPROTECT.DISABLE is writeable.                  */
  #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register ERASEPROTECT.DISABLE is read-only.                    */


/* CTRLAPPERI_ERASEPROTECT_DISABLE: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */
  #define CTRLAPPERI_ERASEPROTECT_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of DISABLE register.                      */

/* KEY @Bits 0..31 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on
                     both the CPU and debugger sides. */

  #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field.                                            */
  #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY
                                                                            field.*/


/* ==================================================== Struct CTRLAPPERI ==================================================== */
/**
  * @brief Control access port
  */
  typedef struct {                                   /*!< CTRLAPPERI Structure                                                 */
    __IM uint32_t RESERVED[64];
    __IOM uint32_t EVENTS_RXREADY;                   /*!< (@ 0x00000100) RXSTATUS is changed to DataPending.                   */
    __IOM uint32_t EVENTS_TXDONE;                    /*!< (@ 0x00000104) TXSTATUS is changed to NoDataPending.                 */
    __IM uint32_t RESERVED1[126];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED2[60];
    __IOM NRF_CTRLAPPERI_MAILBOX_Type MAILBOX;       /*!< (@ 0x00000400) (unspecified)                                         */
    __IM uint32_t RESERVED3[30];
    __IOM NRF_CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT; /*!< (@ 0x00000500) (unspecified)                                     */
    __IM uint32_t RESERVED4[6];
    __OM uint32_t RESET;                             /*!< (@ 0x00000520) System reset request.                                 */
  } NRF_CTRLAPPERI_Type;                             /*!< Size = 1316 (0x524)                                                  */

/* CTRLAPPERI_EVENTS_RXREADY: RXSTATUS is changed to DataPending. */
  #define CTRLAPPERI_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register.                     */

/* EVENTS_RXREADY @Bit 0 : RXSTATUS is changed to DataPending. */
  #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field.                            */
  #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of
                                                                            EVENTS_RXREADY field.*/
  #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field.              */
  #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field.              */
  #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated                               */
  #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated                                      */


/* CTRLAPPERI_EVENTS_TXDONE: TXSTATUS is changed to NoDataPending. */
  #define CTRLAPPERI_EVENTS_TXDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDONE register.                       */

/* EVENTS_TXDONE @Bit 0 : TXSTATUS is changed to NoDataPending. */
  #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos (0UL) /*!< Position of EVENTS_TXDONE field.                               */
  #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Msk (0x1UL << CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos) /*!< Bit mask of
                                                                            EVENTS_TXDONE field.*/
  #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDONE field.                 */
  #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDONE field.                 */
  #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_NotGenerated (0x0UL) /*!< Event not generated                                 */
  #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Generated (0x1UL) /*!< Event generated                                        */


/* CTRLAPPERI_INTEN: Enable or disable interrupt */
  #define CTRLAPPERI_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register.                                       */

/* RXREADY @Bit 0 : Enable or disable interrupt for event RXREADY */
  #define CTRLAPPERI_INTEN_RXREADY_Pos (0UL)         /*!< Position of RXREADY field.                                           */
  #define CTRLAPPERI_INTEN_RXREADY_Msk (0x1UL << CTRLAPPERI_INTEN_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
  #define CTRLAPPERI_INTEN_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTEN_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTEN_RXREADY_Disabled (0x0UL)  /*!< Disable                                                              */
  #define CTRLAPPERI_INTEN_RXREADY_Enabled (0x1UL)   /*!< Enable                                                               */

/* TXDONE @Bit 1 : Enable or disable interrupt for event TXDONE */
  #define CTRLAPPERI_INTEN_TXDONE_Pos (1UL)          /*!< Position of TXDONE field.                                            */
  #define CTRLAPPERI_INTEN_TXDONE_Msk (0x1UL << CTRLAPPERI_INTEN_TXDONE_Pos) /*!< Bit mask of TXDONE field.                    */
  #define CTRLAPPERI_INTEN_TXDONE_Min (0x0UL)        /*!< Min enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTEN_TXDONE_Max (0x1UL)        /*!< Max enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTEN_TXDONE_Disabled (0x0UL)   /*!< Disable                                                              */
  #define CTRLAPPERI_INTEN_TXDONE_Enabled (0x1UL)    /*!< Enable                                                               */


/* CTRLAPPERI_INTENSET: Enable interrupt */
  #define CTRLAPPERI_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register.                                 */

/* RXREADY @Bit 0 : Write '1' to enable interrupt for event RXREADY */
  #define CTRLAPPERI_INTENSET_RXREADY_Pos (0UL)      /*!< Position of RXREADY field.                                           */
  #define CTRLAPPERI_INTENSET_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field.           */
  #define CTRLAPPERI_INTENSET_RXREADY_Min (0x0UL)    /*!< Min enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTENSET_RXREADY_Max (0x1UL)    /*!< Max enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTENSET_RXREADY_Set (0x1UL)    /*!< Enable                                                               */
  #define CTRLAPPERI_INTENSET_RXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define CTRLAPPERI_INTENSET_RXREADY_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* TXDONE @Bit 1 : Write '1' to enable interrupt for event TXDONE */
  #define CTRLAPPERI_INTENSET_TXDONE_Pos (1UL)       /*!< Position of TXDONE field.                                            */
  #define CTRLAPPERI_INTENSET_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENSET_TXDONE_Pos) /*!< Bit mask of TXDONE field.              */
  #define CTRLAPPERI_INTENSET_TXDONE_Min (0x0UL)     /*!< Min enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTENSET_TXDONE_Max (0x1UL)     /*!< Max enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTENSET_TXDONE_Set (0x1UL)     /*!< Enable                                                               */
  #define CTRLAPPERI_INTENSET_TXDONE_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define CTRLAPPERI_INTENSET_TXDONE_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* CTRLAPPERI_INTENCLR: Disable interrupt */
  #define CTRLAPPERI_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register.                                 */

/* RXREADY @Bit 0 : Write '1' to disable interrupt for event RXREADY */
  #define CTRLAPPERI_INTENCLR_RXREADY_Pos (0UL)      /*!< Position of RXREADY field.                                           */
  #define CTRLAPPERI_INTENCLR_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field.           */
  #define CTRLAPPERI_INTENCLR_RXREADY_Min (0x0UL)    /*!< Min enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTENCLR_RXREADY_Max (0x1UL)    /*!< Max enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTENCLR_RXREADY_Clear (0x1UL)  /*!< Disable                                                              */
  #define CTRLAPPERI_INTENCLR_RXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define CTRLAPPERI_INTENCLR_RXREADY_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* TXDONE @Bit 1 : Write '1' to disable interrupt for event TXDONE */
  #define CTRLAPPERI_INTENCLR_TXDONE_Pos (1UL)       /*!< Position of TXDONE field.                                            */
  #define CTRLAPPERI_INTENCLR_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENCLR_TXDONE_Pos) /*!< Bit mask of TXDONE field.              */
  #define CTRLAPPERI_INTENCLR_TXDONE_Min (0x0UL)     /*!< Min enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTENCLR_TXDONE_Max (0x1UL)     /*!< Max enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTENCLR_TXDONE_Clear (0x1UL)   /*!< Disable                                                              */
  #define CTRLAPPERI_INTENCLR_TXDONE_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define CTRLAPPERI_INTENCLR_TXDONE_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* CTRLAPPERI_INTPEND: Pending interrupts */
  #define CTRLAPPERI_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register.                                   */

/* RXREADY @Bit 0 : Read pending status of interrupt for event RXREADY */
  #define CTRLAPPERI_INTPEND_RXREADY_Pos (0UL)       /*!< Position of RXREADY field.                                           */
  #define CTRLAPPERI_INTPEND_RXREADY_Msk (0x1UL << CTRLAPPERI_INTPEND_RXREADY_Pos) /*!< Bit mask of RXREADY field.             */
  #define CTRLAPPERI_INTPEND_RXREADY_Min (0x0UL)     /*!< Min enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTPEND_RXREADY_Max (0x1UL)     /*!< Max enumerator value of RXREADY field.                               */
  #define CTRLAPPERI_INTPEND_RXREADY_NotPending (0x0UL) /*!< Read: Not pending                                                 */
  #define CTRLAPPERI_INTPEND_RXREADY_Pending (0x1UL) /*!< Read: Pending                                                        */

/* TXDONE @Bit 1 : Read pending status of interrupt for event TXDONE */
  #define CTRLAPPERI_INTPEND_TXDONE_Pos (1UL)        /*!< Position of TXDONE field.                                            */
  #define CTRLAPPERI_INTPEND_TXDONE_Msk (0x1UL << CTRLAPPERI_INTPEND_TXDONE_Pos) /*!< Bit mask of TXDONE field.                */
  #define CTRLAPPERI_INTPEND_TXDONE_Min (0x0UL)      /*!< Min enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTPEND_TXDONE_Max (0x1UL)      /*!< Max enumerator value of TXDONE field.                                */
  #define CTRLAPPERI_INTPEND_TXDONE_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define CTRLAPPERI_INTPEND_TXDONE_Pending (0x1UL)  /*!< Read: Pending                                                        */


/* CTRLAPPERI_RESET: System reset request. */
  #define CTRLAPPERI_RESET_ResetValue (0x00000000UL) /*!< Reset value of RESET register.                                       */

/* RESET @Bits 0..2 : Reset request */
  #define CTRLAPPERI_RESET_RESET_Pos (0UL)           /*!< Position of RESET field.                                             */
  #define CTRLAPPERI_RESET_RESET_Msk (0x7UL << CTRLAPPERI_RESET_RESET_Pos) /*!< Bit mask of RESET field.                       */
  #define CTRLAPPERI_RESET_RESET_Min (0x0UL)         /*!< Min enumerator value of RESET field.                                 */
  #define CTRLAPPERI_RESET_RESET_Max (0x4UL)         /*!< Max enumerator value of RESET field.                                 */
  #define CTRLAPPERI_RESET_RESET_NoReset (0x0UL)     /*!< No reset is generated                                                */
  #define CTRLAPPERI_RESET_RESET_SoftReset (0x1UL)   /*!< Perform a device soft reset                                          */
  #define CTRLAPPERI_RESET_RESET_HardReset (0x2UL)   /*!< Perform a device hard reset                                          */
  #define CTRLAPPERI_RESET_RESET_PinReset (0x4UL)    /*!< Perform a device pin reset                                           */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           DPPIC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================= Struct DPPIC_TASKS_CHG ================================================== */
/**
  * @brief TASKS_CHG [DPPIC_TASKS_CHG] Channel group tasks
  */
typedef struct {
  __OM  uint32_t  EN;                                /*!< (@ 0x00000000) Enable channel group n                                */
  __OM  uint32_t  DIS;                               /*!< (@ 0x00000004) Disable channel group n                               */
} NRF_DPPIC_TASKS_CHG_Type;                          /*!< Size = 8 (0x008)                                                     */
  #define DPPIC_TASKS_CHG_MaxCount (6UL)             /*!< Size of TASKS_CHG[6] array.                                          */
  #define DPPIC_TASKS_CHG_MaxIndex (5UL)             /*!< Max index of TASKS_CHG[6] array.                                     */
  #define DPPIC_TASKS_CHG_MinIndex (0UL)             /*!< Min index of TASKS_CHG[6] array.                                     */

/* DPPIC_TASKS_CHG_EN: Enable channel group n */
  #define DPPIC_TASKS_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register.                                        */

/* EN @Bit 0 : Enable channel group n */
  #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL)            /*!< Position of EN field.                                                */
  #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field.                            */
  #define DPPIC_TASKS_CHG_EN_EN_Min (0x1UL)          /*!< Min enumerator value of EN field.                                    */
  #define DPPIC_TASKS_CHG_EN_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL)      /*!< Trigger task                                                         */


/* DPPIC_TASKS_CHG_DIS: Disable channel group n */
  #define DPPIC_TASKS_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register.                                      */

/* DIS @Bit 0 : Disable channel group n */
  #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL)          /*!< Position of DIS field.                                               */
  #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field.                       */
  #define DPPIC_TASKS_CHG_DIS_DIS_Min (0x1UL)        /*!< Min enumerator value of DIS field.                                   */
  #define DPPIC_TASKS_CHG_DIS_DIS_Max (0x1UL)        /*!< Max enumerator value of DIS field.                                   */
  #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL)    /*!< Trigger task                                                         */



/* =============================================== Struct DPPIC_SUBSCRIBE_CHG ================================================ */
/**
  * @brief SUBSCRIBE_CHG [DPPIC_SUBSCRIBE_CHG] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  EN;                                /*!< (@ 0x00000000) Subscribe configuration for task CHG[n].EN            */
  __IOM uint32_t  DIS;                               /*!< (@ 0x00000004) Subscribe configuration for task CHG[n].DIS           */
} NRF_DPPIC_SUBSCRIBE_CHG_Type;                      /*!< Size = 8 (0x008)                                                     */
  #define DPPIC_SUBSCRIBE_CHG_MaxCount (6UL)         /*!< Size of SUBSCRIBE_CHG[6] array.                                      */
  #define DPPIC_SUBSCRIBE_CHG_MaxIndex (5UL)         /*!< Max index of SUBSCRIBE_CHG[6] array.                                 */
  #define DPPIC_SUBSCRIBE_CHG_MinIndex (0UL)         /*!< Min index of SUBSCRIBE_CHG[6] array.                                 */

/* DPPIC_SUBSCRIBE_CHG_EN: Subscribe configuration for task CHG[n].EN */
  #define DPPIC_SUBSCRIBE_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register.                                    */

/* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].EN will subscribe to */
  #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field.                    */
  #define DPPIC_SUBSCRIBE_CHG_EN_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define DPPIC_SUBSCRIBE_CHG_EN_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* DPPIC_SUBSCRIBE_CHG_DIS: Subscribe configuration for task CHG[n].DIS */
  #define DPPIC_SUBSCRIBE_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].DIS will subscribe to */
  #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field.                  */
  #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* ====================================================== Struct DPPIC ======================================================= */
/**
  * @brief Distributed programmable peripheral interconnect controller
  */
  typedef struct {                                   /*!< DPPIC Structure                                                      */
    __OM NRF_DPPIC_TASKS_CHG_Type TASKS_CHG[6];      /*!< (@ 0x00000000) Channel group tasks                                   */
    __IM uint32_t RESERVED[20];
    __IOM NRF_DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6]; /*!< (@ 0x00000080) Subscribe configuration for tasks                 */
    __IM uint32_t RESERVED1[276];
    __IOM uint32_t CHEN;                             /*!< (@ 0x00000500) Channel enable register                               */
    __IOM uint32_t CHENSET;                          /*!< (@ 0x00000504) Channel enable set register                           */
    __IOM uint32_t CHENCLR;                          /*!< (@ 0x00000508) Channel enable clear register                         */
    __IM uint32_t RESERVED2[189];
    __IOM uint32_t CHG[6];                           /*!< (@ 0x00000800) Channel group n Note: Writes to this register are
                                                                         ignored if either SUBSCRIBE_CHG[n].EN or
                                                                         SUBSCRIBE_CHG[n].DIS is enabled*/
  } NRF_DPPIC_Type;                                  /*!< Size = 2072 (0x818)                                                  */

/* DPPIC_CHEN: Channel enable register */
  #define DPPIC_CHEN_ResetValue (0x00000000UL)       /*!< Reset value of CHEN register.                                        */

/* CH0 @Bit 0 : Enable or disable channel 0 */
  #define DPPIC_CHEN_CH0_Pos (0UL)                   /*!< Position of CH0 field.                                               */
  #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field.                                         */
  #define DPPIC_CHEN_CH0_Min (0x0UL)                 /*!< Min enumerator value of CH0 field.                                   */
  #define DPPIC_CHEN_CH0_Max (0x1UL)                 /*!< Max enumerator value of CH0 field.                                   */
  #define DPPIC_CHEN_CH0_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH0_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH1 @Bit 1 : Enable or disable channel 1 */
  #define DPPIC_CHEN_CH1_Pos (1UL)                   /*!< Position of CH1 field.                                               */
  #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field.                                         */
  #define DPPIC_CHEN_CH1_Min (0x0UL)                 /*!< Min enumerator value of CH1 field.                                   */
  #define DPPIC_CHEN_CH1_Max (0x1UL)                 /*!< Max enumerator value of CH1 field.                                   */
  #define DPPIC_CHEN_CH1_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH1_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH2 @Bit 2 : Enable or disable channel 2 */
  #define DPPIC_CHEN_CH2_Pos (2UL)                   /*!< Position of CH2 field.                                               */
  #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field.                                         */
  #define DPPIC_CHEN_CH2_Min (0x0UL)                 /*!< Min enumerator value of CH2 field.                                   */
  #define DPPIC_CHEN_CH2_Max (0x1UL)                 /*!< Max enumerator value of CH2 field.                                   */
  #define DPPIC_CHEN_CH2_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH2_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH3 @Bit 3 : Enable or disable channel 3 */
  #define DPPIC_CHEN_CH3_Pos (3UL)                   /*!< Position of CH3 field.                                               */
  #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field.                                         */
  #define DPPIC_CHEN_CH3_Min (0x0UL)                 /*!< Min enumerator value of CH3 field.                                   */
  #define DPPIC_CHEN_CH3_Max (0x1UL)                 /*!< Max enumerator value of CH3 field.                                   */
  #define DPPIC_CHEN_CH3_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH3_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH4 @Bit 4 : Enable or disable channel 4 */
  #define DPPIC_CHEN_CH4_Pos (4UL)                   /*!< Position of CH4 field.                                               */
  #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field.                                         */
  #define DPPIC_CHEN_CH4_Min (0x0UL)                 /*!< Min enumerator value of CH4 field.                                   */
  #define DPPIC_CHEN_CH4_Max (0x1UL)                 /*!< Max enumerator value of CH4 field.                                   */
  #define DPPIC_CHEN_CH4_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH4_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH5 @Bit 5 : Enable or disable channel 5 */
  #define DPPIC_CHEN_CH5_Pos (5UL)                   /*!< Position of CH5 field.                                               */
  #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field.                                         */
  #define DPPIC_CHEN_CH5_Min (0x0UL)                 /*!< Min enumerator value of CH5 field.                                   */
  #define DPPIC_CHEN_CH5_Max (0x1UL)                 /*!< Max enumerator value of CH5 field.                                   */
  #define DPPIC_CHEN_CH5_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH5_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH6 @Bit 6 : Enable or disable channel 6 */
  #define DPPIC_CHEN_CH6_Pos (6UL)                   /*!< Position of CH6 field.                                               */
  #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field.                                         */
  #define DPPIC_CHEN_CH6_Min (0x0UL)                 /*!< Min enumerator value of CH6 field.                                   */
  #define DPPIC_CHEN_CH6_Max (0x1UL)                 /*!< Max enumerator value of CH6 field.                                   */
  #define DPPIC_CHEN_CH6_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH6_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH7 @Bit 7 : Enable or disable channel 7 */
  #define DPPIC_CHEN_CH7_Pos (7UL)                   /*!< Position of CH7 field.                                               */
  #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field.                                         */
  #define DPPIC_CHEN_CH7_Min (0x0UL)                 /*!< Min enumerator value of CH7 field.                                   */
  #define DPPIC_CHEN_CH7_Max (0x1UL)                 /*!< Max enumerator value of CH7 field.                                   */
  #define DPPIC_CHEN_CH7_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH7_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH8 @Bit 8 : Enable or disable channel 8 */
  #define DPPIC_CHEN_CH8_Pos (8UL)                   /*!< Position of CH8 field.                                               */
  #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field.                                         */
  #define DPPIC_CHEN_CH8_Min (0x0UL)                 /*!< Min enumerator value of CH8 field.                                   */
  #define DPPIC_CHEN_CH8_Max (0x1UL)                 /*!< Max enumerator value of CH8 field.                                   */
  #define DPPIC_CHEN_CH8_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH8_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH9 @Bit 9 : Enable or disable channel 9 */
  #define DPPIC_CHEN_CH9_Pos (9UL)                   /*!< Position of CH9 field.                                               */
  #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field.                                         */
  #define DPPIC_CHEN_CH9_Min (0x0UL)                 /*!< Min enumerator value of CH9 field.                                   */
  #define DPPIC_CHEN_CH9_Max (0x1UL)                 /*!< Max enumerator value of CH9 field.                                   */
  #define DPPIC_CHEN_CH9_Disabled (0x0UL)            /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH9_Enabled (0x1UL)             /*!< Enable channel                                                       */

/* CH10 @Bit 10 : Enable or disable channel 10 */
  #define DPPIC_CHEN_CH10_Pos (10UL)                 /*!< Position of CH10 field.                                              */
  #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field.                                      */
  #define DPPIC_CHEN_CH10_Min (0x0UL)                /*!< Min enumerator value of CH10 field.                                  */
  #define DPPIC_CHEN_CH10_Max (0x1UL)                /*!< Max enumerator value of CH10 field.                                  */
  #define DPPIC_CHEN_CH10_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH10_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH11 @Bit 11 : Enable or disable channel 11 */
  #define DPPIC_CHEN_CH11_Pos (11UL)                 /*!< Position of CH11 field.                                              */
  #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field.                                      */
  #define DPPIC_CHEN_CH11_Min (0x0UL)                /*!< Min enumerator value of CH11 field.                                  */
  #define DPPIC_CHEN_CH11_Max (0x1UL)                /*!< Max enumerator value of CH11 field.                                  */
  #define DPPIC_CHEN_CH11_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH11_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH12 @Bit 12 : Enable or disable channel 12 */
  #define DPPIC_CHEN_CH12_Pos (12UL)                 /*!< Position of CH12 field.                                              */
  #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field.                                      */
  #define DPPIC_CHEN_CH12_Min (0x0UL)                /*!< Min enumerator value of CH12 field.                                  */
  #define DPPIC_CHEN_CH12_Max (0x1UL)                /*!< Max enumerator value of CH12 field.                                  */
  #define DPPIC_CHEN_CH12_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH12_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH13 @Bit 13 : Enable or disable channel 13 */
  #define DPPIC_CHEN_CH13_Pos (13UL)                 /*!< Position of CH13 field.                                              */
  #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field.                                      */
  #define DPPIC_CHEN_CH13_Min (0x0UL)                /*!< Min enumerator value of CH13 field.                                  */
  #define DPPIC_CHEN_CH13_Max (0x1UL)                /*!< Max enumerator value of CH13 field.                                  */
  #define DPPIC_CHEN_CH13_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH13_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH14 @Bit 14 : Enable or disable channel 14 */
  #define DPPIC_CHEN_CH14_Pos (14UL)                 /*!< Position of CH14 field.                                              */
  #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field.                                      */
  #define DPPIC_CHEN_CH14_Min (0x0UL)                /*!< Min enumerator value of CH14 field.                                  */
  #define DPPIC_CHEN_CH14_Max (0x1UL)                /*!< Max enumerator value of CH14 field.                                  */
  #define DPPIC_CHEN_CH14_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH14_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH15 @Bit 15 : Enable or disable channel 15 */
  #define DPPIC_CHEN_CH15_Pos (15UL)                 /*!< Position of CH15 field.                                              */
  #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field.                                      */
  #define DPPIC_CHEN_CH15_Min (0x0UL)                /*!< Min enumerator value of CH15 field.                                  */
  #define DPPIC_CHEN_CH15_Max (0x1UL)                /*!< Max enumerator value of CH15 field.                                  */
  #define DPPIC_CHEN_CH15_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH15_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH16 @Bit 16 : Enable or disable channel 16 */
  #define DPPIC_CHEN_CH16_Pos (16UL)                 /*!< Position of CH16 field.                                              */
  #define DPPIC_CHEN_CH16_Msk (0x1UL << DPPIC_CHEN_CH16_Pos) /*!< Bit mask of CH16 field.                                      */
  #define DPPIC_CHEN_CH16_Min (0x0UL)                /*!< Min enumerator value of CH16 field.                                  */
  #define DPPIC_CHEN_CH16_Max (0x1UL)                /*!< Max enumerator value of CH16 field.                                  */
  #define DPPIC_CHEN_CH16_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH16_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH17 @Bit 17 : Enable or disable channel 17 */
  #define DPPIC_CHEN_CH17_Pos (17UL)                 /*!< Position of CH17 field.                                              */
  #define DPPIC_CHEN_CH17_Msk (0x1UL << DPPIC_CHEN_CH17_Pos) /*!< Bit mask of CH17 field.                                      */
  #define DPPIC_CHEN_CH17_Min (0x0UL)                /*!< Min enumerator value of CH17 field.                                  */
  #define DPPIC_CHEN_CH17_Max (0x1UL)                /*!< Max enumerator value of CH17 field.                                  */
  #define DPPIC_CHEN_CH17_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH17_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH18 @Bit 18 : Enable or disable channel 18 */
  #define DPPIC_CHEN_CH18_Pos (18UL)                 /*!< Position of CH18 field.                                              */
  #define DPPIC_CHEN_CH18_Msk (0x1UL << DPPIC_CHEN_CH18_Pos) /*!< Bit mask of CH18 field.                                      */
  #define DPPIC_CHEN_CH18_Min (0x0UL)                /*!< Min enumerator value of CH18 field.                                  */
  #define DPPIC_CHEN_CH18_Max (0x1UL)                /*!< Max enumerator value of CH18 field.                                  */
  #define DPPIC_CHEN_CH18_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH18_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH19 @Bit 19 : Enable or disable channel 19 */
  #define DPPIC_CHEN_CH19_Pos (19UL)                 /*!< Position of CH19 field.                                              */
  #define DPPIC_CHEN_CH19_Msk (0x1UL << DPPIC_CHEN_CH19_Pos) /*!< Bit mask of CH19 field.                                      */
  #define DPPIC_CHEN_CH19_Min (0x0UL)                /*!< Min enumerator value of CH19 field.                                  */
  #define DPPIC_CHEN_CH19_Max (0x1UL)                /*!< Max enumerator value of CH19 field.                                  */
  #define DPPIC_CHEN_CH19_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH19_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH20 @Bit 20 : Enable or disable channel 20 */
  #define DPPIC_CHEN_CH20_Pos (20UL)                 /*!< Position of CH20 field.                                              */
  #define DPPIC_CHEN_CH20_Msk (0x1UL << DPPIC_CHEN_CH20_Pos) /*!< Bit mask of CH20 field.                                      */
  #define DPPIC_CHEN_CH20_Min (0x0UL)                /*!< Min enumerator value of CH20 field.                                  */
  #define DPPIC_CHEN_CH20_Max (0x1UL)                /*!< Max enumerator value of CH20 field.                                  */
  #define DPPIC_CHEN_CH20_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH20_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH21 @Bit 21 : Enable or disable channel 21 */
  #define DPPIC_CHEN_CH21_Pos (21UL)                 /*!< Position of CH21 field.                                              */
  #define DPPIC_CHEN_CH21_Msk (0x1UL << DPPIC_CHEN_CH21_Pos) /*!< Bit mask of CH21 field.                                      */
  #define DPPIC_CHEN_CH21_Min (0x0UL)                /*!< Min enumerator value of CH21 field.                                  */
  #define DPPIC_CHEN_CH21_Max (0x1UL)                /*!< Max enumerator value of CH21 field.                                  */
  #define DPPIC_CHEN_CH21_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH21_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH22 @Bit 22 : Enable or disable channel 22 */
  #define DPPIC_CHEN_CH22_Pos (22UL)                 /*!< Position of CH22 field.                                              */
  #define DPPIC_CHEN_CH22_Msk (0x1UL << DPPIC_CHEN_CH22_Pos) /*!< Bit mask of CH22 field.                                      */
  #define DPPIC_CHEN_CH22_Min (0x0UL)                /*!< Min enumerator value of CH22 field.                                  */
  #define DPPIC_CHEN_CH22_Max (0x1UL)                /*!< Max enumerator value of CH22 field.                                  */
  #define DPPIC_CHEN_CH22_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH22_Enabled (0x1UL)            /*!< Enable channel                                                       */

/* CH23 @Bit 23 : Enable or disable channel 23 */
  #define DPPIC_CHEN_CH23_Pos (23UL)                 /*!< Position of CH23 field.                                              */
  #define DPPIC_CHEN_CH23_Msk (0x1UL << DPPIC_CHEN_CH23_Pos) /*!< Bit mask of CH23 field.                                      */
  #define DPPIC_CHEN_CH23_Min (0x0UL)                /*!< Min enumerator value of CH23 field.                                  */
  #define DPPIC_CHEN_CH23_Max (0x1UL)                /*!< Max enumerator value of CH23 field.                                  */
  #define DPPIC_CHEN_CH23_Disabled (0x0UL)           /*!< Disable channel                                                      */
  #define DPPIC_CHEN_CH23_Enabled (0x1UL)            /*!< Enable channel                                                       */


/* DPPIC_CHENSET: Channel enable set register */
  #define DPPIC_CHENSET_ResetValue (0x00000000UL)    /*!< Reset value of CHENSET register.                                     */

/* CH0 @Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH0_Pos (0UL)                /*!< Position of CH0 field.                                               */
  #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field.                                   */
  #define DPPIC_CHENSET_CH0_Min (0x0UL)              /*!< Min enumerator value of CH0 field.                                   */
  #define DPPIC_CHENSET_CH0_Max (0x1UL)              /*!< Max enumerator value of CH0 field.                                   */
  #define DPPIC_CHENSET_CH0_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH0_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH0_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH1 @Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH1_Pos (1UL)                /*!< Position of CH1 field.                                               */
  #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field.                                   */
  #define DPPIC_CHENSET_CH1_Min (0x0UL)              /*!< Min enumerator value of CH1 field.                                   */
  #define DPPIC_CHENSET_CH1_Max (0x1UL)              /*!< Max enumerator value of CH1 field.                                   */
  #define DPPIC_CHENSET_CH1_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH1_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH1_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH2 @Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH2_Pos (2UL)                /*!< Position of CH2 field.                                               */
  #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field.                                   */
  #define DPPIC_CHENSET_CH2_Min (0x0UL)              /*!< Min enumerator value of CH2 field.                                   */
  #define DPPIC_CHENSET_CH2_Max (0x1UL)              /*!< Max enumerator value of CH2 field.                                   */
  #define DPPIC_CHENSET_CH2_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH2_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH2_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH3 @Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH3_Pos (3UL)                /*!< Position of CH3 field.                                               */
  #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field.                                   */
  #define DPPIC_CHENSET_CH3_Min (0x0UL)              /*!< Min enumerator value of CH3 field.                                   */
  #define DPPIC_CHENSET_CH3_Max (0x1UL)              /*!< Max enumerator value of CH3 field.                                   */
  #define DPPIC_CHENSET_CH3_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH3_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH3_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH4 @Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH4_Pos (4UL)                /*!< Position of CH4 field.                                               */
  #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field.                                   */
  #define DPPIC_CHENSET_CH4_Min (0x0UL)              /*!< Min enumerator value of CH4 field.                                   */
  #define DPPIC_CHENSET_CH4_Max (0x1UL)              /*!< Max enumerator value of CH4 field.                                   */
  #define DPPIC_CHENSET_CH4_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH4_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH4_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH5 @Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH5_Pos (5UL)                /*!< Position of CH5 field.                                               */
  #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field.                                   */
  #define DPPIC_CHENSET_CH5_Min (0x0UL)              /*!< Min enumerator value of CH5 field.                                   */
  #define DPPIC_CHENSET_CH5_Max (0x1UL)              /*!< Max enumerator value of CH5 field.                                   */
  #define DPPIC_CHENSET_CH5_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH5_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH5_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH6 @Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH6_Pos (6UL)                /*!< Position of CH6 field.                                               */
  #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field.                                   */
  #define DPPIC_CHENSET_CH6_Min (0x0UL)              /*!< Min enumerator value of CH6 field.                                   */
  #define DPPIC_CHENSET_CH6_Max (0x1UL)              /*!< Max enumerator value of CH6 field.                                   */
  #define DPPIC_CHENSET_CH6_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH6_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH6_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH7 @Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH7_Pos (7UL)                /*!< Position of CH7 field.                                               */
  #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field.                                   */
  #define DPPIC_CHENSET_CH7_Min (0x0UL)              /*!< Min enumerator value of CH7 field.                                   */
  #define DPPIC_CHENSET_CH7_Max (0x1UL)              /*!< Max enumerator value of CH7 field.                                   */
  #define DPPIC_CHENSET_CH7_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH7_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH7_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH8 @Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH8_Pos (8UL)                /*!< Position of CH8 field.                                               */
  #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field.                                   */
  #define DPPIC_CHENSET_CH8_Min (0x0UL)              /*!< Min enumerator value of CH8 field.                                   */
  #define DPPIC_CHENSET_CH8_Max (0x1UL)              /*!< Max enumerator value of CH8 field.                                   */
  #define DPPIC_CHENSET_CH8_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH8_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH8_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH9 @Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH9_Pos (9UL)                /*!< Position of CH9 field.                                               */
  #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field.                                   */
  #define DPPIC_CHENSET_CH9_Min (0x0UL)              /*!< Min enumerator value of CH9 field.                                   */
  #define DPPIC_CHENSET_CH9_Max (0x1UL)              /*!< Max enumerator value of CH9 field.                                   */
  #define DPPIC_CHENSET_CH9_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH9_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH9_Set (0x1UL)              /*!< Write: Enable channel                                                */

/* CH10 @Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH10_Pos (10UL)              /*!< Position of CH10 field.                                              */
  #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field.                                */
  #define DPPIC_CHENSET_CH10_Min (0x0UL)             /*!< Min enumerator value of CH10 field.                                  */
  #define DPPIC_CHENSET_CH10_Max (0x1UL)             /*!< Max enumerator value of CH10 field.                                  */
  #define DPPIC_CHENSET_CH10_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH10_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH10_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH11 @Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH11_Pos (11UL)              /*!< Position of CH11 field.                                              */
  #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field.                                */
  #define DPPIC_CHENSET_CH11_Min (0x0UL)             /*!< Min enumerator value of CH11 field.                                  */
  #define DPPIC_CHENSET_CH11_Max (0x1UL)             /*!< Max enumerator value of CH11 field.                                  */
  #define DPPIC_CHENSET_CH11_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH11_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH11_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH12 @Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH12_Pos (12UL)              /*!< Position of CH12 field.                                              */
  #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field.                                */
  #define DPPIC_CHENSET_CH12_Min (0x0UL)             /*!< Min enumerator value of CH12 field.                                  */
  #define DPPIC_CHENSET_CH12_Max (0x1UL)             /*!< Max enumerator value of CH12 field.                                  */
  #define DPPIC_CHENSET_CH12_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH12_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH12_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH13 @Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH13_Pos (13UL)              /*!< Position of CH13 field.                                              */
  #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field.                                */
  #define DPPIC_CHENSET_CH13_Min (0x0UL)             /*!< Min enumerator value of CH13 field.                                  */
  #define DPPIC_CHENSET_CH13_Max (0x1UL)             /*!< Max enumerator value of CH13 field.                                  */
  #define DPPIC_CHENSET_CH13_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH13_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH13_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH14 @Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH14_Pos (14UL)              /*!< Position of CH14 field.                                              */
  #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field.                                */
  #define DPPIC_CHENSET_CH14_Min (0x0UL)             /*!< Min enumerator value of CH14 field.                                  */
  #define DPPIC_CHENSET_CH14_Max (0x1UL)             /*!< Max enumerator value of CH14 field.                                  */
  #define DPPIC_CHENSET_CH14_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH14_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH14_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH15 @Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH15_Pos (15UL)              /*!< Position of CH15 field.                                              */
  #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field.                                */
  #define DPPIC_CHENSET_CH15_Min (0x0UL)             /*!< Min enumerator value of CH15 field.                                  */
  #define DPPIC_CHENSET_CH15_Max (0x1UL)             /*!< Max enumerator value of CH15 field.                                  */
  #define DPPIC_CHENSET_CH15_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH15_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH15_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH16 @Bit 16 : Channel 16 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH16_Pos (16UL)              /*!< Position of CH16 field.                                              */
  #define DPPIC_CHENSET_CH16_Msk (0x1UL << DPPIC_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field.                                */
  #define DPPIC_CHENSET_CH16_Min (0x0UL)             /*!< Min enumerator value of CH16 field.                                  */
  #define DPPIC_CHENSET_CH16_Max (0x1UL)             /*!< Max enumerator value of CH16 field.                                  */
  #define DPPIC_CHENSET_CH16_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH16_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH16_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH17 @Bit 17 : Channel 17 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH17_Pos (17UL)              /*!< Position of CH17 field.                                              */
  #define DPPIC_CHENSET_CH17_Msk (0x1UL << DPPIC_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field.                                */
  #define DPPIC_CHENSET_CH17_Min (0x0UL)             /*!< Min enumerator value of CH17 field.                                  */
  #define DPPIC_CHENSET_CH17_Max (0x1UL)             /*!< Max enumerator value of CH17 field.                                  */
  #define DPPIC_CHENSET_CH17_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH17_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH17_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH18 @Bit 18 : Channel 18 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH18_Pos (18UL)              /*!< Position of CH18 field.                                              */
  #define DPPIC_CHENSET_CH18_Msk (0x1UL << DPPIC_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field.                                */
  #define DPPIC_CHENSET_CH18_Min (0x0UL)             /*!< Min enumerator value of CH18 field.                                  */
  #define DPPIC_CHENSET_CH18_Max (0x1UL)             /*!< Max enumerator value of CH18 field.                                  */
  #define DPPIC_CHENSET_CH18_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH18_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH18_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH19 @Bit 19 : Channel 19 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH19_Pos (19UL)              /*!< Position of CH19 field.                                              */
  #define DPPIC_CHENSET_CH19_Msk (0x1UL << DPPIC_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field.                                */
  #define DPPIC_CHENSET_CH19_Min (0x0UL)             /*!< Min enumerator value of CH19 field.                                  */
  #define DPPIC_CHENSET_CH19_Max (0x1UL)             /*!< Max enumerator value of CH19 field.                                  */
  #define DPPIC_CHENSET_CH19_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH19_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH19_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH20 @Bit 20 : Channel 20 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH20_Pos (20UL)              /*!< Position of CH20 field.                                              */
  #define DPPIC_CHENSET_CH20_Msk (0x1UL << DPPIC_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field.                                */
  #define DPPIC_CHENSET_CH20_Min (0x0UL)             /*!< Min enumerator value of CH20 field.                                  */
  #define DPPIC_CHENSET_CH20_Max (0x1UL)             /*!< Max enumerator value of CH20 field.                                  */
  #define DPPIC_CHENSET_CH20_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH20_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH20_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH21 @Bit 21 : Channel 21 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH21_Pos (21UL)              /*!< Position of CH21 field.                                              */
  #define DPPIC_CHENSET_CH21_Msk (0x1UL << DPPIC_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field.                                */
  #define DPPIC_CHENSET_CH21_Min (0x0UL)             /*!< Min enumerator value of CH21 field.                                  */
  #define DPPIC_CHENSET_CH21_Max (0x1UL)             /*!< Max enumerator value of CH21 field.                                  */
  #define DPPIC_CHENSET_CH21_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH21_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH21_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH22 @Bit 22 : Channel 22 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH22_Pos (22UL)              /*!< Position of CH22 field.                                              */
  #define DPPIC_CHENSET_CH22_Msk (0x1UL << DPPIC_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field.                                */
  #define DPPIC_CHENSET_CH22_Min (0x0UL)             /*!< Min enumerator value of CH22 field.                                  */
  #define DPPIC_CHENSET_CH22_Max (0x1UL)             /*!< Max enumerator value of CH22 field.                                  */
  #define DPPIC_CHENSET_CH22_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH22_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH22_Set (0x1UL)             /*!< Write: Enable channel                                                */

/* CH23 @Bit 23 : Channel 23 enable set register. Writing 0 has no effect. */
  #define DPPIC_CHENSET_CH23_Pos (23UL)              /*!< Position of CH23 field.                                              */
  #define DPPIC_CHENSET_CH23_Msk (0x1UL << DPPIC_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field.                                */
  #define DPPIC_CHENSET_CH23_Min (0x0UL)             /*!< Min enumerator value of CH23 field.                                  */
  #define DPPIC_CHENSET_CH23_Max (0x1UL)             /*!< Max enumerator value of CH23 field.                                  */
  #define DPPIC_CHENSET_CH23_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENSET_CH23_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENSET_CH23_Set (0x1UL)             /*!< Write: Enable channel                                                */


/* DPPIC_CHENCLR: Channel enable clear register */
  #define DPPIC_CHENCLR_ResetValue (0x00000000UL)    /*!< Reset value of CHENCLR register.                                     */

/* CH0 @Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH0_Pos (0UL)                /*!< Position of CH0 field.                                               */
  #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field.                                   */
  #define DPPIC_CHENCLR_CH0_Min (0x0UL)              /*!< Min enumerator value of CH0 field.                                   */
  #define DPPIC_CHENCLR_CH0_Max (0x1UL)              /*!< Max enumerator value of CH0 field.                                   */
  #define DPPIC_CHENCLR_CH0_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH0_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH0_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH1 @Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH1_Pos (1UL)                /*!< Position of CH1 field.                                               */
  #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field.                                   */
  #define DPPIC_CHENCLR_CH1_Min (0x0UL)              /*!< Min enumerator value of CH1 field.                                   */
  #define DPPIC_CHENCLR_CH1_Max (0x1UL)              /*!< Max enumerator value of CH1 field.                                   */
  #define DPPIC_CHENCLR_CH1_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH1_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH1_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH2 @Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH2_Pos (2UL)                /*!< Position of CH2 field.                                               */
  #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field.                                   */
  #define DPPIC_CHENCLR_CH2_Min (0x0UL)              /*!< Min enumerator value of CH2 field.                                   */
  #define DPPIC_CHENCLR_CH2_Max (0x1UL)              /*!< Max enumerator value of CH2 field.                                   */
  #define DPPIC_CHENCLR_CH2_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH2_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH2_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH3 @Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH3_Pos (3UL)                /*!< Position of CH3 field.                                               */
  #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field.                                   */
  #define DPPIC_CHENCLR_CH3_Min (0x0UL)              /*!< Min enumerator value of CH3 field.                                   */
  #define DPPIC_CHENCLR_CH3_Max (0x1UL)              /*!< Max enumerator value of CH3 field.                                   */
  #define DPPIC_CHENCLR_CH3_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH3_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH3_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH4 @Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH4_Pos (4UL)                /*!< Position of CH4 field.                                               */
  #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field.                                   */
  #define DPPIC_CHENCLR_CH4_Min (0x0UL)              /*!< Min enumerator value of CH4 field.                                   */
  #define DPPIC_CHENCLR_CH4_Max (0x1UL)              /*!< Max enumerator value of CH4 field.                                   */
  #define DPPIC_CHENCLR_CH4_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH4_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH4_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH5 @Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH5_Pos (5UL)                /*!< Position of CH5 field.                                               */
  #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field.                                   */
  #define DPPIC_CHENCLR_CH5_Min (0x0UL)              /*!< Min enumerator value of CH5 field.                                   */
  #define DPPIC_CHENCLR_CH5_Max (0x1UL)              /*!< Max enumerator value of CH5 field.                                   */
  #define DPPIC_CHENCLR_CH5_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH5_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH5_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH6 @Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH6_Pos (6UL)                /*!< Position of CH6 field.                                               */
  #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field.                                   */
  #define DPPIC_CHENCLR_CH6_Min (0x0UL)              /*!< Min enumerator value of CH6 field.                                   */
  #define DPPIC_CHENCLR_CH6_Max (0x1UL)              /*!< Max enumerator value of CH6 field.                                   */
  #define DPPIC_CHENCLR_CH6_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH6_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH6_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH7 @Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH7_Pos (7UL)                /*!< Position of CH7 field.                                               */
  #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field.                                   */
  #define DPPIC_CHENCLR_CH7_Min (0x0UL)              /*!< Min enumerator value of CH7 field.                                   */
  #define DPPIC_CHENCLR_CH7_Max (0x1UL)              /*!< Max enumerator value of CH7 field.                                   */
  #define DPPIC_CHENCLR_CH7_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH7_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH7_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH8 @Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH8_Pos (8UL)                /*!< Position of CH8 field.                                               */
  #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field.                                   */
  #define DPPIC_CHENCLR_CH8_Min (0x0UL)              /*!< Min enumerator value of CH8 field.                                   */
  #define DPPIC_CHENCLR_CH8_Max (0x1UL)              /*!< Max enumerator value of CH8 field.                                   */
  #define DPPIC_CHENCLR_CH8_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH8_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH8_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH9 @Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH9_Pos (9UL)                /*!< Position of CH9 field.                                               */
  #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field.                                   */
  #define DPPIC_CHENCLR_CH9_Min (0x0UL)              /*!< Min enumerator value of CH9 field.                                   */
  #define DPPIC_CHENCLR_CH9_Max (0x1UL)              /*!< Max enumerator value of CH9 field.                                   */
  #define DPPIC_CHENCLR_CH9_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH9_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH9_Clear (0x1UL)            /*!< Write: Disable channel                                               */

/* CH10 @Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH10_Pos (10UL)              /*!< Position of CH10 field.                                              */
  #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field.                                */
  #define DPPIC_CHENCLR_CH10_Min (0x0UL)             /*!< Min enumerator value of CH10 field.                                  */
  #define DPPIC_CHENCLR_CH10_Max (0x1UL)             /*!< Max enumerator value of CH10 field.                                  */
  #define DPPIC_CHENCLR_CH10_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH10_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH10_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH11 @Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH11_Pos (11UL)              /*!< Position of CH11 field.                                              */
  #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field.                                */
  #define DPPIC_CHENCLR_CH11_Min (0x0UL)             /*!< Min enumerator value of CH11 field.                                  */
  #define DPPIC_CHENCLR_CH11_Max (0x1UL)             /*!< Max enumerator value of CH11 field.                                  */
  #define DPPIC_CHENCLR_CH11_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH11_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH11_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH12 @Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH12_Pos (12UL)              /*!< Position of CH12 field.                                              */
  #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field.                                */
  #define DPPIC_CHENCLR_CH12_Min (0x0UL)             /*!< Min enumerator value of CH12 field.                                  */
  #define DPPIC_CHENCLR_CH12_Max (0x1UL)             /*!< Max enumerator value of CH12 field.                                  */
  #define DPPIC_CHENCLR_CH12_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH12_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH12_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH13 @Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH13_Pos (13UL)              /*!< Position of CH13 field.                                              */
  #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field.                                */
  #define DPPIC_CHENCLR_CH13_Min (0x0UL)             /*!< Min enumerator value of CH13 field.                                  */
  #define DPPIC_CHENCLR_CH13_Max (0x1UL)             /*!< Max enumerator value of CH13 field.                                  */
  #define DPPIC_CHENCLR_CH13_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH13_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH13_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH14 @Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH14_Pos (14UL)              /*!< Position of CH14 field.                                              */
  #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field.                                */
  #define DPPIC_CHENCLR_CH14_Min (0x0UL)             /*!< Min enumerator value of CH14 field.                                  */
  #define DPPIC_CHENCLR_CH14_Max (0x1UL)             /*!< Max enumerator value of CH14 field.                                  */
  #define DPPIC_CHENCLR_CH14_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH14_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH14_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH15 @Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH15_Pos (15UL)              /*!< Position of CH15 field.                                              */
  #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field.                                */
  #define DPPIC_CHENCLR_CH15_Min (0x0UL)             /*!< Min enumerator value of CH15 field.                                  */
  #define DPPIC_CHENCLR_CH15_Max (0x1UL)             /*!< Max enumerator value of CH15 field.                                  */
  #define DPPIC_CHENCLR_CH15_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH15_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH15_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH16 @Bit 16 : Channel 16 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH16_Pos (16UL)              /*!< Position of CH16 field.                                              */
  #define DPPIC_CHENCLR_CH16_Msk (0x1UL << DPPIC_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field.                                */
  #define DPPIC_CHENCLR_CH16_Min (0x0UL)             /*!< Min enumerator value of CH16 field.                                  */
  #define DPPIC_CHENCLR_CH16_Max (0x1UL)             /*!< Max enumerator value of CH16 field.                                  */
  #define DPPIC_CHENCLR_CH16_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH16_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH16_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH17 @Bit 17 : Channel 17 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH17_Pos (17UL)              /*!< Position of CH17 field.                                              */
  #define DPPIC_CHENCLR_CH17_Msk (0x1UL << DPPIC_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field.                                */
  #define DPPIC_CHENCLR_CH17_Min (0x0UL)             /*!< Min enumerator value of CH17 field.                                  */
  #define DPPIC_CHENCLR_CH17_Max (0x1UL)             /*!< Max enumerator value of CH17 field.                                  */
  #define DPPIC_CHENCLR_CH17_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH17_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH17_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH18 @Bit 18 : Channel 18 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH18_Pos (18UL)              /*!< Position of CH18 field.                                              */
  #define DPPIC_CHENCLR_CH18_Msk (0x1UL << DPPIC_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field.                                */
  #define DPPIC_CHENCLR_CH18_Min (0x0UL)             /*!< Min enumerator value of CH18 field.                                  */
  #define DPPIC_CHENCLR_CH18_Max (0x1UL)             /*!< Max enumerator value of CH18 field.                                  */
  #define DPPIC_CHENCLR_CH18_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH18_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH18_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH19 @Bit 19 : Channel 19 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH19_Pos (19UL)              /*!< Position of CH19 field.                                              */
  #define DPPIC_CHENCLR_CH19_Msk (0x1UL << DPPIC_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field.                                */
  #define DPPIC_CHENCLR_CH19_Min (0x0UL)             /*!< Min enumerator value of CH19 field.                                  */
  #define DPPIC_CHENCLR_CH19_Max (0x1UL)             /*!< Max enumerator value of CH19 field.                                  */
  #define DPPIC_CHENCLR_CH19_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH19_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH19_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH20 @Bit 20 : Channel 20 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH20_Pos (20UL)              /*!< Position of CH20 field.                                              */
  #define DPPIC_CHENCLR_CH20_Msk (0x1UL << DPPIC_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field.                                */
  #define DPPIC_CHENCLR_CH20_Min (0x0UL)             /*!< Min enumerator value of CH20 field.                                  */
  #define DPPIC_CHENCLR_CH20_Max (0x1UL)             /*!< Max enumerator value of CH20 field.                                  */
  #define DPPIC_CHENCLR_CH20_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH20_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH20_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH21 @Bit 21 : Channel 21 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH21_Pos (21UL)              /*!< Position of CH21 field.                                              */
  #define DPPIC_CHENCLR_CH21_Msk (0x1UL << DPPIC_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field.                                */
  #define DPPIC_CHENCLR_CH21_Min (0x0UL)             /*!< Min enumerator value of CH21 field.                                  */
  #define DPPIC_CHENCLR_CH21_Max (0x1UL)             /*!< Max enumerator value of CH21 field.                                  */
  #define DPPIC_CHENCLR_CH21_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH21_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH21_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH22 @Bit 22 : Channel 22 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH22_Pos (22UL)              /*!< Position of CH22 field.                                              */
  #define DPPIC_CHENCLR_CH22_Msk (0x1UL << DPPIC_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field.                                */
  #define DPPIC_CHENCLR_CH22_Min (0x0UL)             /*!< Min enumerator value of CH22 field.                                  */
  #define DPPIC_CHENCLR_CH22_Max (0x1UL)             /*!< Max enumerator value of CH22 field.                                  */
  #define DPPIC_CHENCLR_CH22_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH22_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH22_Clear (0x1UL)           /*!< Write: Disable channel                                               */

/* CH23 @Bit 23 : Channel 23 enable clear register. Writing 0 has no effect. */
  #define DPPIC_CHENCLR_CH23_Pos (23UL)              /*!< Position of CH23 field.                                              */
  #define DPPIC_CHENCLR_CH23_Msk (0x1UL << DPPIC_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field.                                */
  #define DPPIC_CHENCLR_CH23_Min (0x0UL)             /*!< Min enumerator value of CH23 field.                                  */
  #define DPPIC_CHENCLR_CH23_Max (0x1UL)             /*!< Max enumerator value of CH23 field.                                  */
  #define DPPIC_CHENCLR_CH23_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
  #define DPPIC_CHENCLR_CH23_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
  #define DPPIC_CHENCLR_CH23_Clear (0x1UL)           /*!< Write: Disable channel                                               */


/* DPPIC_CHG: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is
               enabled */

  #define DPPIC_CHG_MaxCount (6UL)                   /*!< Max size of CHG[6] array.                                            */
  #define DPPIC_CHG_MaxIndex (5UL)                   /*!< Max index of CHG[6] array.                                           */
  #define DPPIC_CHG_MinIndex (0UL)                   /*!< Min index of CHG[6] array.                                           */
  #define DPPIC_CHG_ResetValue (0x00000000UL)        /*!< Reset value of CHG[6] register.                                      */

/* CH0 @Bit 0 : Include or exclude channel 0 */
  #define DPPIC_CHG_CH0_Pos (0UL)                    /*!< Position of CH0 field.                                               */
  #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field.                                           */
  #define DPPIC_CHG_CH0_Min (0x0UL)                  /*!< Min enumerator value of CH0 field.                                   */
  #define DPPIC_CHG_CH0_Max (0x1UL)                  /*!< Max enumerator value of CH0 field.                                   */
  #define DPPIC_CHG_CH0_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH0_Included (0x1UL)             /*!< Include                                                              */

/* CH1 @Bit 1 : Include or exclude channel 1 */
  #define DPPIC_CHG_CH1_Pos (1UL)                    /*!< Position of CH1 field.                                               */
  #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field.                                           */
  #define DPPIC_CHG_CH1_Min (0x0UL)                  /*!< Min enumerator value of CH1 field.                                   */
  #define DPPIC_CHG_CH1_Max (0x1UL)                  /*!< Max enumerator value of CH1 field.                                   */
  #define DPPIC_CHG_CH1_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH1_Included (0x1UL)             /*!< Include                                                              */

/* CH2 @Bit 2 : Include or exclude channel 2 */
  #define DPPIC_CHG_CH2_Pos (2UL)                    /*!< Position of CH2 field.                                               */
  #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field.                                           */
  #define DPPIC_CHG_CH2_Min (0x0UL)                  /*!< Min enumerator value of CH2 field.                                   */
  #define DPPIC_CHG_CH2_Max (0x1UL)                  /*!< Max enumerator value of CH2 field.                                   */
  #define DPPIC_CHG_CH2_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH2_Included (0x1UL)             /*!< Include                                                              */

/* CH3 @Bit 3 : Include or exclude channel 3 */
  #define DPPIC_CHG_CH3_Pos (3UL)                    /*!< Position of CH3 field.                                               */
  #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field.                                           */
  #define DPPIC_CHG_CH3_Min (0x0UL)                  /*!< Min enumerator value of CH3 field.                                   */
  #define DPPIC_CHG_CH3_Max (0x1UL)                  /*!< Max enumerator value of CH3 field.                                   */
  #define DPPIC_CHG_CH3_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH3_Included (0x1UL)             /*!< Include                                                              */

/* CH4 @Bit 4 : Include or exclude channel 4 */
  #define DPPIC_CHG_CH4_Pos (4UL)                    /*!< Position of CH4 field.                                               */
  #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field.                                           */
  #define DPPIC_CHG_CH4_Min (0x0UL)                  /*!< Min enumerator value of CH4 field.                                   */
  #define DPPIC_CHG_CH4_Max (0x1UL)                  /*!< Max enumerator value of CH4 field.                                   */
  #define DPPIC_CHG_CH4_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH4_Included (0x1UL)             /*!< Include                                                              */

/* CH5 @Bit 5 : Include or exclude channel 5 */
  #define DPPIC_CHG_CH5_Pos (5UL)                    /*!< Position of CH5 field.                                               */
  #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field.                                           */
  #define DPPIC_CHG_CH5_Min (0x0UL)                  /*!< Min enumerator value of CH5 field.                                   */
  #define DPPIC_CHG_CH5_Max (0x1UL)                  /*!< Max enumerator value of CH5 field.                                   */
  #define DPPIC_CHG_CH5_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH5_Included (0x1UL)             /*!< Include                                                              */

/* CH6 @Bit 6 : Include or exclude channel 6 */
  #define DPPIC_CHG_CH6_Pos (6UL)                    /*!< Position of CH6 field.                                               */
  #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field.                                           */
  #define DPPIC_CHG_CH6_Min (0x0UL)                  /*!< Min enumerator value of CH6 field.                                   */
  #define DPPIC_CHG_CH6_Max (0x1UL)                  /*!< Max enumerator value of CH6 field.                                   */
  #define DPPIC_CHG_CH6_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH6_Included (0x1UL)             /*!< Include                                                              */

/* CH7 @Bit 7 : Include or exclude channel 7 */
  #define DPPIC_CHG_CH7_Pos (7UL)                    /*!< Position of CH7 field.                                               */
  #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field.                                           */
  #define DPPIC_CHG_CH7_Min (0x0UL)                  /*!< Min enumerator value of CH7 field.                                   */
  #define DPPIC_CHG_CH7_Max (0x1UL)                  /*!< Max enumerator value of CH7 field.                                   */
  #define DPPIC_CHG_CH7_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH7_Included (0x1UL)             /*!< Include                                                              */

/* CH8 @Bit 8 : Include or exclude channel 8 */
  #define DPPIC_CHG_CH8_Pos (8UL)                    /*!< Position of CH8 field.                                               */
  #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field.                                           */
  #define DPPIC_CHG_CH8_Min (0x0UL)                  /*!< Min enumerator value of CH8 field.                                   */
  #define DPPIC_CHG_CH8_Max (0x1UL)                  /*!< Max enumerator value of CH8 field.                                   */
  #define DPPIC_CHG_CH8_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH8_Included (0x1UL)             /*!< Include                                                              */

/* CH9 @Bit 9 : Include or exclude channel 9 */
  #define DPPIC_CHG_CH9_Pos (9UL)                    /*!< Position of CH9 field.                                               */
  #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field.                                           */
  #define DPPIC_CHG_CH9_Min (0x0UL)                  /*!< Min enumerator value of CH9 field.                                   */
  #define DPPIC_CHG_CH9_Max (0x1UL)                  /*!< Max enumerator value of CH9 field.                                   */
  #define DPPIC_CHG_CH9_Excluded (0x0UL)             /*!< Exclude                                                              */
  #define DPPIC_CHG_CH9_Included (0x1UL)             /*!< Include                                                              */

/* CH10 @Bit 10 : Include or exclude channel 10 */
  #define DPPIC_CHG_CH10_Pos (10UL)                  /*!< Position of CH10 field.                                              */
  #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field.                                        */
  #define DPPIC_CHG_CH10_Min (0x0UL)                 /*!< Min enumerator value of CH10 field.                                  */
  #define DPPIC_CHG_CH10_Max (0x1UL)                 /*!< Max enumerator value of CH10 field.                                  */
  #define DPPIC_CHG_CH10_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH10_Included (0x1UL)            /*!< Include                                                              */

/* CH11 @Bit 11 : Include or exclude channel 11 */
  #define DPPIC_CHG_CH11_Pos (11UL)                  /*!< Position of CH11 field.                                              */
  #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field.                                        */
  #define DPPIC_CHG_CH11_Min (0x0UL)                 /*!< Min enumerator value of CH11 field.                                  */
  #define DPPIC_CHG_CH11_Max (0x1UL)                 /*!< Max enumerator value of CH11 field.                                  */
  #define DPPIC_CHG_CH11_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH11_Included (0x1UL)            /*!< Include                                                              */

/* CH12 @Bit 12 : Include or exclude channel 12 */
  #define DPPIC_CHG_CH12_Pos (12UL)                  /*!< Position of CH12 field.                                              */
  #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field.                                        */
  #define DPPIC_CHG_CH12_Min (0x0UL)                 /*!< Min enumerator value of CH12 field.                                  */
  #define DPPIC_CHG_CH12_Max (0x1UL)                 /*!< Max enumerator value of CH12 field.                                  */
  #define DPPIC_CHG_CH12_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH12_Included (0x1UL)            /*!< Include                                                              */

/* CH13 @Bit 13 : Include or exclude channel 13 */
  #define DPPIC_CHG_CH13_Pos (13UL)                  /*!< Position of CH13 field.                                              */
  #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field.                                        */
  #define DPPIC_CHG_CH13_Min (0x0UL)                 /*!< Min enumerator value of CH13 field.                                  */
  #define DPPIC_CHG_CH13_Max (0x1UL)                 /*!< Max enumerator value of CH13 field.                                  */
  #define DPPIC_CHG_CH13_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH13_Included (0x1UL)            /*!< Include                                                              */

/* CH14 @Bit 14 : Include or exclude channel 14 */
  #define DPPIC_CHG_CH14_Pos (14UL)                  /*!< Position of CH14 field.                                              */
  #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field.                                        */
  #define DPPIC_CHG_CH14_Min (0x0UL)                 /*!< Min enumerator value of CH14 field.                                  */
  #define DPPIC_CHG_CH14_Max (0x1UL)                 /*!< Max enumerator value of CH14 field.                                  */
  #define DPPIC_CHG_CH14_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH14_Included (0x1UL)            /*!< Include                                                              */

/* CH15 @Bit 15 : Include or exclude channel 15 */
  #define DPPIC_CHG_CH15_Pos (15UL)                  /*!< Position of CH15 field.                                              */
  #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field.                                        */
  #define DPPIC_CHG_CH15_Min (0x0UL)                 /*!< Min enumerator value of CH15 field.                                  */
  #define DPPIC_CHG_CH15_Max (0x1UL)                 /*!< Max enumerator value of CH15 field.                                  */
  #define DPPIC_CHG_CH15_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH15_Included (0x1UL)            /*!< Include                                                              */

/* CH16 @Bit 16 : Include or exclude channel 16 */
  #define DPPIC_CHG_CH16_Pos (16UL)                  /*!< Position of CH16 field.                                              */
  #define DPPIC_CHG_CH16_Msk (0x1UL << DPPIC_CHG_CH16_Pos) /*!< Bit mask of CH16 field.                                        */
  #define DPPIC_CHG_CH16_Min (0x0UL)                 /*!< Min enumerator value of CH16 field.                                  */
  #define DPPIC_CHG_CH16_Max (0x1UL)                 /*!< Max enumerator value of CH16 field.                                  */
  #define DPPIC_CHG_CH16_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH16_Included (0x1UL)            /*!< Include                                                              */

/* CH17 @Bit 17 : Include or exclude channel 17 */
  #define DPPIC_CHG_CH17_Pos (17UL)                  /*!< Position of CH17 field.                                              */
  #define DPPIC_CHG_CH17_Msk (0x1UL << DPPIC_CHG_CH17_Pos) /*!< Bit mask of CH17 field.                                        */
  #define DPPIC_CHG_CH17_Min (0x0UL)                 /*!< Min enumerator value of CH17 field.                                  */
  #define DPPIC_CHG_CH17_Max (0x1UL)                 /*!< Max enumerator value of CH17 field.                                  */
  #define DPPIC_CHG_CH17_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH17_Included (0x1UL)            /*!< Include                                                              */

/* CH18 @Bit 18 : Include or exclude channel 18 */
  #define DPPIC_CHG_CH18_Pos (18UL)                  /*!< Position of CH18 field.                                              */
  #define DPPIC_CHG_CH18_Msk (0x1UL << DPPIC_CHG_CH18_Pos) /*!< Bit mask of CH18 field.                                        */
  #define DPPIC_CHG_CH18_Min (0x0UL)                 /*!< Min enumerator value of CH18 field.                                  */
  #define DPPIC_CHG_CH18_Max (0x1UL)                 /*!< Max enumerator value of CH18 field.                                  */
  #define DPPIC_CHG_CH18_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH18_Included (0x1UL)            /*!< Include                                                              */

/* CH19 @Bit 19 : Include or exclude channel 19 */
  #define DPPIC_CHG_CH19_Pos (19UL)                  /*!< Position of CH19 field.                                              */
  #define DPPIC_CHG_CH19_Msk (0x1UL << DPPIC_CHG_CH19_Pos) /*!< Bit mask of CH19 field.                                        */
  #define DPPIC_CHG_CH19_Min (0x0UL)                 /*!< Min enumerator value of CH19 field.                                  */
  #define DPPIC_CHG_CH19_Max (0x1UL)                 /*!< Max enumerator value of CH19 field.                                  */
  #define DPPIC_CHG_CH19_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH19_Included (0x1UL)            /*!< Include                                                              */

/* CH20 @Bit 20 : Include or exclude channel 20 */
  #define DPPIC_CHG_CH20_Pos (20UL)                  /*!< Position of CH20 field.                                              */
  #define DPPIC_CHG_CH20_Msk (0x1UL << DPPIC_CHG_CH20_Pos) /*!< Bit mask of CH20 field.                                        */
  #define DPPIC_CHG_CH20_Min (0x0UL)                 /*!< Min enumerator value of CH20 field.                                  */
  #define DPPIC_CHG_CH20_Max (0x1UL)                 /*!< Max enumerator value of CH20 field.                                  */
  #define DPPIC_CHG_CH20_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH20_Included (0x1UL)            /*!< Include                                                              */

/* CH21 @Bit 21 : Include or exclude channel 21 */
  #define DPPIC_CHG_CH21_Pos (21UL)                  /*!< Position of CH21 field.                                              */
  #define DPPIC_CHG_CH21_Msk (0x1UL << DPPIC_CHG_CH21_Pos) /*!< Bit mask of CH21 field.                                        */
  #define DPPIC_CHG_CH21_Min (0x0UL)                 /*!< Min enumerator value of CH21 field.                                  */
  #define DPPIC_CHG_CH21_Max (0x1UL)                 /*!< Max enumerator value of CH21 field.                                  */
  #define DPPIC_CHG_CH21_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH21_Included (0x1UL)            /*!< Include                                                              */

/* CH22 @Bit 22 : Include or exclude channel 22 */
  #define DPPIC_CHG_CH22_Pos (22UL)                  /*!< Position of CH22 field.                                              */
  #define DPPIC_CHG_CH22_Msk (0x1UL << DPPIC_CHG_CH22_Pos) /*!< Bit mask of CH22 field.                                        */
  #define DPPIC_CHG_CH22_Min (0x0UL)                 /*!< Min enumerator value of CH22 field.                                  */
  #define DPPIC_CHG_CH22_Max (0x1UL)                 /*!< Max enumerator value of CH22 field.                                  */
  #define DPPIC_CHG_CH22_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH22_Included (0x1UL)            /*!< Include                                                              */

/* CH23 @Bit 23 : Include or exclude channel 23 */
  #define DPPIC_CHG_CH23_Pos (23UL)                  /*!< Position of CH23 field.                                              */
  #define DPPIC_CHG_CH23_Msk (0x1UL << DPPIC_CHG_CH23_Pos) /*!< Bit mask of CH23 field.                                        */
  #define DPPIC_CHG_CH23_Min (0x0UL)                 /*!< Min enumerator value of CH23 field.                                  */
  #define DPPIC_CHG_CH23_Max (0x1UL)                 /*!< Max enumerator value of CH23 field.                                  */
  #define DPPIC_CHG_CH23_Excluded (0x0UL)            /*!< Exclude                                                              */
  #define DPPIC_CHG_CH23_Included (0x1UL)            /*!< Include                                                              */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            ECB                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ===================================================== Struct ECB_KEY ====================================================== */
/**
  * @brief KEY [ECB_KEY] (unspecified)
  */
typedef struct {
  __OM  uint32_t  VALUE[4];                          /*!< (@ 0x00000000) 128-bit AES key                                       */
} NRF_ECB_KEY_Type;                                  /*!< Size = 16 (0x010)                                                    */

/* ECB_KEY_VALUE: 128-bit AES key */
  #define ECB_KEY_VALUE_MaxCount (4UL)               /*!< Max size of VALUE[4] array.                                          */
  #define ECB_KEY_VALUE_MaxIndex (3UL)               /*!< Max index of VALUE[4] array.                                         */
  #define ECB_KEY_VALUE_MinIndex (0UL)               /*!< Min index of VALUE[4] array.                                         */
  #define ECB_KEY_VALUE_ResetValue (0x00000000UL)    /*!< Reset value of VALUE[4] register.                                    */

/* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(n+1))-1 : (32*n) */
  #define ECB_KEY_VALUE_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
  #define ECB_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << ECB_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field.                      */



/* ====================================================== Struct ECB_IN ====================================================== */
/**
  * @brief IN [ECB_IN] IN EasyDMA channel
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Input pointer                                         */
} NRF_ECB_IN_Type;                                   /*!< Size = 4 (0x004)                                                     */

/* ECB_IN_PTR: Input pointer */
  #define ECB_IN_PTR_ResetValue (0x00000000UL)       /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Points to a job list containing unencrypted ECB data structure */
  #define ECB_IN_PTR_PTR_Pos (0UL)                   /*!< Position of PTR field.                                               */
  #define ECB_IN_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                  */



/* ===================================================== Struct ECB_OUT ====================================================== */
/**
  * @brief OUT [ECB_OUT] OUT EasyDMA channel
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Output pointer Points to a job list containing
                                                                         encrypted ECB data structure*/
} NRF_ECB_OUT_Type;                                  /*!< Size = 4 (0x004)                                                     */

/* ECB_OUT_PTR: Output pointer Points to a job list containing encrypted ECB data structure */
  #define ECB_OUT_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Output pointer */
  #define ECB_OUT_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
  #define ECB_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */


/* ======================================================= Struct ECB ======================================================== */
/**
  * @brief AES ECB Mode Encryption
  */
  typedef struct {                                   /*!< ECB Structure                                                        */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start ECB block encrypt                               */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Abort a possible executing ECB operation              */
    __IM uint32_t RESERVED[30];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED1[30];
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000100) ECB block encrypt complete                            */
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOP task or due
                                                                         to an error*/
    __IM uint32_t RESERVED2[30];
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000180) Publish configuration for event END                   */
    __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x00000184) Publish configuration for event ERROR                 */
    __IM uint32_t RESERVED3[95];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED4[61];
    __IM uint32_t ERRORSTATUS;                       /*!< (@ 0x00000400) Error status                                          */
    __IM uint32_t RESERVED5[67];
    __IOM NRF_ECB_KEY_Type KEY;                      /*!< (@ 0x00000510) (unspecified)                                         */
    __IM uint32_t RESERVED6[4];
    __IOM NRF_ECB_IN_Type IN;                        /*!< (@ 0x00000530) IN EasyDMA channel                                    */
    __IM uint32_t RESERVED7;
    __IOM NRF_ECB_OUT_Type OUT;                      /*!< (@ 0x00000538) OUT EasyDMA channel                                   */
  } NRF_ECB_Type;                                    /*!< Size = 1340 (0x53C)                                                  */

/* ECB_TASKS_START: Start ECB block encrypt */
  #define ECB_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start ECB block encrypt */
  #define ECB_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
  #define ECB_TASKS_START_TASKS_START_Msk (0x1UL << ECB_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
  #define ECB_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
  #define ECB_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
  #define ECB_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */


/* ECB_TASKS_STOP: Abort a possible executing ECB operation */
  #define ECB_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Abort a possible executing ECB operation */
  #define ECB_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
  #define ECB_TASKS_STOP_TASKS_STOP_Msk (0x1UL << ECB_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
  #define ECB_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
  #define ECB_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
  #define ECB_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* ECB_SUBSCRIBE_START: Subscribe configuration for task START */
  #define ECB_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define ECB_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define ECB_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define ECB_SUBSCRIBE_START_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define ECB_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define ECB_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define ECB_SUBSCRIBE_START_EN_Msk (0x1UL << ECB_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
  #define ECB_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define ECB_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define ECB_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define ECB_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* ECB_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define ECB_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define ECB_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define ECB_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define ECB_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define ECB_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define ECB_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define ECB_SUBSCRIBE_STOP_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
  #define ECB_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define ECB_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define ECB_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
  #define ECB_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */


/* ECB_EVENTS_END: ECB block encrypt complete */
  #define ECB_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : ECB block encrypt complete */
  #define ECB_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
  #define ECB_EVENTS_END_EVENTS_END_Msk (0x1UL << ECB_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
  #define ECB_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
  #define ECB_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
  #define ECB_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
  #define ECB_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */


/* ECB_EVENTS_ERROR: ECB block encrypt aborted because of a STOP task or due to an error */
  #define ECB_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                                */

/* EVENTS_ERROR @Bit 0 : ECB block encrypt aborted because of a STOP task or due to an error */
  #define ECB_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)    /*!< Position of EVENTS_ERROR field.                                      */
  #define ECB_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << ECB_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.  */
  #define ECB_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL)  /*!< Min enumerator value of EVENTS_ERROR field.                          */
  #define ECB_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL)  /*!< Max enumerator value of EVENTS_ERROR field.                          */
  #define ECB_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define ECB_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                 */


/* ECB_PUBLISH_END: Publish configuration for event END */
  #define ECB_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define ECB_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
  #define ECB_PUBLISH_END_CHIDX_Msk (0xFFUL << ECB_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
  #define ECB_PUBLISH_END_CHIDX_Min (0x00UL)         /*!< Min value of CHIDX field.                                            */
  #define ECB_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define ECB_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
  #define ECB_PUBLISH_END_EN_Msk (0x1UL << ECB_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
  #define ECB_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
  #define ECB_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
  #define ECB_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
  #define ECB_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */


/* ECB_PUBLISH_ERROR: Publish configuration for event ERROR */
  #define ECB_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
  #define ECB_PUBLISH_ERROR_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define ECB_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define ECB_PUBLISH_ERROR_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define ECB_PUBLISH_ERROR_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define ECB_PUBLISH_ERROR_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define ECB_PUBLISH_ERROR_EN_Msk (0x1UL << ECB_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                              */
  #define ECB_PUBLISH_ERROR_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define ECB_PUBLISH_ERROR_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define ECB_PUBLISH_ERROR_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define ECB_PUBLISH_ERROR_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* ECB_INTENSET: Enable interrupt */
  #define ECB_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* END @Bit 0 : Write '1' to enable interrupt for event END */
  #define ECB_INTENSET_END_Pos (0UL)                 /*!< Position of END field.                                               */
  #define ECB_INTENSET_END_Msk (0x1UL << ECB_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
  #define ECB_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define ECB_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define ECB_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
  #define ECB_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define ECB_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* ERROR @Bit 1 : Write '1' to enable interrupt for event ERROR */
  #define ECB_INTENSET_ERROR_Pos (1UL)               /*!< Position of ERROR field.                                             */
  #define ECB_INTENSET_ERROR_Msk (0x1UL << ECB_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
  #define ECB_INTENSET_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
  #define ECB_INTENSET_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
  #define ECB_INTENSET_ERROR_Set (0x1UL)             /*!< Enable                                                               */
  #define ECB_INTENSET_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define ECB_INTENSET_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */


/* ECB_INTENCLR: Disable interrupt */
  #define ECB_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* END @Bit 0 : Write '1' to disable interrupt for event END */
  #define ECB_INTENCLR_END_Pos (0UL)                 /*!< Position of END field.                                               */
  #define ECB_INTENCLR_END_Msk (0x1UL << ECB_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
  #define ECB_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define ECB_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define ECB_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
  #define ECB_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define ECB_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* ERROR @Bit 1 : Write '1' to disable interrupt for event ERROR */
  #define ECB_INTENCLR_ERROR_Pos (1UL)               /*!< Position of ERROR field.                                             */
  #define ECB_INTENCLR_ERROR_Msk (0x1UL << ECB_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
  #define ECB_INTENCLR_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
  #define ECB_INTENCLR_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
  #define ECB_INTENCLR_ERROR_Clear (0x1UL)           /*!< Disable                                                              */
  #define ECB_INTENCLR_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define ECB_INTENCLR_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */


/* ECB_ERRORSTATUS: Error status */
  #define ECB_ERRORSTATUS_ResetValue (0x00000000UL)  /*!< Reset value of ERRORSTATUS register.                                 */

/* ERRORSTATUS @Bits 0..2 : Error status when the ERROR event is generated */
  #define ECB_ERRORSTATUS_ERRORSTATUS_Pos (0UL)      /*!< Position of ERRORSTATUS field.                                       */
  #define ECB_ERRORSTATUS_ERRORSTATUS_Msk (0x7UL << ECB_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field.       */
  #define ECB_ERRORSTATUS_ERRORSTATUS_Min (0x0UL)    /*!< Min enumerator value of ERRORSTATUS field.                           */
  #define ECB_ERRORSTATUS_ERRORSTATUS_Max (0x4UL)    /*!< Max enumerator value of ERRORSTATUS field.                           */
  #define ECB_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred                                             */
  #define ECB_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before data structure was read.     */
  #define ECB_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd (0x2UL) /*!< End of OUTPTR job list before data structure was read.   */
  #define ECB_ERRORSTATUS_ERRORSTATUS_EncryptionTooSlow (0x3UL) /*!< Encryption aborted due to higher priority peripheral
                                                                     requesting or using the AES module.*/
  #define ECB_ERRORSTATUS_ERRORSTATUS_Aborted (0x3UL) /*!< Encryption aborted due to higher priority peripheral requesting or
                                                           using the AES module.*/
  #define ECB_ERRORSTATUS_ERRORSTATUS_DmaError (0x4UL) /*!< Bus error during DMA access.                                       */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            EGU                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct EGU ======================================================== */
/**
  * @brief Event generator unit
  */
  typedef struct {                                   /*!< EGU Structure                                                        */
    __OM uint32_t TASKS_TRIGGER[16];                 /*!< (@ 0x00000000) Trigger n for triggering the corresponding TRIGGERED[n]
                                                                         event*/
    __IM uint32_t RESERVED[16];
    __IOM uint32_t SUBSCRIBE_TRIGGER[16];            /*!< (@ 0x00000080) Subscribe configuration for task TRIGGER[n]           */
    __IM uint32_t RESERVED1[16];
    __IOM uint32_t EVENTS_TRIGGERED[16];             /*!< (@ 0x00000100) Event number n generated by triggering the
                                                                         corresponding TRIGGER[n] task*/
    __IM uint32_t RESERVED2[16];
    __IOM uint32_t PUBLISH_TRIGGERED[16];            /*!< (@ 0x00000180) Publish configuration for event TRIGGERED[n]          */
    __IM uint32_t RESERVED3[80];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
  } NRF_EGU_Type;                                    /*!< Size = 780 (0x30C)                                                   */

/* EGU_TASKS_TRIGGER: Trigger n for triggering the corresponding TRIGGERED[n] event */
  #define EGU_TASKS_TRIGGER_MaxCount (16UL)          /*!< Max size of TASKS_TRIGGER[16] array.                                 */
  #define EGU_TASKS_TRIGGER_MaxIndex (15UL)          /*!< Max index of TASKS_TRIGGER[16] array.                                */
  #define EGU_TASKS_TRIGGER_MinIndex (0UL)           /*!< Min index of TASKS_TRIGGER[16] array.                                */
  #define EGU_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[16] register.                          */

/* TASKS_TRIGGER @Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
  #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL)  /*!< Position of TASKS_TRIGGER field.                                     */
  #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER
                                                                            field.*/
  #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field.                        */
  #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field.                        */
  #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task                                                    */


/* EGU_SUBSCRIBE_TRIGGER: Subscribe configuration for task TRIGGER[n] */
  #define EGU_SUBSCRIBE_TRIGGER_MaxCount (16UL)      /*!< Max size of SUBSCRIBE_TRIGGER[16] array.                             */
  #define EGU_SUBSCRIBE_TRIGGER_MaxIndex (15UL)      /*!< Max index of SUBSCRIBE_TRIGGER[16] array.                            */
  #define EGU_SUBSCRIBE_TRIGGER_MinIndex (0UL)       /*!< Min index of SUBSCRIBE_TRIGGER[16] array.                            */
  #define EGU_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[16] register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that task TRIGGER[n] will subscribe to */
  #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field.                      */
  #define EGU_SUBSCRIBE_TRIGGER_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define EGU_SUBSCRIBE_TRIGGER_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* EGU_EVENTS_TRIGGERED: Event number n generated by triggering the corresponding TRIGGER[n] task */
  #define EGU_EVENTS_TRIGGERED_MaxCount (16UL)       /*!< Max size of EVENTS_TRIGGERED[16] array.                              */
  #define EGU_EVENTS_TRIGGERED_MaxIndex (15UL)       /*!< Max index of EVENTS_TRIGGERED[16] array.                             */
  #define EGU_EVENTS_TRIGGERED_MinIndex (0UL)        /*!< Min index of EVENTS_TRIGGERED[16] array.                             */
  #define EGU_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[16] register.                    */

/* EVENTS_TRIGGERED @Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
  #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field.                             */
  #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of
                                                                            EVENTS_TRIGGERED field.*/
  #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field.               */
  #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field.               */
  #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated                                         */


/* EGU_PUBLISH_TRIGGERED: Publish configuration for event TRIGGERED[n] */
  #define EGU_PUBLISH_TRIGGERED_MaxCount (16UL)      /*!< Max size of PUBLISH_TRIGGERED[16] array.                             */
  #define EGU_PUBLISH_TRIGGERED_MaxIndex (15UL)      /*!< Max index of PUBLISH_TRIGGERED[16] array.                            */
  #define EGU_PUBLISH_TRIGGERED_MinIndex (0UL)       /*!< Min index of PUBLISH_TRIGGERED[16] array.                            */
  #define EGU_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[16] register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that event TRIGGERED[n] will publish to */
  #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define EGU_PUBLISH_TRIGGERED_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define EGU_PUBLISH_TRIGGERED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field.                      */
  #define EGU_PUBLISH_TRIGGERED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define EGU_PUBLISH_TRIGGERED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* EGU_INTEN: Enable or disable interrupt */
  #define EGU_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */

/* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
  #define EGU_INTEN_TRIGGERED0_Pos (0UL)             /*!< Position of TRIGGERED0 field.                                        */
  #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                      */
  #define EGU_INTEN_TRIGGERED0_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED0 field.                            */
  #define EGU_INTEN_TRIGGERED0_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED0 field.                            */
  #define EGU_INTEN_TRIGGERED0_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED0_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
  #define EGU_INTEN_TRIGGERED1_Pos (1UL)             /*!< Position of TRIGGERED1 field.                                        */
  #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                      */
  #define EGU_INTEN_TRIGGERED1_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED1 field.                            */
  #define EGU_INTEN_TRIGGERED1_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED1 field.                            */
  #define EGU_INTEN_TRIGGERED1_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED1_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
  #define EGU_INTEN_TRIGGERED2_Pos (2UL)             /*!< Position of TRIGGERED2 field.                                        */
  #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                      */
  #define EGU_INTEN_TRIGGERED2_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED2 field.                            */
  #define EGU_INTEN_TRIGGERED2_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED2 field.                            */
  #define EGU_INTEN_TRIGGERED2_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED2_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
  #define EGU_INTEN_TRIGGERED3_Pos (3UL)             /*!< Position of TRIGGERED3 field.                                        */
  #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                      */
  #define EGU_INTEN_TRIGGERED3_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED3 field.                            */
  #define EGU_INTEN_TRIGGERED3_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED3 field.                            */
  #define EGU_INTEN_TRIGGERED3_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED3_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
  #define EGU_INTEN_TRIGGERED4_Pos (4UL)             /*!< Position of TRIGGERED4 field.                                        */
  #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                      */
  #define EGU_INTEN_TRIGGERED4_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED4 field.                            */
  #define EGU_INTEN_TRIGGERED4_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED4 field.                            */
  #define EGU_INTEN_TRIGGERED4_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED4_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
  #define EGU_INTEN_TRIGGERED5_Pos (5UL)             /*!< Position of TRIGGERED5 field.                                        */
  #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                      */
  #define EGU_INTEN_TRIGGERED5_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED5 field.                            */
  #define EGU_INTEN_TRIGGERED5_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED5 field.                            */
  #define EGU_INTEN_TRIGGERED5_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED5_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
  #define EGU_INTEN_TRIGGERED6_Pos (6UL)             /*!< Position of TRIGGERED6 field.                                        */
  #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                      */
  #define EGU_INTEN_TRIGGERED6_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED6 field.                            */
  #define EGU_INTEN_TRIGGERED6_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED6 field.                            */
  #define EGU_INTEN_TRIGGERED6_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED6_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
  #define EGU_INTEN_TRIGGERED7_Pos (7UL)             /*!< Position of TRIGGERED7 field.                                        */
  #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                      */
  #define EGU_INTEN_TRIGGERED7_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED7 field.                            */
  #define EGU_INTEN_TRIGGERED7_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED7 field.                            */
  #define EGU_INTEN_TRIGGERED7_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED7_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
  #define EGU_INTEN_TRIGGERED8_Pos (8UL)             /*!< Position of TRIGGERED8 field.                                        */
  #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                      */
  #define EGU_INTEN_TRIGGERED8_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED8 field.                            */
  #define EGU_INTEN_TRIGGERED8_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED8 field.                            */
  #define EGU_INTEN_TRIGGERED8_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED8_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
  #define EGU_INTEN_TRIGGERED9_Pos (9UL)             /*!< Position of TRIGGERED9 field.                                        */
  #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                      */
  #define EGU_INTEN_TRIGGERED9_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED9 field.                            */
  #define EGU_INTEN_TRIGGERED9_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED9 field.                            */
  #define EGU_INTEN_TRIGGERED9_Disabled (0x0UL)      /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED9_Enabled (0x1UL)       /*!< Enable                                                               */

/* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
  #define EGU_INTEN_TRIGGERED10_Pos (10UL)           /*!< Position of TRIGGERED10 field.                                       */
  #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.                   */
  #define EGU_INTEN_TRIGGERED10_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED10 field.                           */
  #define EGU_INTEN_TRIGGERED10_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED10 field.                           */
  #define EGU_INTEN_TRIGGERED10_Disabled (0x0UL)     /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED10_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
  #define EGU_INTEN_TRIGGERED11_Pos (11UL)           /*!< Position of TRIGGERED11 field.                                       */
  #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.                   */
  #define EGU_INTEN_TRIGGERED11_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED11 field.                           */
  #define EGU_INTEN_TRIGGERED11_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED11 field.                           */
  #define EGU_INTEN_TRIGGERED11_Disabled (0x0UL)     /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED11_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
  #define EGU_INTEN_TRIGGERED12_Pos (12UL)           /*!< Position of TRIGGERED12 field.                                       */
  #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.                   */
  #define EGU_INTEN_TRIGGERED12_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED12 field.                           */
  #define EGU_INTEN_TRIGGERED12_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED12 field.                           */
  #define EGU_INTEN_TRIGGERED12_Disabled (0x0UL)     /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED12_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
  #define EGU_INTEN_TRIGGERED13_Pos (13UL)           /*!< Position of TRIGGERED13 field.                                       */
  #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.                   */
  #define EGU_INTEN_TRIGGERED13_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED13 field.                           */
  #define EGU_INTEN_TRIGGERED13_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED13 field.                           */
  #define EGU_INTEN_TRIGGERED13_Disabled (0x0UL)     /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED13_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
  #define EGU_INTEN_TRIGGERED14_Pos (14UL)           /*!< Position of TRIGGERED14 field.                                       */
  #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.                   */
  #define EGU_INTEN_TRIGGERED14_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED14 field.                           */
  #define EGU_INTEN_TRIGGERED14_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED14 field.                           */
  #define EGU_INTEN_TRIGGERED14_Disabled (0x0UL)     /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED14_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
  #define EGU_INTEN_TRIGGERED15_Pos (15UL)           /*!< Position of TRIGGERED15 field.                                       */
  #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.                   */
  #define EGU_INTEN_TRIGGERED15_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED15 field.                           */
  #define EGU_INTEN_TRIGGERED15_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED15 field.                           */
  #define EGU_INTEN_TRIGGERED15_Disabled (0x0UL)     /*!< Disable                                                              */
  #define EGU_INTEN_TRIGGERED15_Enabled (0x1UL)      /*!< Enable                                                               */


/* EGU_INTENSET: Enable interrupt */
  #define EGU_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
  #define EGU_INTENSET_TRIGGERED0_Pos (0UL)          /*!< Position of TRIGGERED0 field.                                        */
  #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                */
  #define EGU_INTENSET_TRIGGERED0_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED0 field.                            */
  #define EGU_INTENSET_TRIGGERED0_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED0 field.                            */
  #define EGU_INTENSET_TRIGGERED0_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
  #define EGU_INTENSET_TRIGGERED1_Pos (1UL)          /*!< Position of TRIGGERED1 field.                                        */
  #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                */
  #define EGU_INTENSET_TRIGGERED1_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED1 field.                            */
  #define EGU_INTENSET_TRIGGERED1_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED1 field.                            */
  #define EGU_INTENSET_TRIGGERED1_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
  #define EGU_INTENSET_TRIGGERED2_Pos (2UL)          /*!< Position of TRIGGERED2 field.                                        */
  #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                */
  #define EGU_INTENSET_TRIGGERED2_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED2 field.                            */
  #define EGU_INTENSET_TRIGGERED2_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED2 field.                            */
  #define EGU_INTENSET_TRIGGERED2_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
  #define EGU_INTENSET_TRIGGERED3_Pos (3UL)          /*!< Position of TRIGGERED3 field.                                        */
  #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                */
  #define EGU_INTENSET_TRIGGERED3_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED3 field.                            */
  #define EGU_INTENSET_TRIGGERED3_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED3 field.                            */
  #define EGU_INTENSET_TRIGGERED3_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
  #define EGU_INTENSET_TRIGGERED4_Pos (4UL)          /*!< Position of TRIGGERED4 field.                                        */
  #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                */
  #define EGU_INTENSET_TRIGGERED4_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED4 field.                            */
  #define EGU_INTENSET_TRIGGERED4_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED4 field.                            */
  #define EGU_INTENSET_TRIGGERED4_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
  #define EGU_INTENSET_TRIGGERED5_Pos (5UL)          /*!< Position of TRIGGERED5 field.                                        */
  #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                */
  #define EGU_INTENSET_TRIGGERED5_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED5 field.                            */
  #define EGU_INTENSET_TRIGGERED5_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED5 field.                            */
  #define EGU_INTENSET_TRIGGERED5_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
  #define EGU_INTENSET_TRIGGERED6_Pos (6UL)          /*!< Position of TRIGGERED6 field.                                        */
  #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                */
  #define EGU_INTENSET_TRIGGERED6_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED6 field.                            */
  #define EGU_INTENSET_TRIGGERED6_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED6 field.                            */
  #define EGU_INTENSET_TRIGGERED6_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
  #define EGU_INTENSET_TRIGGERED7_Pos (7UL)          /*!< Position of TRIGGERED7 field.                                        */
  #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                */
  #define EGU_INTENSET_TRIGGERED7_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED7 field.                            */
  #define EGU_INTENSET_TRIGGERED7_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED7 field.                            */
  #define EGU_INTENSET_TRIGGERED7_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
  #define EGU_INTENSET_TRIGGERED8_Pos (8UL)          /*!< Position of TRIGGERED8 field.                                        */
  #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                */
  #define EGU_INTENSET_TRIGGERED8_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED8 field.                            */
  #define EGU_INTENSET_TRIGGERED8_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED8 field.                            */
  #define EGU_INTENSET_TRIGGERED8_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
  #define EGU_INTENSET_TRIGGERED9_Pos (9UL)          /*!< Position of TRIGGERED9 field.                                        */
  #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                */
  #define EGU_INTENSET_TRIGGERED9_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED9 field.                            */
  #define EGU_INTENSET_TRIGGERED9_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED9 field.                            */
  #define EGU_INTENSET_TRIGGERED9_Set (0x1UL)        /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
  #define EGU_INTENSET_TRIGGERED10_Pos (10UL)        /*!< Position of TRIGGERED10 field.                                       */
  #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.             */
  #define EGU_INTENSET_TRIGGERED10_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED10 field.                           */
  #define EGU_INTENSET_TRIGGERED10_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED10 field.                           */
  #define EGU_INTENSET_TRIGGERED10_Set (0x1UL)       /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
  #define EGU_INTENSET_TRIGGERED11_Pos (11UL)        /*!< Position of TRIGGERED11 field.                                       */
  #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.             */
  #define EGU_INTENSET_TRIGGERED11_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED11 field.                           */
  #define EGU_INTENSET_TRIGGERED11_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED11 field.                           */
  #define EGU_INTENSET_TRIGGERED11_Set (0x1UL)       /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
  #define EGU_INTENSET_TRIGGERED12_Pos (12UL)        /*!< Position of TRIGGERED12 field.                                       */
  #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.             */
  #define EGU_INTENSET_TRIGGERED12_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED12 field.                           */
  #define EGU_INTENSET_TRIGGERED12_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED12 field.                           */
  #define EGU_INTENSET_TRIGGERED12_Set (0x1UL)       /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
  #define EGU_INTENSET_TRIGGERED13_Pos (13UL)        /*!< Position of TRIGGERED13 field.                                       */
  #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.             */
  #define EGU_INTENSET_TRIGGERED13_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED13 field.                           */
  #define EGU_INTENSET_TRIGGERED13_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED13 field.                           */
  #define EGU_INTENSET_TRIGGERED13_Set (0x1UL)       /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
  #define EGU_INTENSET_TRIGGERED14_Pos (14UL)        /*!< Position of TRIGGERED14 field.                                       */
  #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.             */
  #define EGU_INTENSET_TRIGGERED14_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED14 field.                           */
  #define EGU_INTENSET_TRIGGERED14_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED14 field.                           */
  #define EGU_INTENSET_TRIGGERED14_Set (0x1UL)       /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
  #define EGU_INTENSET_TRIGGERED15_Pos (15UL)        /*!< Position of TRIGGERED15 field.                                       */
  #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.             */
  #define EGU_INTENSET_TRIGGERED15_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED15 field.                           */
  #define EGU_INTENSET_TRIGGERED15_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED15 field.                           */
  #define EGU_INTENSET_TRIGGERED15_Set (0x1UL)       /*!< Enable                                                               */
  #define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* EGU_INTENCLR: Disable interrupt */
  #define EGU_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
  #define EGU_INTENCLR_TRIGGERED0_Pos (0UL)          /*!< Position of TRIGGERED0 field.                                        */
  #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                */
  #define EGU_INTENCLR_TRIGGERED0_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED0 field.                            */
  #define EGU_INTENCLR_TRIGGERED0_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED0 field.                            */
  #define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
  #define EGU_INTENCLR_TRIGGERED1_Pos (1UL)          /*!< Position of TRIGGERED1 field.                                        */
  #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                */
  #define EGU_INTENCLR_TRIGGERED1_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED1 field.                            */
  #define EGU_INTENCLR_TRIGGERED1_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED1 field.                            */
  #define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
  #define EGU_INTENCLR_TRIGGERED2_Pos (2UL)          /*!< Position of TRIGGERED2 field.                                        */
  #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                */
  #define EGU_INTENCLR_TRIGGERED2_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED2 field.                            */
  #define EGU_INTENCLR_TRIGGERED2_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED2 field.                            */
  #define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
  #define EGU_INTENCLR_TRIGGERED3_Pos (3UL)          /*!< Position of TRIGGERED3 field.                                        */
  #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                */
  #define EGU_INTENCLR_TRIGGERED3_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED3 field.                            */
  #define EGU_INTENCLR_TRIGGERED3_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED3 field.                            */
  #define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
  #define EGU_INTENCLR_TRIGGERED4_Pos (4UL)          /*!< Position of TRIGGERED4 field.                                        */
  #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                */
  #define EGU_INTENCLR_TRIGGERED4_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED4 field.                            */
  #define EGU_INTENCLR_TRIGGERED4_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED4 field.                            */
  #define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
  #define EGU_INTENCLR_TRIGGERED5_Pos (5UL)          /*!< Position of TRIGGERED5 field.                                        */
  #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                */
  #define EGU_INTENCLR_TRIGGERED5_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED5 field.                            */
  #define EGU_INTENCLR_TRIGGERED5_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED5 field.                            */
  #define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
  #define EGU_INTENCLR_TRIGGERED6_Pos (6UL)          /*!< Position of TRIGGERED6 field.                                        */
  #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                */
  #define EGU_INTENCLR_TRIGGERED6_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED6 field.                            */
  #define EGU_INTENCLR_TRIGGERED6_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED6 field.                            */
  #define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
  #define EGU_INTENCLR_TRIGGERED7_Pos (7UL)          /*!< Position of TRIGGERED7 field.                                        */
  #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                */
  #define EGU_INTENCLR_TRIGGERED7_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED7 field.                            */
  #define EGU_INTENCLR_TRIGGERED7_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED7 field.                            */
  #define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
  #define EGU_INTENCLR_TRIGGERED8_Pos (8UL)          /*!< Position of TRIGGERED8 field.                                        */
  #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                */
  #define EGU_INTENCLR_TRIGGERED8_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED8 field.                            */
  #define EGU_INTENCLR_TRIGGERED8_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED8 field.                            */
  #define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
  #define EGU_INTENCLR_TRIGGERED9_Pos (9UL)          /*!< Position of TRIGGERED9 field.                                        */
  #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                */
  #define EGU_INTENCLR_TRIGGERED9_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED9 field.                            */
  #define EGU_INTENCLR_TRIGGERED9_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED9 field.                            */
  #define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL)      /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
  #define EGU_INTENCLR_TRIGGERED10_Pos (10UL)        /*!< Position of TRIGGERED10 field.                                       */
  #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.             */
  #define EGU_INTENCLR_TRIGGERED10_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED10 field.                           */
  #define EGU_INTENCLR_TRIGGERED10_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED10 field.                           */
  #define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL)     /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
  #define EGU_INTENCLR_TRIGGERED11_Pos (11UL)        /*!< Position of TRIGGERED11 field.                                       */
  #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.             */
  #define EGU_INTENCLR_TRIGGERED11_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED11 field.                           */
  #define EGU_INTENCLR_TRIGGERED11_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED11 field.                           */
  #define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL)     /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
  #define EGU_INTENCLR_TRIGGERED12_Pos (12UL)        /*!< Position of TRIGGERED12 field.                                       */
  #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.             */
  #define EGU_INTENCLR_TRIGGERED12_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED12 field.                           */
  #define EGU_INTENCLR_TRIGGERED12_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED12 field.                           */
  #define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL)     /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
  #define EGU_INTENCLR_TRIGGERED13_Pos (13UL)        /*!< Position of TRIGGERED13 field.                                       */
  #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.             */
  #define EGU_INTENCLR_TRIGGERED13_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED13 field.                           */
  #define EGU_INTENCLR_TRIGGERED13_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED13 field.                           */
  #define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL)     /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
  #define EGU_INTENCLR_TRIGGERED14_Pos (14UL)        /*!< Position of TRIGGERED14 field.                                       */
  #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.             */
  #define EGU_INTENCLR_TRIGGERED14_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED14 field.                           */
  #define EGU_INTENCLR_TRIGGERED14_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED14 field.                           */
  #define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL)     /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
  #define EGU_INTENCLR_TRIGGERED15_Pos (15UL)        /*!< Position of TRIGGERED15 field.                                       */
  #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.             */
  #define EGU_INTENCLR_TRIGGERED15_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED15 field.                           */
  #define EGU_INTENCLR_TRIGGERED15_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED15 field.                           */
  #define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL)     /*!< Disable                                                              */
  #define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            ETM                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct ETM ======================================================== */
/**
  * @brief Embedded Trace Macrocell
  */
  typedef struct {                                   /*!< ETM Structure                                                        */
    __IM uint32_t RESERVED;
    __IOM uint32_t TRCPRGCTLR;                       /*!< (@ 0x00000004) Enables the trace unit.                               */
    __IOM uint32_t TRCPROCSELR;                      /*!< (@ 0x00000008) Controls which PE to trace. Might ignore writes when
                                                                         the trace unit is enabled or not idle. Before writing
                                                                         to this register, ensure that TRCSTATR.IDLE == 1 so
                                                                         that the trace unit can synchronize with the chosen PE.
                                                                         Implemented if TRCIDR3.NUMPROC is greater than zero.*/
    __IOM uint32_t TRCSTATR;                         /*!< (@ 0x0000000C) Idle status bit                                       */
    __IOM uint32_t TRCCONFIGR;                       /*!< (@ 0x00000010) Controls the tracing options This register must always
                                                                         be programmed as part of trace unit initialization.
                                                                         Might ignore writes when the trace unit is enabled or
                                                                         not idle.*/
    __IM uint32_t RESERVED1[3];
    __IOM uint32_t TRCEVENTCTL0R;                    /*!< (@ 0x00000020) Controls the tracing of arbitrary events. If the
                                                                         selected event occurs a trace element is generated in
                                                                         the trace stream according to the settings in
                                                                         TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN.*/
    __IOM uint32_t TRCEVENTCTL1R;                    /*!< (@ 0x00000024) Controls the behavior of the events that TRCEVENTCTL0R
                                                                         selects. This register must always be programmed as
                                                                         part of trace unit initialization. Might ignore writes
                                                                         when the trace unit is enabled or not idle.*/
    __IM uint32_t RESERVED2;
    __IOM uint32_t TRCSTALLCTLR;                     /*!< (@ 0x0000002C) Enables trace unit functionality that prevents trace
                                                                         unit buffer overflows. Might ignore writes when the
                                                                         trace unit is enabled or not idle. Must be programmed
                                                                         if TRCIDR3.STALLCTL == 1.*/
    __IOM uint32_t TRCTSCTLR;                        /*!< (@ 0x00000030) Controls the insertion of global timestamps in the
                                                                         trace streams. When the selected event is triggered,
                                                                         the trace unit inserts a global timestamp into the
                                                                         trace streams. Might ignore writes when the trace unit
                                                                         is enabled or not idle. Must be programmed if
                                                                         TRCCONFIGR.TS == 1.*/
    __IOM uint32_t TRCSYNCPR;                        /*!< (@ 0x00000034) Controls how often trace synchronization requests
                                                                         occur. Might ignore writes when the trace unit is
                                                                         enabled or not idle. If writes are permitted then the
                                                                         register must be programmed.*/
    __IOM uint32_t TRCCCCTLR;                        /*!< (@ 0x00000038) Sets the threshold value for cycle counting. Might
                                                                         ignore writes when the trace unit is enabled or not
                                                                         idle. Must be programmed if TRCCONFIGR.CCI==1.*/
    __IOM uint32_t TRCBBCTLR;                        /*!< (@ 0x0000003C) Controls which regions in the memory map are enabled to
                                                                         use branch broadcasting. Might ignore writes when the
                                                                         trace unit is enabled or not idle. Must be programmed
                                                                         if TRCCONFIGR.BB == 1.*/
    __IOM uint32_t TRCTRACEIDR;                      /*!< (@ 0x00000040) Sets the trace ID for instruction trace. If data trace
                                                                         is enabled then it also sets the trace ID for data
                                                                         trace, to (trace ID for instruction trace) + 1. This
                                                                         register must always be programmed as part of trace
                                                                         unit initialization. Might ignore writes when the trace
                                                                         unit is enabled or not idle.*/
    __IOM uint32_t TRCQCTLR;                         /*!< (@ 0x00000044) Controls when Q elements are enabled. Might ignore
                                                                         writes when the trace unit is enabled or not idle. This
                                                                         register must be programmed if it is implemented and
                                                                         TRCCONFIGR.QE is set to any value other than 0b00.*/
    __IM uint32_t RESERVED3[14];
    __IOM uint32_t TRCVICTLR;                        /*!< (@ 0x00000080) Controls instruction trace filtering. Might ignore
                                                                         writes when the trace unit is enabled or not idle. Only
                                                                         returns stable data when TRCSTATR.PMSTABLE == 1. Must
                                                                         be programmed, particularly to set the value of the
                                                                         SSSTATUS bit, which sets the state of the start/stop
                                                                         logic.*/
    __IOM uint32_t TRCVIIECTLR;                      /*!< (@ 0x00000084) ViewInst exclude control. Might ignore writes when the
                                                                         trace unit is enabled or not idle. This register must
                                                                         be programmed when one or more address comparators are
                                                                         implemented.*/
    __IOM uint32_t TRCVISSCTLR;                      /*!< (@ 0x00000088) Use this to set, or read, the single address
                                                                         comparators that control the ViewInst start/stop logic.
                                                                         The start/stop logic is active for an instruction which
                                                                         causes a start and remains active up to and including
                                                                         an instruction which causes a stop, and then the
                                                                         start/stop logic becomes inactive. Might ignore writes
                                                                         when the trace unit is enabled or not idle. If
                                                                         implemented then this register must be programmed.*/
    __IOM uint32_t TRCVIPCSSCTLR;                    /*!< (@ 0x0000008C) Use this to set, or read, which PE comparator inputs
                                                                         can control the ViewInst start/stop logic. Might ignore
                                                                         writes when the trace unit is enabled or not idle. If
                                                                         implemented then this register must be programmed.*/
    __IM uint32_t RESERVED4[4];
    __IOM uint32_t TRCVDCTLR;                        /*!< (@ 0x000000A0) Controls data trace filtering. Might ignore writes when
                                                                         the trace unit is enabled or not idle. This register
                                                                         must be programmed when data tracing is enabled, that
                                                                         is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV ==
                                                                         1.*/
    __IOM uint32_t TRCVDSACCTLR;                     /*!< (@ 0x000000A4) ViewData include / exclude control. Might ignore writes
                                                                         when the trace unit is enabled or not idle. This
                                                                         register must be programmed when one or more address
                                                                         comparators are implemented.*/
    __IOM uint32_t TRCVDARCCTLR;                     /*!< (@ 0x000000A8) ViewData include / exclude control. Might ignore writes
                                                                         when the trace unit is enabled or not idle. This
                                                                         register must be programmed when one or more address
                                                                         comparators are implemented.*/
    __IM uint32_t RESERVED5[21];
    __IOM uint32_t TRCSEQEVR[3];                     /*!< (@ 0x00000100) Moves the sequencer state according to programmed
                                                                         events. Might ignore writes when the trace unit is
                                                                         enabled or not idle. When the sequencer is used, all
                                                                         sequencer state transitions must be programmed with a
                                                                         valid event.*/
    __IM uint32_t RESERVED6[3];
    __IOM uint32_t TRCSEQRSTEVR;                     /*!< (@ 0x00000118) Moves the sequencer to state 0 when a programmed event
                                                                         occurs. Might ignore writes when the trace unit is
                                                                         enabled or not idle. When the sequencer is used, all
                                                                         sequencer state transitions must be programmed with a
                                                                         valid event.*/
    __IOM uint32_t TRCSEQSTR;                        /*!< (@ 0x0000011C) Use this to set, or read, the sequencer state. Might
                                                                         ignore writes when the trace unit is enabled or not
                                                                         idle. Only returns stable data when TRCSTATR.PMSTABLE
                                                                         == 1. When the sequencer is used, all sequencer state
                                                                         transitions must be programmed with a valid event.*/
    __IOM uint32_t TRCEXTINSELR;                     /*!< (@ 0x00000120) Use this to set, or read, which external inputs are
                                                                         resources to the trace unit. Might ignore writes when
                                                                         the trace unit is enabled or not idle. Only returns
                                                                         stable data when TRCSTATR.PMSTABLE == 1. When the
                                                                         sequencer is used, all sequencer state transitions must
                                                                         be programmed with a valid event.*/
    __IM uint32_t RESERVED7[7];
    __IOM uint32_t TRCCNTRLDVR[4];                   /*!< (@ 0x00000140) This sets or returns the reload count value for counter
                                                                         n. Might ignore writes when the trace unit is enabled
                                                                         or not idle.*/
    __IOM uint32_t TRCCNTCTLR[4];                    /*!< (@ 0x00000150) Controls the operation of counter n. Might ignore
                                                                         writes when the trace unit is enabled or not idle.*/
    __IOM uint32_t TRCCNTVR[4];                      /*!< (@ 0x00000160) This sets or returns the value of counter n. The count
                                                                         value is only stable when TRCSTATR.PMSTABLE == 1. If
                                                                         software uses counter n then it must write to this
                                                                         register to set the initial counter value. Might ignore
                                                                         writes when the trace unit is enabled or not idle.*/
    __IM uint32_t RESERVED8[36];
    __IOM uint32_t TRCRSCTLR[32];                    /*!< (@ 0x00000200) Controls the selection of the resources in the trace
                                                                         unit. Might ignore writes when the trace unit is
                                                                         enabled or not idle. If software selects a
                                                                         non-implemented resource then CONSTRAINED UNPREDICTABLE
                                                                         behavior of the resource selector occurs, so the
                                                                         resource selector might fire unexpectedly or might not
                                                                         fire. Reads of the TRCRSCTLRn might return UNKNOWN.*/
    __IOM uint32_t TRCSSCCR0;                        /*!< (@ 0x00000280) Controls the single-shot comparator.                  */
    __IM uint32_t RESERVED9[7];
    __IOM uint32_t TRCSSCSR0;                        /*!< (@ 0x000002A0) Indicates the status of the single-shot comparators.
                                                                         TRCSSCSR0 is sensitive toinstruction addresses.*/
    __IM uint32_t RESERVED10[7];
    __IOM uint32_t TRCSSPCICR0;                      /*!< (@ 0x000002C0) Selects the processor comparator inputs for Single-shot
                                                                         control.*/
    __IM uint32_t RESERVED11[19];
    __IOM uint32_t TRCPDCR;                          /*!< (@ 0x00000310) Controls the single-shot comparator.                  */
    __IOM uint32_t TRCPDSR;                          /*!< (@ 0x00000314) Indicates the power down status of the ETM.           */
    __IM uint32_t RESERVED12[755];
    __IOM uint32_t TRCITATBIDR;                      /*!< (@ 0x00000EE4) Sets the state of output pins.                        */
    __IM uint32_t RESERVED13[3];
    __IOM uint32_t TRCITIATBINR;                     /*!< (@ 0x00000EF4) Reads the state of the input pins.                    */
    __IM uint32_t RESERVED14;
    __IOM uint32_t TRCITIATBOUTR;                    /*!< (@ 0x00000EFC) Sets the state of the output pins.                    */
    __IOM uint32_t TRCITCTRL;                        /*!< (@ 0x00000F00) Enables topology detection or integration testing, by
                                                                         putting ETM-M33 into integration mode.*/
    __IM uint32_t RESERVED15[39];
    __IOM uint32_t TRCCLAIMSET;                      /*!< (@ 0x00000FA0) Sets bits in the claim tag and determines the number of
                                                                         claim tag bits implemented.*/
    __IOM uint32_t TRCCLAIMCLR;                      /*!< (@ 0x00000FA4) Clears bits in the claim tag and determines the current
                                                                         value of the claim tag.*/
    __IM uint32_t RESERVED16[4];
    __IOM uint32_t TRCAUTHSTATUS;                    /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the
                                                                         system*/
    __IM uint32_t TRCDEVARCH;                        /*!< (@ 0x00000FBC) The TRCDEVARCH identifies ETM-M33 as an ETMv4.2
                                                                         component*/
    __IM uint32_t RESERVED17[3];
    __IM uint32_t TRCDEVTYPE;                        /*!< (@ 0x00000FCC) Controls the single-shot comparator.                  */
    __IOM uint32_t TRCPIDR[8];                       /*!< (@ 0x00000FD0) Coresight peripheral identification registers.        */
    __IOM uint32_t TRCCIDR[4];                       /*!< (@ 0x00000FF0) Coresight component identification registers.         */
  } NRF_ETM_Type;                                    /*!< Size = 4096 (0x1000)                                                 */

/* ETM_TRCPRGCTLR: Enables the trace unit. */
  #define ETM_TRCPRGCTLR_ResetValue (0x00000000UL)   /*!< Reset value of TRCPRGCTLR register.                                  */

/* EN @Bit 0 : Trace unit enable bit */
  #define ETM_TRCPRGCTLR_EN_Pos (0UL)                /*!< Position of EN field.                                                */
  #define ETM_TRCPRGCTLR_EN_Msk (0x1UL << ETM_TRCPRGCTLR_EN_Pos) /*!< Bit mask of EN field.                                    */
  #define ETM_TRCPRGCTLR_EN_Min (0x0UL)              /*!< Min enumerator value of EN field.                                    */
  #define ETM_TRCPRGCTLR_EN_Max (0x1UL)              /*!< Max enumerator value of EN field.                                    */
  #define ETM_TRCPRGCTLR_EN_Disabled (0x0UL)         /*!< The trace unit is disabled. All trace resources are inactive and no
                                                          trace is generated.*/
  #define ETM_TRCPRGCTLR_EN_Enabled (0x1UL)          /*!< The trace unit is enabled.                                           */


/* ETM_TRCPROCSELR: Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing
                     to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE.
                     Implemented if TRCIDR3.NUMPROC is greater than zero. */

  #define ETM_TRCPROCSELR_ResetValue (0x00000000UL)  /*!< Reset value of TRCPROCSELR register.                                 */

/* PROCSEL @Bits 0..4 : PE select bits that select the PE to trace. */
  #define ETM_TRCPROCSELR_PROCSEL_Pos (0UL)          /*!< Position of PROCSEL field.                                           */
  #define ETM_TRCPROCSELR_PROCSEL_Msk (0x1FUL << ETM_TRCPROCSELR_PROCSEL_Pos) /*!< Bit mask of PROCSEL field.                  */


/* ETM_TRCSTATR: Idle status bit */
  #define ETM_TRCSTATR_ResetValue (0x00000000UL)     /*!< Reset value of TRCSTATR register.                                    */

/* IDLE @Bit 0 : Trace unit enable bit */
  #define ETM_TRCSTATR_IDLE_Pos (0UL)                /*!< Position of IDLE field.                                              */
  #define ETM_TRCSTATR_IDLE_Msk (0x1UL << ETM_TRCSTATR_IDLE_Pos) /*!< Bit mask of IDLE field.                                  */
  #define ETM_TRCSTATR_IDLE_Min (0x0UL)              /*!< Min enumerator value of IDLE field.                                  */
  #define ETM_TRCSTATR_IDLE_Max (0x1UL)              /*!< Max enumerator value of IDLE field.                                  */
  #define ETM_TRCSTATR_IDLE_NotIdle (0x0UL)          /*!< The trace unit is not idle.                                          */
  #define ETM_TRCSTATR_IDLE_Idle (0x1UL)             /*!< The trace unit is idle.                                              */

/* PMSTABLE @Bit 1 : Programmers' model stable bit */
  #define ETM_TRCSTATR_PMSTABLE_Pos (1UL)            /*!< Position of PMSTABLE field.                                          */
  #define ETM_TRCSTATR_PMSTABLE_Msk (0x1UL << ETM_TRCSTATR_PMSTABLE_Pos) /*!< Bit mask of PMSTABLE field.                      */
  #define ETM_TRCSTATR_PMSTABLE_Min (0x0UL)          /*!< Min enumerator value of PMSTABLE field.                              */
  #define ETM_TRCSTATR_PMSTABLE_Max (0x1UL)          /*!< Max enumerator value of PMSTABLE field.                              */
  #define ETM_TRCSTATR_PMSTABLE_NotStable (0x0UL)    /*!< The programmers' model is not stable.                                */
  #define ETM_TRCSTATR_PMSTABLE_Stable (0x1UL)       /*!< The programmers' model is stable.                                    */


/* ETM_TRCCONFIGR: Controls the tracing options This register must always be programmed as part of trace unit initialization.
                    Might ignore writes when the trace unit is enabled or not idle. */

  #define ETM_TRCCONFIGR_ResetValue (0x00000000UL)   /*!< Reset value of TRCCONFIGR register.                                  */

/* LOADASP0INST @Bit 1 : Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions.
                         */

  #define ETM_TRCCONFIGR_LOADASP0INST_Pos (1UL)      /*!< Position of LOADASP0INST field.                                      */
  #define ETM_TRCCONFIGR_LOADASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_LOADASP0INST_Pos) /*!< Bit mask of LOADASP0INST field.      */
  #define ETM_TRCCONFIGR_LOADASP0INST_Min (0x0UL)    /*!< Min enumerator value of LOADASP0INST field.                          */
  #define ETM_TRCCONFIGR_LOADASP0INST_Max (0x1UL)    /*!< Max enumerator value of LOADASP0INST field.                          */
  #define ETM_TRCCONFIGR_LOADASP0INST_No (0x0UL)     /*!< Do not trace load instructions as P0 instructions.                   */
  #define ETM_TRCCONFIGR_LOADASP0INST_Yes (0x1UL)    /*!< Trace load instructions as P0 instructions.                          */

/* STOREASP0INST @Bit 2 : Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. */
  #define ETM_TRCCONFIGR_STOREASP0INST_Pos (2UL)     /*!< Position of STOREASP0INST field.                                     */
  #define ETM_TRCCONFIGR_STOREASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_STOREASP0INST_Pos) /*!< Bit mask of STOREASP0INST field.   */
  #define ETM_TRCCONFIGR_STOREASP0INST_Min (0x0UL)   /*!< Min enumerator value of STOREASP0INST field.                         */
  #define ETM_TRCCONFIGR_STOREASP0INST_Max (0x1UL)   /*!< Max enumerator value of STOREASP0INST field.                         */
  #define ETM_TRCCONFIGR_STOREASP0INST_No (0x0UL)    /*!< Do not trace store instructions as P0 instructions.                  */
  #define ETM_TRCCONFIGR_STOREASP0INST_Yes (0x1UL)   /*!< Trace store instructions as P0 instructions.                         */

/* BB @Bit 3 : Branch broadcast mode bit. */
  #define ETM_TRCCONFIGR_BB_Pos (3UL)                /*!< Position of BB field.                                                */
  #define ETM_TRCCONFIGR_BB_Msk (0x1UL << ETM_TRCCONFIGR_BB_Pos) /*!< Bit mask of BB field.                                    */
  #define ETM_TRCCONFIGR_BB_Min (0x0UL)              /*!< Min enumerator value of BB field.                                    */
  #define ETM_TRCCONFIGR_BB_Max (0x1UL)              /*!< Max enumerator value of BB field.                                    */
  #define ETM_TRCCONFIGR_BB_Disabled (0x0UL)         /*!< Branch broadcast mode is disabled.                                   */
  #define ETM_TRCCONFIGR_BB_Enabled (0x1UL)          /*!< Branch broadcast mode is enabled.                                    */

/* CCI @Bit 4 : Cycle counting instruction trace bit. */
  #define ETM_TRCCONFIGR_CCI_Pos (4UL)               /*!< Position of CCI field.                                               */
  #define ETM_TRCCONFIGR_CCI_Msk (0x1UL << ETM_TRCCONFIGR_CCI_Pos) /*!< Bit mask of CCI field.                                 */
  #define ETM_TRCCONFIGR_CCI_Min (0x0UL)             /*!< Min enumerator value of CCI field.                                   */
  #define ETM_TRCCONFIGR_CCI_Max (0x1UL)             /*!< Max enumerator value of CCI field.                                   */
  #define ETM_TRCCONFIGR_CCI_Disabled (0x0UL)        /*!< Cycle counting in the instruction trace is disabled.                 */
  #define ETM_TRCCONFIGR_CCI_Enabled (0x1UL)         /*!< Cycle counting in the instruction trace is enabled.                  */

/* CID @Bit 6 : Context ID tracing bit. */
  #define ETM_TRCCONFIGR_CID_Pos (6UL)               /*!< Position of CID field.                                               */
  #define ETM_TRCCONFIGR_CID_Msk (0x1UL << ETM_TRCCONFIGR_CID_Pos) /*!< Bit mask of CID field.                                 */
  #define ETM_TRCCONFIGR_CID_Min (0x0UL)             /*!< Min enumerator value of CID field.                                   */
  #define ETM_TRCCONFIGR_CID_Max (0x1UL)             /*!< Max enumerator value of CID field.                                   */
  #define ETM_TRCCONFIGR_CID_Disabled (0x0UL)        /*!< Context ID tracing is disabled.                                      */
  #define ETM_TRCCONFIGR_CID_Enabled (0x1UL)         /*!< Context ID tracing is enabled.                                       */

/* VMID @Bit 7 : Virtual context identifier tracing bit. */
  #define ETM_TRCCONFIGR_VMID_Pos (7UL)              /*!< Position of VMID field.                                              */
  #define ETM_TRCCONFIGR_VMID_Msk (0x1UL << ETM_TRCCONFIGR_VMID_Pos) /*!< Bit mask of VMID field.                              */
  #define ETM_TRCCONFIGR_VMID_Min (0x0UL)            /*!< Min enumerator value of VMID field.                                  */
  #define ETM_TRCCONFIGR_VMID_Max (0x1UL)            /*!< Max enumerator value of VMID field.                                  */
  #define ETM_TRCCONFIGR_VMID_Disabled (0x0UL)       /*!< Virtual context identifier tracing is disabled.                      */
  #define ETM_TRCCONFIGR_VMID_Enabled (0x1UL)        /*!< Virtual context identifier tracing is enabled.                       */

/* COND @Bits 8..10 : Conditional instruction tracing bit. */
  #define ETM_TRCCONFIGR_COND_Pos (8UL)              /*!< Position of COND field.                                              */
  #define ETM_TRCCONFIGR_COND_Msk (0x7UL << ETM_TRCCONFIGR_COND_Pos) /*!< Bit mask of COND field.                              */
  #define ETM_TRCCONFIGR_COND_Min (0x0UL)            /*!< Min enumerator value of COND field.                                  */
  #define ETM_TRCCONFIGR_COND_Max (0x7UL)            /*!< Max enumerator value of COND field.                                  */
  #define ETM_TRCCONFIGR_COND_Disabled (0x0UL)       /*!< Conditional instruction tracing is disabled.                         */
  #define ETM_TRCCONFIGR_COND_LoadOnly (0x1UL)       /*!< Conditional load instructions are traced.                            */
  #define ETM_TRCCONFIGR_COND_StoreOnly (0x2UL)      /*!< Conditional store instructions are traced.                           */
  #define ETM_TRCCONFIGR_COND_LoadAndStore (0x3UL)   /*!< Conditional load and store instructions are traced.                  */
  #define ETM_TRCCONFIGR_COND_All (0x7UL)            /*!< All conditional instructions are traced.                             */

/* TS @Bit 11 : Global timestamp tracing bit. */
  #define ETM_TRCCONFIGR_TS_Pos (11UL)               /*!< Position of TS field.                                                */
  #define ETM_TRCCONFIGR_TS_Msk (0x1UL << ETM_TRCCONFIGR_TS_Pos) /*!< Bit mask of TS field.                                    */
  #define ETM_TRCCONFIGR_TS_Min (0x0UL)              /*!< Min enumerator value of TS field.                                    */
  #define ETM_TRCCONFIGR_TS_Max (0x1UL)              /*!< Max enumerator value of TS field.                                    */
  #define ETM_TRCCONFIGR_TS_Disabled (0x0UL)         /*!< Global timestamp tracing is disabled.                                */
  #define ETM_TRCCONFIGR_TS_Enabled (0x1UL)          /*!< Global timestamp tracing is enabled.                                 */

/* RS @Bit 12 : Return stack enable bit. */
  #define ETM_TRCCONFIGR_RS_Pos (12UL)               /*!< Position of RS field.                                                */
  #define ETM_TRCCONFIGR_RS_Msk (0x1UL << ETM_TRCCONFIGR_RS_Pos) /*!< Bit mask of RS field.                                    */
  #define ETM_TRCCONFIGR_RS_Min (0x0UL)              /*!< Min enumerator value of RS field.                                    */
  #define ETM_TRCCONFIGR_RS_Max (0x1UL)              /*!< Max enumerator value of RS field.                                    */
  #define ETM_TRCCONFIGR_RS_Disabled (0x0UL)         /*!< Return stack is disabled.                                            */
  #define ETM_TRCCONFIGR_RS_Enabled (0x1UL)          /*!< Return stack is enabled.                                             */

/* QE @Bits 13..14 : Q element enable field. */
  #define ETM_TRCCONFIGR_QE_Pos (13UL)               /*!< Position of QE field.                                                */
  #define ETM_TRCCONFIGR_QE_Msk (0x3UL << ETM_TRCCONFIGR_QE_Pos) /*!< Bit mask of QE field.                                    */
  #define ETM_TRCCONFIGR_QE_Min (0x0UL)              /*!< Min enumerator value of QE field.                                    */
  #define ETM_TRCCONFIGR_QE_Max (0x3UL)              /*!< Max enumerator value of QE field.                                    */
  #define ETM_TRCCONFIGR_QE_Disabled (0x0UL)         /*!< Q elements are disabled.                                             */
  #define ETM_TRCCONFIGR_QE_OnlyWithoutInstCounts (0x1UL) /*!< Q elements with instruction counts are enabled. Q elements
                                                               without instruction counts are disabled.*/
  #define ETM_TRCCONFIGR_QE_Enabled (0x3UL)          /*!< Q elements with and without instruction counts are enabled.          */

/* VMIDOPT @Bit 15 : Control bit to select the Virtual context identifier value used by the trace unit, both for trace
                     generation and in the Virtual context identifier comparators. */

  #define ETM_TRCCONFIGR_VMIDOPT_Pos (15UL)          /*!< Position of VMIDOPT field.                                           */
  #define ETM_TRCCONFIGR_VMIDOPT_Msk (0x1UL << ETM_TRCCONFIGR_VMIDOPT_Pos) /*!< Bit mask of VMIDOPT field.                     */
  #define ETM_TRCCONFIGR_VMIDOPT_Min (0x0UL)         /*!< Min enumerator value of VMIDOPT field.                               */
  #define ETM_TRCCONFIGR_VMIDOPT_Max (0x1UL)         /*!< Max enumerator value of VMIDOPT field.                               */
  #define ETM_TRCCONFIGR_VMIDOPT_VTTBR_EL2 (0x0UL)   /*!< VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context
                                                          identifier larger than the VTTBR_EL2.VMID, the upper unused bits are
                                                          always zero. If the trace unit supports a Virtual context identifier
                                                          larger than 8 bits and if the VTCR_EL2.VS bit forces use of an 8-bit
                                                          Virtual context identifier, bits [15:8] of the trace unit Virtual
                                                          context identifier are always zero.*/
  #define ETM_TRCCONFIGR_VMIDOPT_CONTEXTIDR_EL2 (0x1UL) /*!< CONTEXTIDR_EL2 is used.                                           */

/* DA @Bit 16 : Data address tracing bit. */
  #define ETM_TRCCONFIGR_DA_Pos (16UL)               /*!< Position of DA field.                                                */
  #define ETM_TRCCONFIGR_DA_Msk (0x1UL << ETM_TRCCONFIGR_DA_Pos) /*!< Bit mask of DA field.                                    */
  #define ETM_TRCCONFIGR_DA_Min (0x0UL)              /*!< Min enumerator value of DA field.                                    */
  #define ETM_TRCCONFIGR_DA_Max (0x1UL)              /*!< Max enumerator value of DA field.                                    */
  #define ETM_TRCCONFIGR_DA_Disabled (0x0UL)         /*!< Data address tracing is disabled.                                    */
  #define ETM_TRCCONFIGR_DA_Enabled (0x1UL)          /*!< Data address tracing is enabled.                                     */

/* DV @Bit 17 : Data value tracing bit. */
  #define ETM_TRCCONFIGR_DV_Pos (17UL)               /*!< Position of DV field.                                                */
  #define ETM_TRCCONFIGR_DV_Msk (0x1UL << ETM_TRCCONFIGR_DV_Pos) /*!< Bit mask of DV field.                                    */
  #define ETM_TRCCONFIGR_DV_Min (0x0UL)              /*!< Min enumerator value of DV field.                                    */
  #define ETM_TRCCONFIGR_DV_Max (0x1UL)              /*!< Max enumerator value of DV field.                                    */
  #define ETM_TRCCONFIGR_DV_Disabled (0x0UL)         /*!< Data value tracing is disabled.                                      */
  #define ETM_TRCCONFIGR_DV_Enabled (0x1UL)          /*!< Data value tracing is enabled.                                       */


/* ETM_TRCEVENTCTL0R: Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the
                       trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. */

  #define ETM_TRCEVENTCTL0R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL0R register.                              */

/* EVENT @Bits 0..7 : Select which event should generate trace elements. */
  #define ETM_TRCEVENTCTL0R_EVENT_Pos (0UL)          /*!< Position of EVENT field.                                             */
  #define ETM_TRCEVENTCTL0R_EVENT_Msk (0xFFUL << ETM_TRCEVENTCTL0R_EVENT_Pos) /*!< Bit mask of EVENT field.                    */
  #define ETM_TRCEVENTCTL0R_EVENT_Min (0x00UL)       /*!< Min value of EVENT field.                                            */
  #define ETM_TRCEVENTCTL0R_EVENT_Max (0xFFUL)       /*!< Max size of EVENT field.                                             */


/* ETM_TRCEVENTCTL1R: Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as
                       part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */

  #define ETM_TRCEVENTCTL1R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL1R register.                              */

/* INSTEN0 @Bit 0 : Instruction event enable field. */
  #define ETM_TRCEVENTCTL1R_INSTEN0_Pos (0UL)        /*!< Position of INSTEN0 field.                                           */
  #define ETM_TRCEVENTCTL1R_INSTEN0_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN0_Pos) /*!< Bit mask of INSTEN0 field.               */
  #define ETM_TRCEVENTCTL1R_INSTEN0_Min (0x0UL)      /*!< Min enumerator value of INSTEN0 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN0_Max (0x1UL)      /*!< Max enumerator value of INSTEN0 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN0_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
  #define ETM_TRCEVENTCTL1R_INSTEN0_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 0, in the
                                                          instruction trace stream.*/

/* INSTEN1 @Bit 1 : Instruction event enable field. */
  #define ETM_TRCEVENTCTL1R_INSTEN1_Pos (1UL)        /*!< Position of INSTEN1 field.                                           */
  #define ETM_TRCEVENTCTL1R_INSTEN1_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN1_Pos) /*!< Bit mask of INSTEN1 field.               */
  #define ETM_TRCEVENTCTL1R_INSTEN1_Min (0x0UL)      /*!< Min enumerator value of INSTEN1 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN1_Max (0x1UL)      /*!< Max enumerator value of INSTEN1 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN1_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
  #define ETM_TRCEVENTCTL1R_INSTEN1_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 1, in the
                                                          instruction trace stream.*/

/* INSTEN2 @Bit 2 : Instruction event enable field. */
  #define ETM_TRCEVENTCTL1R_INSTEN2_Pos (2UL)        /*!< Position of INSTEN2 field.                                           */
  #define ETM_TRCEVENTCTL1R_INSTEN2_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN2_Pos) /*!< Bit mask of INSTEN2 field.               */
  #define ETM_TRCEVENTCTL1R_INSTEN2_Min (0x0UL)      /*!< Min enumerator value of INSTEN2 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN2_Max (0x1UL)      /*!< Max enumerator value of INSTEN2 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN2_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
  #define ETM_TRCEVENTCTL1R_INSTEN2_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 2, in the
                                                          instruction trace stream.*/

/* INSTEN3 @Bit 3 : Instruction event enable field. */
  #define ETM_TRCEVENTCTL1R_INSTEN3_Pos (3UL)        /*!< Position of INSTEN3 field.                                           */
  #define ETM_TRCEVENTCTL1R_INSTEN3_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN3_Pos) /*!< Bit mask of INSTEN3 field.               */
  #define ETM_TRCEVENTCTL1R_INSTEN3_Min (0x0UL)      /*!< Min enumerator value of INSTEN3 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN3_Max (0x1UL)      /*!< Max enumerator value of INSTEN3 field.                               */
  #define ETM_TRCEVENTCTL1R_INSTEN3_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
  #define ETM_TRCEVENTCTL1R_INSTEN3_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 3, in the
                                                          instruction trace stream.*/

/* DATAEN @Bit 4 : Data event enable bit. */
  #define ETM_TRCEVENTCTL1R_DATAEN_Pos (4UL)         /*!< Position of DATAEN field.                                            */
  #define ETM_TRCEVENTCTL1R_DATAEN_Msk (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos) /*!< Bit mask of DATAEN field.                  */
  #define ETM_TRCEVENTCTL1R_DATAEN_Min (0x0UL)       /*!< Min enumerator value of DATAEN field.                                */
  #define ETM_TRCEVENTCTL1R_DATAEN_Max (0x1UL)       /*!< Max enumerator value of DATAEN field.                                */
  #define ETM_TRCEVENTCTL1R_DATAEN_Disabled (0x0UL)  /*!< The trace unit does not generate an Event element if event 0 occurs. */
  #define ETM_TRCEVENTCTL1R_DATAEN_Enabled (0x1UL)   /*!< The trace unit generates an Event element in the data trace stream if
                                                          event 0 occurs.*/

/* ATB @Bit 11 : AMBA Trace Bus (ATB) trigger enable bit. */
  #define ETM_TRCEVENTCTL1R_ATB_Pos (11UL)           /*!< Position of ATB field.                                               */
  #define ETM_TRCEVENTCTL1R_ATB_Msk (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos) /*!< Bit mask of ATB field.                           */
  #define ETM_TRCEVENTCTL1R_ATB_Min (0x0UL)          /*!< Min enumerator value of ATB field.                                   */
  #define ETM_TRCEVENTCTL1R_ATB_Max (0x1UL)          /*!< Max enumerator value of ATB field.                                   */
  #define ETM_TRCEVENTCTL1R_ATB_Disabled (0x0UL)     /*!< ATB trigger is disabled.                                             */
  #define ETM_TRCEVENTCTL1R_ATB_Enabled (0x1UL)      /*!< ATB trigger is enabled. If a CoreSight ATB interface is implemented
                                                          then when event 0 occurs the trace unit generates an ATB event.*/

/* LPOVERRIDE @Bit 12 : Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. */
  #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos (12UL)    /*!< Position of LPOVERRIDE field.                                        */
  #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos) /*!< Bit mask of LPOVERRIDE field.      */
  #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Min (0x0UL)   /*!< Min enumerator value of LPOVERRIDE field.                            */
  #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Max (0x1UL)   /*!< Max enumerator value of LPOVERRIDE field.                            */
  #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Disabled (0x0UL) /*!< Trace unit low-power state behavior is not affected. That is, the
                                                             trace unit is enabled to enter low-power state.*/
  #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Enabled (0x1UL) /*!< Trace unit low-power state behavior is overridden. That is, entry to
                                                            a low-power state does not affect the trace unit resources or trace
                                                            generation.*/


/* ETM_TRCSTALLCTLR: Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the
                      trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. */

  #define ETM_TRCSTALLCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCSTALLCTLR register.                                */

/* LEVEL @Bits 0..3 : Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global
                      timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction
                      trace stream, although the cumulative cycle count remains correct. */

  #define ETM_TRCSTALLCTLR_LEVEL_Pos (0UL)           /*!< Position of LEVEL field.                                             */
  #define ETM_TRCSTALLCTLR_LEVEL_Msk (0xFUL << ETM_TRCSTALLCTLR_LEVEL_Pos) /*!< Bit mask of LEVEL field.                       */
  #define ETM_TRCSTALLCTLR_LEVEL_Min (0x0UL)         /*!< Zero invasion. This setting has a greater risk of a FIFO overflow    */
  #define ETM_TRCSTALLCTLR_LEVEL_Max (0xFUL)         /*!< Maximum invasion occurs but there is less risk of a FIFO overflow.   */

/* ISTALL @Bit 8 : Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is
                   less than LEVEL. */

  #define ETM_TRCSTALLCTLR_ISTALL_Pos (8UL)          /*!< Position of ISTALL field.                                            */
  #define ETM_TRCSTALLCTLR_ISTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos) /*!< Bit mask of ISTALL field.                    */
  #define ETM_TRCSTALLCTLR_ISTALL_Min (0x0UL)        /*!< Min enumerator value of ISTALL field.                                */
  #define ETM_TRCSTALLCTLR_ISTALL_Max (0x1UL)        /*!< Max enumerator value of ISTALL field.                                */
  #define ETM_TRCSTALLCTLR_ISTALL_Disabled (0x0UL)   /*!< The trace unit must not stall the PE.                                */
  #define ETM_TRCSTALLCTLR_ISTALL_Enabled (0x1UL)    /*!< The trace unit can stall the PE.                                     */

/* DSTALL @Bit 9 : Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than
                   LEVEL. */

  #define ETM_TRCSTALLCTLR_DSTALL_Pos (9UL)          /*!< Position of DSTALL field.                                            */
  #define ETM_TRCSTALLCTLR_DSTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos) /*!< Bit mask of DSTALL field.                    */
  #define ETM_TRCSTALLCTLR_DSTALL_Min (0x0UL)        /*!< Min enumerator value of DSTALL field.                                */
  #define ETM_TRCSTALLCTLR_DSTALL_Max (0x1UL)        /*!< Max enumerator value of DSTALL field.                                */
  #define ETM_TRCSTALLCTLR_DSTALL_Disabled (0x0UL)   /*!< The trace unit must not stall the PE.                                */
  #define ETM_TRCSTALLCTLR_DSTALL_Enabled (0x1UL)    /*!< The trace unit can stall the PE.                                     */

/* INSTPRIORITY @Bit 10 : Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the
                          instruction trace buffer space is less than LEVEL. */

  #define ETM_TRCSTALLCTLR_INSTPRIORITY_Pos (10UL)   /*!< Position of INSTPRIORITY field.                                      */
  #define ETM_TRCSTALLCTLR_INSTPRIORITY_Msk (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos) /*!< Bit mask of INSTPRIORITY field.  */
  #define ETM_TRCSTALLCTLR_INSTPRIORITY_Min (0x0UL)  /*!< Min enumerator value of INSTPRIORITY field.                          */
  #define ETM_TRCSTALLCTLR_INSTPRIORITY_Max (0x1UL)  /*!< Max enumerator value of INSTPRIORITY field.                          */
  #define ETM_TRCSTALLCTLR_INSTPRIORITY_Disabled (0x0UL) /*!< The trace unit must not prioritize instruction trace.            */
  #define ETM_TRCSTALLCTLR_INSTPRIORITY_Enabled (0x1UL) /*!< The trace unit can prioritize instruction trace. A trace unit might
                                                             prioritize instruction trace by preventing output of data trace, or
                                                             other means which ensure that the instruction trace has a higher
                                                             priority than the data trace.*/

/* DATADISCARDLOAD @Bit 11 : Data discard field. Controls if a trace unit can discard data trace elements on a load when the
                             data trace buffer space is less than LEVEL. */

  #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos (11UL) /*!< Position of DATADISCARDLOAD field.                                  */
  #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos) /*!< Bit mask of DATADISCARDLOAD
                                                                            field.*/
  #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Min (0x0UL) /*!< Min enumerator value of DATADISCARDLOAD field.                     */
  #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Max (0x1UL) /*!< Max enumerator value of DATADISCARDLOAD field.                     */
  #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements.      */
  #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with
                                                                data loads.*/

/* DATADISCARDSTORE @Bit 12 : Data discard field. Controls if a trace unit can discard data trace elements on a store when the
                              data trace buffer space is less than LEVEL. */

  #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos (12UL) /*!< Position of DATADISCARDSTORE field.                                */
  #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos) /*!< Bit mask of
                                                                            DATADISCARDSTORE field.*/
  #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Min (0x0UL) /*!< Min enumerator value of DATADISCARDSTORE field.                   */
  #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Max (0x1UL) /*!< Max enumerator value of DATADISCARDSTORE field.                   */
  #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements.     */
  #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with
                                                                 data stores.*/

/* NOOVERFLOW @Bit 13 : Trace overflow prevention bit. */
  #define ETM_TRCSTALLCTLR_NOOVERFLOW_Pos (13UL)     /*!< Position of NOOVERFLOW field.                                        */
  #define ETM_TRCSTALLCTLR_NOOVERFLOW_Msk (0x1UL << ETM_TRCSTALLCTLR_NOOVERFLOW_Pos) /*!< Bit mask of NOOVERFLOW field.        */
  #define ETM_TRCSTALLCTLR_NOOVERFLOW_Min (0x0UL)    /*!< Min enumerator value of NOOVERFLOW field.                            */
  #define ETM_TRCSTALLCTLR_NOOVERFLOW_Max (0x1UL)    /*!< Max enumerator value of NOOVERFLOW field.                            */
  #define ETM_TRCSTALLCTLR_NOOVERFLOW_Disabled (0x0UL) /*!< Trace overflow prevention is disabled.                             */
  #define ETM_TRCSTALLCTLR_NOOVERFLOW_Enabled (0x1UL) /*!< Trace overflow prevention is enabled. This might cause a significant
                                                           performance impact.*/


/* ETM_TRCTSCTLR: Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the
                   trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is
                   enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. */

  #define ETM_TRCTSCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCTSCTLR register.                                   */

/* EVENT @Bits 0..7 : Select which event should generate time stamps. */
  #define ETM_TRCTSCTLR_EVENT_Pos (0UL)              /*!< Position of EVENT field.                                             */
  #define ETM_TRCTSCTLR_EVENT_Msk (0xFFUL << ETM_TRCTSCTLR_EVENT_Pos) /*!< Bit mask of EVENT field.                            */
  #define ETM_TRCTSCTLR_EVENT_Min (0x00UL)           /*!< Min value of EVENT field.                                            */
  #define ETM_TRCTSCTLR_EVENT_Max (0xFFUL)           /*!< Max size of EVENT field.                                             */


/* ETM_TRCSYNCPR: Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or
                   not idle. If writes are permitted then the register must be programmed. */

  #define ETM_TRCSYNCPR_ResetValue (0x00000000UL)    /*!< Reset value of TRCSYNCPR register.                                   */

/* PERIOD @Bits 0..4 : Controls how many bytes of trace, the sum of instruction and data, that a trace unit can generate before
                       a trace synchronization request occurs. The number of bytes is always a power of two, calculated by
                       2^PERIOD */

  #define ETM_TRCSYNCPR_PERIOD_Pos (0UL)             /*!< Position of PERIOD field.                                            */
  #define ETM_TRCSYNCPR_PERIOD_Msk (0x1FUL << ETM_TRCSYNCPR_PERIOD_Pos) /*!< Bit mask of PERIOD field.                         */
  #define ETM_TRCSYNCPR_PERIOD_Min (0x00UL)          /*!< Min value of PERIOD field.                                           */
  #define ETM_TRCSYNCPR_PERIOD_Max (0x1FUL)          /*!< Max size of PERIOD field.                                            */
  #define ETM_TRCSYNCPR_PERIOD_Disabled (0x00UL)     /*!< Trace synchronization requests are disabled. This setting does not
                                                          disable other types of trace synchronization request.*/


/* ETM_TRCCCCTLR: Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle.
                   Must be programmed if TRCCONFIGR.CCI==1. */

  #define ETM_TRCCCCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCCCCTLR register.                                   */

/* THRESHOLD @Bits 0..11 : Sets the threshold value for instruction trace cycle counting. */
  #define ETM_TRCCCCTLR_THRESHOLD_Pos (0UL)          /*!< Position of THRESHOLD field.                                         */
  #define ETM_TRCCCCTLR_THRESHOLD_Msk (0xFFFUL << ETM_TRCCCCTLR_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field.               */
  #define ETM_TRCCCCTLR_THRESHOLD_Min (0x000UL)      /*!< Min value of THRESHOLD field.                                        */
  #define ETM_TRCCCCTLR_THRESHOLD_Max (0x7FFUL)      /*!< Max size of THRESHOLD field.                                         */


/* ETM_TRCBBCTLR: Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the
                   trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. */

  #define ETM_TRCBBCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCBBCTLR register.                                   */

/* RANGE0 @Bit 0 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[0] controls the selection of address range
                   comparator pair 0. */

  #define ETM_TRCBBCTLR_RANGE0_Pos (0UL)             /*!< Position of RANGE0 field.                                            */
  #define ETM_TRCBBCTLR_RANGE0_Msk (0x1UL << ETM_TRCBBCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field.                          */
  #define ETM_TRCBBCTLR_RANGE0_Min (0x0UL)           /*!< Min enumerator value of RANGE0 field.                                */
  #define ETM_TRCBBCTLR_RANGE0_Max (0x1UL)           /*!< Max enumerator value of RANGE0 field.                                */
  #define ETM_TRCBBCTLR_RANGE0_Disabled (0x0UL)      /*!< The address range that address range comparator pair 0 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE0_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/

/* RANGE1 @Bit 1 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[1] controls the selection of address range
                   comparator pair 1. */

  #define ETM_TRCBBCTLR_RANGE1_Pos (1UL)             /*!< Position of RANGE1 field.                                            */
  #define ETM_TRCBBCTLR_RANGE1_Msk (0x1UL << ETM_TRCBBCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field.                          */
  #define ETM_TRCBBCTLR_RANGE1_Min (0x0UL)           /*!< Min enumerator value of RANGE1 field.                                */
  #define ETM_TRCBBCTLR_RANGE1_Max (0x1UL)           /*!< Max enumerator value of RANGE1 field.                                */
  #define ETM_TRCBBCTLR_RANGE1_Disabled (0x0UL)      /*!< The address range that address range comparator pair 1 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE1_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/

/* RANGE2 @Bit 2 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[2] controls the selection of address range
                   comparator pair 2. */

  #define ETM_TRCBBCTLR_RANGE2_Pos (2UL)             /*!< Position of RANGE2 field.                                            */
  #define ETM_TRCBBCTLR_RANGE2_Msk (0x1UL << ETM_TRCBBCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field.                          */
  #define ETM_TRCBBCTLR_RANGE2_Min (0x0UL)           /*!< Min enumerator value of RANGE2 field.                                */
  #define ETM_TRCBBCTLR_RANGE2_Max (0x1UL)           /*!< Max enumerator value of RANGE2 field.                                */
  #define ETM_TRCBBCTLR_RANGE2_Disabled (0x0UL)      /*!< The address range that address range comparator pair 2 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE2_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/

/* RANGE3 @Bit 3 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[3] controls the selection of address range
                   comparator pair 3. */

  #define ETM_TRCBBCTLR_RANGE3_Pos (3UL)             /*!< Position of RANGE3 field.                                            */
  #define ETM_TRCBBCTLR_RANGE3_Msk (0x1UL << ETM_TRCBBCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field.                          */
  #define ETM_TRCBBCTLR_RANGE3_Min (0x0UL)           /*!< Min enumerator value of RANGE3 field.                                */
  #define ETM_TRCBBCTLR_RANGE3_Max (0x1UL)           /*!< Max enumerator value of RANGE3 field.                                */
  #define ETM_TRCBBCTLR_RANGE3_Disabled (0x0UL)      /*!< The address range that address range comparator pair 3 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE3_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/

/* RANGE4 @Bit 4 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[4] controls the selection of address range
                   comparator pair 4. */

  #define ETM_TRCBBCTLR_RANGE4_Pos (4UL)             /*!< Position of RANGE4 field.                                            */
  #define ETM_TRCBBCTLR_RANGE4_Msk (0x1UL << ETM_TRCBBCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field.                          */
  #define ETM_TRCBBCTLR_RANGE4_Min (0x0UL)           /*!< Min enumerator value of RANGE4 field.                                */
  #define ETM_TRCBBCTLR_RANGE4_Max (0x1UL)           /*!< Max enumerator value of RANGE4 field.                                */
  #define ETM_TRCBBCTLR_RANGE4_Disabled (0x0UL)      /*!< The address range that address range comparator pair 4 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE4_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/

/* RANGE5 @Bit 5 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[5] controls the selection of address range
                   comparator pair 5. */

  #define ETM_TRCBBCTLR_RANGE5_Pos (5UL)             /*!< Position of RANGE5 field.                                            */
  #define ETM_TRCBBCTLR_RANGE5_Msk (0x1UL << ETM_TRCBBCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field.                          */
  #define ETM_TRCBBCTLR_RANGE5_Min (0x0UL)           /*!< Min enumerator value of RANGE5 field.                                */
  #define ETM_TRCBBCTLR_RANGE5_Max (0x1UL)           /*!< Max enumerator value of RANGE5 field.                                */
  #define ETM_TRCBBCTLR_RANGE5_Disabled (0x0UL)      /*!< The address range that address range comparator pair 5 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE5_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/

/* RANGE6 @Bit 6 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[6] controls the selection of address range
                   comparator pair 6. */

  #define ETM_TRCBBCTLR_RANGE6_Pos (6UL)             /*!< Position of RANGE6 field.                                            */
  #define ETM_TRCBBCTLR_RANGE6_Msk (0x1UL << ETM_TRCBBCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field.                          */
  #define ETM_TRCBBCTLR_RANGE6_Min (0x0UL)           /*!< Min enumerator value of RANGE6 field.                                */
  #define ETM_TRCBBCTLR_RANGE6_Max (0x1UL)           /*!< Max enumerator value of RANGE6 field.                                */
  #define ETM_TRCBBCTLR_RANGE6_Disabled (0x0UL)      /*!< The address range that address range comparator pair 6 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE6_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/

/* RANGE7 @Bit 7 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
                   field represents an address range comparator pair, so field[7] controls the selection of address range
                   comparator pair 7. */

  #define ETM_TRCBBCTLR_RANGE7_Pos (7UL)             /*!< Position of RANGE7 field.                                            */
  #define ETM_TRCBBCTLR_RANGE7_Msk (0x1UL << ETM_TRCBBCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field.                          */
  #define ETM_TRCBBCTLR_RANGE7_Min (0x0UL)           /*!< Min enumerator value of RANGE7 field.                                */
  #define ETM_TRCBBCTLR_RANGE7_Max (0x1UL)           /*!< Max enumerator value of RANGE7 field.                                */
  #define ETM_TRCBBCTLR_RANGE7_Disabled (0x0UL)      /*!< The address range that address range comparator pair 7 defines, is not
                                                          selected.*/
  #define ETM_TRCBBCTLR_RANGE7_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
                                                          selected.*/


/* ETM_TRCTRACEIDR: Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data
                     trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace
                     unit initialization. Might ignore writes when the trace unit is enabled or not idle. */

  #define ETM_TRCTRACEIDR_ResetValue (0x00000000UL)  /*!< Reset value of TRCTRACEIDR register.                                 */

/* TRACEID @Bits 0..6 : Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is
                        enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. */

  #define ETM_TRCTRACEIDR_TRACEID_Pos (0UL)          /*!< Position of TRACEID field.                                           */
  #define ETM_TRCTRACEIDR_TRACEID_Msk (0x7FUL << ETM_TRCTRACEIDR_TRACEID_Pos) /*!< Bit mask of TRACEID field.                  */


/* ETM_TRCQCTLR: Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This
                  register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. */

  #define ETM_TRCQCTLR_ResetValue (0x00000000UL)     /*!< Reset value of TRCQCTLR register.                                    */

/* RANGE0 @Bit 0 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE0_Pos (0UL)              /*!< Position of RANGE0 field.                                            */
  #define ETM_TRCQCTLR_RANGE0_Msk (0x1UL << ETM_TRCQCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field.                            */
  #define ETM_TRCQCTLR_RANGE0_Min (0x0UL)            /*!< Min enumerator value of RANGE0 field.                                */
  #define ETM_TRCQCTLR_RANGE0_Max (0x1UL)            /*!< Max enumerator value of RANGE0 field.                                */
  #define ETM_TRCQCTLR_RANGE0_Disabled (0x0UL)       /*!< Address range comparator 0 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE0_Enabled (0x1UL)        /*!< Address range comparator 0 is selected for use.                      */

/* RANGE1 @Bit 1 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE1_Pos (1UL)              /*!< Position of RANGE1 field.                                            */
  #define ETM_TRCQCTLR_RANGE1_Msk (0x1UL << ETM_TRCQCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field.                            */
  #define ETM_TRCQCTLR_RANGE1_Min (0x0UL)            /*!< Min enumerator value of RANGE1 field.                                */
  #define ETM_TRCQCTLR_RANGE1_Max (0x1UL)            /*!< Max enumerator value of RANGE1 field.                                */
  #define ETM_TRCQCTLR_RANGE1_Disabled (0x0UL)       /*!< Address range comparator 1 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE1_Enabled (0x1UL)        /*!< Address range comparator 1 is selected for use.                      */

/* RANGE2 @Bit 2 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE2_Pos (2UL)              /*!< Position of RANGE2 field.                                            */
  #define ETM_TRCQCTLR_RANGE2_Msk (0x1UL << ETM_TRCQCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field.                            */
  #define ETM_TRCQCTLR_RANGE2_Min (0x0UL)            /*!< Min enumerator value of RANGE2 field.                                */
  #define ETM_TRCQCTLR_RANGE2_Max (0x1UL)            /*!< Max enumerator value of RANGE2 field.                                */
  #define ETM_TRCQCTLR_RANGE2_Disabled (0x0UL)       /*!< Address range comparator 2 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE2_Enabled (0x1UL)        /*!< Address range comparator 2 is selected for use.                      */

/* RANGE3 @Bit 3 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE3_Pos (3UL)              /*!< Position of RANGE3 field.                                            */
  #define ETM_TRCQCTLR_RANGE3_Msk (0x1UL << ETM_TRCQCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field.                            */
  #define ETM_TRCQCTLR_RANGE3_Min (0x0UL)            /*!< Min enumerator value of RANGE3 field.                                */
  #define ETM_TRCQCTLR_RANGE3_Max (0x1UL)            /*!< Max enumerator value of RANGE3 field.                                */
  #define ETM_TRCQCTLR_RANGE3_Disabled (0x0UL)       /*!< Address range comparator 3 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE3_Enabled (0x1UL)        /*!< Address range comparator 3 is selected for use.                      */

/* RANGE4 @Bit 4 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE4_Pos (4UL)              /*!< Position of RANGE4 field.                                            */
  #define ETM_TRCQCTLR_RANGE4_Msk (0x1UL << ETM_TRCQCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field.                            */
  #define ETM_TRCQCTLR_RANGE4_Min (0x0UL)            /*!< Min enumerator value of RANGE4 field.                                */
  #define ETM_TRCQCTLR_RANGE4_Max (0x1UL)            /*!< Max enumerator value of RANGE4 field.                                */
  #define ETM_TRCQCTLR_RANGE4_Disabled (0x0UL)       /*!< Address range comparator 4 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE4_Enabled (0x1UL)        /*!< Address range comparator 4 is selected for use.                      */

/* RANGE5 @Bit 5 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE5_Pos (5UL)              /*!< Position of RANGE5 field.                                            */
  #define ETM_TRCQCTLR_RANGE5_Msk (0x1UL << ETM_TRCQCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field.                            */
  #define ETM_TRCQCTLR_RANGE5_Min (0x0UL)            /*!< Min enumerator value of RANGE5 field.                                */
  #define ETM_TRCQCTLR_RANGE5_Max (0x1UL)            /*!< Max enumerator value of RANGE5 field.                                */
  #define ETM_TRCQCTLR_RANGE5_Disabled (0x0UL)       /*!< Address range comparator 5 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE5_Enabled (0x1UL)        /*!< Address range comparator 5 is selected for use.                      */

/* RANGE6 @Bit 6 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE6_Pos (6UL)              /*!< Position of RANGE6 field.                                            */
  #define ETM_TRCQCTLR_RANGE6_Msk (0x1UL << ETM_TRCQCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field.                            */
  #define ETM_TRCQCTLR_RANGE6_Min (0x0UL)            /*!< Min enumerator value of RANGE6 field.                                */
  #define ETM_TRCQCTLR_RANGE6_Max (0x1UL)            /*!< Max enumerator value of RANGE6 field.                                */
  #define ETM_TRCQCTLR_RANGE6_Disabled (0x0UL)       /*!< Address range comparator 6 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE6_Enabled (0x1UL)        /*!< Address range comparator 6 is selected for use.                      */

/* RANGE7 @Bit 7 : Specifies the address range comparators to be used for controlling Q elements. */
  #define ETM_TRCQCTLR_RANGE7_Pos (7UL)              /*!< Position of RANGE7 field.                                            */
  #define ETM_TRCQCTLR_RANGE7_Msk (0x1UL << ETM_TRCQCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field.                            */
  #define ETM_TRCQCTLR_RANGE7_Min (0x0UL)            /*!< Min enumerator value of RANGE7 field.                                */
  #define ETM_TRCQCTLR_RANGE7_Max (0x1UL)            /*!< Max enumerator value of RANGE7 field.                                */
  #define ETM_TRCQCTLR_RANGE7_Disabled (0x0UL)       /*!< Address range comparator 7 is disabled.                              */
  #define ETM_TRCQCTLR_RANGE7_Enabled (0x1UL)        /*!< Address range comparator 7 is selected for use.                      */

/* MODE @Bit 8 : Selects whether the address range comparators selected by the RANGE field indicate address ranges where the
                 trace unit is permitted to generate Q elements or address ranges where the trace unit is not permitted to
                 generate Q elements: */

  #define ETM_TRCQCTLR_MODE_Pos (8UL)                /*!< Position of MODE field.                                              */
  #define ETM_TRCQCTLR_MODE_Msk (0x1UL << ETM_TRCQCTLR_MODE_Pos) /*!< Bit mask of MODE field.                                  */
  #define ETM_TRCQCTLR_MODE_Min (0x0UL)              /*!< Min enumerator value of MODE field.                                  */
  #define ETM_TRCQCTLR_MODE_Max (0x1UL)              /*!< Max enumerator value of MODE field.                                  */
  #define ETM_TRCQCTLR_MODE_Exclude (0x0UL)          /*!< Exclude mode. The address range comparators selected by the RANGE
                                                          field indicate address ranges where the trace unit cannot generate Q
                                                          elements. If no ranges are selected, Q elements are permitted across
                                                          the entire memory map.*/
  #define ETM_TRCQCTLR_MODE_Include (0x1UL)          /*!< Include mode. The address range comparators selected by the RANGE
                                                          field indicate address ranges where the trace unit can generate Q
                                                          elements. If all the implemented bits in RANGE are set to 0 then Q
                                                          elements are disabled.*/


/* ETM_TRCVICTLR: Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only
                   returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the
                   SSSTATUS bit, which sets the state of the start/stop logic. */

  #define ETM_TRCVICTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCVICTLR register.                                   */

/* EVENT_SEL @Bits 0..4 : Select which resource number should be filtered. */
  #define ETM_TRCVICTLR_EVENT_SEL_Pos (0UL)          /*!< Position of EVENT_SEL field.                                         */
  #define ETM_TRCVICTLR_EVENT_SEL_Msk (0x1FUL << ETM_TRCVICTLR_EVENT_SEL_Pos) /*!< Bit mask of EVENT_SEL field.                */
  #define ETM_TRCVICTLR_EVENT_SEL_Min (0x0UL)        /*!< Min enumerator value of EVENT_SEL field.                             */
  #define ETM_TRCVICTLR_EVENT_SEL_Max (0x1UL)        /*!< Max enumerator value of EVENT_SEL field.                             */
  #define ETM_TRCVICTLR_EVENT_SEL_Disabled (0x00UL)  /*!< This event is not filtered.                                          */
  #define ETM_TRCVICTLR_EVENT_SEL_Enabled (0x01UL)   /*!< This event is filtered.                                              */

/* SSSTATUS @Bit 9 : When TRCIDR4.NUMACPAIRS > 0 or TRCIDR4.NUMPC > 0, this bit returns the status of the start/stop logic. */
  #define ETM_TRCVICTLR_SSSTATUS_Pos (9UL)           /*!< Position of SSSTATUS field.                                          */
  #define ETM_TRCVICTLR_SSSTATUS_Msk (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos) /*!< Bit mask of SSSTATUS field.                    */
  #define ETM_TRCVICTLR_SSSTATUS_Min (0x0UL)         /*!< Min enumerator value of SSSTATUS field.                              */
  #define ETM_TRCVICTLR_SSSTATUS_Max (0x1UL)         /*!< Max enumerator value of SSSTATUS field.                              */
  #define ETM_TRCVICTLR_SSSTATUS_Stopped (0x0UL)     /*!< The start/stop logic is in the stopped state.                        */
  #define ETM_TRCVICTLR_SSSTATUS_Started (0x1UL)     /*!< The start/stop logic is in the started state.                        */

/* TRCRESET @Bit 10 : Controls whether a trace unit must trace a Reset exception. */
  #define ETM_TRCVICTLR_TRCRESET_Pos (10UL)          /*!< Position of TRCRESET field.                                          */
  #define ETM_TRCVICTLR_TRCRESET_Msk (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos) /*!< Bit mask of TRCRESET field.                    */
  #define ETM_TRCVICTLR_TRCRESET_Min (0x0UL)         /*!< Min enumerator value of TRCRESET field.                              */
  #define ETM_TRCVICTLR_TRCRESET_Max (0x1UL)         /*!< Max enumerator value of TRCRESET field.                              */
  #define ETM_TRCVICTLR_TRCRESET_Disabled (0x0UL)    /*!< The trace unit does not trace a Reset exception unless it traces the
                                                          exception or instruction immediately prior to the Reset exception.*/
  #define ETM_TRCVICTLR_TRCRESET_Enabled (0x1UL)     /*!< The trace unit always traces a Reset exception.                      */

/* TRCERR @Bit 11 : When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. */
  #define ETM_TRCVICTLR_TRCERR_Pos (11UL)            /*!< Position of TRCERR field.                                            */
  #define ETM_TRCVICTLR_TRCERR_Msk (0x1UL << ETM_TRCVICTLR_TRCERR_Pos) /*!< Bit mask of TRCERR field.                          */
  #define ETM_TRCVICTLR_TRCERR_Min (0x0UL)           /*!< Min enumerator value of TRCERR field.                                */
  #define ETM_TRCVICTLR_TRCERR_Max (0x1UL)           /*!< Max enumerator value of TRCERR field.                                */
  #define ETM_TRCVICTLR_TRCERR_Disabled (0x0UL)      /*!< The trace unit does not trace a System error exception unless it
                                                          traces the exception or instruction immediately prior to the System
                                                          error exception.*/
  #define ETM_TRCVICTLR_TRCERR_Enabled (0x1UL)       /*!< The trace unit always traces a System error exception, regardless of
                                                          the value of ViewInst.*/

/* EXLEVEL0_S @Bit 16 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
                        Exception level 0. */

  #define ETM_TRCVICTLR_EXLEVEL0_S_Pos (16UL)        /*!< Position of EXLEVEL0_S field.                                        */
  #define ETM_TRCVICTLR_EXLEVEL0_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_S_Pos) /*!< Bit mask of EXLEVEL0_S field.              */
  #define ETM_TRCVICTLR_EXLEVEL0_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL0_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL0_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL0_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL0_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
                                                          for Exception level 0.*/
  #define ETM_TRCVICTLR_EXLEVEL0_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
                                                          Exception level 0.*/

/* EXLEVEL1_S @Bit 17 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
                        Exception level 1. */

  #define ETM_TRCVICTLR_EXLEVEL1_S_Pos (17UL)        /*!< Position of EXLEVEL1_S field.                                        */
  #define ETM_TRCVICTLR_EXLEVEL1_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_S_Pos) /*!< Bit mask of EXLEVEL1_S field.              */
  #define ETM_TRCVICTLR_EXLEVEL1_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL1_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL1_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL1_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL1_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
                                                          for Exception level 1.*/
  #define ETM_TRCVICTLR_EXLEVEL1_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
                                                          Exception level 1.*/

/* EXLEVEL2_S @Bit 18 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
                        Exception level 2. */

  #define ETM_TRCVICTLR_EXLEVEL2_S_Pos (18UL)        /*!< Position of EXLEVEL2_S field.                                        */
  #define ETM_TRCVICTLR_EXLEVEL2_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_S_Pos) /*!< Bit mask of EXLEVEL2_S field.              */
  #define ETM_TRCVICTLR_EXLEVEL2_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL2_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL2_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL2_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL2_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
                                                          for Exception level 2.*/
  #define ETM_TRCVICTLR_EXLEVEL2_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
                                                          Exception level 2.*/

/* EXLEVEL3_S @Bit 19 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
                        Exception level 3. */

  #define ETM_TRCVICTLR_EXLEVEL3_S_Pos (19UL)        /*!< Position of EXLEVEL3_S field.                                        */
  #define ETM_TRCVICTLR_EXLEVEL3_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_S_Pos) /*!< Bit mask of EXLEVEL3_S field.              */
  #define ETM_TRCVICTLR_EXLEVEL3_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL3_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL3_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL3_S field.                            */
  #define ETM_TRCVICTLR_EXLEVEL3_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
                                                          for Exception level 3.*/
  #define ETM_TRCVICTLR_EXLEVEL3_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
                                                          Exception level 3.*/

/* EXLEVEL0_NS @Bit 20 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
                         Exception level 0. */

  #define ETM_TRCVICTLR_EXLEVEL0_NS_Pos (20UL)       /*!< Position of EXLEVEL0_NS field.                                       */
  #define ETM_TRCVICTLR_EXLEVEL0_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_NS_Pos) /*!< Bit mask of EXLEVEL0_NS field.           */
  #define ETM_TRCVICTLR_EXLEVEL0_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL0_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL0_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL0_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL0_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
                                                          state, for Exception level 0.*/
  #define ETM_TRCVICTLR_EXLEVEL0_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
                                                          Exception level 0.*/

/* EXLEVEL1_NS @Bit 21 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
                         Exception level 1. */

  #define ETM_TRCVICTLR_EXLEVEL1_NS_Pos (21UL)       /*!< Position of EXLEVEL1_NS field.                                       */
  #define ETM_TRCVICTLR_EXLEVEL1_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_NS_Pos) /*!< Bit mask of EXLEVEL1_NS field.           */
  #define ETM_TRCVICTLR_EXLEVEL1_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL1_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL1_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL1_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL1_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
                                                          state, for Exception level 1.*/
  #define ETM_TRCVICTLR_EXLEVEL1_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
                                                          Exception level 1.*/

/* EXLEVEL2_NS @Bit 22 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
                         Exception level 2. */

  #define ETM_TRCVICTLR_EXLEVEL2_NS_Pos (22UL)       /*!< Position of EXLEVEL2_NS field.                                       */
  #define ETM_TRCVICTLR_EXLEVEL2_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_NS_Pos) /*!< Bit mask of EXLEVEL2_NS field.           */
  #define ETM_TRCVICTLR_EXLEVEL2_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL2_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL2_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL2_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL2_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
                                                          state, for Exception level 2.*/
  #define ETM_TRCVICTLR_EXLEVEL2_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
                                                          Exception level 2.*/

/* EXLEVEL3_NS @Bit 23 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
                         Exception level 3. */

  #define ETM_TRCVICTLR_EXLEVEL3_NS_Pos (23UL)       /*!< Position of EXLEVEL3_NS field.                                       */
  #define ETM_TRCVICTLR_EXLEVEL3_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_NS_Pos) /*!< Bit mask of EXLEVEL3_NS field.           */
  #define ETM_TRCVICTLR_EXLEVEL3_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL3_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL3_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL3_NS field.                           */
  #define ETM_TRCVICTLR_EXLEVEL3_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
                                                          state, for Exception level 3.*/
  #define ETM_TRCVICTLR_EXLEVEL3_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
                                                          Exception level 3.*/


/* ETM_TRCVIIECTLR: ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must
                     be programmed when one or more address comparators are implemented. */

  #define ETM_TRCVIIECTLR_ResetValue (0x00000000UL)  /*!< Reset value of TRCVIIECTLR register.                                 */

/* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE0_Pos (0UL)         /*!< Position of INCLUDE0 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE0_Min (0x0UL)       /*!< Min enumerator value of INCLUDE0 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE0_Max (0x1UL)       /*!< Max enumerator value of INCLUDE0 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE0_Disabled (0x0UL)  /*!< The address range that address range comparator pair 0 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE0_Enabled (0x1UL)   /*!< The address range that address range comparator pair 0 defines, is
                                                          selected for ViewInst include control.*/

/* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE1_Pos (1UL)         /*!< Position of INCLUDE1 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE1_Min (0x0UL)       /*!< Min enumerator value of INCLUDE1 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE1_Max (0x1UL)       /*!< Max enumerator value of INCLUDE1 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE1_Disabled (0x0UL)  /*!< The address range that address range comparator pair 1 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE1_Enabled (0x1UL)   /*!< The address range that address range comparator pair 1 defines, is
                                                          selected for ViewInst include control.*/

/* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE2_Pos (2UL)         /*!< Position of INCLUDE2 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE2_Min (0x0UL)       /*!< Min enumerator value of INCLUDE2 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE2_Max (0x1UL)       /*!< Max enumerator value of INCLUDE2 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE2_Disabled (0x0UL)  /*!< The address range that address range comparator pair 2 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE2_Enabled (0x1UL)   /*!< The address range that address range comparator pair 2 defines, is
                                                          selected for ViewInst include control.*/

/* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE3_Pos (3UL)         /*!< Position of INCLUDE3 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE3_Min (0x0UL)       /*!< Min enumerator value of INCLUDE3 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE3_Max (0x1UL)       /*!< Max enumerator value of INCLUDE3 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE3_Disabled (0x0UL)  /*!< The address range that address range comparator pair 3 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE3_Enabled (0x1UL)   /*!< The address range that address range comparator pair 3 defines, is
                                                          selected for ViewInst include control.*/

/* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE4_Pos (4UL)         /*!< Position of INCLUDE4 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE4_Min (0x0UL)       /*!< Min enumerator value of INCLUDE4 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE4_Max (0x1UL)       /*!< Max enumerator value of INCLUDE4 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE4_Disabled (0x0UL)  /*!< The address range that address range comparator pair 4 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE4_Enabled (0x1UL)   /*!< The address range that address range comparator pair 4 defines, is
                                                          selected for ViewInst include control.*/

/* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE5_Pos (5UL)         /*!< Position of INCLUDE5 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE5_Min (0x0UL)       /*!< Min enumerator value of INCLUDE5 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE5_Max (0x1UL)       /*!< Max enumerator value of INCLUDE5 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE5_Disabled (0x0UL)  /*!< The address range that address range comparator pair 5 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE5_Enabled (0x1UL)   /*!< The address range that address range comparator pair 5 defines, is
                                                          selected for ViewInst include control.*/

/* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE6_Pos (6UL)         /*!< Position of INCLUDE6 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE6_Min (0x0UL)       /*!< Min enumerator value of INCLUDE6 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE6_Max (0x1UL)       /*!< Max enumerator value of INCLUDE6 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE6_Disabled (0x0UL)  /*!< The address range that address range comparator pair 6 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE6_Enabled (0x1UL)   /*!< The address range that address range comparator pair 6 defines, is
                                                          selected for ViewInst include control.*/

/* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
                     */

  #define ETM_TRCVIIECTLR_INCLUDE7_Pos (7UL)         /*!< Position of INCLUDE7 field.                                          */
  #define ETM_TRCVIIECTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field.                */
  #define ETM_TRCVIIECTLR_INCLUDE7_Min (0x0UL)       /*!< Min enumerator value of INCLUDE7 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE7_Max (0x1UL)       /*!< Max enumerator value of INCLUDE7 field.                              */
  #define ETM_TRCVIIECTLR_INCLUDE7_Disabled (0x0UL)  /*!< The address range that address range comparator pair 7 defines, is not
                                                          selected for ViewInst include control.*/
  #define ETM_TRCVIIECTLR_INCLUDE7_Enabled (0x1UL)   /*!< The address range that address range comparator pair 7 defines, is
                                                          selected for ViewInst include control.*/

/* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE0_Pos (16UL)        /*!< Position of EXCLUDE0 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE0_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE0 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE0_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE0 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE0_Disabled (0x0UL)  /*!< The address range that address range comparator pair 0 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE0_Enabled (0x1UL)   /*!< The address range that address range comparator pair 0 defines, is
                                                          selected for ViewInst exclude control.*/

/* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE1_Pos (17UL)        /*!< Position of EXCLUDE1 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE1_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE1 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE1_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE1 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE1_Disabled (0x0UL)  /*!< The address range that address range comparator pair 1 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE1_Enabled (0x1UL)   /*!< The address range that address range comparator pair 1 defines, is
                                                          selected for ViewInst exclude control.*/

/* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE2_Pos (18UL)        /*!< Position of EXCLUDE2 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE2_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE2 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE2_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE2 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE2_Disabled (0x0UL)  /*!< The address range that address range comparator pair 2 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE2_Enabled (0x1UL)   /*!< The address range that address range comparator pair 2 defines, is
                                                          selected for ViewInst exclude control.*/

/* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE3_Pos (19UL)        /*!< Position of EXCLUDE3 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE3_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE3 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE3_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE3 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE3_Disabled (0x0UL)  /*!< The address range that address range comparator pair 3 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE3_Enabled (0x1UL)   /*!< The address range that address range comparator pair 3 defines, is
                                                          selected for ViewInst exclude control.*/

/* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE4_Pos (20UL)        /*!< Position of EXCLUDE4 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE4_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE4 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE4_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE4 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE4_Disabled (0x0UL)  /*!< The address range that address range comparator pair 4 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE4_Enabled (0x1UL)   /*!< The address range that address range comparator pair 4 defines, is
                                                          selected for ViewInst exclude control.*/

/* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE5_Pos (21UL)        /*!< Position of EXCLUDE5 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE5_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE5 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE5_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE5 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE5_Disabled (0x0UL)  /*!< The address range that address range comparator pair 5 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE5_Enabled (0x1UL)   /*!< The address range that address range comparator pair 5 defines, is
                                                          selected for ViewInst exclude control.*/

/* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE6_Pos (22UL)        /*!< Position of EXCLUDE6 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE6_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE6 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE6_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE6 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE6_Disabled (0x0UL)  /*!< The address range that address range comparator pair 6 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE6_Enabled (0x1UL)   /*!< The address range that address range comparator pair 6 defines, is
                                                          selected for ViewInst exclude control.*/

/* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
                      control. */

  #define ETM_TRCVIIECTLR_EXCLUDE7_Pos (23UL)        /*!< Position of EXCLUDE7 field.                                          */
  #define ETM_TRCVIIECTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field.                */
  #define ETM_TRCVIIECTLR_EXCLUDE7_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE7 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE7_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE7 field.                              */
  #define ETM_TRCVIIECTLR_EXCLUDE7_Disabled (0x0UL)  /*!< The address range that address range comparator pair 7 defines, is not
                                                          selected for ViewInst exclude control.*/
  #define ETM_TRCVIIECTLR_EXCLUDE7_Enabled (0x1UL)   /*!< The address range that address range comparator pair 7 defines, is
                                                          selected for ViewInst exclude control.*/


/* ETM_TRCVISSCTLR: Use this to set, or read, the single address comparators that control the ViewInst start/stop logic. The
                     start/stop logic is active for an instruction which causes a start and remains active up to and including
                     an instruction which causes a stop, and then the start/stop logic becomes inactive. Might ignore writes
                     when the trace unit is enabled or not idle. If implemented then this register must be programmed. */

  #define ETM_TRCVISSCTLR_ResetValue (0x00000000UL)  /*!< Reset value of TRCVISSCTLR register.                                 */

/* START0 @Bit 0 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START0_Pos (0UL)           /*!< Position of START0 field.                                            */
  #define ETM_TRCVISSCTLR_START0_Msk (0x1UL << ETM_TRCVISSCTLR_START0_Pos) /*!< Bit mask of START0 field.                      */
  #define ETM_TRCVISSCTLR_START0_Min (0x0UL)         /*!< Min enumerator value of START0 field.                                */
  #define ETM_TRCVISSCTLR_START0_Max (0x1UL)         /*!< Max enumerator value of START0 field.                                */
  #define ETM_TRCVISSCTLR_START0_Disabled (0x0UL)    /*!< The single address comparator 0, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START0_Enabled (0x1UL)     /*!< The single address comparator 0, is selected as a start resource.    */

/* START1 @Bit 1 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START1_Pos (1UL)           /*!< Position of START1 field.                                            */
  #define ETM_TRCVISSCTLR_START1_Msk (0x1UL << ETM_TRCVISSCTLR_START1_Pos) /*!< Bit mask of START1 field.                      */
  #define ETM_TRCVISSCTLR_START1_Min (0x0UL)         /*!< Min enumerator value of START1 field.                                */
  #define ETM_TRCVISSCTLR_START1_Max (0x1UL)         /*!< Max enumerator value of START1 field.                                */
  #define ETM_TRCVISSCTLR_START1_Disabled (0x0UL)    /*!< The single address comparator 1, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START1_Enabled (0x1UL)     /*!< The single address comparator 1, is selected as a start resource.    */

/* START2 @Bit 2 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START2_Pos (2UL)           /*!< Position of START2 field.                                            */
  #define ETM_TRCVISSCTLR_START2_Msk (0x1UL << ETM_TRCVISSCTLR_START2_Pos) /*!< Bit mask of START2 field.                      */
  #define ETM_TRCVISSCTLR_START2_Min (0x0UL)         /*!< Min enumerator value of START2 field.                                */
  #define ETM_TRCVISSCTLR_START2_Max (0x1UL)         /*!< Max enumerator value of START2 field.                                */
  #define ETM_TRCVISSCTLR_START2_Disabled (0x0UL)    /*!< The single address comparator 2, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START2_Enabled (0x1UL)     /*!< The single address comparator 2, is selected as a start resource.    */

/* START3 @Bit 3 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START3_Pos (3UL)           /*!< Position of START3 field.                                            */
  #define ETM_TRCVISSCTLR_START3_Msk (0x1UL << ETM_TRCVISSCTLR_START3_Pos) /*!< Bit mask of START3 field.                      */
  #define ETM_TRCVISSCTLR_START3_Min (0x0UL)         /*!< Min enumerator value of START3 field.                                */
  #define ETM_TRCVISSCTLR_START3_Max (0x1UL)         /*!< Max enumerator value of START3 field.                                */
  #define ETM_TRCVISSCTLR_START3_Disabled (0x0UL)    /*!< The single address comparator 3, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START3_Enabled (0x1UL)     /*!< The single address comparator 3, is selected as a start resource.    */

/* START4 @Bit 4 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START4_Pos (4UL)           /*!< Position of START4 field.                                            */
  #define ETM_TRCVISSCTLR_START4_Msk (0x1UL << ETM_TRCVISSCTLR_START4_Pos) /*!< Bit mask of START4 field.                      */
  #define ETM_TRCVISSCTLR_START4_Min (0x0UL)         /*!< Min enumerator value of START4 field.                                */
  #define ETM_TRCVISSCTLR_START4_Max (0x1UL)         /*!< Max enumerator value of START4 field.                                */
  #define ETM_TRCVISSCTLR_START4_Disabled (0x0UL)    /*!< The single address comparator 4, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START4_Enabled (0x1UL)     /*!< The single address comparator 4, is selected as a start resource.    */

/* START5 @Bit 5 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START5_Pos (5UL)           /*!< Position of START5 field.                                            */
  #define ETM_TRCVISSCTLR_START5_Msk (0x1UL << ETM_TRCVISSCTLR_START5_Pos) /*!< Bit mask of START5 field.                      */
  #define ETM_TRCVISSCTLR_START5_Min (0x0UL)         /*!< Min enumerator value of START5 field.                                */
  #define ETM_TRCVISSCTLR_START5_Max (0x1UL)         /*!< Max enumerator value of START5 field.                                */
  #define ETM_TRCVISSCTLR_START5_Disabled (0x0UL)    /*!< The single address comparator 5, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START5_Enabled (0x1UL)     /*!< The single address comparator 5, is selected as a start resource.    */

/* START6 @Bit 6 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START6_Pos (6UL)           /*!< Position of START6 field.                                            */
  #define ETM_TRCVISSCTLR_START6_Msk (0x1UL << ETM_TRCVISSCTLR_START6_Pos) /*!< Bit mask of START6 field.                      */
  #define ETM_TRCVISSCTLR_START6_Min (0x0UL)         /*!< Min enumerator value of START6 field.                                */
  #define ETM_TRCVISSCTLR_START6_Max (0x1UL)         /*!< Max enumerator value of START6 field.                                */
  #define ETM_TRCVISSCTLR_START6_Disabled (0x0UL)    /*!< The single address comparator 6, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START6_Enabled (0x1UL)     /*!< The single address comparator 6, is selected as a start resource.    */

/* START7 @Bit 7 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   starting trace. */

  #define ETM_TRCVISSCTLR_START7_Pos (7UL)           /*!< Position of START7 field.                                            */
  #define ETM_TRCVISSCTLR_START7_Msk (0x1UL << ETM_TRCVISSCTLR_START7_Pos) /*!< Bit mask of START7 field.                      */
  #define ETM_TRCVISSCTLR_START7_Min (0x0UL)         /*!< Min enumerator value of START7 field.                                */
  #define ETM_TRCVISSCTLR_START7_Max (0x1UL)         /*!< Max enumerator value of START7 field.                                */
  #define ETM_TRCVISSCTLR_START7_Disabled (0x0UL)    /*!< The single address comparator 7, is not selected as a start resource.*/
  #define ETM_TRCVISSCTLR_START7_Enabled (0x1UL)     /*!< The single address comparator 7, is selected as a start resource.    */

/* STOP0 @Bit 16 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP0_Pos (16UL)           /*!< Position of STOP0 field.                                             */
  #define ETM_TRCVISSCTLR_STOP0_Msk (0x1UL << ETM_TRCVISSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field.                         */
  #define ETM_TRCVISSCTLR_STOP0_Min (0x0UL)          /*!< Min enumerator value of STOP0 field.                                 */
  #define ETM_TRCVISSCTLR_STOP0_Max (0x1UL)          /*!< Max enumerator value of STOP0 field.                                 */
  #define ETM_TRCVISSCTLR_STOP0_Disabled (0x0UL)     /*!< The single address comparator 0, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP0_Enabled (0x1UL)      /*!< The single address comparator 0, is selected as a stop resource.     */

/* STOP1 @Bit 17 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP1_Pos (17UL)           /*!< Position of STOP1 field.                                             */
  #define ETM_TRCVISSCTLR_STOP1_Msk (0x1UL << ETM_TRCVISSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field.                         */
  #define ETM_TRCVISSCTLR_STOP1_Min (0x0UL)          /*!< Min enumerator value of STOP1 field.                                 */
  #define ETM_TRCVISSCTLR_STOP1_Max (0x1UL)          /*!< Max enumerator value of STOP1 field.                                 */
  #define ETM_TRCVISSCTLR_STOP1_Disabled (0x0UL)     /*!< The single address comparator 1, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP1_Enabled (0x1UL)      /*!< The single address comparator 1, is selected as a stop resource.     */

/* STOP2 @Bit 18 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP2_Pos (18UL)           /*!< Position of STOP2 field.                                             */
  #define ETM_TRCVISSCTLR_STOP2_Msk (0x1UL << ETM_TRCVISSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field.                         */
  #define ETM_TRCVISSCTLR_STOP2_Min (0x0UL)          /*!< Min enumerator value of STOP2 field.                                 */
  #define ETM_TRCVISSCTLR_STOP2_Max (0x1UL)          /*!< Max enumerator value of STOP2 field.                                 */
  #define ETM_TRCVISSCTLR_STOP2_Disabled (0x0UL)     /*!< The single address comparator 2, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP2_Enabled (0x1UL)      /*!< The single address comparator 2, is selected as a stop resource.     */

/* STOP3 @Bit 19 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP3_Pos (19UL)           /*!< Position of STOP3 field.                                             */
  #define ETM_TRCVISSCTLR_STOP3_Msk (0x1UL << ETM_TRCVISSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field.                         */
  #define ETM_TRCVISSCTLR_STOP3_Min (0x0UL)          /*!< Min enumerator value of STOP3 field.                                 */
  #define ETM_TRCVISSCTLR_STOP3_Max (0x1UL)          /*!< Max enumerator value of STOP3 field.                                 */
  #define ETM_TRCVISSCTLR_STOP3_Disabled (0x0UL)     /*!< The single address comparator 3, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP3_Enabled (0x1UL)      /*!< The single address comparator 3, is selected as a stop resource.     */

/* STOP4 @Bit 20 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP4_Pos (20UL)           /*!< Position of STOP4 field.                                             */
  #define ETM_TRCVISSCTLR_STOP4_Msk (0x1UL << ETM_TRCVISSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field.                         */
  #define ETM_TRCVISSCTLR_STOP4_Min (0x0UL)          /*!< Min enumerator value of STOP4 field.                                 */
  #define ETM_TRCVISSCTLR_STOP4_Max (0x1UL)          /*!< Max enumerator value of STOP4 field.                                 */
  #define ETM_TRCVISSCTLR_STOP4_Disabled (0x0UL)     /*!< The single address comparator 4, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP4_Enabled (0x1UL)      /*!< The single address comparator 4, is selected as a stop resource.     */

/* STOP5 @Bit 21 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP5_Pos (21UL)           /*!< Position of STOP5 field.                                             */
  #define ETM_TRCVISSCTLR_STOP5_Msk (0x1UL << ETM_TRCVISSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field.                         */
  #define ETM_TRCVISSCTLR_STOP5_Min (0x0UL)          /*!< Min enumerator value of STOP5 field.                                 */
  #define ETM_TRCVISSCTLR_STOP5_Max (0x1UL)          /*!< Max enumerator value of STOP5 field.                                 */
  #define ETM_TRCVISSCTLR_STOP5_Disabled (0x0UL)     /*!< The single address comparator 5, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP5_Enabled (0x1UL)      /*!< The single address comparator 5, is selected as a stop resource.     */

/* STOP6 @Bit 22 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP6_Pos (22UL)           /*!< Position of STOP6 field.                                             */
  #define ETM_TRCVISSCTLR_STOP6_Msk (0x1UL << ETM_TRCVISSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field.                         */
  #define ETM_TRCVISSCTLR_STOP6_Min (0x0UL)          /*!< Min enumerator value of STOP6 field.                                 */
  #define ETM_TRCVISSCTLR_STOP6_Max (0x1UL)          /*!< Max enumerator value of STOP6 field.                                 */
  #define ETM_TRCVISSCTLR_STOP6_Disabled (0x0UL)     /*!< The single address comparator 6, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP6_Enabled (0x1UL)      /*!< The single address comparator 6, is selected as a stop resource.     */

/* STOP7 @Bit 23 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
                   stopping trace */

  #define ETM_TRCVISSCTLR_STOP7_Pos (23UL)           /*!< Position of STOP7 field.                                             */
  #define ETM_TRCVISSCTLR_STOP7_Msk (0x1UL << ETM_TRCVISSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field.                         */
  #define ETM_TRCVISSCTLR_STOP7_Min (0x0UL)          /*!< Min enumerator value of STOP7 field.                                 */
  #define ETM_TRCVISSCTLR_STOP7_Max (0x1UL)          /*!< Max enumerator value of STOP7 field.                                 */
  #define ETM_TRCVISSCTLR_STOP7_Disabled (0x0UL)     /*!< The single address comparator 7, is not selected as a stop resource. */
  #define ETM_TRCVISSCTLR_STOP7_Enabled (0x1UL)      /*!< The single address comparator 7, is selected as a stop resource.     */


/* ETM_TRCVIPCSSCTLR: Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might
                       ignore writes when the trace unit is enabled or not idle. If implemented then this register must be
                       programmed. */

  #define ETM_TRCVIPCSSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVIPCSSCTLR register.                              */

/* START0 @Bit 0 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START0_Pos (0UL)         /*!< Position of START0 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START0_Pos) /*!< Bit mask of START0 field.                  */
  #define ETM_TRCVIPCSSCTLR_START0_Min (0x0UL)       /*!< Min enumerator value of START0 field.                                */
  #define ETM_TRCVIPCSSCTLR_START0_Max (0x1UL)       /*!< Max enumerator value of START0 field.                                */
  #define ETM_TRCVIPCSSCTLR_START0_Disabled (0x0UL)  /*!< The single PE comparator input 0, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START0_Enabled (0x1UL)   /*!< The single PE comparator input 0, is selected as a start resource.   */

/* START1 @Bit 1 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START1_Pos (1UL)         /*!< Position of START1 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START1_Pos) /*!< Bit mask of START1 field.                  */
  #define ETM_TRCVIPCSSCTLR_START1_Min (0x0UL)       /*!< Min enumerator value of START1 field.                                */
  #define ETM_TRCVIPCSSCTLR_START1_Max (0x1UL)       /*!< Max enumerator value of START1 field.                                */
  #define ETM_TRCVIPCSSCTLR_START1_Disabled (0x0UL)  /*!< The single PE comparator input 1, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START1_Enabled (0x1UL)   /*!< The single PE comparator input 1, is selected as a start resource.   */

/* START2 @Bit 2 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START2_Pos (2UL)         /*!< Position of START2 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START2_Pos) /*!< Bit mask of START2 field.                  */
  #define ETM_TRCVIPCSSCTLR_START2_Min (0x0UL)       /*!< Min enumerator value of START2 field.                                */
  #define ETM_TRCVIPCSSCTLR_START2_Max (0x1UL)       /*!< Max enumerator value of START2 field.                                */
  #define ETM_TRCVIPCSSCTLR_START2_Disabled (0x0UL)  /*!< The single PE comparator input 2, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START2_Enabled (0x1UL)   /*!< The single PE comparator input 2, is selected as a start resource.   */

/* START3 @Bit 3 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START3_Pos (3UL)         /*!< Position of START3 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START3_Pos) /*!< Bit mask of START3 field.                  */
  #define ETM_TRCVIPCSSCTLR_START3_Min (0x0UL)       /*!< Min enumerator value of START3 field.                                */
  #define ETM_TRCVIPCSSCTLR_START3_Max (0x1UL)       /*!< Max enumerator value of START3 field.                                */
  #define ETM_TRCVIPCSSCTLR_START3_Disabled (0x0UL)  /*!< The single PE comparator input 3, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START3_Enabled (0x1UL)   /*!< The single PE comparator input 3, is selected as a start resource.   */

/* START4 @Bit 4 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START4_Pos (4UL)         /*!< Position of START4 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START4_Pos) /*!< Bit mask of START4 field.                  */
  #define ETM_TRCVIPCSSCTLR_START4_Min (0x0UL)       /*!< Min enumerator value of START4 field.                                */
  #define ETM_TRCVIPCSSCTLR_START4_Max (0x1UL)       /*!< Max enumerator value of START4 field.                                */
  #define ETM_TRCVIPCSSCTLR_START4_Disabled (0x0UL)  /*!< The single PE comparator input 4, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START4_Enabled (0x1UL)   /*!< The single PE comparator input 4, is selected as a start resource.   */

/* START5 @Bit 5 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START5_Pos (5UL)         /*!< Position of START5 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START5_Pos) /*!< Bit mask of START5 field.                  */
  #define ETM_TRCVIPCSSCTLR_START5_Min (0x0UL)       /*!< Min enumerator value of START5 field.                                */
  #define ETM_TRCVIPCSSCTLR_START5_Max (0x1UL)       /*!< Max enumerator value of START5 field.                                */
  #define ETM_TRCVIPCSSCTLR_START5_Disabled (0x0UL)  /*!< The single PE comparator input 5, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START5_Enabled (0x1UL)   /*!< The single PE comparator input 5, is selected as a start resource.   */

/* START6 @Bit 6 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START6_Pos (6UL)         /*!< Position of START6 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START6_Pos) /*!< Bit mask of START6 field.                  */
  #define ETM_TRCVIPCSSCTLR_START6_Min (0x0UL)       /*!< Min enumerator value of START6 field.                                */
  #define ETM_TRCVIPCSSCTLR_START6_Max (0x1UL)       /*!< Max enumerator value of START6 field.                                */
  #define ETM_TRCVIPCSSCTLR_START6_Disabled (0x0UL)  /*!< The single PE comparator input 6, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START6_Enabled (0x1UL)   /*!< The single PE comparator input 6, is selected as a start resource.   */

/* START7 @Bit 7 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
                   trace */

  #define ETM_TRCVIPCSSCTLR_START7_Pos (7UL)         /*!< Position of START7 field.                                            */
  #define ETM_TRCVIPCSSCTLR_START7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START7_Pos) /*!< Bit mask of START7 field.                  */
  #define ETM_TRCVIPCSSCTLR_START7_Min (0x0UL)       /*!< Min enumerator value of START7 field.                                */
  #define ETM_TRCVIPCSSCTLR_START7_Max (0x1UL)       /*!< Max enumerator value of START7 field.                                */
  #define ETM_TRCVIPCSSCTLR_START7_Disabled (0x0UL)  /*!< The single PE comparator input 7, is not selected as a start
                                                          resource.*/
  #define ETM_TRCVIPCSSCTLR_START7_Enabled (0x1UL)   /*!< The single PE comparator input 7, is selected as a start resource.   */

/* STOP0 @Bit 16 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP0_Pos (16UL)         /*!< Position of STOP0 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP0_Min (0x0UL)        /*!< Min enumerator value of STOP0 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP0_Max (0x1UL)        /*!< Max enumerator value of STOP0 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP0_Disabled (0x0UL)   /*!< The single PE comparator input 0, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP0_Enabled (0x1UL)    /*!< The single PE comparator input 0, is selected as a stop resource.    */

/* STOP1 @Bit 17 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP1_Pos (17UL)         /*!< Position of STOP1 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP1_Min (0x0UL)        /*!< Min enumerator value of STOP1 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP1_Max (0x1UL)        /*!< Max enumerator value of STOP1 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP1_Disabled (0x0UL)   /*!< The single PE comparator input 1, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP1_Enabled (0x1UL)    /*!< The single PE comparator input 1, is selected as a stop resource.    */

/* STOP2 @Bit 18 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP2_Pos (18UL)         /*!< Position of STOP2 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP2_Min (0x0UL)        /*!< Min enumerator value of STOP2 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP2_Max (0x1UL)        /*!< Max enumerator value of STOP2 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP2_Disabled (0x0UL)   /*!< The single PE comparator input 2, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP2_Enabled (0x1UL)    /*!< The single PE comparator input 2, is selected as a stop resource.    */

/* STOP3 @Bit 19 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP3_Pos (19UL)         /*!< Position of STOP3 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP3_Min (0x0UL)        /*!< Min enumerator value of STOP3 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP3_Max (0x1UL)        /*!< Max enumerator value of STOP3 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP3_Disabled (0x0UL)   /*!< The single PE comparator input 3, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP3_Enabled (0x1UL)    /*!< The single PE comparator input 3, is selected as a stop resource.    */

/* STOP4 @Bit 20 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP4_Pos (20UL)         /*!< Position of STOP4 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP4_Min (0x0UL)        /*!< Min enumerator value of STOP4 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP4_Max (0x1UL)        /*!< Max enumerator value of STOP4 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP4_Disabled (0x0UL)   /*!< The single PE comparator input 4, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP4_Enabled (0x1UL)    /*!< The single PE comparator input 4, is selected as a stop resource.    */

/* STOP5 @Bit 21 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP5_Pos (21UL)         /*!< Position of STOP5 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP5_Min (0x0UL)        /*!< Min enumerator value of STOP5 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP5_Max (0x1UL)        /*!< Max enumerator value of STOP5 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP5_Disabled (0x0UL)   /*!< The single PE comparator input 5, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP5_Enabled (0x1UL)    /*!< The single PE comparator input 5, is selected as a stop resource.    */

/* STOP6 @Bit 22 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP6_Pos (22UL)         /*!< Position of STOP6 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP6_Min (0x0UL)        /*!< Min enumerator value of STOP6 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP6_Max (0x1UL)        /*!< Max enumerator value of STOP6 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP6_Disabled (0x0UL)   /*!< The single PE comparator input 6, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP6_Enabled (0x1UL)    /*!< The single PE comparator input 6, is selected as a stop resource.    */

/* STOP7 @Bit 23 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
                   trace. */

  #define ETM_TRCVIPCSSCTLR_STOP7_Pos (23UL)         /*!< Position of STOP7 field.                                             */
  #define ETM_TRCVIPCSSCTLR_STOP7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field.                     */
  #define ETM_TRCVIPCSSCTLR_STOP7_Min (0x0UL)        /*!< Min enumerator value of STOP7 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP7_Max (0x1UL)        /*!< Max enumerator value of STOP7 field.                                 */
  #define ETM_TRCVIPCSSCTLR_STOP7_Disabled (0x0UL)   /*!< The single PE comparator input 7, is not selected as a stop resource.*/
  #define ETM_TRCVIPCSSCTLR_STOP7_Enabled (0x1UL)    /*!< The single PE comparator input 7, is selected as a stop resource.    */


/* ETM_TRCVDCTLR: Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register
                   must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV ==
                   1. */

  #define ETM_TRCVDCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCVDCTLR register.                                   */

/* EVENT0 @Bit 0 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT0_Pos (0UL)             /*!< Position of EVENT0 field.                                            */
  #define ETM_TRCVDCTLR_EVENT0_Msk (0x1UL << ETM_TRCVDCTLR_EVENT0_Pos) /*!< Bit mask of EVENT0 field.                          */
  #define ETM_TRCVDCTLR_EVENT0_Min (0x0UL)           /*!< Min enumerator value of EVENT0 field.                                */
  #define ETM_TRCVDCTLR_EVENT0_Max (0x1UL)           /*!< Max enumerator value of EVENT0 field.                                */
  #define ETM_TRCVDCTLR_EVENT0_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT0_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* EVENT1 @Bit 1 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT1_Pos (1UL)             /*!< Position of EVENT1 field.                                            */
  #define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field.                          */
  #define ETM_TRCVDCTLR_EVENT1_Min (0x0UL)           /*!< Min enumerator value of EVENT1 field.                                */
  #define ETM_TRCVDCTLR_EVENT1_Max (0x1UL)           /*!< Max enumerator value of EVENT1 field.                                */
  #define ETM_TRCVDCTLR_EVENT1_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT1_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* EVENT2 @Bit 2 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT2_Pos (2UL)             /*!< Position of EVENT2 field.                                            */
  #define ETM_TRCVDCTLR_EVENT2_Msk (0x1UL << ETM_TRCVDCTLR_EVENT2_Pos) /*!< Bit mask of EVENT2 field.                          */
  #define ETM_TRCVDCTLR_EVENT2_Min (0x0UL)           /*!< Min enumerator value of EVENT2 field.                                */
  #define ETM_TRCVDCTLR_EVENT2_Max (0x1UL)           /*!< Max enumerator value of EVENT2 field.                                */
  #define ETM_TRCVDCTLR_EVENT2_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT2_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* EVENT3 @Bit 3 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT3_Pos (3UL)             /*!< Position of EVENT3 field.                                            */
  #define ETM_TRCVDCTLR_EVENT3_Msk (0x1UL << ETM_TRCVDCTLR_EVENT3_Pos) /*!< Bit mask of EVENT3 field.                          */
  #define ETM_TRCVDCTLR_EVENT3_Min (0x0UL)           /*!< Min enumerator value of EVENT3 field.                                */
  #define ETM_TRCVDCTLR_EVENT3_Max (0x1UL)           /*!< Max enumerator value of EVENT3 field.                                */
  #define ETM_TRCVDCTLR_EVENT3_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT3_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* EVENT4 @Bit 4 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT4_Pos (4UL)             /*!< Position of EVENT4 field.                                            */
  #define ETM_TRCVDCTLR_EVENT4_Msk (0x1UL << ETM_TRCVDCTLR_EVENT4_Pos) /*!< Bit mask of EVENT4 field.                          */
  #define ETM_TRCVDCTLR_EVENT4_Min (0x0UL)           /*!< Min enumerator value of EVENT4 field.                                */
  #define ETM_TRCVDCTLR_EVENT4_Max (0x1UL)           /*!< Max enumerator value of EVENT4 field.                                */
  #define ETM_TRCVDCTLR_EVENT4_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT4_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* EVENT5 @Bit 5 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT5_Pos (5UL)             /*!< Position of EVENT5 field.                                            */
  #define ETM_TRCVDCTLR_EVENT5_Msk (0x1UL << ETM_TRCVDCTLR_EVENT5_Pos) /*!< Bit mask of EVENT5 field.                          */
  #define ETM_TRCVDCTLR_EVENT5_Min (0x0UL)           /*!< Min enumerator value of EVENT5 field.                                */
  #define ETM_TRCVDCTLR_EVENT5_Max (0x1UL)           /*!< Max enumerator value of EVENT5 field.                                */
  #define ETM_TRCVDCTLR_EVENT5_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT5_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* EVENT6 @Bit 6 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT6_Pos (6UL)             /*!< Position of EVENT6 field.                                            */
  #define ETM_TRCVDCTLR_EVENT6_Msk (0x1UL << ETM_TRCVDCTLR_EVENT6_Pos) /*!< Bit mask of EVENT6 field.                          */
  #define ETM_TRCVDCTLR_EVENT6_Min (0x0UL)           /*!< Min enumerator value of EVENT6 field.                                */
  #define ETM_TRCVDCTLR_EVENT6_Max (0x1UL)           /*!< Max enumerator value of EVENT6 field.                                */
  #define ETM_TRCVDCTLR_EVENT6_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT6_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* EVENT7 @Bit 7 : Event unit enable bit. */
  #define ETM_TRCVDCTLR_EVENT7_Pos (7UL)             /*!< Position of EVENT7 field.                                            */
  #define ETM_TRCVDCTLR_EVENT7_Msk (0x1UL << ETM_TRCVDCTLR_EVENT7_Pos) /*!< Bit mask of EVENT7 field.                          */
  #define ETM_TRCVDCTLR_EVENT7_Min (0x0UL)           /*!< Min enumerator value of EVENT7 field.                                */
  #define ETM_TRCVDCTLR_EVENT7_Max (0x1UL)           /*!< Max enumerator value of EVENT7 field.                                */
  #define ETM_TRCVDCTLR_EVENT7_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
  #define ETM_TRCVDCTLR_EVENT7_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */

/* SPREL @Bits 8..9 : Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). */
  #define ETM_TRCVDCTLR_SPREL_Pos (8UL)              /*!< Position of SPREL field.                                             */
  #define ETM_TRCVDCTLR_SPREL_Msk (0x3UL << ETM_TRCVDCTLR_SPREL_Pos) /*!< Bit mask of SPREL field.                             */
  #define ETM_TRCVDCTLR_SPREL_Min (0x0UL)            /*!< Min enumerator value of SPREL field.                                 */
  #define ETM_TRCVDCTLR_SPREL_Max (0x3UL)            /*!< Max enumerator value of SPREL field.                                 */
  #define ETM_TRCVDCTLR_SPREL_Enabled (0x0UL)        /*!< The trace unit does not affect the tracing of SP-relative transfers. */
  #define ETM_TRCVDCTLR_SPREL_DataOnly (0x2UL)       /*!< The trace unit does not trace the address portion of SP-relative
                                                          transfers. If data value tracing is enabled then the trace unit
                                                          generates a P1 data address element.*/
  #define ETM_TRCVDCTLR_SPREL_Disabled (0x3UL)       /*!< The trace unit does not trace the address or value portions of
                                                          SP-relative transfers.*/

/* PCREL @Bit 10 : Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). */
  #define ETM_TRCVDCTLR_PCREL_Pos (10UL)             /*!< Position of PCREL field.                                             */
  #define ETM_TRCVDCTLR_PCREL_Msk (0x1UL << ETM_TRCVDCTLR_PCREL_Pos) /*!< Bit mask of PCREL field.                             */
  #define ETM_TRCVDCTLR_PCREL_Min (0x0UL)            /*!< Min enumerator value of PCREL field.                                 */
  #define ETM_TRCVDCTLR_PCREL_Max (0x1UL)            /*!< Max enumerator value of PCREL field.                                 */
  #define ETM_TRCVDCTLR_PCREL_Enabled (0x0UL)        /*!< The trace unit does not affect the tracing of PC-relative transfers. */
  #define ETM_TRCVDCTLR_PCREL_Disabled (0x1UL)       /*!< The trace unit does not trace the address or value portions of
                                                          PC-relative transfers.*/

/* TBI @Bit 11 : Controls which information a trace unit populates in bits[63:56] of the data address. */
  #define ETM_TRCVDCTLR_TBI_Pos (11UL)               /*!< Position of TBI field.                                               */
  #define ETM_TRCVDCTLR_TBI_Msk (0x1UL << ETM_TRCVDCTLR_TBI_Pos) /*!< Bit mask of TBI field.                                   */
  #define ETM_TRCVDCTLR_TBI_Min (0x0UL)              /*!< Min enumerator value of TBI field.                                   */
  #define ETM_TRCVDCTLR_TBI_Max (0x1UL)              /*!< Max enumerator value of TBI field.                                   */
  #define ETM_TRCVDCTLR_TBI_SignExtend (0x0UL)       /*!< The trace unit assigns bits[63:56] to have the same value as bit[55]
                                                          of the data address, that is, it sign-extends the value.*/
  #define ETM_TRCVDCTLR_TBI_Copy (0x1UL)             /*!< The trace unit assigns bits[63:56] to have the same value as
                                                          bits[63:56] of the data address.*/

/* TRCEXDATA @Bit 12 : Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and
                       Armv8-M PEs. */

  #define ETM_TRCVDCTLR_TRCEXDATA_Pos (12UL)         /*!< Position of TRCEXDATA field.                                         */
  #define ETM_TRCVDCTLR_TRCEXDATA_Msk (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos) /*!< Bit mask of TRCEXDATA field.                 */
  #define ETM_TRCVDCTLR_TRCEXDATA_Min (0x0UL)        /*!< Min enumerator value of TRCEXDATA field.                             */
  #define ETM_TRCVDCTLR_TRCEXDATA_Max (0x1UL)        /*!< Max enumerator value of TRCEXDATA field.                             */
  #define ETM_TRCVDCTLR_TRCEXDATA_Disabled (0x0UL)   /*!< Exception and exception return data transfers are not traced.        */
  #define ETM_TRCVDCTLR_TRCEXDATA_Enabled (0x1UL)    /*!< Exception and exception return data transfers are traced if the other
                                                          aspects of ViewData indicate that the data transfers must be traced.*/


/* ETM_TRCVDSACCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This
                      register must be programmed when one or more address comparators are implemented. */

  #define ETM_TRCVDSACCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDSACCTLR register.                                */

/* INCLUDE0 @Bit 0 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE0_Pos (0UL)        /*!< Position of INCLUDE0 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE0_Min (0x0UL)      /*!< Min enumerator value of INCLUDE0 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE0_Max (0x1UL)      /*!< Max enumerator value of INCLUDE0 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE0_Enabled (0x1UL)  /*!< The single address comparator 0, is selected for ViewData include
                                                          control.*/

/* INCLUDE1 @Bit 1 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE1_Pos (1UL)        /*!< Position of INCLUDE1 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE1_Min (0x0UL)      /*!< Min enumerator value of INCLUDE1 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE1_Max (0x1UL)      /*!< Max enumerator value of INCLUDE1 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE1_Enabled (0x1UL)  /*!< The single address comparator 1, is selected for ViewData include
                                                          control.*/

/* INCLUDE2 @Bit 2 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE2_Pos (2UL)        /*!< Position of INCLUDE2 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE2_Min (0x0UL)      /*!< Min enumerator value of INCLUDE2 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE2_Max (0x1UL)      /*!< Max enumerator value of INCLUDE2 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE2_Enabled (0x1UL)  /*!< The single address comparator 2, is selected for ViewData include
                                                          control.*/

/* INCLUDE3 @Bit 3 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE3_Pos (3UL)        /*!< Position of INCLUDE3 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE3_Min (0x0UL)      /*!< Min enumerator value of INCLUDE3 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE3_Max (0x1UL)      /*!< Max enumerator value of INCLUDE3 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE3_Enabled (0x1UL)  /*!< The single address comparator 3, is selected for ViewData include
                                                          control.*/

/* INCLUDE4 @Bit 4 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE4_Pos (4UL)        /*!< Position of INCLUDE4 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE4_Min (0x0UL)      /*!< Min enumerator value of INCLUDE4 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE4_Max (0x1UL)      /*!< Max enumerator value of INCLUDE4 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE4_Enabled (0x1UL)  /*!< The single address comparator 4, is selected for ViewData include
                                                          control.*/

/* INCLUDE5 @Bit 5 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE5_Pos (5UL)        /*!< Position of INCLUDE5 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE5_Min (0x0UL)      /*!< Min enumerator value of INCLUDE5 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE5_Max (0x1UL)      /*!< Max enumerator value of INCLUDE5 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE5_Enabled (0x1UL)  /*!< The single address comparator 5, is selected for ViewData include
                                                          control.*/

/* INCLUDE6 @Bit 6 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE6_Pos (6UL)        /*!< Position of INCLUDE6 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE6_Min (0x0UL)      /*!< Min enumerator value of INCLUDE6 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE6_Max (0x1UL)      /*!< Max enumerator value of INCLUDE6 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE6_Enabled (0x1UL)  /*!< The single address comparator 6, is selected for ViewData include
                                                          control.*/

/* INCLUDE7 @Bit 7 : Selects which single address comparators are in use with ViewData include control. */
  #define ETM_TRCVDSACCTLR_INCLUDE7_Pos (7UL)        /*!< Position of INCLUDE7 field.                                          */
  #define ETM_TRCVDSACCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field.              */
  #define ETM_TRCVDSACCTLR_INCLUDE7_Min (0x0UL)      /*!< Min enumerator value of INCLUDE7 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE7_Max (0x1UL)      /*!< Max enumerator value of INCLUDE7 field.                              */
  #define ETM_TRCVDSACCTLR_INCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData include
                                                          control.*/
  #define ETM_TRCVDSACCTLR_INCLUDE7_Enabled (0x1UL)  /*!< The single address comparator 7, is selected for ViewData include
                                                          control.*/

/* EXCLUDE0 @Bit 16 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE0_Pos (16UL)       /*!< Position of EXCLUDE0 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE0_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE0 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE0_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE0 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE0_Enabled (0x1UL)  /*!< The single address comparator 0, s selected for ViewData exclude
                                                          control.*/

/* EXCLUDE1 @Bit 17 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE1_Pos (17UL)       /*!< Position of EXCLUDE1 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE1_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE1 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE1_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE1 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE1_Enabled (0x1UL)  /*!< The single address comparator 1, s selected for ViewData exclude
                                                          control.*/

/* EXCLUDE2 @Bit 18 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE2_Pos (18UL)       /*!< Position of EXCLUDE2 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE2_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE2 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE2_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE2 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE2_Enabled (0x1UL)  /*!< The single address comparator 2, s selected for ViewData exclude
                                                          control.*/

/* EXCLUDE3 @Bit 19 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE3_Pos (19UL)       /*!< Position of EXCLUDE3 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE3_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE3 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE3_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE3 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE3_Enabled (0x1UL)  /*!< The single address comparator 3, s selected for ViewData exclude
                                                          control.*/

/* EXCLUDE4 @Bit 20 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE4_Pos (20UL)       /*!< Position of EXCLUDE4 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE4_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE4 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE4_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE4 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE4_Enabled (0x1UL)  /*!< The single address comparator 4, s selected for ViewData exclude
                                                          control.*/

/* EXCLUDE5 @Bit 21 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE5_Pos (21UL)       /*!< Position of EXCLUDE5 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE5_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE5 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE5_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE5 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE5_Enabled (0x1UL)  /*!< The single address comparator 5, s selected for ViewData exclude
                                                          control.*/

/* EXCLUDE6 @Bit 22 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE6_Pos (22UL)       /*!< Position of EXCLUDE6 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE6_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE6 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE6_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE6 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE6_Enabled (0x1UL)  /*!< The single address comparator 6, s selected for ViewData exclude
                                                          control.*/

/* EXCLUDE7 @Bit 23 : Selects which single address comparators are in use with ViewData exclude control. */
  #define ETM_TRCVDSACCTLR_EXCLUDE7_Pos (23UL)       /*!< Position of EXCLUDE7 field.                                          */
  #define ETM_TRCVDSACCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field.              */
  #define ETM_TRCVDSACCTLR_EXCLUDE7_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE7 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE7_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE7 field.                              */
  #define ETM_TRCVDSACCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData exclude
                                                          control.*/
  #define ETM_TRCVDSACCTLR_EXCLUDE7_Enabled (0x1UL)  /*!< The single address comparator 7, s selected for ViewData exclude
                                                          control.*/


/* ETM_TRCVDARCCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This
                      register must be programmed when one or more address comparators are implemented. */

  #define ETM_TRCVDARCCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDARCCTLR register.                                */

/* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE0_Pos (0UL)        /*!< Position of INCLUDE0 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE0_Min (0x0UL)      /*!< Min enumerator value of INCLUDE0 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE0_Max (0x1UL)      /*!< Max enumerator value of INCLUDE0 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE0_Enabled (0x1UL)  /*!< The address range that address range comparator 0 defines, is selected
                                                          for ViewData include control.*/

/* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE1_Pos (1UL)        /*!< Position of INCLUDE1 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE1_Min (0x0UL)      /*!< Min enumerator value of INCLUDE1 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE1_Max (0x1UL)      /*!< Max enumerator value of INCLUDE1 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE1_Enabled (0x1UL)  /*!< The address range that address range comparator 1 defines, is selected
                                                          for ViewData include control.*/

/* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE2_Pos (2UL)        /*!< Position of INCLUDE2 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE2_Min (0x0UL)      /*!< Min enumerator value of INCLUDE2 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE2_Max (0x1UL)      /*!< Max enumerator value of INCLUDE2 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE2_Enabled (0x1UL)  /*!< The address range that address range comparator 2 defines, is selected
                                                          for ViewData include control.*/

/* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE3_Pos (3UL)        /*!< Position of INCLUDE3 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE3_Min (0x0UL)      /*!< Min enumerator value of INCLUDE3 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE3_Max (0x1UL)      /*!< Max enumerator value of INCLUDE3 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE3_Enabled (0x1UL)  /*!< The address range that address range comparator 3 defines, is selected
                                                          for ViewData include control.*/

/* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE4_Pos (4UL)        /*!< Position of INCLUDE4 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE4_Min (0x0UL)      /*!< Min enumerator value of INCLUDE4 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE4_Max (0x1UL)      /*!< Max enumerator value of INCLUDE4 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE4_Enabled (0x1UL)  /*!< The address range that address range comparator 4 defines, is selected
                                                          for ViewData include control.*/

/* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE5_Pos (5UL)        /*!< Position of INCLUDE5 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE5_Min (0x0UL)      /*!< Min enumerator value of INCLUDE5 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE5_Max (0x1UL)      /*!< Max enumerator value of INCLUDE5 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE5_Enabled (0x1UL)  /*!< The address range that address range comparator 5 defines, is selected
                                                          for ViewData include control.*/

/* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE6_Pos (6UL)        /*!< Position of INCLUDE6 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE6_Min (0x0UL)      /*!< Min enumerator value of INCLUDE6 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE6_Max (0x1UL)      /*!< Max enumerator value of INCLUDE6 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE6_Enabled (0x1UL)  /*!< The address range that address range comparator 6 defines, is selected
                                                          for ViewData include control.*/

/* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
                     */

  #define ETM_TRCVDARCCTLR_INCLUDE7_Pos (7UL)        /*!< Position of INCLUDE7 field.                                          */
  #define ETM_TRCVDARCCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field.              */
  #define ETM_TRCVDARCCTLR_INCLUDE7_Min (0x0UL)      /*!< Min enumerator value of INCLUDE7 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE7_Max (0x1UL)      /*!< Max enumerator value of INCLUDE7 field.                              */
  #define ETM_TRCVDARCCTLR_INCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not
                                                          selected for ViewData include control.*/
  #define ETM_TRCVDARCCTLR_INCLUDE7_Enabled (0x1UL)  /*!< The address range that address range comparator 7 defines, is selected
                                                          for ViewData include control.*/

/* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE0_Pos (16UL)       /*!< Position of EXCLUDE0 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE0_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE0 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE0_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE0 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE0_Enabled (0x1UL)  /*!< The address range that address range comparator 0 defines, s selected
                                                          for ViewData exclude control.*/

/* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE1_Pos (17UL)       /*!< Position of EXCLUDE1 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE1_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE1 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE1_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE1 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE1_Enabled (0x1UL)  /*!< The address range that address range comparator 1 defines, s selected
                                                          for ViewData exclude control.*/

/* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE2_Pos (18UL)       /*!< Position of EXCLUDE2 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE2_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE2 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE2_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE2 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE2_Enabled (0x1UL)  /*!< The address range that address range comparator 2 defines, s selected
                                                          for ViewData exclude control.*/

/* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE3_Pos (19UL)       /*!< Position of EXCLUDE3 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE3_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE3 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE3_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE3 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE3_Enabled (0x1UL)  /*!< The address range that address range comparator 3 defines, s selected
                                                          for ViewData exclude control.*/

/* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE4_Pos (20UL)       /*!< Position of EXCLUDE4 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE4_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE4 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE4_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE4 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE4_Enabled (0x1UL)  /*!< The address range that address range comparator 4 defines, s selected
                                                          for ViewData exclude control.*/

/* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE5_Pos (21UL)       /*!< Position of EXCLUDE5 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE5_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE5 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE5_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE5 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE5_Enabled (0x1UL)  /*!< The address range that address range comparator 5 defines, s selected
                                                          for ViewData exclude control.*/

/* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE6_Pos (22UL)       /*!< Position of EXCLUDE6 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE6_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE6 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE6_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE6 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE6_Enabled (0x1UL)  /*!< The address range that address range comparator 6 defines, s selected
                                                          for ViewData exclude control.*/

/* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
                      control. */

  #define ETM_TRCVDARCCTLR_EXCLUDE7_Pos (23UL)       /*!< Position of EXCLUDE7 field.                                          */
  #define ETM_TRCVDARCCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field.              */
  #define ETM_TRCVDARCCTLR_EXCLUDE7_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE7 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE7_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE7 field.                              */
  #define ETM_TRCVDARCCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not
                                                          selected for ViewData exclude control.*/
  #define ETM_TRCVDARCCTLR_EXCLUDE7_Enabled (0x1UL)  /*!< The address range that address range comparator 7 defines, s selected
                                                          for ViewData exclude control.*/


/* ETM_TRCSEQEVR: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled
                   or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid
                   event. */

  #define ETM_TRCSEQEVR_MaxCount (3UL)               /*!< Max size of TRCSEQEVR[3] array.                                      */
  #define ETM_TRCSEQEVR_MaxIndex (2UL)               /*!< Max index of TRCSEQEVR[3] array.                                     */
  #define ETM_TRCSEQEVR_MinIndex (0UL)               /*!< Min index of TRCSEQEVR[3] array.                                     */
  #define ETM_TRCSEQEVR_ResetValue (0x00000000UL)    /*!< Reset value of TRCSEQEVR[3] register.                                */

/* F0 @Bit 0 : Forward field. */
  #define ETM_TRCSEQEVR_F0_Pos (0UL)                 /*!< Position of F0 field.                                                */
  #define ETM_TRCSEQEVR_F0_Msk (0x1UL << ETM_TRCSEQEVR_F0_Pos) /*!< Bit mask of F0 field.                                      */
  #define ETM_TRCSEQEVR_F0_Min (0x0UL)               /*!< Min enumerator value of F0 field.                                    */
  #define ETM_TRCSEQEVR_F0_Max (0x1UL)               /*!< Max enumerator value of F0 field.                                    */
  #define ETM_TRCSEQEVR_F0_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F0_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* F1 @Bit 1 : Forward field. */
  #define ETM_TRCSEQEVR_F1_Pos (1UL)                 /*!< Position of F1 field.                                                */
  #define ETM_TRCSEQEVR_F1_Msk (0x1UL << ETM_TRCSEQEVR_F1_Pos) /*!< Bit mask of F1 field.                                      */
  #define ETM_TRCSEQEVR_F1_Min (0x0UL)               /*!< Min enumerator value of F1 field.                                    */
  #define ETM_TRCSEQEVR_F1_Max (0x1UL)               /*!< Max enumerator value of F1 field.                                    */
  #define ETM_TRCSEQEVR_F1_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F1_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* F2 @Bit 2 : Forward field. */
  #define ETM_TRCSEQEVR_F2_Pos (2UL)                 /*!< Position of F2 field.                                                */
  #define ETM_TRCSEQEVR_F2_Msk (0x1UL << ETM_TRCSEQEVR_F2_Pos) /*!< Bit mask of F2 field.                                      */
  #define ETM_TRCSEQEVR_F2_Min (0x0UL)               /*!< Min enumerator value of F2 field.                                    */
  #define ETM_TRCSEQEVR_F2_Max (0x1UL)               /*!< Max enumerator value of F2 field.                                    */
  #define ETM_TRCSEQEVR_F2_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F2_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* F3 @Bit 3 : Forward field. */
  #define ETM_TRCSEQEVR_F3_Pos (3UL)                 /*!< Position of F3 field.                                                */
  #define ETM_TRCSEQEVR_F3_Msk (0x1UL << ETM_TRCSEQEVR_F3_Pos) /*!< Bit mask of F3 field.                                      */
  #define ETM_TRCSEQEVR_F3_Min (0x0UL)               /*!< Min enumerator value of F3 field.                                    */
  #define ETM_TRCSEQEVR_F3_Max (0x1UL)               /*!< Max enumerator value of F3 field.                                    */
  #define ETM_TRCSEQEVR_F3_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F3_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* F4 @Bit 4 : Forward field. */
  #define ETM_TRCSEQEVR_F4_Pos (4UL)                 /*!< Position of F4 field.                                                */
  #define ETM_TRCSEQEVR_F4_Msk (0x1UL << ETM_TRCSEQEVR_F4_Pos) /*!< Bit mask of F4 field.                                      */
  #define ETM_TRCSEQEVR_F4_Min (0x0UL)               /*!< Min enumerator value of F4 field.                                    */
  #define ETM_TRCSEQEVR_F4_Max (0x1UL)               /*!< Max enumerator value of F4 field.                                    */
  #define ETM_TRCSEQEVR_F4_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F4_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* F5 @Bit 5 : Forward field. */
  #define ETM_TRCSEQEVR_F5_Pos (5UL)                 /*!< Position of F5 field.                                                */
  #define ETM_TRCSEQEVR_F5_Msk (0x1UL << ETM_TRCSEQEVR_F5_Pos) /*!< Bit mask of F5 field.                                      */
  #define ETM_TRCSEQEVR_F5_Min (0x0UL)               /*!< Min enumerator value of F5 field.                                    */
  #define ETM_TRCSEQEVR_F5_Max (0x1UL)               /*!< Max enumerator value of F5 field.                                    */
  #define ETM_TRCSEQEVR_F5_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F5_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* F6 @Bit 6 : Forward field. */
  #define ETM_TRCSEQEVR_F6_Pos (6UL)                 /*!< Position of F6 field.                                                */
  #define ETM_TRCSEQEVR_F6_Msk (0x1UL << ETM_TRCSEQEVR_F6_Pos) /*!< Bit mask of F6 field.                                      */
  #define ETM_TRCSEQEVR_F6_Min (0x0UL)               /*!< Min enumerator value of F6 field.                                    */
  #define ETM_TRCSEQEVR_F6_Max (0x1UL)               /*!< Max enumerator value of F6 field.                                    */
  #define ETM_TRCSEQEVR_F6_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F6_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* F7 @Bit 7 : Forward field. */
  #define ETM_TRCSEQEVR_F7_Pos (7UL)                 /*!< Position of F7 field.                                                */
  #define ETM_TRCSEQEVR_F7_Msk (0x1UL << ETM_TRCSEQEVR_F7_Pos) /*!< Bit mask of F7 field.                                      */
  #define ETM_TRCSEQEVR_F7_Min (0x0UL)               /*!< Min enumerator value of F7 field.                                    */
  #define ETM_TRCSEQEVR_F7_Max (0x1UL)               /*!< Max enumerator value of F7 field.                                    */
  #define ETM_TRCSEQEVR_F7_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_F7_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
                                                          state n+1.*/

/* B0 @Bit 8 : Backward field. */
  #define ETM_TRCSEQEVR_B0_Pos (8UL)                 /*!< Position of B0 field.                                                */
  #define ETM_TRCSEQEVR_B0_Msk (0x1UL << ETM_TRCSEQEVR_B0_Pos) /*!< Bit mask of B0 field.                                      */
  #define ETM_TRCSEQEVR_B0_Min (0x0UL)               /*!< Min enumerator value of B0 field.                                    */
  #define ETM_TRCSEQEVR_B0_Max (0x1UL)               /*!< Max enumerator value of B0 field.                                    */
  #define ETM_TRCSEQEVR_B0_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B0_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/

/* B1 @Bit 9 : Backward field. */
  #define ETM_TRCSEQEVR_B1_Pos (9UL)                 /*!< Position of B1 field.                                                */
  #define ETM_TRCSEQEVR_B1_Msk (0x1UL << ETM_TRCSEQEVR_B1_Pos) /*!< Bit mask of B1 field.                                      */
  #define ETM_TRCSEQEVR_B1_Min (0x0UL)               /*!< Min enumerator value of B1 field.                                    */
  #define ETM_TRCSEQEVR_B1_Max (0x1UL)               /*!< Max enumerator value of B1 field.                                    */
  #define ETM_TRCSEQEVR_B1_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B1_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/

/* B2 @Bit 10 : Backward field. */
  #define ETM_TRCSEQEVR_B2_Pos (10UL)                /*!< Position of B2 field.                                                */
  #define ETM_TRCSEQEVR_B2_Msk (0x1UL << ETM_TRCSEQEVR_B2_Pos) /*!< Bit mask of B2 field.                                      */
  #define ETM_TRCSEQEVR_B2_Min (0x0UL)               /*!< Min enumerator value of B2 field.                                    */
  #define ETM_TRCSEQEVR_B2_Max (0x1UL)               /*!< Max enumerator value of B2 field.                                    */
  #define ETM_TRCSEQEVR_B2_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B2_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/

/* B3 @Bit 11 : Backward field. */
  #define ETM_TRCSEQEVR_B3_Pos (11UL)                /*!< Position of B3 field.                                                */
  #define ETM_TRCSEQEVR_B3_Msk (0x1UL << ETM_TRCSEQEVR_B3_Pos) /*!< Bit mask of B3 field.                                      */
  #define ETM_TRCSEQEVR_B3_Min (0x0UL)               /*!< Min enumerator value of B3 field.                                    */
  #define ETM_TRCSEQEVR_B3_Max (0x1UL)               /*!< Max enumerator value of B3 field.                                    */
  #define ETM_TRCSEQEVR_B3_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B3_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/

/* B4 @Bit 12 : Backward field. */
  #define ETM_TRCSEQEVR_B4_Pos (12UL)                /*!< Position of B4 field.                                                */
  #define ETM_TRCSEQEVR_B4_Msk (0x1UL << ETM_TRCSEQEVR_B4_Pos) /*!< Bit mask of B4 field.                                      */
  #define ETM_TRCSEQEVR_B4_Min (0x0UL)               /*!< Min enumerator value of B4 field.                                    */
  #define ETM_TRCSEQEVR_B4_Max (0x1UL)               /*!< Max enumerator value of B4 field.                                    */
  #define ETM_TRCSEQEVR_B4_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B4_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/

/* B5 @Bit 13 : Backward field. */
  #define ETM_TRCSEQEVR_B5_Pos (13UL)                /*!< Position of B5 field.                                                */
  #define ETM_TRCSEQEVR_B5_Msk (0x1UL << ETM_TRCSEQEVR_B5_Pos) /*!< Bit mask of B5 field.                                      */
  #define ETM_TRCSEQEVR_B5_Min (0x0UL)               /*!< Min enumerator value of B5 field.                                    */
  #define ETM_TRCSEQEVR_B5_Max (0x1UL)               /*!< Max enumerator value of B5 field.                                    */
  #define ETM_TRCSEQEVR_B5_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B5_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/

/* B6 @Bit 14 : Backward field. */
  #define ETM_TRCSEQEVR_B6_Pos (14UL)                /*!< Position of B6 field.                                                */
  #define ETM_TRCSEQEVR_B6_Msk (0x1UL << ETM_TRCSEQEVR_B6_Pos) /*!< Bit mask of B6 field.                                      */
  #define ETM_TRCSEQEVR_B6_Min (0x0UL)               /*!< Min enumerator value of B6 field.                                    */
  #define ETM_TRCSEQEVR_B6_Max (0x1UL)               /*!< Max enumerator value of B6 field.                                    */
  #define ETM_TRCSEQEVR_B6_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B6_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/

/* B7 @Bit 15 : Backward field. */
  #define ETM_TRCSEQEVR_B7_Pos (15UL)                /*!< Position of B7 field.                                                */
  #define ETM_TRCSEQEVR_B7_Msk (0x1UL << ETM_TRCSEQEVR_B7_Pos) /*!< Bit mask of B7 field.                                      */
  #define ETM_TRCSEQEVR_B7_Min (0x0UL)               /*!< Min enumerator value of B7 field.                                    */
  #define ETM_TRCSEQEVR_B7_Max (0x1UL)               /*!< Max enumerator value of B7 field.                                    */
  #define ETM_TRCSEQEVR_B7_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
  #define ETM_TRCSEQEVR_B7_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
                                                          state n.*/


/* ETM_TRCSEQRSTEVR: Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is
                      enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a
                      valid event. */

  #define ETM_TRCSEQRSTEVR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQRSTEVR register.                                */

/* EVENT @Bits 0..7 : Select which event should reset the sequencer. */
  #define ETM_TRCSEQRSTEVR_EVENT_Pos (0UL)           /*!< Position of EVENT field.                                             */
  #define ETM_TRCSEQRSTEVR_EVENT_Msk (0xFFUL << ETM_TRCSEQRSTEVR_EVENT_Pos) /*!< Bit mask of EVENT field.                      */
  #define ETM_TRCSEQRSTEVR_EVENT_Min (0x00UL)        /*!< Min value of EVENT field.                                            */
  #define ETM_TRCSEQRSTEVR_EVENT_Max (0xFFUL)        /*!< Max size of EVENT field.                                             */


/* ETM_TRCSEQSTR: Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle.
                   Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state
                   transitions must be programmed with a valid event. */

  #define ETM_TRCSEQSTR_ResetValue (0x00000000UL)    /*!< Reset value of TRCSEQSTR register.                                   */

/* STATE @Bits 0..1 : Sets or returns the state of the sequencer. */
  #define ETM_TRCSEQSTR_STATE_Pos (0UL)              /*!< Position of STATE field.                                             */
  #define ETM_TRCSEQSTR_STATE_Msk (0x3UL << ETM_TRCSEQSTR_STATE_Pos) /*!< Bit mask of STATE field.                             */
  #define ETM_TRCSEQSTR_STATE_Min (0x0UL)            /*!< Min enumerator value of STATE field.                                 */
  #define ETM_TRCSEQSTR_STATE_Max (0x3UL)            /*!< Max enumerator value of STATE field.                                 */
  #define ETM_TRCSEQSTR_STATE_State0 (0x0UL)         /*!< The sequencer is in state 0.                                         */
  #define ETM_TRCSEQSTR_STATE_State1 (0x1UL)         /*!< The sequencer is in state 1.                                         */
  #define ETM_TRCSEQSTR_STATE_State2 (0x2UL)         /*!< The sequencer is in state 2.                                         */
  #define ETM_TRCSEQSTR_STATE_State3 (0x3UL)         /*!< The sequencer is in state 3.                                         */


/* ETM_TRCEXTINSELR: Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when
                      the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the
                      sequencer is used, all sequencer state transitions must be programmed with a valid event. */

  #define ETM_TRCEXTINSELR_ResetValue (0x00000000UL) /*!< Reset value of TRCEXTINSELR register.                                */

/* SEL0 @Bits 0..7 : Each field in this collection selects an external input as a resource for the trace unit. */
  #define ETM_TRCEXTINSELR_SEL0_Pos (0UL)            /*!< Position of SEL0 field.                                              */
  #define ETM_TRCEXTINSELR_SEL0_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL0_Pos) /*!< Bit mask of SEL0 field.                         */
  #define ETM_TRCEXTINSELR_SEL0_Min (0x00UL)         /*!< Min value of SEL0 field.                                             */
  #define ETM_TRCEXTINSELR_SEL0_Max (0xFFUL)         /*!< Max size of SEL0 field.                                              */

/* SEL1 @Bits 8..15 : Each field in this collection selects an external input as a resource for the trace unit. */
  #define ETM_TRCEXTINSELR_SEL1_Pos (8UL)            /*!< Position of SEL1 field.                                              */
  #define ETM_TRCEXTINSELR_SEL1_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL1_Pos) /*!< Bit mask of SEL1 field.                         */
  #define ETM_TRCEXTINSELR_SEL1_Min (0x00UL)         /*!< Min value of SEL1 field.                                             */
  #define ETM_TRCEXTINSELR_SEL1_Max (0xFFUL)         /*!< Max size of SEL1 field.                                              */

/* SEL2 @Bits 16..23 : Each field in this collection selects an external input as a resource for the trace unit. */
  #define ETM_TRCEXTINSELR_SEL2_Pos (16UL)           /*!< Position of SEL2 field.                                              */
  #define ETM_TRCEXTINSELR_SEL2_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL2_Pos) /*!< Bit mask of SEL2 field.                         */
  #define ETM_TRCEXTINSELR_SEL2_Min (0x00UL)         /*!< Min value of SEL2 field.                                             */
  #define ETM_TRCEXTINSELR_SEL2_Max (0xFFUL)         /*!< Max size of SEL2 field.                                              */

/* SEL3 @Bits 24..31 : Each field in this collection selects an external input as a resource for the trace unit. */
  #define ETM_TRCEXTINSELR_SEL3_Pos (24UL)           /*!< Position of SEL3 field.                                              */
  #define ETM_TRCEXTINSELR_SEL3_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL3_Pos) /*!< Bit mask of SEL3 field.                         */
  #define ETM_TRCEXTINSELR_SEL3_Min (0x00UL)         /*!< Min value of SEL3 field.                                             */
  #define ETM_TRCEXTINSELR_SEL3_Max (0xFFUL)         /*!< Max size of SEL3 field.                                              */


/* ETM_TRCCNTRLDVR: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is
                     enabled or not idle. */

  #define ETM_TRCCNTRLDVR_MaxCount (4UL)             /*!< Max size of TRCCNTRLDVR[4] array.                                    */
  #define ETM_TRCCNTRLDVR_MaxIndex (3UL)             /*!< Max index of TRCCNTRLDVR[4] array.                                   */
  #define ETM_TRCCNTRLDVR_MinIndex (0UL)             /*!< Min index of TRCCNTRLDVR[4] array.                                   */
  #define ETM_TRCCNTRLDVR_ResetValue (0x00000000UL)  /*!< Reset value of TRCCNTRLDVR[4] register.                              */

/* VALUE @Bits 0..15 : Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit
                       copies the VALUEn field into counter n. */

  #define ETM_TRCCNTRLDVR_VALUE_Pos (0UL)            /*!< Position of VALUE field.                                             */
  #define ETM_TRCCNTRLDVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTRLDVR_VALUE_Pos) /*!< Bit mask of VALUE field.                      */
  #define ETM_TRCCNTRLDVR_VALUE_Min (0x0000UL)       /*!< Min value of VALUE field.                                            */
  #define ETM_TRCCNTRLDVR_VALUE_Max (0xFFFFUL)       /*!< Max size of VALUE field.                                             */


/* ETM_TRCCNTCTLR: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. */
  #define ETM_TRCCNTCTLR_MaxCount (4UL)              /*!< Max size of TRCCNTCTLR[4] array.                                     */
  #define ETM_TRCCNTCTLR_MaxIndex (3UL)              /*!< Max index of TRCCNTCTLR[4] array.                                    */
  #define ETM_TRCCNTCTLR_MinIndex (0UL)              /*!< Min index of TRCCNTCTLR[4] array.                                    */
  #define ETM_TRCCNTCTLR_ResetValue (0x00000000UL)   /*!< Reset value of TRCCNTCTLR[4] register.                               */

/* CNTEVENT @Bits 0..7 : Selects an event, that when it occurs causes counter n to decrement. */
  #define ETM_TRCCNTCTLR_CNTEVENT_Pos (0UL)          /*!< Position of CNTEVENT field.                                          */
  #define ETM_TRCCNTCTLR_CNTEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_CNTEVENT_Pos) /*!< Bit mask of CNTEVENT field.                 */
  #define ETM_TRCCNTCTLR_CNTEVENT_Min (0x00UL)       /*!< Min value of CNTEVENT field.                                         */
  #define ETM_TRCCNTCTLR_CNTEVENT_Max (0xFFUL)       /*!< Max size of CNTEVENT field.                                          */

/* RLDEVENT @Bits 8..15 : Selects an event, that when it occurs causes a reload event for counter n. */
  #define ETM_TRCCNTCTLR_RLDEVENT_Pos (8UL)          /*!< Position of RLDEVENT field.                                          */
  #define ETM_TRCCNTCTLR_RLDEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_RLDEVENT_Pos) /*!< Bit mask of RLDEVENT field.                 */
  #define ETM_TRCCNTCTLR_RLDEVENT_Min (0x00UL)       /*!< Min value of RLDEVENT field.                                         */
  #define ETM_TRCCNTCTLR_RLDEVENT_Max (0xFFUL)       /*!< Max size of RLDEVENT field.                                          */

/* RLDSELF @Bit 16 : Controls whether a reload event occurs for counter n, when counter n reaches zero. */
  #define ETM_TRCCNTCTLR_RLDSELF_Pos (16UL)          /*!< Position of RLDSELF field.                                           */
  #define ETM_TRCCNTCTLR_RLDSELF_Msk (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos) /*!< Bit mask of RLDSELF field.                     */
  #define ETM_TRCCNTCTLR_RLDSELF_Min (0x0UL)         /*!< Min enumerator value of RLDSELF field.                               */
  #define ETM_TRCCNTCTLR_RLDSELF_Max (0x1UL)         /*!< Max enumerator value of RLDSELF field.                               */
  #define ETM_TRCCNTCTLR_RLDSELF_Disabled (0x0UL)    /*!< The counter is in Normal mode.                                       */
  #define ETM_TRCCNTCTLR_RLDSELF_Enabled (0x1UL)     /*!< The counter is in Self-reload mode.                                  */

/* CNTCHAIN @Bit 17 : For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs
                      for counter n-1. */

  #define ETM_TRCCNTCTLR_CNTCHAIN_Pos (17UL)         /*!< Position of CNTCHAIN field.                                          */
  #define ETM_TRCCNTCTLR_CNTCHAIN_Msk (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos) /*!< Bit mask of CNTCHAIN field.                  */
  #define ETM_TRCCNTCTLR_CNTCHAIN_Min (0x0UL)        /*!< Min enumerator value of CNTCHAIN field.                              */
  #define ETM_TRCCNTCTLR_CNTCHAIN_Max (0x1UL)        /*!< Max enumerator value of CNTCHAIN field.                              */
  #define ETM_TRCCNTCTLR_CNTCHAIN_Disabled (0x0UL)   /*!< Counter n does not decrement when a reload event for counter n-1
                                                          occurs.*/
  #define ETM_TRCCNTCTLR_CNTCHAIN_Enabled (0x1UL)    /*!< Counter n decrements when a reload event for counter n-1 occurs. This
                                                          concatenates counter n and counter n-1, to provide a larger count
                                                          value.*/


/* ETM_TRCCNTVR: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If
                  software uses counter n then it must write to this register to set the initial counter value. Might ignore
                  writes when the trace unit is enabled or not idle. */

  #define ETM_TRCCNTVR_MaxCount (4UL)                /*!< Max size of TRCCNTVR[4] array.                                       */
  #define ETM_TRCCNTVR_MaxIndex (3UL)                /*!< Max index of TRCCNTVR[4] array.                                      */
  #define ETM_TRCCNTVR_MinIndex (0UL)                /*!< Min index of TRCCNTVR[4] array.                                      */
  #define ETM_TRCCNTVR_ResetValue (0x00000000UL)     /*!< Reset value of TRCCNTVR[4] register.                                 */

/* VALUE @Bits 0..15 : Contains the count value of counter n. */
  #define ETM_TRCCNTVR_VALUE_Pos (0UL)               /*!< Position of VALUE field.                                             */
  #define ETM_TRCCNTVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTVR_VALUE_Pos) /*!< Bit mask of VALUE field.                            */
  #define ETM_TRCCNTVR_VALUE_Min (0x0000UL)          /*!< Min value of VALUE field.                                            */
  #define ETM_TRCCNTVR_VALUE_Max (0xFFFFUL)          /*!< Max size of VALUE field.                                             */


/* ETM_TRCRSCTLR: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled
                   or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE behavior of the
                   resource selector occurs, so the resource selector might fire unexpectedly or might not fire. Reads of the
                   TRCRSCTLRn might return UNKNOWN. */

  #define ETM_TRCRSCTLR_MaxCount (30UL)              /*!< Max size of TRCRSCTLR[32] array.                                     */
  #define ETM_TRCRSCTLR_MaxIndex (31UL)              /*!< Max index of TRCRSCTLR[32] array.                                    */
  #define ETM_TRCRSCTLR_MinIndex (2UL)               /*!< Min index of TRCRSCTLR[32] array.                                    */
  #define ETM_TRCRSCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCRSCTLR[32] register.                               */

/* EN @Bit 0 : Trace unit enable bit */
  #define ETM_TRCRSCTLR_EN_Pos (0UL)                 /*!< Position of EN field.                                                */
  #define ETM_TRCRSCTLR_EN_Msk (0x1UL << ETM_TRCRSCTLR_EN_Pos) /*!< Bit mask of EN field.                                      */
  #define ETM_TRCRSCTLR_EN_Min (0x0UL)               /*!< Min enumerator value of EN field.                                    */
  #define ETM_TRCRSCTLR_EN_Max (0x1UL)               /*!< Max enumerator value of EN field.                                    */
  #define ETM_TRCRSCTLR_EN_Disabled (0x0UL)          /*!< The trace unit is disabled. All trace resources are inactive and no
                                                          trace is generated.*/
  #define ETM_TRCRSCTLR_EN_Enabled (0x1UL)           /*!< The trace unit is enabled.                                           */


/* ETM_TRCSSCCR0: Controls the single-shot comparator. */
  #define ETM_TRCSSCCR0_ResetValue (0x00000000UL)    /*!< Reset value of TRCSSCCR0 register.                                   */

/* RST @Bit 24 : Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to
                 be detected */

  #define ETM_TRCSSCCR0_RST_Pos (24UL)               /*!< Position of RST field.                                               */
  #define ETM_TRCSSCCR0_RST_Msk (0x1UL << ETM_TRCSSCCR0_RST_Pos) /*!< Bit mask of RST field.                                   */
  #define ETM_TRCSSCCR0_RST_Min (0x0UL)              /*!< Min enumerator value of RST field.                                   */
  #define ETM_TRCSSCCR0_RST_Max (0x1UL)              /*!< Max enumerator value of RST field.                                   */
  #define ETM_TRCSSCCR0_RST_Disabled (0x0UL)         /*!< Multiple matches can not be detected.                                */
  #define ETM_TRCSSCCR0_RST_Enabled (0x1UL)          /*!< Multiple matches can occur.                                          */


/* ETM_TRCSSCSR0: Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. */
  #define ETM_TRCSSCSR0_ResetValue (0x00000000UL)    /*!< Reset value of TRCSSCSR0 register.                                   */

/* INST @Bit 0 : Instruction address comparator support */
  #define ETM_TRCSSCSR0_INST_Pos (0UL)               /*!< Position of INST field.                                              */
  #define ETM_TRCSSCSR0_INST_Msk (0x1UL << ETM_TRCSSCSR0_INST_Pos) /*!< Bit mask of INST field.                                */
  #define ETM_TRCSSCSR0_INST_Min (0x0UL)             /*!< Min enumerator value of INST field.                                  */
  #define ETM_TRCSSCSR0_INST_Max (0x1UL)             /*!< Max enumerator value of INST field.                                  */
  #define ETM_TRCSSCSR0_INST_False (0x0UL)           /*!< Single-shot instruction address comparisons not supported.           */
  #define ETM_TRCSSCSR0_INST_True (0x1UL)            /*!< Single-shot instruction address comparisons supported.               */

/* DA @Bit 1 : Data address comparator support */
  #define ETM_TRCSSCSR0_DA_Pos (1UL)                 /*!< Position of DA field.                                                */
  #define ETM_TRCSSCSR0_DA_Msk (0x1UL << ETM_TRCSSCSR0_DA_Pos) /*!< Bit mask of DA field.                                      */
  #define ETM_TRCSSCSR0_DA_Min (0x0UL)               /*!< Min enumerator value of DA field.                                    */
  #define ETM_TRCSSCSR0_DA_Max (0x1UL)               /*!< Max enumerator value of DA field.                                    */
  #define ETM_TRCSSCSR0_DA_False (0x0UL)             /*!< Data address comparisons not supported.                              */
  #define ETM_TRCSSCSR0_DA_True (0x1UL)              /*!< Data address comparisons supported.                                  */

/* DV @Bit 2 : Data value comparator support */
  #define ETM_TRCSSCSR0_DV_Pos (2UL)                 /*!< Position of DV field.                                                */
  #define ETM_TRCSSCSR0_DV_Msk (0x1UL << ETM_TRCSSCSR0_DV_Pos) /*!< Bit mask of DV field.                                      */
  #define ETM_TRCSSCSR0_DV_Min (0x0UL)               /*!< Min enumerator value of DV field.                                    */
  #define ETM_TRCSSCSR0_DV_Max (0x1UL)               /*!< Max enumerator value of DV field.                                    */
  #define ETM_TRCSSCSR0_DV_False (0x0UL)             /*!< Data value comparisons not supported.                                */
  #define ETM_TRCSSCSR0_DV_True (0x1UL)              /*!< Data value comparisons supported.                                    */

/* PC @Bit 3 : Process counter value comparator support */
  #define ETM_TRCSSCSR0_PC_Pos (3UL)                 /*!< Position of PC field.                                                */
  #define ETM_TRCSSCSR0_PC_Msk (0x1UL << ETM_TRCSSCSR0_PC_Pos) /*!< Bit mask of PC field.                                      */
  #define ETM_TRCSSCSR0_PC_Min (0x0UL)               /*!< Min enumerator value of PC field.                                    */
  #define ETM_TRCSSCSR0_PC_Max (0x1UL)               /*!< Max enumerator value of PC field.                                    */
  #define ETM_TRCSSCSR0_PC_False (0x0UL)             /*!< Process counter value comparisons not supported.                     */
  #define ETM_TRCSSCSR0_PC_True (0x1UL)              /*!< Process counter value comparisons supported.                         */

/* STATUS @Bit 31 : Single-shot status. This indicates whether any of the selected comparators have matched. */
  #define ETM_TRCSSCSR0_STATUS_Pos (31UL)            /*!< Position of STATUS field.                                            */
  #define ETM_TRCSSCSR0_STATUS_Msk (0x1UL << ETM_TRCSSCSR0_STATUS_Pos) /*!< Bit mask of STATUS field.                          */
  #define ETM_TRCSSCSR0_STATUS_Min (0x0UL)           /*!< Min enumerator value of STATUS field.                                */
  #define ETM_TRCSSCSR0_STATUS_Max (0x1UL)           /*!< Max enumerator value of STATUS field.                                */
  #define ETM_TRCSSCSR0_STATUS_NoMatch (0x0UL)       /*!< Match has not occurred.                                              */
  #define ETM_TRCSSCSR0_STATUS_Match (0x1UL)         /*!< Match has occurred at least once.                                    */


/* ETM_TRCSSPCICR0: Selects the processor comparator inputs for Single-shot control. */
  #define ETM_TRCSSPCICR0_ResetValue (0x00000000UL)  /*!< Reset value of TRCSSPCICR0 register.                                 */

/* PC0 @Bit 0 : Selects processor comparator 0 inputs for Single-shot control */
  #define ETM_TRCSSPCICR0_PC0_Pos (0UL)              /*!< Position of PC0 field.                                               */
  #define ETM_TRCSSPCICR0_PC0_Msk (0x1UL << ETM_TRCSSPCICR0_PC0_Pos) /*!< Bit mask of PC0 field.                               */
  #define ETM_TRCSSPCICR0_PC0_Min (0x0UL)            /*!< Min enumerator value of PC0 field.                                   */
  #define ETM_TRCSSPCICR0_PC0_Max (0x1UL)            /*!< Max enumerator value of PC0 field.                                   */
  #define ETM_TRCSSPCICR0_PC0_Disabled (0x0UL)       /*!< Processor comparator 0 is not selected for Single-shot control.      */
  #define ETM_TRCSSPCICR0_PC0_Enabled (0x1UL)        /*!< Processor comparator 0 is selected for Single-shot control.          */

/* PC1 @Bit 1 : Selects processor comparator 1 inputs for Single-shot control */
  #define ETM_TRCSSPCICR0_PC1_Pos (1UL)              /*!< Position of PC1 field.                                               */
  #define ETM_TRCSSPCICR0_PC1_Msk (0x1UL << ETM_TRCSSPCICR0_PC1_Pos) /*!< Bit mask of PC1 field.                               */
  #define ETM_TRCSSPCICR0_PC1_Min (0x0UL)            /*!< Min enumerator value of PC1 field.                                   */
  #define ETM_TRCSSPCICR0_PC1_Max (0x1UL)            /*!< Max enumerator value of PC1 field.                                   */
  #define ETM_TRCSSPCICR0_PC1_Disabled (0x0UL)       /*!< Processor comparator 1 is not selected for Single-shot control.      */
  #define ETM_TRCSSPCICR0_PC1_Enabled (0x1UL)        /*!< Processor comparator 1 is selected for Single-shot control.          */

/* PC2 @Bit 2 : Selects processor comparator 2 inputs for Single-shot control */
  #define ETM_TRCSSPCICR0_PC2_Pos (2UL)              /*!< Position of PC2 field.                                               */
  #define ETM_TRCSSPCICR0_PC2_Msk (0x1UL << ETM_TRCSSPCICR0_PC2_Pos) /*!< Bit mask of PC2 field.                               */
  #define ETM_TRCSSPCICR0_PC2_Min (0x0UL)            /*!< Min enumerator value of PC2 field.                                   */
  #define ETM_TRCSSPCICR0_PC2_Max (0x1UL)            /*!< Max enumerator value of PC2 field.                                   */
  #define ETM_TRCSSPCICR0_PC2_Disabled (0x0UL)       /*!< Processor comparator 2 is not selected for Single-shot control.      */
  #define ETM_TRCSSPCICR0_PC2_Enabled (0x1UL)        /*!< Processor comparator 2 is selected for Single-shot control.          */

/* PC3 @Bit 3 : Selects processor comparator 3 inputs for Single-shot control */
  #define ETM_TRCSSPCICR0_PC3_Pos (3UL)              /*!< Position of PC3 field.                                               */
  #define ETM_TRCSSPCICR0_PC3_Msk (0x1UL << ETM_TRCSSPCICR0_PC3_Pos) /*!< Bit mask of PC3 field.                               */
  #define ETM_TRCSSPCICR0_PC3_Min (0x0UL)            /*!< Min enumerator value of PC3 field.                                   */
  #define ETM_TRCSSPCICR0_PC3_Max (0x1UL)            /*!< Max enumerator value of PC3 field.                                   */
  #define ETM_TRCSSPCICR0_PC3_Disabled (0x0UL)       /*!< Processor comparator 3 is not selected for Single-shot control.      */
  #define ETM_TRCSSPCICR0_PC3_Enabled (0x1UL)        /*!< Processor comparator 3 is selected for Single-shot control.          */


/* ETM_TRCPDCR: Controls the single-shot comparator. */
  #define ETM_TRCPDCR_ResetValue (0x00000000UL)      /*!< Reset value of TRCPDCR register.                                     */

/* PU @Bit 24 : Power up request, to request that power to ETM and access to the trace registers is maintained. */
  #define ETM_TRCPDCR_PU_Pos (24UL)                  /*!< Position of PU field.                                                */
  #define ETM_TRCPDCR_PU_Msk (0x1UL << ETM_TRCPDCR_PU_Pos) /*!< Bit mask of PU field.                                          */
  #define ETM_TRCPDCR_PU_Min (0x0UL)                 /*!< Min enumerator value of PU field.                                    */
  #define ETM_TRCPDCR_PU_Max (0x1UL)                 /*!< Max enumerator value of PU field.                                    */
  #define ETM_TRCPDCR_PU_Disabled (0x0UL)            /*!< Power not requested.                                                 */
  #define ETM_TRCPDCR_PU_Enabled (0x1UL)             /*!< Power requested.                                                     */


/* ETM_TRCPDSR: Indicates the power down status of the ETM. */
  #define ETM_TRCPDSR_ResetValue (0x00000000UL)      /*!< Reset value of TRCPDSR register.                                     */

/* POWER @Bit 0 : Indicates ETM is powered up */
  #define ETM_TRCPDSR_POWER_Pos (0UL)                /*!< Position of POWER field.                                             */
  #define ETM_TRCPDSR_POWER_Msk (0x1UL << ETM_TRCPDSR_POWER_Pos) /*!< Bit mask of POWER field.                                 */
  #define ETM_TRCPDSR_POWER_Min (0x0UL)              /*!< Min enumerator value of POWER field.                                 */
  #define ETM_TRCPDSR_POWER_Max (0x1UL)              /*!< Max enumerator value of POWER field.                                 */
  #define ETM_TRCPDSR_POWER_NotPoweredUp (0x0UL)     /*!< ETM is not powered up. All registers are not accessible.             */
  #define ETM_TRCPDSR_POWER_PoweredUp (0x1UL)        /*!< ETM is powered up. All registers are accessible.                     */

/* STICKYPD @Bit 1 : Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that
                     programming state has been lost. It is cleared after a read of the TRCPDSR */

  #define ETM_TRCPDSR_STICKYPD_Pos (1UL)             /*!< Position of STICKYPD field.                                          */
  #define ETM_TRCPDSR_STICKYPD_Msk (0x1UL << ETM_TRCPDSR_STICKYPD_Pos) /*!< Bit mask of STICKYPD field.                        */
  #define ETM_TRCPDSR_STICKYPD_Min (0x0UL)           /*!< Min enumerator value of STICKYPD field.                              */
  #define ETM_TRCPDSR_STICKYPD_Max (0x1UL)           /*!< Max enumerator value of STICKYPD field.                              */
  #define ETM_TRCPDSR_STICKYPD_NotPoweredDown (0x0UL) /*!< Trace register power has not been removed since the TRCPDSR was last
                                                           read.*/
  #define ETM_TRCPDSR_STICKYPD_PoweredDown (0x1UL)   /*!< Trace register power has been removed since the TRCPDSR was last
                                                          read.*/


/* ETM_TRCITATBIDR: Sets the state of output pins. */
  #define ETM_TRCITATBIDR_ResetValue (0x00000000UL)  /*!< Reset value of TRCITATBIDR register.                                 */

/* ID0 @Bit 0 : Drives the ATIDMI[0] output pin. */
  #define ETM_TRCITATBIDR_ID0_Pos (0UL)              /*!< Position of ID0 field.                                               */
  #define ETM_TRCITATBIDR_ID0_Msk (0x1UL << ETM_TRCITATBIDR_ID0_Pos) /*!< Bit mask of ID0 field.                               */

/* ID1 @Bit 1 : Drives the ATIDMI[1] output pin. */
  #define ETM_TRCITATBIDR_ID1_Pos (1UL)              /*!< Position of ID1 field.                                               */
  #define ETM_TRCITATBIDR_ID1_Msk (0x1UL << ETM_TRCITATBIDR_ID1_Pos) /*!< Bit mask of ID1 field.                               */

/* ID2 @Bit 2 : Drives the ATIDMI[2] output pin. */
  #define ETM_TRCITATBIDR_ID2_Pos (2UL)              /*!< Position of ID2 field.                                               */
  #define ETM_TRCITATBIDR_ID2_Msk (0x1UL << ETM_TRCITATBIDR_ID2_Pos) /*!< Bit mask of ID2 field.                               */

/* ID3 @Bit 3 : Drives the ATIDMI[3] output pin. */
  #define ETM_TRCITATBIDR_ID3_Pos (3UL)              /*!< Position of ID3 field.                                               */
  #define ETM_TRCITATBIDR_ID3_Msk (0x1UL << ETM_TRCITATBIDR_ID3_Pos) /*!< Bit mask of ID3 field.                               */

/* ID4 @Bit 4 : Drives the ATIDMI[4] output pin. */
  #define ETM_TRCITATBIDR_ID4_Pos (4UL)              /*!< Position of ID4 field.                                               */
  #define ETM_TRCITATBIDR_ID4_Msk (0x1UL << ETM_TRCITATBIDR_ID4_Pos) /*!< Bit mask of ID4 field.                               */

/* ID5 @Bit 5 : Drives the ATIDMI[5] output pin. */
  #define ETM_TRCITATBIDR_ID5_Pos (5UL)              /*!< Position of ID5 field.                                               */
  #define ETM_TRCITATBIDR_ID5_Msk (0x1UL << ETM_TRCITATBIDR_ID5_Pos) /*!< Bit mask of ID5 field.                               */

/* ID6 @Bit 6 : Drives the ATIDMI[6] output pin. */
  #define ETM_TRCITATBIDR_ID6_Pos (6UL)              /*!< Position of ID6 field.                                               */
  #define ETM_TRCITATBIDR_ID6_Msk (0x1UL << ETM_TRCITATBIDR_ID6_Pos) /*!< Bit mask of ID6 field.                               */


/* ETM_TRCITIATBINR: Reads the state of the input pins. */
  #define ETM_TRCITIATBINR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBINR register.                                */

/* ATVALID @Bit 0 : Returns the value of the ATVALIDMI input pin. */
  #define ETM_TRCITIATBINR_ATVALID_Pos (0UL)         /*!< Position of ATVALID field.                                           */
  #define ETM_TRCITIATBINR_ATVALID_Msk (0x1UL << ETM_TRCITIATBINR_ATVALID_Pos) /*!< Bit mask of ATVALID field.                 */

/* AFREADY @Bit 1 : Returns the value of the AFREADYMI input pin. */
  #define ETM_TRCITIATBINR_AFREADY_Pos (1UL)         /*!< Position of AFREADY field.                                           */
  #define ETM_TRCITIATBINR_AFREADY_Msk (0x1UL << ETM_TRCITIATBINR_AFREADY_Pos) /*!< Bit mask of AFREADY field.                 */


/* ETM_TRCITIATBOUTR: Sets the state of the output pins. */
  #define ETM_TRCITIATBOUTR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBOUTR register.                              */

/* ATVALID @Bit 0 : Drives the ATVALIDMI output pin. */
  #define ETM_TRCITIATBOUTR_ATVALID_Pos (0UL)        /*!< Position of ATVALID field.                                           */
  #define ETM_TRCITIATBOUTR_ATVALID_Msk (0x1UL << ETM_TRCITIATBOUTR_ATVALID_Pos) /*!< Bit mask of ATVALID field.               */

/* AFREADY @Bit 1 : Drives the AFREADYMI output pin. */
  #define ETM_TRCITIATBOUTR_AFREADY_Pos (1UL)        /*!< Position of AFREADY field.                                           */
  #define ETM_TRCITIATBOUTR_AFREADY_Msk (0x1UL << ETM_TRCITIATBOUTR_AFREADY_Pos) /*!< Bit mask of AFREADY field.               */


/* ETM_TRCITCTRL: Enables topology detection or integration testing, by putting ETM-M33 into integration mode. */
  #define ETM_TRCITCTRL_ResetValue (0x00000000UL)    /*!< Reset value of TRCITCTRL register.                                   */

/* IME @Bit 0 : Integration mode enable */
  #define ETM_TRCITCTRL_IME_Pos (0UL)                /*!< Position of IME field.                                               */
  #define ETM_TRCITCTRL_IME_Msk (0x1UL << ETM_TRCITCTRL_IME_Pos) /*!< Bit mask of IME field.                                   */
  #define ETM_TRCITCTRL_IME_Min (0x0UL)              /*!< Min enumerator value of IME field.                                   */
  #define ETM_TRCITCTRL_IME_Max (0x1UL)              /*!< Max enumerator value of IME field.                                   */
  #define ETM_TRCITCTRL_IME_Disabled (0x0UL)         /*!< ETM is not in integration mode.                                      */
  #define ETM_TRCITCTRL_IME_Enabled (0x1UL)          /*!< ETM is in integration mode.                                          */


/* ETM_TRCCLAIMSET: Sets bits in the claim tag and determines the number of claim tag bits implemented. */
  #define ETM_TRCCLAIMSET_ResetValue (0x00000000UL)  /*!< Reset value of TRCCLAIMSET register.                                 */

/* SET0 @Bit 0 : Claim tag set register */
  #define ETM_TRCCLAIMSET_SET0_Pos (0UL)             /*!< Position of SET0 field.                                              */
  #define ETM_TRCCLAIMSET_SET0_Msk (0x1UL << ETM_TRCCLAIMSET_SET0_Pos) /*!< Bit mask of SET0 field.                            */
  #define ETM_TRCCLAIMSET_SET0_Min (0x0UL)           /*!< Min enumerator value of SET0 field.                                  */
  #define ETM_TRCCLAIMSET_SET0_Max (0x1UL)           /*!< Max enumerator value of SET0 field.                                  */
  #define ETM_TRCCLAIMSET_SET0_NotSet (0x0UL)        /*!< Claim tag 0 is not set.                                              */
  #define ETM_TRCCLAIMSET_SET0_Set (0x1UL)           /*!< Claim tag 0 is set.                                                  */
  #define ETM_TRCCLAIMSET_SET0_Claim (0x1UL)         /*!< Set claim tag 0.                                                     */

/* SET1 @Bit 1 : Claim tag set register */
  #define ETM_TRCCLAIMSET_SET1_Pos (1UL)             /*!< Position of SET1 field.                                              */
  #define ETM_TRCCLAIMSET_SET1_Msk (0x1UL << ETM_TRCCLAIMSET_SET1_Pos) /*!< Bit mask of SET1 field.                            */
  #define ETM_TRCCLAIMSET_SET1_Min (0x0UL)           /*!< Min enumerator value of SET1 field.                                  */
  #define ETM_TRCCLAIMSET_SET1_Max (0x1UL)           /*!< Max enumerator value of SET1 field.                                  */
  #define ETM_TRCCLAIMSET_SET1_NotSet (0x0UL)        /*!< Claim tag 1 is not set.                                              */
  #define ETM_TRCCLAIMSET_SET1_Set (0x1UL)           /*!< Claim tag 1 is set.                                                  */
  #define ETM_TRCCLAIMSET_SET1_Claim (0x1UL)         /*!< Set claim tag 1.                                                     */

/* SET2 @Bit 2 : Claim tag set register */
  #define ETM_TRCCLAIMSET_SET2_Pos (2UL)             /*!< Position of SET2 field.                                              */
  #define ETM_TRCCLAIMSET_SET2_Msk (0x1UL << ETM_TRCCLAIMSET_SET2_Pos) /*!< Bit mask of SET2 field.                            */
  #define ETM_TRCCLAIMSET_SET2_Min (0x0UL)           /*!< Min enumerator value of SET2 field.                                  */
  #define ETM_TRCCLAIMSET_SET2_Max (0x1UL)           /*!< Max enumerator value of SET2 field.                                  */
  #define ETM_TRCCLAIMSET_SET2_NotSet (0x0UL)        /*!< Claim tag 2 is not set.                                              */
  #define ETM_TRCCLAIMSET_SET2_Set (0x1UL)           /*!< Claim tag 2 is set.                                                  */
  #define ETM_TRCCLAIMSET_SET2_Claim (0x1UL)         /*!< Set claim tag 2.                                                     */

/* SET3 @Bit 3 : Claim tag set register */
  #define ETM_TRCCLAIMSET_SET3_Pos (3UL)             /*!< Position of SET3 field.                                              */
  #define ETM_TRCCLAIMSET_SET3_Msk (0x1UL << ETM_TRCCLAIMSET_SET3_Pos) /*!< Bit mask of SET3 field.                            */
  #define ETM_TRCCLAIMSET_SET3_Min (0x0UL)           /*!< Min enumerator value of SET3 field.                                  */
  #define ETM_TRCCLAIMSET_SET3_Max (0x1UL)           /*!< Max enumerator value of SET3 field.                                  */
  #define ETM_TRCCLAIMSET_SET3_NotSet (0x0UL)        /*!< Claim tag 3 is not set.                                              */
  #define ETM_TRCCLAIMSET_SET3_Set (0x1UL)           /*!< Claim tag 3 is set.                                                  */
  #define ETM_TRCCLAIMSET_SET3_Claim (0x1UL)         /*!< Set claim tag 3.                                                     */


/* ETM_TRCCLAIMCLR: Clears bits in the claim tag and determines the current value of the claim tag. */
  #define ETM_TRCCLAIMCLR_ResetValue (0x00000000UL)  /*!< Reset value of TRCCLAIMCLR register.                                 */

/* CLR0 @Bit 0 : Claim tag clear register */
  #define ETM_TRCCLAIMCLR_CLR0_Pos (0UL)             /*!< Position of CLR0 field.                                              */
  #define ETM_TRCCLAIMCLR_CLR0_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR0_Pos) /*!< Bit mask of CLR0 field.                            */
  #define ETM_TRCCLAIMCLR_CLR0_Min (0x0UL)           /*!< Min enumerator value of CLR0 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR0_Max (0x1UL)           /*!< Max enumerator value of CLR0 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR0_NotSet (0x0UL)        /*!< Claim tag 0 is not set.                                              */
  #define ETM_TRCCLAIMCLR_CLR0_Set (0x1UL)           /*!< Claim tag 0 is set.                                                  */
  #define ETM_TRCCLAIMCLR_CLR0_Clear (0x1UL)         /*!< Clear claim tag 0.                                                   */

/* CLR1 @Bit 1 : Claim tag clear register */
  #define ETM_TRCCLAIMCLR_CLR1_Pos (1UL)             /*!< Position of CLR1 field.                                              */
  #define ETM_TRCCLAIMCLR_CLR1_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR1_Pos) /*!< Bit mask of CLR1 field.                            */
  #define ETM_TRCCLAIMCLR_CLR1_Min (0x0UL)           /*!< Min enumerator value of CLR1 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR1_Max (0x1UL)           /*!< Max enumerator value of CLR1 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR1_NotSet (0x0UL)        /*!< Claim tag 1 is not set.                                              */
  #define ETM_TRCCLAIMCLR_CLR1_Set (0x1UL)           /*!< Claim tag 1 is set.                                                  */
  #define ETM_TRCCLAIMCLR_CLR1_Clear (0x1UL)         /*!< Clear claim tag 1.                                                   */

/* CLR2 @Bit 2 : Claim tag clear register */
  #define ETM_TRCCLAIMCLR_CLR2_Pos (2UL)             /*!< Position of CLR2 field.                                              */
  #define ETM_TRCCLAIMCLR_CLR2_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR2_Pos) /*!< Bit mask of CLR2 field.                            */
  #define ETM_TRCCLAIMCLR_CLR2_Min (0x0UL)           /*!< Min enumerator value of CLR2 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR2_Max (0x1UL)           /*!< Max enumerator value of CLR2 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR2_NotSet (0x0UL)        /*!< Claim tag 2 is not set.                                              */
  #define ETM_TRCCLAIMCLR_CLR2_Set (0x1UL)           /*!< Claim tag 2 is set.                                                  */
  #define ETM_TRCCLAIMCLR_CLR2_Clear (0x1UL)         /*!< Clear claim tag 2.                                                   */

/* CLR3 @Bit 3 : Claim tag clear register */
  #define ETM_TRCCLAIMCLR_CLR3_Pos (3UL)             /*!< Position of CLR3 field.                                              */
  #define ETM_TRCCLAIMCLR_CLR3_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR3_Pos) /*!< Bit mask of CLR3 field.                            */
  #define ETM_TRCCLAIMCLR_CLR3_Min (0x0UL)           /*!< Min enumerator value of CLR3 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR3_Max (0x1UL)           /*!< Max enumerator value of CLR3 field.                                  */
  #define ETM_TRCCLAIMCLR_CLR3_NotSet (0x0UL)        /*!< Claim tag 3 is not set.                                              */
  #define ETM_TRCCLAIMCLR_CLR3_Set (0x1UL)           /*!< Claim tag 3 is set.                                                  */
  #define ETM_TRCCLAIMCLR_CLR3_Clear (0x1UL)         /*!< Clear claim tag 3.                                                   */


/* ETM_TRCAUTHSTATUS: Indicates the current level of tracing permitted by the system */
  #define ETM_TRCAUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TRCAUTHSTATUS register.                              */

/* NSID @Bits 0..1 : Non-secure Invasive Debug */
  #define ETM_TRCAUTHSTATUS_NSID_Pos (0UL)           /*!< Position of NSID field.                                              */
  #define ETM_TRCAUTHSTATUS_NSID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.                        */
  #define ETM_TRCAUTHSTATUS_NSID_Min (0x0UL)         /*!< Min enumerator value of NSID field.                                  */
  #define ETM_TRCAUTHSTATUS_NSID_Max (0x1UL)         /*!< Max enumerator value of NSID field.                                  */
  #define ETM_TRCAUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                   */
  #define ETM_TRCAUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented.                                          */

/* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */
  #define ETM_TRCAUTHSTATUS_NSNID_Pos (2UL)          /*!< Position of NSNID field.                                             */
  #define ETM_TRCAUTHSTATUS_NSNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.                     */
  #define ETM_TRCAUTHSTATUS_NSNID_Min (0x0UL)        /*!< Min enumerator value of NSNID field.                                 */
  #define ETM_TRCAUTHSTATUS_NSNID_Max (0x1UL)        /*!< Max enumerator value of NSNID field.                                 */
  #define ETM_TRCAUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                  */
  #define ETM_TRCAUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented.                                         */

/* SID @Bits 4..5 : Secure Invasive Debug */
  #define ETM_TRCAUTHSTATUS_SID_Pos (4UL)            /*!< Position of SID field.                                               */
  #define ETM_TRCAUTHSTATUS_SID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.                           */
  #define ETM_TRCAUTHSTATUS_SID_Min (0x0UL)          /*!< Min enumerator value of SID field.                                   */
  #define ETM_TRCAUTHSTATUS_SID_Max (0x1UL)          /*!< Max enumerator value of SID field.                                   */
  #define ETM_TRCAUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                    */
  #define ETM_TRCAUTHSTATUS_SID_Implemented (0x1UL)  /*!< The feature is implemented.                                          */

/* SNID @Bits 6..7 : Secure Non-Invasive Debug */
  #define ETM_TRCAUTHSTATUS_SNID_Pos (6UL)           /*!< Position of SNID field.                                              */
  #define ETM_TRCAUTHSTATUS_SNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.                        */
  #define ETM_TRCAUTHSTATUS_SNID_Min (0x0UL)         /*!< Min enumerator value of SNID field.                                  */
  #define ETM_TRCAUTHSTATUS_SNID_Max (0x1UL)         /*!< Max enumerator value of SNID field.                                  */
  #define ETM_TRCAUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                   */
  #define ETM_TRCAUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented.                                          */


/* ETM_TRCDEVARCH: The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component */
  #define ETM_TRCDEVARCH_ResetValue (0x00000000UL)   /*!< Reset value of TRCDEVARCH register.                                  */

/* ARCHID @Bits 0..15 : Architecture ID */
  #define ETM_TRCDEVARCH_ARCHID_Pos (0UL)            /*!< Position of ARCHID field.                                            */
  #define ETM_TRCDEVARCH_ARCHID_Msk (0xFFFFUL << ETM_TRCDEVARCH_ARCHID_Pos) /*!< Bit mask of ARCHID field.                     */
  #define ETM_TRCDEVARCH_ARCHID_Min (0x4A13UL)       /*!< Min enumerator value of ARCHID field.                                */
  #define ETM_TRCDEVARCH_ARCHID_Max (0x4A13UL)       /*!< Max enumerator value of ARCHID field.                                */
  #define ETM_TRCDEVARCH_ARCHID_ETMv42 (0x4A13UL)    /*!< Component is an ETMv4 component                                      */

/* REVISION @Bits 16..19 : Architecture revision */
  #define ETM_TRCDEVARCH_REVISION_Pos (16UL)         /*!< Position of REVISION field.                                          */
  #define ETM_TRCDEVARCH_REVISION_Msk (0xFUL << ETM_TRCDEVARCH_REVISION_Pos) /*!< Bit mask of REVISION field.                  */
  #define ETM_TRCDEVARCH_REVISION_Min (0x2UL)        /*!< Min enumerator value of REVISION field.                              */
  #define ETM_TRCDEVARCH_REVISION_Max (0x2UL)        /*!< Max enumerator value of REVISION field.                              */
  #define ETM_TRCDEVARCH_REVISION_v2 (0x2UL)         /*!< Component is part of architecture 4.2                                */

/* PRESENT @Bit 20 : This register is implemented */
  #define ETM_TRCDEVARCH_PRESENT_Pos (20UL)          /*!< Position of PRESENT field.                                           */
  #define ETM_TRCDEVARCH_PRESENT_Msk (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos) /*!< Bit mask of PRESENT field.                     */
  #define ETM_TRCDEVARCH_PRESENT_Min (0x0UL)         /*!< Min enumerator value of PRESENT field.                               */
  #define ETM_TRCDEVARCH_PRESENT_Max (0x1UL)         /*!< Max enumerator value of PRESENT field.                               */
  #define ETM_TRCDEVARCH_PRESENT_Absent (0x0UL)      /*!< The register is not implemented.                                     */
  #define ETM_TRCDEVARCH_PRESENT_Present (0x1UL)     /*!< The register is implemented.                                         */

/* ARCHITECT @Bits 21..31 : Defines the architect of the component */
  #define ETM_TRCDEVARCH_ARCHITECT_Pos (21UL)        /*!< Position of ARCHITECT field.                                         */
  #define ETM_TRCDEVARCH_ARCHITECT_Msk (0x7FFUL << ETM_TRCDEVARCH_ARCHITECT_Pos) /*!< Bit mask of ARCHITECT field.             */
  #define ETM_TRCDEVARCH_ARCHITECT_Min (0x23BUL)     /*!< Min enumerator value of ARCHITECT field.                             */
  #define ETM_TRCDEVARCH_ARCHITECT_Max (0x23BUL)     /*!< Max enumerator value of ARCHITECT field.                             */
  #define ETM_TRCDEVARCH_ARCHITECT_Arm (0x23BUL)     /*!< This peripheral was architected by Arm.                              */


/* ETM_TRCDEVTYPE: Controls the single-shot comparator. */
  #define ETM_TRCDEVTYPE_ResetValue (0x00000000UL)   /*!< Reset value of TRCDEVTYPE register.                                  */

/* MAJOR @Bits 0..3 : The main type of the component */
  #define ETM_TRCDEVTYPE_MAJOR_Pos (0UL)             /*!< Position of MAJOR field.                                             */
  #define ETM_TRCDEVTYPE_MAJOR_Msk (0xFUL << ETM_TRCDEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field.                           */
  #define ETM_TRCDEVTYPE_MAJOR_Min (0x3UL)           /*!< Min enumerator value of MAJOR field.                                 */
  #define ETM_TRCDEVTYPE_MAJOR_Max (0x3UL)           /*!< Max enumerator value of MAJOR field.                                 */
  #define ETM_TRCDEVTYPE_MAJOR_TraceSource (0x3UL)   /*!< Peripheral is a trace source.                                        */

/* SUB @Bits 4..7 : The sub-type of the component */
  #define ETM_TRCDEVTYPE_SUB_Pos (4UL)               /*!< Position of SUB field.                                               */
  #define ETM_TRCDEVTYPE_SUB_Msk (0xFUL << ETM_TRCDEVTYPE_SUB_Pos) /*!< Bit mask of SUB field.                                 */
  #define ETM_TRCDEVTYPE_SUB_Min (0x1UL)             /*!< Min enumerator value of SUB field.                                   */
  #define ETM_TRCDEVTYPE_SUB_Max (0x1UL)             /*!< Max enumerator value of SUB field.                                   */
  #define ETM_TRCDEVTYPE_SUB_ProcessorTrace (0x1UL)  /*!< Peripheral is a processor trace source.                              */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           FICR                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ==================================================== Struct FICR_INFO ===================================================== */
/**
  * @brief INFO [FICR_INFO] Device info
  */
typedef struct {
  __IM  uint32_t  CONFIGID;                          /*!< (@ 0x00000000) Configuration identifier                              */
  __IM  uint32_t  DEVICEID[2];                       /*!< (@ 0x00000004) Device identifier                                     */
  __IOM uint32_t  UUID[4];                           /*!< (@ 0x0000000C) 128-bit Universally Unique IDentifier (UUID).         */
  __IM  uint32_t  PART;                              /*!< (@ 0x0000001C) Part code                                             */
  __IM  uint32_t  VARIANT;                           /*!< (@ 0x00000020) Part Variant, Hardware version and Production
                                                                         configuration*/
  __IM  uint32_t  PACKAGE;                           /*!< (@ 0x00000024) Package option                                        */
  __IM  uint32_t  RAM;                               /*!< (@ 0x00000028) RAM size (KB)                                         */
  __IM  uint32_t  RRAM;                              /*!< (@ 0x0000002C) RRAM size (KB)                                        */
} NRF_FICR_INFO_Type;                                /*!< Size = 48 (0x030)                                                    */

/* FICR_INFO_CONFIGID: Configuration identifier */
  #define FICR_INFO_CONFIGID_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIGID register.                                  */

/* HWID @Bits 0..15 : Identification number for the HW */
  #define FICR_INFO_CONFIGID_HWID_Pos (0UL)          /*!< Position of HWID field.                                              */
  #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field.                   */


/* FICR_INFO_DEVICEID: Device identifier */
  #define FICR_INFO_DEVICEID_MaxCount (2UL)          /*!< Max size of DEVICEID[2] array.                                       */
  #define FICR_INFO_DEVICEID_MaxIndex (1UL)          /*!< Max index of DEVICEID[2] array.                                      */
  #define FICR_INFO_DEVICEID_MinIndex (0UL)          /*!< Min index of DEVICEID[2] array.                                      */
  #define FICR_INFO_DEVICEID_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DEVICEID[2] register.                               */

/* DEVICEID @Bits 0..31 : 64 bit unique device identifier */
  #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL)      /*!< Position of DEVICEID field.                                          */
  #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field.   */


/* FICR_INFO_UUID: 128-bit Universally Unique IDentifier (UUID). */
  #define FICR_INFO_UUID_MaxCount (4UL)              /*!< Max size of UUID[4] array.                                           */
  #define FICR_INFO_UUID_MaxIndex (3UL)              /*!< Max index of UUID[4] array.                                          */
  #define FICR_INFO_UUID_MinIndex (0UL)              /*!< Min index of UUID[4] array.                                          */
  #define FICR_INFO_UUID_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of UUID[4] register.                                     */

/* UUID @Bits 0..31 : Device UUID [n]. */
  #define FICR_INFO_UUID_UUID_Pos (0UL)              /*!< Position of UUID field.                                              */
  #define FICR_INFO_UUID_UUID_Msk (0xFFFFFFFFUL << FICR_INFO_UUID_UUID_Pos) /*!< Bit mask of UUID field.                       */


/* FICR_INFO_PART: Part code */
  #define FICR_INFO_PART_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of PART register.                                        */

/* PART @Bits 0..31 : Part code */
  #define FICR_INFO_PART_PART_Pos (0UL)              /*!< Position of PART field.                                              */
  #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field.                       */
  #define FICR_INFO_PART_PART_Min (0x54B05UL)        /*!< Min enumerator value of PART field.                                  */
  #define FICR_INFO_PART_PART_Max (0xFFFFFFFFUL)     /*!< Max enumerator value of PART field.                                  */
  #define FICR_INFO_PART_PART_N54L15 (0x00054B15UL)  /*!< nRF54L15                                                             */
  #define FICR_INFO_PART_PART_N54L10 (0x00054B10UL)  /*!< nRF54L10                                                             */
  #define FICR_INFO_PART_PART_N54L05 (0x00054B05UL)  /*!< nRF54L05                                                             */
  #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                      */


/* FICR_INFO_VARIANT: Part Variant, Hardware version and Production configuration */
  #define FICR_INFO_VARIANT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VARIANT register.                                    */

/* VARIANT @Bits 0..31 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
  #define FICR_INFO_VARIANT_VARIANT_Pos (0UL)        /*!< Position of VARIANT field.                                           */
  #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field.        */
  #define FICR_INFO_VARIANT_VARIANT_Min (0xFFFFFFFFUL) /*!< Min enumerator value of VARIANT field.                             */
  #define FICR_INFO_VARIANT_VARIANT_Max (0xFFFFFFFFUL) /*!< Max enumerator value of VARIANT field.                             */
  #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                */


/* FICR_INFO_PACKAGE: Package option */
  #define FICR_INFO_PACKAGE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PACKAGE register.                                    */

/* PACKAGE @Bits 0..31 : Package option */
  #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL)        /*!< Position of PACKAGE field.                                           */
  #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field.        */
  #define FICR_INFO_PACKAGE_PACKAGE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PACKAGE field.                             */
  #define FICR_INFO_PACKAGE_PACKAGE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PACKAGE field.                             */
  #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                */


/* FICR_INFO_RAM: RAM size (KB) */
  #define FICR_INFO_RAM_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of RAM register.                                         */

/* RAM @Bits 0..31 : RAM size (KB) */
  #define FICR_INFO_RAM_RAM_Pos (0UL)                /*!< Position of RAM field.                                               */
  #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field.                            */
  #define FICR_INFO_RAM_RAM_Min (0x60UL)             /*!< Min enumerator value of RAM field.                                   */
  #define FICR_INFO_RAM_RAM_Max (0xFFFFFFFFUL)       /*!< Max enumerator value of RAM field.                                   */
  #define FICR_INFO_RAM_RAM_K256 (0x00000100UL)      /*!< 256 kByte RAM                                                        */
  #define FICR_INFO_RAM_RAM_K192 (0x000000C0UL)      /*!< 192 kByte RAM                                                        */
  #define FICR_INFO_RAM_RAM_K96 (0x00000060UL)       /*!< 96 kByte RAM                                                         */
  #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                        */


/* FICR_INFO_RRAM: RRAM size (KB) */
  #define FICR_INFO_RRAM_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of RRAM register.                                        */

/* RRAM @Bits 0..31 : RRAM size (KB) */
  #define FICR_INFO_RRAM_RRAM_Pos (0UL)              /*!< Position of RRAM field.                                              */
  #define FICR_INFO_RRAM_RRAM_Msk (0xFFFFFFFFUL << FICR_INFO_RRAM_RRAM_Pos) /*!< Bit mask of RRAM field.                       */
  #define FICR_INFO_RRAM_RRAM_Min (0x1F4UL)          /*!< Min enumerator value of RRAM field.                                  */
  #define FICR_INFO_RRAM_RRAM_Max (0xFFFFFFFFUL)     /*!< Max enumerator value of RRAM field.                                  */
  #define FICR_INFO_RRAM_RRAM_K1524 (0x000005F4UL)   /*!< 1524 KByte RRAM                                                      */
  #define FICR_INFO_RRAM_RRAM_K1012 (0x000003F4UL)   /*!< 1012 KByte RRAM                                                      */
  #define FICR_INFO_RRAM_RRAM_K500 (0x000001F4UL)    /*!< 500 KByte RRAM                                                       */
  #define FICR_INFO_RRAM_RRAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                      */



/* =================================================== Struct FICR_TRIMCNF =================================================== */
/**
  * @brief TRIMCNF [FICR_TRIMCNF] (unspecified)
  */
typedef struct {
  __IM  uint32_t  ADDR;                              /*!< (@ 0x00000000) Address of the register which will be written         */
  __IM  uint32_t  DATA;                              /*!< (@ 0x00000004) Data to be written into the register                  */
} NRF_FICR_TRIMCNF_Type;                             /*!< Size = 8 (0x008)                                                     */
  #define FICR_TRIMCNF_MaxCount (64UL)               /*!< Size of TRIMCNF[64] array.                                           */
  #define FICR_TRIMCNF_MaxIndex (63UL)               /*!< Max index of TRIMCNF[64] array.                                      */
  #define FICR_TRIMCNF_MinIndex (0UL)                /*!< Min index of TRIMCNF[64] array.                                      */

/* FICR_TRIMCNF_ADDR: Address of the register which will be written */
  #define FICR_TRIMCNF_ADDR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ADDR register.                                       */

/* Address @Bits 0..31 : Address */
  #define FICR_TRIMCNF_ADDR_Address_Pos (0UL)        /*!< Position of Address field.                                           */
  #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field.        */


/* FICR_TRIMCNF_DATA: Data to be written into the register */
  #define FICR_TRIMCNF_DATA_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DATA register.                                       */

/* Data @Bits 0..31 : Data */
  #define FICR_TRIMCNF_DATA_Data_Pos (0UL)           /*!< Position of Data field.                                              */
  #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field.                 */



/* ===================================================== Struct FICR_NFC ===================================================== */
/**
  * @brief NFC [FICR_NFC] (unspecified)
  */
typedef struct {
  __IM  uint32_t  TAGHEADER0;                        /*!< (@ 0x00000000) Default header for NFC Tag. Software can read these
                                                                         values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and
                                                                         NFCID1_LAST.*/
  __IM  uint32_t  TAGHEADER1;                        /*!< (@ 0x00000004) Default header for NFC Tag. Software can read these
                                                                         values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and
                                                                         NFCID1_LAST.*/
  __IM  uint32_t  TAGHEADER2;                        /*!< (@ 0x00000008) Default header for NFC Tag. Software can read these
                                                                         values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and
                                                                         NFCID1_LAST.*/
  __IM  uint32_t  TAGHEADER3;                        /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read these
                                                                         values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and
                                                                         NFCID1_LAST.*/
} NRF_FICR_NFC_Type;                                 /*!< Size = 16 (0x010)                                                    */

/* FICR_NFC_TAGHEADER0: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST
                         and NFCID1_LAST. */

  #define FICR_NFC_TAGHEADER0_ResetValue (0xFFFFFF5FUL) /*!< Reset value of TAGHEADER0 register.                               */

/* MFGID @Bits 0..7 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
  #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL)        /*!< Position of MFGID field.                                             */
  #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field.                */

/* UD1 @Bits 8..15 : Unique identifier byte 1 */
  #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL)          /*!< Position of UD1 field.                                               */
  #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field.                      */

/* UD2 @Bits 16..23 : Unique identifier byte 2 */
  #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL)         /*!< Position of UD2 field.                                               */
  #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field.                      */

/* UD3 @Bits 24..31 : Unique identifier byte 3 */
  #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL)         /*!< Position of UD3 field.                                               */
  #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field.                      */


/* FICR_NFC_TAGHEADER1: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST
                         and NFCID1_LAST. */

  #define FICR_NFC_TAGHEADER1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAGHEADER1 register.                               */

/* UD4 @Bits 0..7 : Unique identifier byte 4 */
  #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL)          /*!< Position of UD4 field.                                               */
  #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field.                      */

/* UD5 @Bits 8..15 : Unique identifier byte 5 */
  #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL)          /*!< Position of UD5 field.                                               */
  #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field.                      */

/* UD6 @Bits 16..23 : Unique identifier byte 6 */
  #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL)         /*!< Position of UD6 field.                                               */
  #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field.                      */

/* UD7 @Bits 24..31 : Unique identifier byte 7 */
  #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL)         /*!< Position of UD7 field.                                               */
  #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field.                      */


/* FICR_NFC_TAGHEADER2: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST
                         and NFCID1_LAST. */

  #define FICR_NFC_TAGHEADER2_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAGHEADER2 register.                               */

/* UD8 @Bits 0..7 : Unique identifier byte 8 */
  #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL)          /*!< Position of UD8 field.                                               */
  #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field.                      */

/* UD9 @Bits 8..15 : Unique identifier byte 9 */
  #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL)          /*!< Position of UD9 field.                                               */
  #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field.                      */

/* UD10 @Bits 16..23 : Unique identifier byte 10 */
  #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL)        /*!< Position of UD10 field.                                              */
  #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field.                   */

/* UD11 @Bits 24..31 : Unique identifier byte 11 */
  #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL)        /*!< Position of UD11 field.                                              */
  #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field.                   */


/* FICR_NFC_TAGHEADER3: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST
                         and NFCID1_LAST. */

  #define FICR_NFC_TAGHEADER3_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAGHEADER3 register.                               */

/* UD12 @Bits 0..7 : Unique identifier byte 12 */
  #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL)         /*!< Position of UD12 field.                                              */
  #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field.                   */

/* UD13 @Bits 8..15 : Unique identifier byte 13 */
  #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL)         /*!< Position of UD13 field.                                              */
  #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field.                   */

/* UD14 @Bits 16..23 : Unique identifier byte 14 */
  #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL)        /*!< Position of UD14 field.                                              */
  #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field.                   */

/* UD15 @Bits 24..31 : Unique identifier byte 15 */
  #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL)        /*!< Position of UD15 field.                                              */
  #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field.                   */


/* ======================================================= Struct FICR ======================================================= */
/**
  * @brief Factory Information Configuration Registers
  */
  typedef struct {                                   /*!< FICR Structure                                                       */
    __IM uint32_t RESERVED[192];
    __IOM NRF_FICR_INFO_Type INFO;                   /*!< (@ 0x00000300) Device info                                           */
    __IM uint32_t RESERVED1[20];
    __IM uint32_t ER[4];                             /*!< (@ 0x00000380) Common encryption root key, word n                    */
    __IM uint32_t IR[4];                             /*!< (@ 0x00000390) Common identity root key, word n                      */
    __IM uint32_t DEVICEADDRTYPE;                    /*!< (@ 0x000003A0) Device address type                                   */
    __IM uint32_t DEVICEADDR[2];                     /*!< (@ 0x000003A4) Device address n                                      */
    __IM uint32_t RESERVED2[21];
    __IOM NRF_FICR_TRIMCNF_Type TRIMCNF[64];         /*!< (@ 0x00000400) (unspecified)                                         */
    __IOM NRF_FICR_NFC_Type NFC;                     /*!< (@ 0x00000600) (unspecified)                                         */
    __IM uint32_t RESERVED3[4];
    __IM uint32_t XOSC32MTRIM;                       /*!< (@ 0x00000620) XOSC32M capacitor selection trim values               */
    __IM uint32_t XOSC32KTRIM;                       /*!< (@ 0x00000624) XOSC32K capacitor selection trim values               */
  } NRF_FICR_Type;                                   /*!< Size = 1576 (0x628)                                                  */

/* FICR_ER: Common encryption root key, word n */
  #define FICR_ER_MaxCount (4UL)                     /*!< Max size of ER[4] array.                                             */
  #define FICR_ER_MaxIndex (3UL)                     /*!< Max index of ER[4] array.                                            */
  #define FICR_ER_MinIndex (0UL)                     /*!< Min index of ER[4] array.                                            */
  #define FICR_ER_ResetValue (0xFFFFFFFFUL)          /*!< Reset value of ER[4] register.                                       */

/* ER @Bits 0..31 : Encryption Root, word n */
  #define FICR_ER_ER_Pos (0UL)                       /*!< Position of ER field.                                                */
  #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field.                                           */


/* FICR_IR: Common identity root key, word n */
  #define FICR_IR_MaxCount (4UL)                     /*!< Max size of IR[4] array.                                             */
  #define FICR_IR_MaxIndex (3UL)                     /*!< Max index of IR[4] array.                                            */
  #define FICR_IR_MinIndex (0UL)                     /*!< Min index of IR[4] array.                                            */
  #define FICR_IR_ResetValue (0xFFFFFFFFUL)          /*!< Reset value of IR[4] register.                                       */

/* IR @Bits 0..31 : Identity Root, word n */
  #define FICR_IR_IR_Pos (0UL)                       /*!< Position of IR field.                                                */
  #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field.                                           */


/* FICR_DEVICEADDRTYPE: Device address type */
  #define FICR_DEVICEADDRTYPE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DEVICEADDRTYPE register.                           */

/* DEVICEADDRTYPE @Bit 0 : Device address type */
  #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field.                                  */
  #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of
                                                                            DEVICEADDRTYPE field.*/
  #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Min (0x0UL) /*!< Min enumerator value of DEVICEADDRTYPE field.                    */
  #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Max (0x1UL) /*!< Max enumerator value of DEVICEADDRTYPE field.                    */
  #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0x0UL) /*!< Public address                                                */
  #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (0x1UL) /*!< Random address                                                */


/* FICR_DEVICEADDR: Device address n */
  #define FICR_DEVICEADDR_MaxCount (2UL)             /*!< Max size of DEVICEADDR[2] array.                                     */
  #define FICR_DEVICEADDR_MaxIndex (1UL)             /*!< Max index of DEVICEADDR[2] array.                                    */
  #define FICR_DEVICEADDR_MinIndex (0UL)             /*!< Min index of DEVICEADDR[2] array.                                    */
  #define FICR_DEVICEADDR_ResetValue (0xFFFFFFFFUL)  /*!< Reset value of DEVICEADDR[2] register.                               */

/* DEVICEADDR @Bits 0..31 : 48 bit device address */
  #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL)       /*!< Position of DEVICEADDR field.                                        */
  #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field.   */


/* FICR_XOSC32MTRIM: XOSC32M capacitor selection trim values */
  #define FICR_XOSC32MTRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of XOSC32MTRIM register.                                 */

/* SLOPE @Bits 0..8 : Slope trim factor on twos complement form */
  #define FICR_XOSC32MTRIM_SLOPE_Pos (0UL)           /*!< Position of SLOPE field.                                             */
  #define FICR_XOSC32MTRIM_SLOPE_Msk (0x1FFUL << FICR_XOSC32MTRIM_SLOPE_Pos) /*!< Bit mask of SLOPE field.                     */

/* OFFSET @Bits 16..25 : Offset trim factor on integer form */
  #define FICR_XOSC32MTRIM_OFFSET_Pos (16UL)         /*!< Position of OFFSET field.                                            */
  #define FICR_XOSC32MTRIM_OFFSET_Msk (0x3FFUL << FICR_XOSC32MTRIM_OFFSET_Pos) /*!< Bit mask of OFFSET field.                  */


/* FICR_XOSC32KTRIM: XOSC32K capacitor selection trim values */
  #define FICR_XOSC32KTRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of XOSC32KTRIM register.                                 */

/* SLOPE @Bits 0..8 : Slope trim factor on twos complement form */
  #define FICR_XOSC32KTRIM_SLOPE_Pos (0UL)           /*!< Position of SLOPE field.                                             */
  #define FICR_XOSC32KTRIM_SLOPE_Msk (0x1FFUL << FICR_XOSC32KTRIM_SLOPE_Pos) /*!< Bit mask of SLOPE field.                     */

/* OFFSET @Bits 16..25 : Offset trim factor on integer form */
  #define FICR_XOSC32KTRIM_OFFSET_Pos (16UL)         /*!< Position of OFFSET field.                                            */
  #define FICR_XOSC32KTRIM_OFFSET_Msk (0x3FFUL << FICR_XOSC32KTRIM_OFFSET_Pos) /*!< Bit mask of OFFSET field.                  */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                         GLITCHDET                                         ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ==================================================== Struct GLITCHDET ===================================================== */
/**
  * @brief Voltage glitch detectors
  */
  typedef struct {                                   /*!< GLITCHDET Structure                                                  */
    __IM uint32_t RESERVED[360];
    __IOM uint32_t CONFIG;                           /*!< (@ 0x000005A0) Configuration for glitch detector                     */
  } NRF_GLITCHDET_Type;                              /*!< Size = 1444 (0x5A4)                                                  */

/* GLITCHDET_CONFIG: Configuration for glitch detector */
  #define GLITCHDET_CONFIG_ResetValue (0x00000001UL) /*!< Reset value of CONFIG register.                                      */

/* ENABLE @Bit 0 : Enable glitch detector */
  #define GLITCHDET_CONFIG_ENABLE_Pos (0UL)          /*!< Position of ENABLE field.                                            */
  #define GLITCHDET_CONFIG_ENABLE_Msk (0x1UL << GLITCHDET_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field.                    */
  #define GLITCHDET_CONFIG_ENABLE_Min (0x0UL)        /*!< Min enumerator value of ENABLE field.                                */
  #define GLITCHDET_CONFIG_ENABLE_Max (0x1UL)        /*!< Max enumerator value of ENABLE field.                                */
  #define GLITCHDET_CONFIG_ENABLE_Disable (0x0UL)    /*!< Disable glitch detector                                              */
  #define GLITCHDET_CONFIG_ENABLE_Enable (0x1UL)     /*!< Enable glitch detector                                               */

/* MODE @Bit 4 : Glitch detector mode */
  #define GLITCHDET_CONFIG_MODE_Pos (4UL)            /*!< Position of MODE field.                                              */
  #define GLITCHDET_CONFIG_MODE_Msk (0x1UL << GLITCHDET_CONFIG_MODE_Pos) /*!< Bit mask of MODE field.                          */
  #define GLITCHDET_CONFIG_MODE_Min (0x0UL)          /*!< Min enumerator value of MODE field.                                  */
  #define GLITCHDET_CONFIG_MODE_Max (0x1UL)          /*!< Max enumerator value of MODE field.                                  */
  #define GLITCHDET_CONFIG_MODE_HighPassFilter (0x0UL) /*!< High pass filter mode                                              */
  #define GLITCHDET_CONFIG_MODE_CapDiv (0x1UL)       /*!< Cap divider mode                                                     */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           GPIO                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct GPIO ======================================================= */
/**
  * @brief GPIO Port
  */
  typedef struct {                                   /*!< GPIO Structure                                                       */
    __IOM uint32_t OUT;                              /*!< (@ 0x00000000) Write GPIO port                                       */
    __IOM uint32_t OUTSET;                           /*!< (@ 0x00000004) Set individual bits in GPIO port                      */
    __IOM uint32_t OUTCLR;                           /*!< (@ 0x00000008) Clear individual bits in GPIO port                    */
    __IM uint32_t IN;                                /*!< (@ 0x0000000C) Read GPIO port                                        */
    __IOM uint32_t DIR;                              /*!< (@ 0x00000010) Direction of GPIO pins                                */
    __IOM uint32_t DIRSET;                           /*!< (@ 0x00000014) DIR set register                                      */
    __IOM uint32_t DIRCLR;                           /*!< (@ 0x00000018) DIR clear register                                    */
    __IM uint32_t RESERVED;
    __IOM uint32_t LATCH;                            /*!< (@ 0x00000020) Latch register indicating what GPIO pins that have met
                                                                         the criteria set in the PIN_CNF[n].SENSE registers*/
    __IOM uint32_t DETECTMODE;                       /*!< (@ 0x00000024) Select between default DETECT signal behavior and
                                                                         LDETECT mode*/
    __IM uint32_t RESERVED1[22];
    __IOM uint32_t PIN_CNF[32];                      /*!< (@ 0x00000080) Pin n configuration of GPIO pin                       */
  } NRF_GPIO_Type;                                   /*!< Size = 256 (0x100)                                                   */

/* GPIO_OUT: Write GPIO port */
  #define GPIO_OUT_ResetValue (0x00000000UL)         /*!< Reset value of OUT register.                                         */

/* PIN0 @Bit 0 : Pin 0 */
  #define GPIO_OUT_PIN0_Pos (0UL)                    /*!< Position of PIN0 field.                                              */
  #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field.                                          */
  #define GPIO_OUT_PIN0_Min (0x0UL)                  /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_OUT_PIN0_Max (0x1UL)                  /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_OUT_PIN0_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN0_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN1 @Bit 1 : Pin 1 */
  #define GPIO_OUT_PIN1_Pos (1UL)                    /*!< Position of PIN1 field.                                              */
  #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field.                                          */
  #define GPIO_OUT_PIN1_Min (0x0UL)                  /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_OUT_PIN1_Max (0x1UL)                  /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_OUT_PIN1_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN1_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN2 @Bit 2 : Pin 2 */
  #define GPIO_OUT_PIN2_Pos (2UL)                    /*!< Position of PIN2 field.                                              */
  #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field.                                          */
  #define GPIO_OUT_PIN2_Min (0x0UL)                  /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_OUT_PIN2_Max (0x1UL)                  /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_OUT_PIN2_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN2_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN3 @Bit 3 : Pin 3 */
  #define GPIO_OUT_PIN3_Pos (3UL)                    /*!< Position of PIN3 field.                                              */
  #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field.                                          */
  #define GPIO_OUT_PIN3_Min (0x0UL)                  /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_OUT_PIN3_Max (0x1UL)                  /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_OUT_PIN3_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN3_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN4 @Bit 4 : Pin 4 */
  #define GPIO_OUT_PIN4_Pos (4UL)                    /*!< Position of PIN4 field.                                              */
  #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field.                                          */
  #define GPIO_OUT_PIN4_Min (0x0UL)                  /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_OUT_PIN4_Max (0x1UL)                  /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_OUT_PIN4_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN4_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN5 @Bit 5 : Pin 5 */
  #define GPIO_OUT_PIN5_Pos (5UL)                    /*!< Position of PIN5 field.                                              */
  #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field.                                          */
  #define GPIO_OUT_PIN5_Min (0x0UL)                  /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_OUT_PIN5_Max (0x1UL)                  /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_OUT_PIN5_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN5_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN6 @Bit 6 : Pin 6 */
  #define GPIO_OUT_PIN6_Pos (6UL)                    /*!< Position of PIN6 field.                                              */
  #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field.                                          */
  #define GPIO_OUT_PIN6_Min (0x0UL)                  /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_OUT_PIN6_Max (0x1UL)                  /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_OUT_PIN6_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN6_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN7 @Bit 7 : Pin 7 */
  #define GPIO_OUT_PIN7_Pos (7UL)                    /*!< Position of PIN7 field.                                              */
  #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field.                                          */
  #define GPIO_OUT_PIN7_Min (0x0UL)                  /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_OUT_PIN7_Max (0x1UL)                  /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_OUT_PIN7_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN7_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN8 @Bit 8 : Pin 8 */
  #define GPIO_OUT_PIN8_Pos (8UL)                    /*!< Position of PIN8 field.                                              */
  #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field.                                          */
  #define GPIO_OUT_PIN8_Min (0x0UL)                  /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_OUT_PIN8_Max (0x1UL)                  /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_OUT_PIN8_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN8_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN9 @Bit 9 : Pin 9 */
  #define GPIO_OUT_PIN9_Pos (9UL)                    /*!< Position of PIN9 field.                                              */
  #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field.                                          */
  #define GPIO_OUT_PIN9_Min (0x0UL)                  /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_OUT_PIN9_Max (0x1UL)                  /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_OUT_PIN9_Low (0x0UL)                  /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN9_High (0x1UL)                 /*!< Pin driver is high                                                   */

/* PIN10 @Bit 10 : Pin 10 */
  #define GPIO_OUT_PIN10_Pos (10UL)                  /*!< Position of PIN10 field.                                             */
  #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field.                                       */
  #define GPIO_OUT_PIN10_Min (0x0UL)                 /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_OUT_PIN10_Max (0x1UL)                 /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_OUT_PIN10_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN10_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN11 @Bit 11 : Pin 11 */
  #define GPIO_OUT_PIN11_Pos (11UL)                  /*!< Position of PIN11 field.                                             */
  #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field.                                       */
  #define GPIO_OUT_PIN11_Min (0x0UL)                 /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_OUT_PIN11_Max (0x1UL)                 /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_OUT_PIN11_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN11_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN12 @Bit 12 : Pin 12 */
  #define GPIO_OUT_PIN12_Pos (12UL)                  /*!< Position of PIN12 field.                                             */
  #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field.                                       */
  #define GPIO_OUT_PIN12_Min (0x0UL)                 /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_OUT_PIN12_Max (0x1UL)                 /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_OUT_PIN12_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN12_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN13 @Bit 13 : Pin 13 */
  #define GPIO_OUT_PIN13_Pos (13UL)                  /*!< Position of PIN13 field.                                             */
  #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field.                                       */
  #define GPIO_OUT_PIN13_Min (0x0UL)                 /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_OUT_PIN13_Max (0x1UL)                 /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_OUT_PIN13_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN13_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN14 @Bit 14 : Pin 14 */
  #define GPIO_OUT_PIN14_Pos (14UL)                  /*!< Position of PIN14 field.                                             */
  #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field.                                       */
  #define GPIO_OUT_PIN14_Min (0x0UL)                 /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_OUT_PIN14_Max (0x1UL)                 /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_OUT_PIN14_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN14_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN15 @Bit 15 : Pin 15 */
  #define GPIO_OUT_PIN15_Pos (15UL)                  /*!< Position of PIN15 field.                                             */
  #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field.                                       */
  #define GPIO_OUT_PIN15_Min (0x0UL)                 /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_OUT_PIN15_Max (0x1UL)                 /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_OUT_PIN15_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN15_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN16 @Bit 16 : Pin 16 */
  #define GPIO_OUT_PIN16_Pos (16UL)                  /*!< Position of PIN16 field.                                             */
  #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field.                                       */
  #define GPIO_OUT_PIN16_Min (0x0UL)                 /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_OUT_PIN16_Max (0x1UL)                 /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_OUT_PIN16_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN16_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN17 @Bit 17 : Pin 17 */
  #define GPIO_OUT_PIN17_Pos (17UL)                  /*!< Position of PIN17 field.                                             */
  #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field.                                       */
  #define GPIO_OUT_PIN17_Min (0x0UL)                 /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_OUT_PIN17_Max (0x1UL)                 /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_OUT_PIN17_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN17_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN18 @Bit 18 : Pin 18 */
  #define GPIO_OUT_PIN18_Pos (18UL)                  /*!< Position of PIN18 field.                                             */
  #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field.                                       */
  #define GPIO_OUT_PIN18_Min (0x0UL)                 /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_OUT_PIN18_Max (0x1UL)                 /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_OUT_PIN18_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN18_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN19 @Bit 19 : Pin 19 */
  #define GPIO_OUT_PIN19_Pos (19UL)                  /*!< Position of PIN19 field.                                             */
  #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field.                                       */
  #define GPIO_OUT_PIN19_Min (0x0UL)                 /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_OUT_PIN19_Max (0x1UL)                 /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_OUT_PIN19_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN19_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN20 @Bit 20 : Pin 20 */
  #define GPIO_OUT_PIN20_Pos (20UL)                  /*!< Position of PIN20 field.                                             */
  #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field.                                       */
  #define GPIO_OUT_PIN20_Min (0x0UL)                 /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_OUT_PIN20_Max (0x1UL)                 /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_OUT_PIN20_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN20_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN21 @Bit 21 : Pin 21 */
  #define GPIO_OUT_PIN21_Pos (21UL)                  /*!< Position of PIN21 field.                                             */
  #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field.                                       */
  #define GPIO_OUT_PIN21_Min (0x0UL)                 /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_OUT_PIN21_Max (0x1UL)                 /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_OUT_PIN21_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN21_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN22 @Bit 22 : Pin 22 */
  #define GPIO_OUT_PIN22_Pos (22UL)                  /*!< Position of PIN22 field.                                             */
  #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field.                                       */
  #define GPIO_OUT_PIN22_Min (0x0UL)                 /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_OUT_PIN22_Max (0x1UL)                 /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_OUT_PIN22_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN22_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN23 @Bit 23 : Pin 23 */
  #define GPIO_OUT_PIN23_Pos (23UL)                  /*!< Position of PIN23 field.                                             */
  #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field.                                       */
  #define GPIO_OUT_PIN23_Min (0x0UL)                 /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_OUT_PIN23_Max (0x1UL)                 /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_OUT_PIN23_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN23_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN24 @Bit 24 : Pin 24 */
  #define GPIO_OUT_PIN24_Pos (24UL)                  /*!< Position of PIN24 field.                                             */
  #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field.                                       */
  #define GPIO_OUT_PIN24_Min (0x0UL)                 /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_OUT_PIN24_Max (0x1UL)                 /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_OUT_PIN24_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN24_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN25 @Bit 25 : Pin 25 */
  #define GPIO_OUT_PIN25_Pos (25UL)                  /*!< Position of PIN25 field.                                             */
  #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field.                                       */
  #define GPIO_OUT_PIN25_Min (0x0UL)                 /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_OUT_PIN25_Max (0x1UL)                 /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_OUT_PIN25_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN25_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN26 @Bit 26 : Pin 26 */
  #define GPIO_OUT_PIN26_Pos (26UL)                  /*!< Position of PIN26 field.                                             */
  #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field.                                       */
  #define GPIO_OUT_PIN26_Min (0x0UL)                 /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_OUT_PIN26_Max (0x1UL)                 /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_OUT_PIN26_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN26_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN27 @Bit 27 : Pin 27 */
  #define GPIO_OUT_PIN27_Pos (27UL)                  /*!< Position of PIN27 field.                                             */
  #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field.                                       */
  #define GPIO_OUT_PIN27_Min (0x0UL)                 /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_OUT_PIN27_Max (0x1UL)                 /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_OUT_PIN27_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN27_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN28 @Bit 28 : Pin 28 */
  #define GPIO_OUT_PIN28_Pos (28UL)                  /*!< Position of PIN28 field.                                             */
  #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field.                                       */
  #define GPIO_OUT_PIN28_Min (0x0UL)                 /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_OUT_PIN28_Max (0x1UL)                 /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_OUT_PIN28_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN28_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN29 @Bit 29 : Pin 29 */
  #define GPIO_OUT_PIN29_Pos (29UL)                  /*!< Position of PIN29 field.                                             */
  #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field.                                       */
  #define GPIO_OUT_PIN29_Min (0x0UL)                 /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_OUT_PIN29_Max (0x1UL)                 /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_OUT_PIN29_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN29_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN30 @Bit 30 : Pin 30 */
  #define GPIO_OUT_PIN30_Pos (30UL)                  /*!< Position of PIN30 field.                                             */
  #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field.                                       */
  #define GPIO_OUT_PIN30_Min (0x0UL)                 /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_OUT_PIN30_Max (0x1UL)                 /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_OUT_PIN30_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN30_High (0x1UL)                /*!< Pin driver is high                                                   */

/* PIN31 @Bit 31 : Pin 31 */
  #define GPIO_OUT_PIN31_Pos (31UL)                  /*!< Position of PIN31 field.                                             */
  #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field.                                       */
  #define GPIO_OUT_PIN31_Min (0x0UL)                 /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_OUT_PIN31_Max (0x1UL)                 /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_OUT_PIN31_Low (0x0UL)                 /*!< Pin driver is low                                                    */
  #define GPIO_OUT_PIN31_High (0x1UL)                /*!< Pin driver is high                                                   */


/* GPIO_OUTSET: Set individual bits in GPIO port */
  #define GPIO_OUTSET_ResetValue (0x00000000UL)      /*!< Reset value of OUTSET register.                                      */

/* PIN0 @Bit 0 : Pin 0 */
  #define GPIO_OUTSET_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
  #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
  #define GPIO_OUTSET_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_OUTSET_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_OUTSET_PIN0_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN0_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN0_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN1 @Bit 1 : Pin 1 */
  #define GPIO_OUTSET_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
  #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
  #define GPIO_OUTSET_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_OUTSET_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_OUTSET_PIN1_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN1_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN1_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN2 @Bit 2 : Pin 2 */
  #define GPIO_OUTSET_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
  #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
  #define GPIO_OUTSET_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_OUTSET_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_OUTSET_PIN2_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN2_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN2_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN3 @Bit 3 : Pin 3 */
  #define GPIO_OUTSET_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
  #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
  #define GPIO_OUTSET_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_OUTSET_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_OUTSET_PIN3_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN3_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN3_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN4 @Bit 4 : Pin 4 */
  #define GPIO_OUTSET_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
  #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
  #define GPIO_OUTSET_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_OUTSET_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_OUTSET_PIN4_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN4_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN4_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN5 @Bit 5 : Pin 5 */
  #define GPIO_OUTSET_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
  #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
  #define GPIO_OUTSET_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_OUTSET_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_OUTSET_PIN5_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN5_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN5_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN6 @Bit 6 : Pin 6 */
  #define GPIO_OUTSET_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
  #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
  #define GPIO_OUTSET_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_OUTSET_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_OUTSET_PIN6_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN6_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN6_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN7 @Bit 7 : Pin 7 */
  #define GPIO_OUTSET_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
  #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
  #define GPIO_OUTSET_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_OUTSET_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_OUTSET_PIN7_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN7_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN7_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN8 @Bit 8 : Pin 8 */
  #define GPIO_OUTSET_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
  #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
  #define GPIO_OUTSET_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_OUTSET_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_OUTSET_PIN8_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN8_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN8_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN9 @Bit 9 : Pin 9 */
  #define GPIO_OUTSET_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
  #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
  #define GPIO_OUTSET_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_OUTSET_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_OUTSET_PIN9_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN9_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN9_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN10 @Bit 10 : Pin 10 */
  #define GPIO_OUTSET_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
  #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
  #define GPIO_OUTSET_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_OUTSET_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_OUTSET_PIN10_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN10_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN10_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN11 @Bit 11 : Pin 11 */
  #define GPIO_OUTSET_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
  #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
  #define GPIO_OUTSET_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_OUTSET_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_OUTSET_PIN11_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN11_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN11_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN12 @Bit 12 : Pin 12 */
  #define GPIO_OUTSET_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
  #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
  #define GPIO_OUTSET_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_OUTSET_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_OUTSET_PIN12_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN12_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN12_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN13 @Bit 13 : Pin 13 */
  #define GPIO_OUTSET_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
  #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
  #define GPIO_OUTSET_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_OUTSET_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_OUTSET_PIN13_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN13_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN13_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN14 @Bit 14 : Pin 14 */
  #define GPIO_OUTSET_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
  #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
  #define GPIO_OUTSET_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_OUTSET_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_OUTSET_PIN14_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN14_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN14_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN15 @Bit 15 : Pin 15 */
  #define GPIO_OUTSET_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
  #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
  #define GPIO_OUTSET_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_OUTSET_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_OUTSET_PIN15_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN15_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN15_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN16 @Bit 16 : Pin 16 */
  #define GPIO_OUTSET_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
  #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
  #define GPIO_OUTSET_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_OUTSET_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_OUTSET_PIN16_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN16_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN16_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN17 @Bit 17 : Pin 17 */
  #define GPIO_OUTSET_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
  #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
  #define GPIO_OUTSET_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_OUTSET_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_OUTSET_PIN17_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN17_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN17_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN18 @Bit 18 : Pin 18 */
  #define GPIO_OUTSET_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
  #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
  #define GPIO_OUTSET_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_OUTSET_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_OUTSET_PIN18_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN18_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN18_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN19 @Bit 19 : Pin 19 */
  #define GPIO_OUTSET_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
  #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
  #define GPIO_OUTSET_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_OUTSET_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_OUTSET_PIN19_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN19_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN19_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN20 @Bit 20 : Pin 20 */
  #define GPIO_OUTSET_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
  #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
  #define GPIO_OUTSET_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_OUTSET_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_OUTSET_PIN20_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN20_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN20_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN21 @Bit 21 : Pin 21 */
  #define GPIO_OUTSET_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
  #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
  #define GPIO_OUTSET_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_OUTSET_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_OUTSET_PIN21_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN21_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN21_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN22 @Bit 22 : Pin 22 */
  #define GPIO_OUTSET_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
  #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
  #define GPIO_OUTSET_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_OUTSET_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_OUTSET_PIN22_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN22_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN22_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN23 @Bit 23 : Pin 23 */
  #define GPIO_OUTSET_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
  #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
  #define GPIO_OUTSET_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_OUTSET_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_OUTSET_PIN23_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN23_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN23_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN24 @Bit 24 : Pin 24 */
  #define GPIO_OUTSET_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
  #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
  #define GPIO_OUTSET_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_OUTSET_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_OUTSET_PIN24_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN24_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN24_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN25 @Bit 25 : Pin 25 */
  #define GPIO_OUTSET_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
  #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
  #define GPIO_OUTSET_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_OUTSET_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_OUTSET_PIN25_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN25_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN25_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN26 @Bit 26 : Pin 26 */
  #define GPIO_OUTSET_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
  #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
  #define GPIO_OUTSET_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_OUTSET_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_OUTSET_PIN26_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN26_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN26_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN27 @Bit 27 : Pin 27 */
  #define GPIO_OUTSET_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
  #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
  #define GPIO_OUTSET_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_OUTSET_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_OUTSET_PIN27_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN27_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN27_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN28 @Bit 28 : Pin 28 */
  #define GPIO_OUTSET_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
  #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
  #define GPIO_OUTSET_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_OUTSET_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_OUTSET_PIN28_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN28_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN28_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN29 @Bit 29 : Pin 29 */
  #define GPIO_OUTSET_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
  #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
  #define GPIO_OUTSET_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_OUTSET_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_OUTSET_PIN29_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN29_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN29_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN30 @Bit 30 : Pin 30 */
  #define GPIO_OUTSET_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
  #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
  #define GPIO_OUTSET_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_OUTSET_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_OUTSET_PIN30_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN30_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN30_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */

/* PIN31 @Bit 31 : Pin 31 */
  #define GPIO_OUTSET_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
  #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
  #define GPIO_OUTSET_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_OUTSET_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_OUTSET_PIN31_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTSET_PIN31_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTSET_PIN31_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */


/* GPIO_OUTCLR: Clear individual bits in GPIO port */
  #define GPIO_OUTCLR_ResetValue (0x00000000UL)      /*!< Reset value of OUTCLR register.                                      */

/* PIN0 @Bit 0 : Pin 0 */
  #define GPIO_OUTCLR_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
  #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
  #define GPIO_OUTCLR_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_OUTCLR_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_OUTCLR_PIN0_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN0_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN0_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN1 @Bit 1 : Pin 1 */
  #define GPIO_OUTCLR_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
  #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
  #define GPIO_OUTCLR_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_OUTCLR_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_OUTCLR_PIN1_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN1_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN1_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN2 @Bit 2 : Pin 2 */
  #define GPIO_OUTCLR_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
  #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
  #define GPIO_OUTCLR_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_OUTCLR_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_OUTCLR_PIN2_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN2_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN2_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN3 @Bit 3 : Pin 3 */
  #define GPIO_OUTCLR_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
  #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
  #define GPIO_OUTCLR_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_OUTCLR_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_OUTCLR_PIN3_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN3_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN3_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN4 @Bit 4 : Pin 4 */
  #define GPIO_OUTCLR_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
  #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
  #define GPIO_OUTCLR_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_OUTCLR_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_OUTCLR_PIN4_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN4_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN4_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN5 @Bit 5 : Pin 5 */
  #define GPIO_OUTCLR_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
  #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
  #define GPIO_OUTCLR_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_OUTCLR_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_OUTCLR_PIN5_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN5_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN5_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN6 @Bit 6 : Pin 6 */
  #define GPIO_OUTCLR_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
  #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
  #define GPIO_OUTCLR_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_OUTCLR_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_OUTCLR_PIN6_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN6_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN6_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN7 @Bit 7 : Pin 7 */
  #define GPIO_OUTCLR_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
  #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
  #define GPIO_OUTCLR_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_OUTCLR_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_OUTCLR_PIN7_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN7_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN7_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN8 @Bit 8 : Pin 8 */
  #define GPIO_OUTCLR_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
  #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
  #define GPIO_OUTCLR_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_OUTCLR_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_OUTCLR_PIN8_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN8_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN8_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN9 @Bit 9 : Pin 9 */
  #define GPIO_OUTCLR_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
  #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
  #define GPIO_OUTCLR_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_OUTCLR_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_OUTCLR_PIN9_Low (0x0UL)               /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN9_High (0x1UL)              /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN9_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN10 @Bit 10 : Pin 10 */
  #define GPIO_OUTCLR_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
  #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
  #define GPIO_OUTCLR_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_OUTCLR_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_OUTCLR_PIN10_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN10_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN10_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN11 @Bit 11 : Pin 11 */
  #define GPIO_OUTCLR_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
  #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
  #define GPIO_OUTCLR_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_OUTCLR_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_OUTCLR_PIN11_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN11_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN11_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN12 @Bit 12 : Pin 12 */
  #define GPIO_OUTCLR_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
  #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
  #define GPIO_OUTCLR_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_OUTCLR_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_OUTCLR_PIN12_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN12_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN12_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN13 @Bit 13 : Pin 13 */
  #define GPIO_OUTCLR_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
  #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
  #define GPIO_OUTCLR_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_OUTCLR_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_OUTCLR_PIN13_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN13_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN13_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN14 @Bit 14 : Pin 14 */
  #define GPIO_OUTCLR_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
  #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
  #define GPIO_OUTCLR_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_OUTCLR_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_OUTCLR_PIN14_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN14_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN14_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN15 @Bit 15 : Pin 15 */
  #define GPIO_OUTCLR_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
  #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
  #define GPIO_OUTCLR_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_OUTCLR_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_OUTCLR_PIN15_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN15_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN15_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN16 @Bit 16 : Pin 16 */
  #define GPIO_OUTCLR_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
  #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
  #define GPIO_OUTCLR_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_OUTCLR_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_OUTCLR_PIN16_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN16_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN16_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN17 @Bit 17 : Pin 17 */
  #define GPIO_OUTCLR_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
  #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
  #define GPIO_OUTCLR_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_OUTCLR_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_OUTCLR_PIN17_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN17_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN17_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN18 @Bit 18 : Pin 18 */
  #define GPIO_OUTCLR_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
  #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
  #define GPIO_OUTCLR_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_OUTCLR_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_OUTCLR_PIN18_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN18_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN18_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN19 @Bit 19 : Pin 19 */
  #define GPIO_OUTCLR_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
  #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
  #define GPIO_OUTCLR_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_OUTCLR_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_OUTCLR_PIN19_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN19_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN19_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN20 @Bit 20 : Pin 20 */
  #define GPIO_OUTCLR_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
  #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
  #define GPIO_OUTCLR_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_OUTCLR_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_OUTCLR_PIN20_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN20_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN20_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN21 @Bit 21 : Pin 21 */
  #define GPIO_OUTCLR_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
  #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
  #define GPIO_OUTCLR_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_OUTCLR_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_OUTCLR_PIN21_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN21_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN21_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN22 @Bit 22 : Pin 22 */
  #define GPIO_OUTCLR_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
  #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
  #define GPIO_OUTCLR_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_OUTCLR_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_OUTCLR_PIN22_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN22_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN22_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN23 @Bit 23 : Pin 23 */
  #define GPIO_OUTCLR_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
  #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
  #define GPIO_OUTCLR_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_OUTCLR_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_OUTCLR_PIN23_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN23_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN23_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN24 @Bit 24 : Pin 24 */
  #define GPIO_OUTCLR_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
  #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
  #define GPIO_OUTCLR_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_OUTCLR_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_OUTCLR_PIN24_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN24_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN24_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN25 @Bit 25 : Pin 25 */
  #define GPIO_OUTCLR_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
  #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
  #define GPIO_OUTCLR_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_OUTCLR_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_OUTCLR_PIN25_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN25_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN25_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN26 @Bit 26 : Pin 26 */
  #define GPIO_OUTCLR_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
  #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
  #define GPIO_OUTCLR_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_OUTCLR_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_OUTCLR_PIN26_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN26_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN26_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN27 @Bit 27 : Pin 27 */
  #define GPIO_OUTCLR_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
  #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
  #define GPIO_OUTCLR_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_OUTCLR_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_OUTCLR_PIN27_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN27_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN27_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN28 @Bit 28 : Pin 28 */
  #define GPIO_OUTCLR_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
  #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
  #define GPIO_OUTCLR_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_OUTCLR_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_OUTCLR_PIN28_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN28_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN28_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN29 @Bit 29 : Pin 29 */
  #define GPIO_OUTCLR_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
  #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
  #define GPIO_OUTCLR_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_OUTCLR_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_OUTCLR_PIN29_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN29_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN29_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN30 @Bit 30 : Pin 30 */
  #define GPIO_OUTCLR_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
  #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
  #define GPIO_OUTCLR_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_OUTCLR_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_OUTCLR_PIN30_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN30_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN30_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */

/* PIN31 @Bit 31 : Pin 31 */
  #define GPIO_OUTCLR_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
  #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
  #define GPIO_OUTCLR_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_OUTCLR_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_OUTCLR_PIN31_Low (0x0UL)              /*!< Read: pin driver is low                                              */
  #define GPIO_OUTCLR_PIN31_High (0x1UL)             /*!< Read: pin driver is high                                             */
  #define GPIO_OUTCLR_PIN31_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */


/* GPIO_IN: Read GPIO port */
  #define GPIO_IN_ResetValue (0x00000000UL)          /*!< Reset value of IN register.                                          */

/* PIN0 @Bit 0 : Pin 0 */
  #define GPIO_IN_PIN0_Pos (0UL)                     /*!< Position of PIN0 field.                                              */
  #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field.                                            */
  #define GPIO_IN_PIN0_Min (0x0UL)                   /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_IN_PIN0_Max (0x1UL)                   /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_IN_PIN0_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN0_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN1 @Bit 1 : Pin 1 */
  #define GPIO_IN_PIN1_Pos (1UL)                     /*!< Position of PIN1 field.                                              */
  #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field.                                            */
  #define GPIO_IN_PIN1_Min (0x0UL)                   /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_IN_PIN1_Max (0x1UL)                   /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_IN_PIN1_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN1_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN2 @Bit 2 : Pin 2 */
  #define GPIO_IN_PIN2_Pos (2UL)                     /*!< Position of PIN2 field.                                              */
  #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field.                                            */
  #define GPIO_IN_PIN2_Min (0x0UL)                   /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_IN_PIN2_Max (0x1UL)                   /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_IN_PIN2_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN2_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN3 @Bit 3 : Pin 3 */
  #define GPIO_IN_PIN3_Pos (3UL)                     /*!< Position of PIN3 field.                                              */
  #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field.                                            */
  #define GPIO_IN_PIN3_Min (0x0UL)                   /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_IN_PIN3_Max (0x1UL)                   /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_IN_PIN3_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN3_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN4 @Bit 4 : Pin 4 */
  #define GPIO_IN_PIN4_Pos (4UL)                     /*!< Position of PIN4 field.                                              */
  #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field.                                            */
  #define GPIO_IN_PIN4_Min (0x0UL)                   /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_IN_PIN4_Max (0x1UL)                   /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_IN_PIN4_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN4_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN5 @Bit 5 : Pin 5 */
  #define GPIO_IN_PIN5_Pos (5UL)                     /*!< Position of PIN5 field.                                              */
  #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field.                                            */
  #define GPIO_IN_PIN5_Min (0x0UL)                   /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_IN_PIN5_Max (0x1UL)                   /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_IN_PIN5_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN5_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN6 @Bit 6 : Pin 6 */
  #define GPIO_IN_PIN6_Pos (6UL)                     /*!< Position of PIN6 field.                                              */
  #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field.                                            */
  #define GPIO_IN_PIN6_Min (0x0UL)                   /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_IN_PIN6_Max (0x1UL)                   /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_IN_PIN6_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN6_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN7 @Bit 7 : Pin 7 */
  #define GPIO_IN_PIN7_Pos (7UL)                     /*!< Position of PIN7 field.                                              */
  #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field.                                            */
  #define GPIO_IN_PIN7_Min (0x0UL)                   /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_IN_PIN7_Max (0x1UL)                   /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_IN_PIN7_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN7_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN8 @Bit 8 : Pin 8 */
  #define GPIO_IN_PIN8_Pos (8UL)                     /*!< Position of PIN8 field.                                              */
  #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field.                                            */
  #define GPIO_IN_PIN8_Min (0x0UL)                   /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_IN_PIN8_Max (0x1UL)                   /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_IN_PIN8_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN8_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN9 @Bit 9 : Pin 9 */
  #define GPIO_IN_PIN9_Pos (9UL)                     /*!< Position of PIN9 field.                                              */
  #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field.                                            */
  #define GPIO_IN_PIN9_Min (0x0UL)                   /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_IN_PIN9_Max (0x1UL)                   /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_IN_PIN9_Low (0x0UL)                   /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN9_High (0x1UL)                  /*!< Pin input is high                                                    */

/* PIN10 @Bit 10 : Pin 10 */
  #define GPIO_IN_PIN10_Pos (10UL)                   /*!< Position of PIN10 field.                                             */
  #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field.                                         */
  #define GPIO_IN_PIN10_Min (0x0UL)                  /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_IN_PIN10_Max (0x1UL)                  /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_IN_PIN10_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN10_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN11 @Bit 11 : Pin 11 */
  #define GPIO_IN_PIN11_Pos (11UL)                   /*!< Position of PIN11 field.                                             */
  #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field.                                         */
  #define GPIO_IN_PIN11_Min (0x0UL)                  /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_IN_PIN11_Max (0x1UL)                  /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_IN_PIN11_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN11_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN12 @Bit 12 : Pin 12 */
  #define GPIO_IN_PIN12_Pos (12UL)                   /*!< Position of PIN12 field.                                             */
  #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field.                                         */
  #define GPIO_IN_PIN12_Min (0x0UL)                  /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_IN_PIN12_Max (0x1UL)                  /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_IN_PIN12_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN12_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN13 @Bit 13 : Pin 13 */
  #define GPIO_IN_PIN13_Pos (13UL)                   /*!< Position of PIN13 field.                                             */
  #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field.                                         */
  #define GPIO_IN_PIN13_Min (0x0UL)                  /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_IN_PIN13_Max (0x1UL)                  /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_IN_PIN13_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN13_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN14 @Bit 14 : Pin 14 */
  #define GPIO_IN_PIN14_Pos (14UL)                   /*!< Position of PIN14 field.                                             */
  #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field.                                         */
  #define GPIO_IN_PIN14_Min (0x0UL)                  /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_IN_PIN14_Max (0x1UL)                  /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_IN_PIN14_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN14_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN15 @Bit 15 : Pin 15 */
  #define GPIO_IN_PIN15_Pos (15UL)                   /*!< Position of PIN15 field.                                             */
  #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field.                                         */
  #define GPIO_IN_PIN15_Min (0x0UL)                  /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_IN_PIN15_Max (0x1UL)                  /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_IN_PIN15_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN15_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN16 @Bit 16 : Pin 16 */
  #define GPIO_IN_PIN16_Pos (16UL)                   /*!< Position of PIN16 field.                                             */
  #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field.                                         */
  #define GPIO_IN_PIN16_Min (0x0UL)                  /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_IN_PIN16_Max (0x1UL)                  /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_IN_PIN16_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN16_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN17 @Bit 17 : Pin 17 */
  #define GPIO_IN_PIN17_Pos (17UL)                   /*!< Position of PIN17 field.                                             */
  #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field.                                         */
  #define GPIO_IN_PIN17_Min (0x0UL)                  /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_IN_PIN17_Max (0x1UL)                  /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_IN_PIN17_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN17_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN18 @Bit 18 : Pin 18 */
  #define GPIO_IN_PIN18_Pos (18UL)                   /*!< Position of PIN18 field.                                             */
  #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field.                                         */
  #define GPIO_IN_PIN18_Min (0x0UL)                  /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_IN_PIN18_Max (0x1UL)                  /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_IN_PIN18_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN18_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN19 @Bit 19 : Pin 19 */
  #define GPIO_IN_PIN19_Pos (19UL)                   /*!< Position of PIN19 field.                                             */
  #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field.                                         */
  #define GPIO_IN_PIN19_Min (0x0UL)                  /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_IN_PIN19_Max (0x1UL)                  /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_IN_PIN19_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN19_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN20 @Bit 20 : Pin 20 */
  #define GPIO_IN_PIN20_Pos (20UL)                   /*!< Position of PIN20 field.                                             */
  #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field.                                         */
  #define GPIO_IN_PIN20_Min (0x0UL)                  /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_IN_PIN20_Max (0x1UL)                  /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_IN_PIN20_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN20_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN21 @Bit 21 : Pin 21 */
  #define GPIO_IN_PIN21_Pos (21UL)                   /*!< Position of PIN21 field.                                             */
  #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field.                                         */
  #define GPIO_IN_PIN21_Min (0x0UL)                  /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_IN_PIN21_Max (0x1UL)                  /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_IN_PIN21_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN21_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN22 @Bit 22 : Pin 22 */
  #define GPIO_IN_PIN22_Pos (22UL)                   /*!< Position of PIN22 field.                                             */
  #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field.                                         */
  #define GPIO_IN_PIN22_Min (0x0UL)                  /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_IN_PIN22_Max (0x1UL)                  /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_IN_PIN22_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN22_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN23 @Bit 23 : Pin 23 */
  #define GPIO_IN_PIN23_Pos (23UL)                   /*!< Position of PIN23 field.                                             */
  #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field.                                         */
  #define GPIO_IN_PIN23_Min (0x0UL)                  /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_IN_PIN23_Max (0x1UL)                  /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_IN_PIN23_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN23_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN24 @Bit 24 : Pin 24 */
  #define GPIO_IN_PIN24_Pos (24UL)                   /*!< Position of PIN24 field.                                             */
  #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field.                                         */
  #define GPIO_IN_PIN24_Min (0x0UL)                  /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_IN_PIN24_Max (0x1UL)                  /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_IN_PIN24_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN24_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN25 @Bit 25 : Pin 25 */
  #define GPIO_IN_PIN25_Pos (25UL)                   /*!< Position of PIN25 field.                                             */
  #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field.                                         */
  #define GPIO_IN_PIN25_Min (0x0UL)                  /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_IN_PIN25_Max (0x1UL)                  /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_IN_PIN25_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN25_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN26 @Bit 26 : Pin 26 */
  #define GPIO_IN_PIN26_Pos (26UL)                   /*!< Position of PIN26 field.                                             */
  #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field.                                         */
  #define GPIO_IN_PIN26_Min (0x0UL)                  /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_IN_PIN26_Max (0x1UL)                  /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_IN_PIN26_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN26_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN27 @Bit 27 : Pin 27 */
  #define GPIO_IN_PIN27_Pos (27UL)                   /*!< Position of PIN27 field.                                             */
  #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field.                                         */
  #define GPIO_IN_PIN27_Min (0x0UL)                  /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_IN_PIN27_Max (0x1UL)                  /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_IN_PIN27_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN27_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN28 @Bit 28 : Pin 28 */
  #define GPIO_IN_PIN28_Pos (28UL)                   /*!< Position of PIN28 field.                                             */
  #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field.                                         */
  #define GPIO_IN_PIN28_Min (0x0UL)                  /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_IN_PIN28_Max (0x1UL)                  /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_IN_PIN28_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN28_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN29 @Bit 29 : Pin 29 */
  #define GPIO_IN_PIN29_Pos (29UL)                   /*!< Position of PIN29 field.                                             */
  #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field.                                         */
  #define GPIO_IN_PIN29_Min (0x0UL)                  /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_IN_PIN29_Max (0x1UL)                  /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_IN_PIN29_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN29_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN30 @Bit 30 : Pin 30 */
  #define GPIO_IN_PIN30_Pos (30UL)                   /*!< Position of PIN30 field.                                             */
  #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field.                                         */
  #define GPIO_IN_PIN30_Min (0x0UL)                  /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_IN_PIN30_Max (0x1UL)                  /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_IN_PIN30_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN30_High (0x1UL)                 /*!< Pin input is high                                                    */

/* PIN31 @Bit 31 : Pin 31 */
  #define GPIO_IN_PIN31_Pos (31UL)                   /*!< Position of PIN31 field.                                             */
  #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field.                                         */
  #define GPIO_IN_PIN31_Min (0x0UL)                  /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_IN_PIN31_Max (0x1UL)                  /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_IN_PIN31_Low (0x0UL)                  /*!< Pin input is low                                                     */
  #define GPIO_IN_PIN31_High (0x1UL)                 /*!< Pin input is high                                                    */


/* GPIO_DIR: Direction of GPIO pins */
  #define GPIO_DIR_ResetValue (0x00000000UL)         /*!< Reset value of DIR register.                                         */

/* PIN0 @Bit 0 : Pin 0 */
  #define GPIO_DIR_PIN0_Pos (0UL)                    /*!< Position of PIN0 field.                                              */
  #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field.                                          */
  #define GPIO_DIR_PIN0_Min (0x0UL)                  /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_DIR_PIN0_Max (0x1UL)                  /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_DIR_PIN0_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN0_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN1 @Bit 1 : Pin 1 */
  #define GPIO_DIR_PIN1_Pos (1UL)                    /*!< Position of PIN1 field.                                              */
  #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field.                                          */
  #define GPIO_DIR_PIN1_Min (0x0UL)                  /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_DIR_PIN1_Max (0x1UL)                  /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_DIR_PIN1_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN1_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN2 @Bit 2 : Pin 2 */
  #define GPIO_DIR_PIN2_Pos (2UL)                    /*!< Position of PIN2 field.                                              */
  #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field.                                          */
  #define GPIO_DIR_PIN2_Min (0x0UL)                  /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_DIR_PIN2_Max (0x1UL)                  /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_DIR_PIN2_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN2_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN3 @Bit 3 : Pin 3 */
  #define GPIO_DIR_PIN3_Pos (3UL)                    /*!< Position of PIN3 field.                                              */
  #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field.                                          */
  #define GPIO_DIR_PIN3_Min (0x0UL)                  /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_DIR_PIN3_Max (0x1UL)                  /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_DIR_PIN3_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN3_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN4 @Bit 4 : Pin 4 */
  #define GPIO_DIR_PIN4_Pos (4UL)                    /*!< Position of PIN4 field.                                              */
  #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field.                                          */
  #define GPIO_DIR_PIN4_Min (0x0UL)                  /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_DIR_PIN4_Max (0x1UL)                  /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_DIR_PIN4_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN4_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN5 @Bit 5 : Pin 5 */
  #define GPIO_DIR_PIN5_Pos (5UL)                    /*!< Position of PIN5 field.                                              */
  #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field.                                          */
  #define GPIO_DIR_PIN5_Min (0x0UL)                  /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_DIR_PIN5_Max (0x1UL)                  /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_DIR_PIN5_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN5_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN6 @Bit 6 : Pin 6 */
  #define GPIO_DIR_PIN6_Pos (6UL)                    /*!< Position of PIN6 field.                                              */
  #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field.                                          */
  #define GPIO_DIR_PIN6_Min (0x0UL)                  /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_DIR_PIN6_Max (0x1UL)                  /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_DIR_PIN6_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN6_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN7 @Bit 7 : Pin 7 */
  #define GPIO_DIR_PIN7_Pos (7UL)                    /*!< Position of PIN7 field.                                              */
  #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field.                                          */
  #define GPIO_DIR_PIN7_Min (0x0UL)                  /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_DIR_PIN7_Max (0x1UL)                  /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_DIR_PIN7_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN7_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN8 @Bit 8 : Pin 8 */
  #define GPIO_DIR_PIN8_Pos (8UL)                    /*!< Position of PIN8 field.                                              */
  #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field.                                          */
  #define GPIO_DIR_PIN8_Min (0x0UL)                  /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_DIR_PIN8_Max (0x1UL)                  /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_DIR_PIN8_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN8_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN9 @Bit 9 : Pin 9 */
  #define GPIO_DIR_PIN9_Pos (9UL)                    /*!< Position of PIN9 field.                                              */
  #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field.                                          */
  #define GPIO_DIR_PIN9_Min (0x0UL)                  /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_DIR_PIN9_Max (0x1UL)                  /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_DIR_PIN9_Input (0x0UL)                /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN9_Output (0x1UL)               /*!< Pin set as output                                                    */

/* PIN10 @Bit 10 : Pin 10 */
  #define GPIO_DIR_PIN10_Pos (10UL)                  /*!< Position of PIN10 field.                                             */
  #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field.                                       */
  #define GPIO_DIR_PIN10_Min (0x0UL)                 /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_DIR_PIN10_Max (0x1UL)                 /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_DIR_PIN10_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN10_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN11 @Bit 11 : Pin 11 */
  #define GPIO_DIR_PIN11_Pos (11UL)                  /*!< Position of PIN11 field.                                             */
  #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field.                                       */
  #define GPIO_DIR_PIN11_Min (0x0UL)                 /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_DIR_PIN11_Max (0x1UL)                 /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_DIR_PIN11_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN11_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN12 @Bit 12 : Pin 12 */
  #define GPIO_DIR_PIN12_Pos (12UL)                  /*!< Position of PIN12 field.                                             */
  #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field.                                       */
  #define GPIO_DIR_PIN12_Min (0x0UL)                 /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_DIR_PIN12_Max (0x1UL)                 /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_DIR_PIN12_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN12_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN13 @Bit 13 : Pin 13 */
  #define GPIO_DIR_PIN13_Pos (13UL)                  /*!< Position of PIN13 field.                                             */
  #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field.                                       */
  #define GPIO_DIR_PIN13_Min (0x0UL)                 /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_DIR_PIN13_Max (0x1UL)                 /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_DIR_PIN13_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN13_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN14 @Bit 14 : Pin 14 */
  #define GPIO_DIR_PIN14_Pos (14UL)                  /*!< Position of PIN14 field.                                             */
  #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field.                                       */
  #define GPIO_DIR_PIN14_Min (0x0UL)                 /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_DIR_PIN14_Max (0x1UL)                 /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_DIR_PIN14_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN14_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN15 @Bit 15 : Pin 15 */
  #define GPIO_DIR_PIN15_Pos (15UL)                  /*!< Position of PIN15 field.                                             */
  #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field.                                       */
  #define GPIO_DIR_PIN15_Min (0x0UL)                 /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_DIR_PIN15_Max (0x1UL)                 /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_DIR_PIN15_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN15_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN16 @Bit 16 : Pin 16 */
  #define GPIO_DIR_PIN16_Pos (16UL)                  /*!< Position of PIN16 field.                                             */
  #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field.                                       */
  #define GPIO_DIR_PIN16_Min (0x0UL)                 /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_DIR_PIN16_Max (0x1UL)                 /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_DIR_PIN16_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN16_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN17 @Bit 17 : Pin 17 */
  #define GPIO_DIR_PIN17_Pos (17UL)                  /*!< Position of PIN17 field.                                             */
  #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field.                                       */
  #define GPIO_DIR_PIN17_Min (0x0UL)                 /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_DIR_PIN17_Max (0x1UL)                 /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_DIR_PIN17_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN17_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN18 @Bit 18 : Pin 18 */
  #define GPIO_DIR_PIN18_Pos (18UL)                  /*!< Position of PIN18 field.                                             */
  #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field.                                       */
  #define GPIO_DIR_PIN18_Min (0x0UL)                 /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_DIR_PIN18_Max (0x1UL)                 /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_DIR_PIN18_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN18_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN19 @Bit 19 : Pin 19 */
  #define GPIO_DIR_PIN19_Pos (19UL)                  /*!< Position of PIN19 field.                                             */
  #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field.                                       */
  #define GPIO_DIR_PIN19_Min (0x0UL)                 /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_DIR_PIN19_Max (0x1UL)                 /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_DIR_PIN19_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN19_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN20 @Bit 20 : Pin 20 */
  #define GPIO_DIR_PIN20_Pos (20UL)                  /*!< Position of PIN20 field.                                             */
  #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field.                                       */
  #define GPIO_DIR_PIN20_Min (0x0UL)                 /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_DIR_PIN20_Max (0x1UL)                 /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_DIR_PIN20_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN20_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN21 @Bit 21 : Pin 21 */
  #define GPIO_DIR_PIN21_Pos (21UL)                  /*!< Position of PIN21 field.                                             */
  #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field.                                       */
  #define GPIO_DIR_PIN21_Min (0x0UL)                 /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_DIR_PIN21_Max (0x1UL)                 /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_DIR_PIN21_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN21_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN22 @Bit 22 : Pin 22 */
  #define GPIO_DIR_PIN22_Pos (22UL)                  /*!< Position of PIN22 field.                                             */
  #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field.                                       */
  #define GPIO_DIR_PIN22_Min (0x0UL)                 /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_DIR_PIN22_Max (0x1UL)                 /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_DIR_PIN22_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN22_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN23 @Bit 23 : Pin 23 */
  #define GPIO_DIR_PIN23_Pos (23UL)                  /*!< Position of PIN23 field.                                             */
  #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field.                                       */
  #define GPIO_DIR_PIN23_Min (0x0UL)                 /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_DIR_PIN23_Max (0x1UL)                 /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_DIR_PIN23_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN23_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN24 @Bit 24 : Pin 24 */
  #define GPIO_DIR_PIN24_Pos (24UL)                  /*!< Position of PIN24 field.                                             */
  #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field.                                       */
  #define GPIO_DIR_PIN24_Min (0x0UL)                 /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_DIR_PIN24_Max (0x1UL)                 /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_DIR_PIN24_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN24_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN25 @Bit 25 : Pin 25 */
  #define GPIO_DIR_PIN25_Pos (25UL)                  /*!< Position of PIN25 field.                                             */
  #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field.                                       */
  #define GPIO_DIR_PIN25_Min (0x0UL)                 /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_DIR_PIN25_Max (0x1UL)                 /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_DIR_PIN25_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN25_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN26 @Bit 26 : Pin 26 */
  #define GPIO_DIR_PIN26_Pos (26UL)                  /*!< Position of PIN26 field.                                             */
  #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field.                                       */
  #define GPIO_DIR_PIN26_Min (0x0UL)                 /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_DIR_PIN26_Max (0x1UL)                 /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_DIR_PIN26_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN26_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN27 @Bit 27 : Pin 27 */
  #define GPIO_DIR_PIN27_Pos (27UL)                  /*!< Position of PIN27 field.                                             */
  #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field.                                       */
  #define GPIO_DIR_PIN27_Min (0x0UL)                 /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_DIR_PIN27_Max (0x1UL)                 /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_DIR_PIN27_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN27_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN28 @Bit 28 : Pin 28 */
  #define GPIO_DIR_PIN28_Pos (28UL)                  /*!< Position of PIN28 field.                                             */
  #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field.                                       */
  #define GPIO_DIR_PIN28_Min (0x0UL)                 /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_DIR_PIN28_Max (0x1UL)                 /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_DIR_PIN28_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN28_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN29 @Bit 29 : Pin 29 */
  #define GPIO_DIR_PIN29_Pos (29UL)                  /*!< Position of PIN29 field.                                             */
  #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field.                                       */
  #define GPIO_DIR_PIN29_Min (0x0UL)                 /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_DIR_PIN29_Max (0x1UL)                 /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_DIR_PIN29_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN29_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN30 @Bit 30 : Pin 30 */
  #define GPIO_DIR_PIN30_Pos (30UL)                  /*!< Position of PIN30 field.                                             */
  #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field.                                       */
  #define GPIO_DIR_PIN30_Min (0x0UL)                 /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_DIR_PIN30_Max (0x1UL)                 /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_DIR_PIN30_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN30_Output (0x1UL)              /*!< Pin set as output                                                    */

/* PIN31 @Bit 31 : Pin 31 */
  #define GPIO_DIR_PIN31_Pos (31UL)                  /*!< Position of PIN31 field.                                             */
  #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field.                                       */
  #define GPIO_DIR_PIN31_Min (0x0UL)                 /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_DIR_PIN31_Max (0x1UL)                 /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_DIR_PIN31_Input (0x0UL)               /*!< Pin set as input                                                     */
  #define GPIO_DIR_PIN31_Output (0x1UL)              /*!< Pin set as output                                                    */


/* GPIO_DIRSET: DIR set register */
  #define GPIO_DIRSET_ResetValue (0x00000000UL)      /*!< Reset value of DIRSET register.                                      */

/* PIN0 @Bit 0 : Set as output pin 0 */
  #define GPIO_DIRSET_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
  #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
  #define GPIO_DIRSET_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_DIRSET_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_DIRSET_PIN0_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN0_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN0_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN1 @Bit 1 : Set as output pin 1 */
  #define GPIO_DIRSET_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
  #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
  #define GPIO_DIRSET_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_DIRSET_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_DIRSET_PIN1_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN1_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN1_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN2 @Bit 2 : Set as output pin 2 */
  #define GPIO_DIRSET_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
  #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
  #define GPIO_DIRSET_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_DIRSET_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_DIRSET_PIN2_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN2_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN2_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN3 @Bit 3 : Set as output pin 3 */
  #define GPIO_DIRSET_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
  #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
  #define GPIO_DIRSET_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_DIRSET_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_DIRSET_PIN3_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN3_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN3_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN4 @Bit 4 : Set as output pin 4 */
  #define GPIO_DIRSET_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
  #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
  #define GPIO_DIRSET_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_DIRSET_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_DIRSET_PIN4_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN4_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN4_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN5 @Bit 5 : Set as output pin 5 */
  #define GPIO_DIRSET_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
  #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
  #define GPIO_DIRSET_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_DIRSET_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_DIRSET_PIN5_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN5_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN5_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN6 @Bit 6 : Set as output pin 6 */
  #define GPIO_DIRSET_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
  #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
  #define GPIO_DIRSET_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_DIRSET_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_DIRSET_PIN6_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN6_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN6_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN7 @Bit 7 : Set as output pin 7 */
  #define GPIO_DIRSET_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
  #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
  #define GPIO_DIRSET_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_DIRSET_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_DIRSET_PIN7_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN7_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN7_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN8 @Bit 8 : Set as output pin 8 */
  #define GPIO_DIRSET_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
  #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
  #define GPIO_DIRSET_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_DIRSET_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_DIRSET_PIN8_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN8_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN8_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN9 @Bit 9 : Set as output pin 9 */
  #define GPIO_DIRSET_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
  #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
  #define GPIO_DIRSET_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_DIRSET_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_DIRSET_PIN9_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN9_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN9_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN10 @Bit 10 : Set as output pin 10 */
  #define GPIO_DIRSET_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
  #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
  #define GPIO_DIRSET_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_DIRSET_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_DIRSET_PIN10_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN10_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN10_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN11 @Bit 11 : Set as output pin 11 */
  #define GPIO_DIRSET_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
  #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
  #define GPIO_DIRSET_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_DIRSET_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_DIRSET_PIN11_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN11_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN11_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN12 @Bit 12 : Set as output pin 12 */
  #define GPIO_DIRSET_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
  #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
  #define GPIO_DIRSET_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_DIRSET_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_DIRSET_PIN12_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN12_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN12_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN13 @Bit 13 : Set as output pin 13 */
  #define GPIO_DIRSET_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
  #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
  #define GPIO_DIRSET_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_DIRSET_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_DIRSET_PIN13_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN13_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN13_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN14 @Bit 14 : Set as output pin 14 */
  #define GPIO_DIRSET_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
  #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
  #define GPIO_DIRSET_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_DIRSET_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_DIRSET_PIN14_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN14_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN14_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN15 @Bit 15 : Set as output pin 15 */
  #define GPIO_DIRSET_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
  #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
  #define GPIO_DIRSET_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_DIRSET_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_DIRSET_PIN15_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN15_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN15_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN16 @Bit 16 : Set as output pin 16 */
  #define GPIO_DIRSET_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
  #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
  #define GPIO_DIRSET_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_DIRSET_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_DIRSET_PIN16_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN16_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN16_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN17 @Bit 17 : Set as output pin 17 */
  #define GPIO_DIRSET_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
  #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
  #define GPIO_DIRSET_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_DIRSET_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_DIRSET_PIN17_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN17_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN17_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN18 @Bit 18 : Set as output pin 18 */
  #define GPIO_DIRSET_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
  #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
  #define GPIO_DIRSET_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_DIRSET_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_DIRSET_PIN18_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN18_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN18_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN19 @Bit 19 : Set as output pin 19 */
  #define GPIO_DIRSET_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
  #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
  #define GPIO_DIRSET_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_DIRSET_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_DIRSET_PIN19_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN19_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN19_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN20 @Bit 20 : Set as output pin 20 */
  #define GPIO_DIRSET_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
  #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
  #define GPIO_DIRSET_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_DIRSET_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_DIRSET_PIN20_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN20_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN20_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN21 @Bit 21 : Set as output pin 21 */
  #define GPIO_DIRSET_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
  #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
  #define GPIO_DIRSET_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_DIRSET_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_DIRSET_PIN21_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN21_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN21_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN22 @Bit 22 : Set as output pin 22 */
  #define GPIO_DIRSET_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
  #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
  #define GPIO_DIRSET_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_DIRSET_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_DIRSET_PIN22_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN22_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN22_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN23 @Bit 23 : Set as output pin 23 */
  #define GPIO_DIRSET_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
  #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
  #define GPIO_DIRSET_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_DIRSET_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_DIRSET_PIN23_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN23_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN23_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN24 @Bit 24 : Set as output pin 24 */
  #define GPIO_DIRSET_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
  #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
  #define GPIO_DIRSET_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_DIRSET_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_DIRSET_PIN24_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN24_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN24_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN25 @Bit 25 : Set as output pin 25 */
  #define GPIO_DIRSET_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
  #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
  #define GPIO_DIRSET_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_DIRSET_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_DIRSET_PIN25_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN25_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN25_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN26 @Bit 26 : Set as output pin 26 */
  #define GPIO_DIRSET_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
  #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
  #define GPIO_DIRSET_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_DIRSET_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_DIRSET_PIN26_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN26_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN26_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN27 @Bit 27 : Set as output pin 27 */
  #define GPIO_DIRSET_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
  #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
  #define GPIO_DIRSET_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_DIRSET_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_DIRSET_PIN27_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN27_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN27_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN28 @Bit 28 : Set as output pin 28 */
  #define GPIO_DIRSET_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
  #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
  #define GPIO_DIRSET_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_DIRSET_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_DIRSET_PIN28_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN28_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN28_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN29 @Bit 29 : Set as output pin 29 */
  #define GPIO_DIRSET_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
  #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
  #define GPIO_DIRSET_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_DIRSET_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_DIRSET_PIN29_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN29_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN29_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN30 @Bit 30 : Set as output pin 30 */
  #define GPIO_DIRSET_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
  #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
  #define GPIO_DIRSET_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_DIRSET_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_DIRSET_PIN30_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN30_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN30_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */

/* PIN31 @Bit 31 : Set as output pin 31 */
  #define GPIO_DIRSET_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
  #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
  #define GPIO_DIRSET_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_DIRSET_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_DIRSET_PIN31_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRSET_PIN31_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRSET_PIN31_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */


/* GPIO_DIRCLR: DIR clear register */
  #define GPIO_DIRCLR_ResetValue (0x00000000UL)      /*!< Reset value of DIRCLR register.                                      */

/* PIN0 @Bit 0 : Set as input pin 0 */
  #define GPIO_DIRCLR_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
  #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
  #define GPIO_DIRCLR_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_DIRCLR_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_DIRCLR_PIN0_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN0_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN0_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN1 @Bit 1 : Set as input pin 1 */
  #define GPIO_DIRCLR_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
  #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
  #define GPIO_DIRCLR_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_DIRCLR_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_DIRCLR_PIN1_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN1_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN1_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN2 @Bit 2 : Set as input pin 2 */
  #define GPIO_DIRCLR_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
  #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
  #define GPIO_DIRCLR_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_DIRCLR_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_DIRCLR_PIN2_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN2_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN2_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN3 @Bit 3 : Set as input pin 3 */
  #define GPIO_DIRCLR_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
  #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
  #define GPIO_DIRCLR_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_DIRCLR_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_DIRCLR_PIN3_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN3_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN3_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN4 @Bit 4 : Set as input pin 4 */
  #define GPIO_DIRCLR_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
  #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
  #define GPIO_DIRCLR_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_DIRCLR_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_DIRCLR_PIN4_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN4_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN4_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN5 @Bit 5 : Set as input pin 5 */
  #define GPIO_DIRCLR_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
  #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
  #define GPIO_DIRCLR_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_DIRCLR_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_DIRCLR_PIN5_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN5_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN5_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN6 @Bit 6 : Set as input pin 6 */
  #define GPIO_DIRCLR_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
  #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
  #define GPIO_DIRCLR_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_DIRCLR_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_DIRCLR_PIN6_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN6_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN6_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN7 @Bit 7 : Set as input pin 7 */
  #define GPIO_DIRCLR_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
  #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
  #define GPIO_DIRCLR_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_DIRCLR_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_DIRCLR_PIN7_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN7_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN7_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN8 @Bit 8 : Set as input pin 8 */
  #define GPIO_DIRCLR_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
  #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
  #define GPIO_DIRCLR_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_DIRCLR_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_DIRCLR_PIN8_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN8_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN8_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN9 @Bit 9 : Set as input pin 9 */
  #define GPIO_DIRCLR_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
  #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
  #define GPIO_DIRCLR_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_DIRCLR_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_DIRCLR_PIN9_Input (0x0UL)             /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN9_Output (0x1UL)            /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN9_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN10 @Bit 10 : Set as input pin 10 */
  #define GPIO_DIRCLR_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
  #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
  #define GPIO_DIRCLR_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_DIRCLR_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_DIRCLR_PIN10_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN10_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN10_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN11 @Bit 11 : Set as input pin 11 */
  #define GPIO_DIRCLR_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
  #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
  #define GPIO_DIRCLR_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_DIRCLR_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_DIRCLR_PIN11_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN11_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN11_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN12 @Bit 12 : Set as input pin 12 */
  #define GPIO_DIRCLR_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
  #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
  #define GPIO_DIRCLR_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_DIRCLR_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_DIRCLR_PIN12_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN12_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN12_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN13 @Bit 13 : Set as input pin 13 */
  #define GPIO_DIRCLR_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
  #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
  #define GPIO_DIRCLR_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_DIRCLR_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_DIRCLR_PIN13_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN13_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN13_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN14 @Bit 14 : Set as input pin 14 */
  #define GPIO_DIRCLR_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
  #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
  #define GPIO_DIRCLR_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_DIRCLR_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_DIRCLR_PIN14_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN14_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN14_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN15 @Bit 15 : Set as input pin 15 */
  #define GPIO_DIRCLR_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
  #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
  #define GPIO_DIRCLR_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_DIRCLR_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_DIRCLR_PIN15_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN15_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN15_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN16 @Bit 16 : Set as input pin 16 */
  #define GPIO_DIRCLR_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
  #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
  #define GPIO_DIRCLR_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_DIRCLR_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_DIRCLR_PIN16_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN16_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN16_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN17 @Bit 17 : Set as input pin 17 */
  #define GPIO_DIRCLR_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
  #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
  #define GPIO_DIRCLR_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_DIRCLR_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_DIRCLR_PIN17_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN17_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN17_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN18 @Bit 18 : Set as input pin 18 */
  #define GPIO_DIRCLR_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
  #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
  #define GPIO_DIRCLR_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_DIRCLR_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_DIRCLR_PIN18_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN18_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN18_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN19 @Bit 19 : Set as input pin 19 */
  #define GPIO_DIRCLR_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
  #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
  #define GPIO_DIRCLR_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_DIRCLR_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_DIRCLR_PIN19_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN19_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN19_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN20 @Bit 20 : Set as input pin 20 */
  #define GPIO_DIRCLR_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
  #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
  #define GPIO_DIRCLR_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_DIRCLR_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_DIRCLR_PIN20_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN20_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN20_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN21 @Bit 21 : Set as input pin 21 */
  #define GPIO_DIRCLR_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
  #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
  #define GPIO_DIRCLR_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_DIRCLR_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_DIRCLR_PIN21_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN21_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN21_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN22 @Bit 22 : Set as input pin 22 */
  #define GPIO_DIRCLR_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
  #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
  #define GPIO_DIRCLR_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_DIRCLR_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_DIRCLR_PIN22_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN22_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN22_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN23 @Bit 23 : Set as input pin 23 */
  #define GPIO_DIRCLR_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
  #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
  #define GPIO_DIRCLR_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_DIRCLR_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_DIRCLR_PIN23_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN23_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN23_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN24 @Bit 24 : Set as input pin 24 */
  #define GPIO_DIRCLR_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
  #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
  #define GPIO_DIRCLR_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_DIRCLR_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_DIRCLR_PIN24_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN24_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN24_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN25 @Bit 25 : Set as input pin 25 */
  #define GPIO_DIRCLR_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
  #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
  #define GPIO_DIRCLR_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_DIRCLR_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_DIRCLR_PIN25_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN25_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN25_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN26 @Bit 26 : Set as input pin 26 */
  #define GPIO_DIRCLR_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
  #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
  #define GPIO_DIRCLR_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_DIRCLR_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_DIRCLR_PIN26_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN26_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN26_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN27 @Bit 27 : Set as input pin 27 */
  #define GPIO_DIRCLR_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
  #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
  #define GPIO_DIRCLR_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_DIRCLR_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_DIRCLR_PIN27_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN27_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN27_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN28 @Bit 28 : Set as input pin 28 */
  #define GPIO_DIRCLR_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
  #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
  #define GPIO_DIRCLR_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_DIRCLR_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_DIRCLR_PIN28_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN28_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN28_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN29 @Bit 29 : Set as input pin 29 */
  #define GPIO_DIRCLR_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
  #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
  #define GPIO_DIRCLR_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_DIRCLR_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_DIRCLR_PIN29_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN29_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN29_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN30 @Bit 30 : Set as input pin 30 */
  #define GPIO_DIRCLR_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
  #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
  #define GPIO_DIRCLR_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_DIRCLR_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_DIRCLR_PIN30_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN30_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN30_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */

/* PIN31 @Bit 31 : Set as input pin 31 */
  #define GPIO_DIRCLR_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
  #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
  #define GPIO_DIRCLR_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_DIRCLR_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_DIRCLR_PIN31_Input (0x0UL)            /*!< Read: pin set as input                                               */
  #define GPIO_DIRCLR_PIN31_Output (0x1UL)           /*!< Read: pin set as output                                              */
  #define GPIO_DIRCLR_PIN31_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */


/* GPIO_LATCH: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
  #define GPIO_LATCH_ResetValue (0x00000000UL)       /*!< Reset value of LATCH register.                                       */

/* PIN0 @Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN0_Pos (0UL)                  /*!< Position of PIN0 field.                                              */
  #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field.                                      */
  #define GPIO_LATCH_PIN0_Min (0x0UL)                /*!< Min enumerator value of PIN0 field.                                  */
  #define GPIO_LATCH_PIN0_Max (0x1UL)                /*!< Max enumerator value of PIN0 field.                                  */
  #define GPIO_LATCH_PIN0_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN0_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN1 @Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN1_Pos (1UL)                  /*!< Position of PIN1 field.                                              */
  #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field.                                      */
  #define GPIO_LATCH_PIN1_Min (0x0UL)                /*!< Min enumerator value of PIN1 field.                                  */
  #define GPIO_LATCH_PIN1_Max (0x1UL)                /*!< Max enumerator value of PIN1 field.                                  */
  #define GPIO_LATCH_PIN1_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN1_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN2 @Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN2_Pos (2UL)                  /*!< Position of PIN2 field.                                              */
  #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field.                                      */
  #define GPIO_LATCH_PIN2_Min (0x0UL)                /*!< Min enumerator value of PIN2 field.                                  */
  #define GPIO_LATCH_PIN2_Max (0x1UL)                /*!< Max enumerator value of PIN2 field.                                  */
  #define GPIO_LATCH_PIN2_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN2_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN3 @Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN3_Pos (3UL)                  /*!< Position of PIN3 field.                                              */
  #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field.                                      */
  #define GPIO_LATCH_PIN3_Min (0x0UL)                /*!< Min enumerator value of PIN3 field.                                  */
  #define GPIO_LATCH_PIN3_Max (0x1UL)                /*!< Max enumerator value of PIN3 field.                                  */
  #define GPIO_LATCH_PIN3_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN3_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN4 @Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN4_Pos (4UL)                  /*!< Position of PIN4 field.                                              */
  #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field.                                      */
  #define GPIO_LATCH_PIN4_Min (0x0UL)                /*!< Min enumerator value of PIN4 field.                                  */
  #define GPIO_LATCH_PIN4_Max (0x1UL)                /*!< Max enumerator value of PIN4 field.                                  */
  #define GPIO_LATCH_PIN4_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN4_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN5 @Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN5_Pos (5UL)                  /*!< Position of PIN5 field.                                              */
  #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field.                                      */
  #define GPIO_LATCH_PIN5_Min (0x0UL)                /*!< Min enumerator value of PIN5 field.                                  */
  #define GPIO_LATCH_PIN5_Max (0x1UL)                /*!< Max enumerator value of PIN5 field.                                  */
  #define GPIO_LATCH_PIN5_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN5_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN6 @Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN6_Pos (6UL)                  /*!< Position of PIN6 field.                                              */
  #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field.                                      */
  #define GPIO_LATCH_PIN6_Min (0x0UL)                /*!< Min enumerator value of PIN6 field.                                  */
  #define GPIO_LATCH_PIN6_Max (0x1UL)                /*!< Max enumerator value of PIN6 field.                                  */
  #define GPIO_LATCH_PIN6_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN6_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN7 @Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN7_Pos (7UL)                  /*!< Position of PIN7 field.                                              */
  #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field.                                      */
  #define GPIO_LATCH_PIN7_Min (0x0UL)                /*!< Min enumerator value of PIN7 field.                                  */
  #define GPIO_LATCH_PIN7_Max (0x1UL)                /*!< Max enumerator value of PIN7 field.                                  */
  #define GPIO_LATCH_PIN7_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN7_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN8 @Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN8_Pos (8UL)                  /*!< Position of PIN8 field.                                              */
  #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field.                                      */
  #define GPIO_LATCH_PIN8_Min (0x0UL)                /*!< Min enumerator value of PIN8 field.                                  */
  #define GPIO_LATCH_PIN8_Max (0x1UL)                /*!< Max enumerator value of PIN8 field.                                  */
  #define GPIO_LATCH_PIN8_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN8_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN9 @Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN9_Pos (9UL)                  /*!< Position of PIN9 field.                                              */
  #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field.                                      */
  #define GPIO_LATCH_PIN9_Min (0x0UL)                /*!< Min enumerator value of PIN9 field.                                  */
  #define GPIO_LATCH_PIN9_Max (0x1UL)                /*!< Max enumerator value of PIN9 field.                                  */
  #define GPIO_LATCH_PIN9_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN9_Latched (0x1UL)            /*!< Criteria has been met                                                */

/* PIN10 @Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN10_Pos (10UL)                /*!< Position of PIN10 field.                                             */
  #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field.                                   */
  #define GPIO_LATCH_PIN10_Min (0x0UL)               /*!< Min enumerator value of PIN10 field.                                 */
  #define GPIO_LATCH_PIN10_Max (0x1UL)               /*!< Max enumerator value of PIN10 field.                                 */
  #define GPIO_LATCH_PIN10_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN10_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN11 @Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN11_Pos (11UL)                /*!< Position of PIN11 field.                                             */
  #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field.                                   */
  #define GPIO_LATCH_PIN11_Min (0x0UL)               /*!< Min enumerator value of PIN11 field.                                 */
  #define GPIO_LATCH_PIN11_Max (0x1UL)               /*!< Max enumerator value of PIN11 field.                                 */
  #define GPIO_LATCH_PIN11_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN11_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN12 @Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN12_Pos (12UL)                /*!< Position of PIN12 field.                                             */
  #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field.                                   */
  #define GPIO_LATCH_PIN12_Min (0x0UL)               /*!< Min enumerator value of PIN12 field.                                 */
  #define GPIO_LATCH_PIN12_Max (0x1UL)               /*!< Max enumerator value of PIN12 field.                                 */
  #define GPIO_LATCH_PIN12_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN12_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN13 @Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN13_Pos (13UL)                /*!< Position of PIN13 field.                                             */
  #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field.                                   */
  #define GPIO_LATCH_PIN13_Min (0x0UL)               /*!< Min enumerator value of PIN13 field.                                 */
  #define GPIO_LATCH_PIN13_Max (0x1UL)               /*!< Max enumerator value of PIN13 field.                                 */
  #define GPIO_LATCH_PIN13_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN13_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN14 @Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN14_Pos (14UL)                /*!< Position of PIN14 field.                                             */
  #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field.                                   */
  #define GPIO_LATCH_PIN14_Min (0x0UL)               /*!< Min enumerator value of PIN14 field.                                 */
  #define GPIO_LATCH_PIN14_Max (0x1UL)               /*!< Max enumerator value of PIN14 field.                                 */
  #define GPIO_LATCH_PIN14_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN14_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN15 @Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN15_Pos (15UL)                /*!< Position of PIN15 field.                                             */
  #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field.                                   */
  #define GPIO_LATCH_PIN15_Min (0x0UL)               /*!< Min enumerator value of PIN15 field.                                 */
  #define GPIO_LATCH_PIN15_Max (0x1UL)               /*!< Max enumerator value of PIN15 field.                                 */
  #define GPIO_LATCH_PIN15_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN15_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN16 @Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN16_Pos (16UL)                /*!< Position of PIN16 field.                                             */
  #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field.                                   */
  #define GPIO_LATCH_PIN16_Min (0x0UL)               /*!< Min enumerator value of PIN16 field.                                 */
  #define GPIO_LATCH_PIN16_Max (0x1UL)               /*!< Max enumerator value of PIN16 field.                                 */
  #define GPIO_LATCH_PIN16_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN16_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN17 @Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN17_Pos (17UL)                /*!< Position of PIN17 field.                                             */
  #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field.                                   */
  #define GPIO_LATCH_PIN17_Min (0x0UL)               /*!< Min enumerator value of PIN17 field.                                 */
  #define GPIO_LATCH_PIN17_Max (0x1UL)               /*!< Max enumerator value of PIN17 field.                                 */
  #define GPIO_LATCH_PIN17_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN17_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN18 @Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN18_Pos (18UL)                /*!< Position of PIN18 field.                                             */
  #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field.                                   */
  #define GPIO_LATCH_PIN18_Min (0x0UL)               /*!< Min enumerator value of PIN18 field.                                 */
  #define GPIO_LATCH_PIN18_Max (0x1UL)               /*!< Max enumerator value of PIN18 field.                                 */
  #define GPIO_LATCH_PIN18_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN18_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN19 @Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN19_Pos (19UL)                /*!< Position of PIN19 field.                                             */
  #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field.                                   */
  #define GPIO_LATCH_PIN19_Min (0x0UL)               /*!< Min enumerator value of PIN19 field.                                 */
  #define GPIO_LATCH_PIN19_Max (0x1UL)               /*!< Max enumerator value of PIN19 field.                                 */
  #define GPIO_LATCH_PIN19_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN19_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN20 @Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN20_Pos (20UL)                /*!< Position of PIN20 field.                                             */
  #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field.                                   */
  #define GPIO_LATCH_PIN20_Min (0x0UL)               /*!< Min enumerator value of PIN20 field.                                 */
  #define GPIO_LATCH_PIN20_Max (0x1UL)               /*!< Max enumerator value of PIN20 field.                                 */
  #define GPIO_LATCH_PIN20_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN20_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN21 @Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN21_Pos (21UL)                /*!< Position of PIN21 field.                                             */
  #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field.                                   */
  #define GPIO_LATCH_PIN21_Min (0x0UL)               /*!< Min enumerator value of PIN21 field.                                 */
  #define GPIO_LATCH_PIN21_Max (0x1UL)               /*!< Max enumerator value of PIN21 field.                                 */
  #define GPIO_LATCH_PIN21_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN21_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN22 @Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN22_Pos (22UL)                /*!< Position of PIN22 field.                                             */
  #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field.                                   */
  #define GPIO_LATCH_PIN22_Min (0x0UL)               /*!< Min enumerator value of PIN22 field.                                 */
  #define GPIO_LATCH_PIN22_Max (0x1UL)               /*!< Max enumerator value of PIN22 field.                                 */
  #define GPIO_LATCH_PIN22_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN22_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN23 @Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN23_Pos (23UL)                /*!< Position of PIN23 field.                                             */
  #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field.                                   */
  #define GPIO_LATCH_PIN23_Min (0x0UL)               /*!< Min enumerator value of PIN23 field.                                 */
  #define GPIO_LATCH_PIN23_Max (0x1UL)               /*!< Max enumerator value of PIN23 field.                                 */
  #define GPIO_LATCH_PIN23_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN23_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN24 @Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN24_Pos (24UL)                /*!< Position of PIN24 field.                                             */
  #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field.                                   */
  #define GPIO_LATCH_PIN24_Min (0x0UL)               /*!< Min enumerator value of PIN24 field.                                 */
  #define GPIO_LATCH_PIN24_Max (0x1UL)               /*!< Max enumerator value of PIN24 field.                                 */
  #define GPIO_LATCH_PIN24_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN24_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN25 @Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN25_Pos (25UL)                /*!< Position of PIN25 field.                                             */
  #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field.                                   */
  #define GPIO_LATCH_PIN25_Min (0x0UL)               /*!< Min enumerator value of PIN25 field.                                 */
  #define GPIO_LATCH_PIN25_Max (0x1UL)               /*!< Max enumerator value of PIN25 field.                                 */
  #define GPIO_LATCH_PIN25_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN25_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN26 @Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN26_Pos (26UL)                /*!< Position of PIN26 field.                                             */
  #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field.                                   */
  #define GPIO_LATCH_PIN26_Min (0x0UL)               /*!< Min enumerator value of PIN26 field.                                 */
  #define GPIO_LATCH_PIN26_Max (0x1UL)               /*!< Max enumerator value of PIN26 field.                                 */
  #define GPIO_LATCH_PIN26_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN26_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN27 @Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN27_Pos (27UL)                /*!< Position of PIN27 field.                                             */
  #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field.                                   */
  #define GPIO_LATCH_PIN27_Min (0x0UL)               /*!< Min enumerator value of PIN27 field.                                 */
  #define GPIO_LATCH_PIN27_Max (0x1UL)               /*!< Max enumerator value of PIN27 field.                                 */
  #define GPIO_LATCH_PIN27_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN27_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN28 @Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN28_Pos (28UL)                /*!< Position of PIN28 field.                                             */
  #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field.                                   */
  #define GPIO_LATCH_PIN28_Min (0x0UL)               /*!< Min enumerator value of PIN28 field.                                 */
  #define GPIO_LATCH_PIN28_Max (0x1UL)               /*!< Max enumerator value of PIN28 field.                                 */
  #define GPIO_LATCH_PIN28_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN28_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN29 @Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN29_Pos (29UL)                /*!< Position of PIN29 field.                                             */
  #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field.                                   */
  #define GPIO_LATCH_PIN29_Min (0x0UL)               /*!< Min enumerator value of PIN29 field.                                 */
  #define GPIO_LATCH_PIN29_Max (0x1UL)               /*!< Max enumerator value of PIN29 field.                                 */
  #define GPIO_LATCH_PIN29_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN29_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN30 @Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN30_Pos (30UL)                /*!< Position of PIN30 field.                                             */
  #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field.                                   */
  #define GPIO_LATCH_PIN30_Min (0x0UL)               /*!< Min enumerator value of PIN30 field.                                 */
  #define GPIO_LATCH_PIN30_Max (0x1UL)               /*!< Max enumerator value of PIN30 field.                                 */
  #define GPIO_LATCH_PIN30_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN30_Latched (0x1UL)           /*!< Criteria has been met                                                */

/* PIN31 @Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
  #define GPIO_LATCH_PIN31_Pos (31UL)                /*!< Position of PIN31 field.                                             */
  #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field.                                   */
  #define GPIO_LATCH_PIN31_Min (0x0UL)               /*!< Min enumerator value of PIN31 field.                                 */
  #define GPIO_LATCH_PIN31_Max (0x1UL)               /*!< Max enumerator value of PIN31 field.                                 */
  #define GPIO_LATCH_PIN31_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
  #define GPIO_LATCH_PIN31_Latched (0x1UL)           /*!< Criteria has been met                                                */


/* GPIO_DETECTMODE: Select between default DETECT signal behavior and LDETECT mode */
  #define GPIO_DETECTMODE_ResetValue (0x00000000UL)  /*!< Reset value of DETECTMODE register.                                  */

/* DETECTMODE @Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
  #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL)       /*!< Position of DETECTMODE field.                                        */
  #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field.          */
  #define GPIO_DETECTMODE_DETECTMODE_Min (0x0UL)     /*!< Min enumerator value of DETECTMODE field.                            */
  #define GPIO_DETECTMODE_DETECTMODE_Max (0x1UL)     /*!< Max enumerator value of DETECTMODE field.                            */
  #define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals                      */
  #define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior                                     */


/* GPIO_PIN_CNF: Pin n configuration of GPIO pin */
  #define GPIO_PIN_CNF_MaxCount (32UL)               /*!< Max size of PIN_CNF[32] array.                                       */
  #define GPIO_PIN_CNF_MaxIndex (31UL)               /*!< Max index of PIN_CNF[32] array.                                      */
  #define GPIO_PIN_CNF_MinIndex (0UL)                /*!< Min index of PIN_CNF[32] array.                                      */
  #define GPIO_PIN_CNF_ResetValue (0x00000002UL)     /*!< Reset value of PIN_CNF[32] register.                                 */

/* DIR @Bit 0 : Pin direction. Same physical register as DIR register */
  #define GPIO_PIN_CNF_DIR_Pos (0UL)                 /*!< Position of DIR field.                                               */
  #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field.                                     */
  #define GPIO_PIN_CNF_DIR_Min (0x0UL)               /*!< Min enumerator value of DIR field.                                   */
  #define GPIO_PIN_CNF_DIR_Max (0x1UL)               /*!< Max enumerator value of DIR field.                                   */
  #define GPIO_PIN_CNF_DIR_Input (0x0UL)             /*!< Configure pin as an input pin                                        */
  #define GPIO_PIN_CNF_DIR_Output (0x1UL)            /*!< Configure pin as an output pin                                       */

/* INPUT @Bit 1 : Connect or disconnect input buffer */
  #define GPIO_PIN_CNF_INPUT_Pos (1UL)               /*!< Position of INPUT field.                                             */
  #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field.                               */
  #define GPIO_PIN_CNF_INPUT_Min (0x0UL)             /*!< Min enumerator value of INPUT field.                                 */
  #define GPIO_PIN_CNF_INPUT_Max (0x1UL)             /*!< Max enumerator value of INPUT field.                                 */
  #define GPIO_PIN_CNF_INPUT_Connect (0x0UL)         /*!< Connect input buffer                                                 */
  #define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL)      /*!< Disconnect input buffer                                              */

/* PULL @Bits 2..3 : Pull configuration */
  #define GPIO_PIN_CNF_PULL_Pos (2UL)                /*!< Position of PULL field.                                              */
  #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field.                                  */
  #define GPIO_PIN_CNF_PULL_Min (0x0UL)              /*!< Min enumerator value of PULL field.                                  */
  #define GPIO_PIN_CNF_PULL_Max (0x3UL)              /*!< Max enumerator value of PULL field.                                  */
  #define GPIO_PIN_CNF_PULL_Disabled (0x0UL)         /*!< No pull                                                              */
  #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL)         /*!< Pull down on pin                                                     */
  #define GPIO_PIN_CNF_PULL_Pullup (0x3UL)           /*!< Pull up on pin                                                       */

/* DRIVE0 @Bits 8..9 : Drive configuration for '0' */
  #define GPIO_PIN_CNF_DRIVE0_Pos (8UL)              /*!< Position of DRIVE0 field.                                            */
  #define GPIO_PIN_CNF_DRIVE0_Msk (0x3UL << GPIO_PIN_CNF_DRIVE0_Pos) /*!< Bit mask of DRIVE0 field.                            */
  #define GPIO_PIN_CNF_DRIVE0_Min (0x0UL)            /*!< Min enumerator value of DRIVE0 field.                                */
  #define GPIO_PIN_CNF_DRIVE0_Max (0x3UL)            /*!< Max enumerator value of DRIVE0 field.                                */
  #define GPIO_PIN_CNF_DRIVE0_S0 (0x0UL)             /*!< Standard '0'                                                         */
  #define GPIO_PIN_CNF_DRIVE0_H0 (0x1UL)             /*!< High drive '0'                                                       */
  #define GPIO_PIN_CNF_DRIVE0_D0 (0x2UL)             /*!< Disconnect '0'(normally used for wired-or connections)               */
  #define GPIO_PIN_CNF_DRIVE0_E0 (0x3UL)             /*!< Extra high drive '0'                                                 */

/* DRIVE1 @Bits 10..11 : Drive configuration for '1' */
  #define GPIO_PIN_CNF_DRIVE1_Pos (10UL)             /*!< Position of DRIVE1 field.                                            */
  #define GPIO_PIN_CNF_DRIVE1_Msk (0x3UL << GPIO_PIN_CNF_DRIVE1_Pos) /*!< Bit mask of DRIVE1 field.                            */
  #define GPIO_PIN_CNF_DRIVE1_Min (0x0UL)            /*!< Min enumerator value of DRIVE1 field.                                */
  #define GPIO_PIN_CNF_DRIVE1_Max (0x3UL)            /*!< Max enumerator value of DRIVE1 field.                                */
  #define GPIO_PIN_CNF_DRIVE1_S1 (0x0UL)             /*!< Standard '1'                                                         */
  #define GPIO_PIN_CNF_DRIVE1_H1 (0x1UL)             /*!< High drive '1'                                                       */
  #define GPIO_PIN_CNF_DRIVE1_D1 (0x2UL)             /*!< Disconnect '1'(normally used for wired-or connections)               */
  #define GPIO_PIN_CNF_DRIVE1_E1 (0x3UL)             /*!< Extra high drive '1'                                                 */

/* SENSE @Bits 16..17 : Pin sensing mechanism */
  #define GPIO_PIN_CNF_SENSE_Pos (16UL)              /*!< Position of SENSE field.                                             */
  #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field.                               */
  #define GPIO_PIN_CNF_SENSE_Min (0x0UL)             /*!< Min enumerator value of SENSE field.                                 */
  #define GPIO_PIN_CNF_SENSE_Max (0x3UL)             /*!< Max enumerator value of SENSE field.                                 */
  #define GPIO_PIN_CNF_SENSE_Disabled (0x0UL)        /*!< Disabled                                                             */
  #define GPIO_PIN_CNF_SENSE_High (0x2UL)            /*!< Sense for high level                                                 */
  #define GPIO_PIN_CNF_SENSE_Low (0x3UL)             /*!< Sense for low level                                                  */

/* CTRLSEL @Bits 28..30 : Select which module has direct control over this pin */
  #define GPIO_PIN_CNF_CTRLSEL_Pos (28UL)            /*!< Position of CTRLSEL field.                                           */
  #define GPIO_PIN_CNF_CTRLSEL_Msk (0x7UL << GPIO_PIN_CNF_CTRLSEL_Pos) /*!< Bit mask of CTRLSEL field.                         */
  #define GPIO_PIN_CNF_CTRLSEL_Min (0x0UL)           /*!< Min enumerator value of CTRLSEL field.                               */
  #define GPIO_PIN_CNF_CTRLSEL_Max (0x4UL)           /*!< Max enumerator value of CTRLSEL field.                               */
  #define GPIO_PIN_CNF_CTRLSEL_GPIO (0x0UL)          /*!< GPIO or peripherals with PSEL registers                              */
  #define GPIO_PIN_CNF_CTRLSEL_VPR (0x1UL)           /*!< VPR processor                                                        */
  #define GPIO_PIN_CNF_CTRLSEL_GRTC (0x4UL)          /*!< GRTC peripheral                                                      */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                       GPIOHSPADCTRL                                       ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ================================================== Struct GPIOHSPADCTRL =================================================== */
/**
  * @brief GPIO high-speed pad control
  */
  typedef struct {                                   /*!< GPIOHSPADCTRL Structure                                              */
    __IM uint32_t RESERVED[12];
    __IOM uint32_t BIAS;                             /*!< (@ 0x00000030) Bias control                                          */
    __IM uint32_t RESERVED1;
    __IOM uint32_t CTRL;                             /*!< (@ 0x00000038) Input sampling and buffering control (used by the VPR
                                                                         coprocessor for emulating a QSPI peripheral)*/
  } NRF_GPIOHSPADCTRL_Type;                          /*!< Size = 60 (0x03C)                                                    */

/* GPIOHSPADCTRL_BIAS: Bias control */
  #define GPIOHSPADCTRL_BIAS_ResetValue (0x00000000UL) /*!< Reset value of BIAS register.                                      */

/* HSBIAS @Bits 0..1 : Slew setting for high-speed pad (higher value is faster) */
  #define GPIOHSPADCTRL_BIAS_HSBIAS_Pos (0UL)        /*!< Position of HSBIAS field.                                            */
  #define GPIOHSPADCTRL_BIAS_HSBIAS_Msk (0x3UL << GPIOHSPADCTRL_BIAS_HSBIAS_Pos) /*!< Bit mask of HSBIAS field.                */
  #define GPIOHSPADCTRL_BIAS_HSBIAS_Min (0x0UL)      /*!< Min value of HSBIAS field.                                           */
  #define GPIOHSPADCTRL_BIAS_HSBIAS_Max (0x3UL)      /*!< Max size of HSBIAS field.                                            */

/* REPLICABIAS @Bit 2 : Slew setting for replica clock (used by the VPR coprocessor for emulating a QSPI peripheral) */
  #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Pos (2UL)   /*!< Position of REPLICABIAS field.                                       */
  #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Msk (0x1UL << GPIOHSPADCTRL_BIAS_REPLICABIAS_Pos) /*!< Bit mask of REPLICABIAS field. */
  #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Min (0x0UL) /*!< Min value of REPLICABIAS field.                                      */
  #define GPIOHSPADCTRL_BIAS_REPLICABIAS_Max (0x1UL) /*!< Max size of REPLICABIAS field.                                       */


/* GPIOHSPADCTRL_CTRL: Input sampling and buffering control (used by the VPR coprocessor for emulating a QSPI peripheral) */
  #define GPIOHSPADCTRL_CTRL_ResetValue (0x00000000UL) /*!< Reset value of CTRL register.                                      */

/* RXDELAY @Bits 0..2 : Delay selection */
  #define GPIOHSPADCTRL_CTRL_RXDELAY_Pos (0UL)       /*!< Position of RXDELAY field.                                           */
  #define GPIOHSPADCTRL_CTRL_RXDELAY_Msk (0x7UL << GPIOHSPADCTRL_CTRL_RXDELAY_Pos) /*!< Bit mask of RXDELAY field.             */

/* SCKEN @Bit 3 : Enable SCK */
  #define GPIOHSPADCTRL_CTRL_SCKEN_Pos (3UL)         /*!< Position of SCKEN field.                                             */
  #define GPIOHSPADCTRL_CTRL_SCKEN_Msk (0x1UL << GPIOHSPADCTRL_CTRL_SCKEN_Pos) /*!< Bit mask of SCKEN field.                   */
  #define GPIOHSPADCTRL_CTRL_SCKEN_Min (0x0UL)       /*!< Min enumerator value of SCKEN field.                                 */
  #define GPIOHSPADCTRL_CTRL_SCKEN_Max (0x1UL)       /*!< Max enumerator value of SCKEN field.                                 */
  #define GPIOHSPADCTRL_CTRL_SCKEN_Disabled (0x0UL)  /*!< Delay chain is reset and delayed sampling is disabled                */
  #define GPIOHSPADCTRL_CTRL_SCKEN_Enabled (0x1UL)   /*!< Delay chain and delayed sampling is active                           */

/* SCKPHASE @Bit 4 : SCK phase */
  #define GPIOHSPADCTRL_CTRL_SCKPHASE_Pos (4UL)      /*!< Position of SCKPHASE field.                                          */
  #define GPIOHSPADCTRL_CTRL_SCKPHASE_Msk (0x1UL << GPIOHSPADCTRL_CTRL_SCKPHASE_Pos) /*!< Bit mask of SCKPHASE field.          */
  #define GPIOHSPADCTRL_CTRL_SCKPHASE_Min (0x0UL)    /*!< Min enumerator value of SCKPHASE field.                              */
  #define GPIOHSPADCTRL_CTRL_SCKPHASE_Max (0x1UL)    /*!< Max enumerator value of SCKPHASE field.                              */
  #define GPIOHSPADCTRL_CTRL_SCKPHASE_Inverted (0x0UL) /*!< Invert SCK phase                                                   */
  #define GPIOHSPADCTRL_CTRL_SCKPHASE_NonInverted (0x1UL) /*!< Non-inverted SCK phase                                          */

/* CSNEN @Bit 5 : Enable CSN synchronization of sampling */
  #define GPIOHSPADCTRL_CTRL_CSNEN_Pos (5UL)         /*!< Position of CSNEN field.                                             */
  #define GPIOHSPADCTRL_CTRL_CSNEN_Msk (0x1UL << GPIOHSPADCTRL_CTRL_CSNEN_Pos) /*!< Bit mask of CSNEN field.                   */
  #define GPIOHSPADCTRL_CTRL_CSNEN_Min (0x0UL)       /*!< Min enumerator value of CSNEN field.                                 */
  #define GPIOHSPADCTRL_CTRL_CSNEN_Max (0x1UL)       /*!< Max enumerator value of CSNEN field.                                 */
  #define GPIOHSPADCTRL_CTRL_CSNEN_Enabled (0x0UL)   /*!< Delay chain is reset on active edge of CSN                           */
  #define GPIOHSPADCTRL_CTRL_CSNEN_Disabled (0x1UL)  /*!< Delay chain is not reset on active edge of CSN                       */

/* DATAENABLE @Bits 6..9 : Enable delayed sampling */
  #define GPIOHSPADCTRL_CTRL_DATAENABLE_Pos (6UL)    /*!< Position of DATAENABLE field.                                        */
  #define GPIOHSPADCTRL_CTRL_DATAENABLE_Msk (0xFUL << GPIOHSPADCTRL_CTRL_DATAENABLE_Pos) /*!< Bit mask of DATAENABLE field.    */
  #define GPIOHSPADCTRL_CTRL_DATAENABLE_Min (0x0UL)  /*!< Min enumerator value of DATAENABLE field.                            */
  #define GPIOHSPADCTRL_CTRL_DATAENABLE_Max (0xFUL)  /*!< Max enumerator value of DATAENABLE field.                            */
  #define GPIOHSPADCTRL_CTRL_DATAENABLE_Disabled (0x0UL) /*!< Delayed sampling is disabled                                     */
  #define GPIOHSPADCTRL_CTRL_DATAENABLE_Enabled (0xFUL) /*!< Delayed sampling is enabled                                       */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                       GPIOINTERNAL                                       ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* =================================================== Struct GPIOINTERNAL =================================================== */
/**
  * @brief GPIO Internal
  */
  typedef struct {                                   /*!< GPIOINTERNAL Structure                                               */
    __IM uint32_t RESERVED;
  } NRF_GPIOINTERNAL_Type;                           /*!< Size = 4 (0x004)                                                     */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                          GPIOTE                                          ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct GPIOTE_EVENTS_PORT ================================================ */
/**
  * @brief EVENTS_PORT [GPIOTE_EVENTS_PORT] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  NONSECURE;                         /*!< (@ 0x00000000) Non-secure port event from owner n                    */
  __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Secure port event from owner n                        */
} NRF_GPIOTE_EVENTS_PORT_Type;                       /*!< Size = 8 (0x008)                                                     */
  #define GPIOTE_EVENTS_PORT_MaxCount (1UL)          /*!< Size of EVENTS_PORT[1] array.                                        */
  #define GPIOTE_EVENTS_PORT_MaxIndex (0UL)          /*!< Max index of EVENTS_PORT[1] array.                                   */
  #define GPIOTE_EVENTS_PORT_MinIndex (0UL)          /*!< Min index of EVENTS_PORT[1] array.                                   */

/* GPIOTE_EVENTS_PORT_NONSECURE: Non-secure port event from owner n */
  #define GPIOTE_EVENTS_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register.                       */

/* NONSECURE @Bit 0 : Non-secure port event from owner n */
  #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos (0UL) /*!< Position of NONSECURE field.                                   */
  #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos) /*!< Bit mask of
                                                                            NONSECURE field.*/
  #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Min (0x0UL) /*!< Min enumerator value of NONSECURE field.                     */
  #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Max (0x1UL) /*!< Max enumerator value of NONSECURE field.                     */
  #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_NotGenerated (0x0UL) /*!< Event not generated                                 */
  #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Generated (0x1UL) /*!< Event generated                                        */


/* GPIOTE_EVENTS_PORT_SECURE: Secure port event from owner n */
  #define GPIOTE_EVENTS_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register.                             */

/* SECURE @Bit 0 : Secure port event from owner n */
  #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos (0UL) /*!< Position of SECURE field.                                            */
  #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos) /*!< Bit mask of SECURE field.  */
  #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field.                              */
  #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field.                              */
  #define GPIOTE_EVENTS_PORT_SECURE_SECURE_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Generated (0x1UL) /*!< Event generated                                              */



/* =============================================== Struct GPIOTE_PUBLISH_PORT ================================================ */
/**
  * @brief PUBLISH_PORT [GPIOTE_PUBLISH_PORT] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  NONSECURE;                         /*!< (@ 0x00000000) Publish configuration for event PORT[n].NONSECURE     */
  __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Publish configuration for event PORT[n].SECURE        */
} NRF_GPIOTE_PUBLISH_PORT_Type;                      /*!< Size = 8 (0x008)                                                     */
  #define GPIOTE_PUBLISH_PORT_MaxCount (1UL)         /*!< Size of PUBLISH_PORT[1] array.                                       */
  #define GPIOTE_PUBLISH_PORT_MaxIndex (0UL)         /*!< Max index of PUBLISH_PORT[1] array.                                  */
  #define GPIOTE_PUBLISH_PORT_MinIndex (0UL)         /*!< Min index of PUBLISH_PORT[1] array.                                  */

/* GPIOTE_PUBLISH_PORT_NONSECURE: Publish configuration for event PORT[n].NONSECURE */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].NONSECURE will publish to */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                          */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                      */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                       */

/* EN @Bit 31 : (unspecified) */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos (31UL) /*!< Position of EN field.                                               */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos) /*!< Bit mask of EN field.      */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                  */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                  */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Disabled (0x0UL) /*!< Disable publishing                                            */
  #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Enabled (0x1UL) /*!< Enable publishing                                              */


/* GPIOTE_PUBLISH_PORT_SECURE: Publish configuration for event PORT[n].SECURE */
  #define GPIOTE_PUBLISH_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].SECURE will publish to */
  #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define GPIOTE_PUBLISH_PORT_SECURE_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define GPIOTE_PUBLISH_PORT_SECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_SECURE_EN_Pos) /*!< Bit mask of EN field.            */
  #define GPIOTE_PUBLISH_PORT_SECURE_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define GPIOTE_PUBLISH_PORT_SECURE_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define GPIOTE_PUBLISH_PORT_SECURE_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
  #define GPIOTE_PUBLISH_PORT_SECURE_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */


/* ====================================================== Struct GPIOTE ====================================================== */
/**
  * @brief GPIO Tasks and Events
  */
  typedef struct {                                   /*!< GPIOTE Structure                                                     */
    __OM uint32_t TASKS_OUT[8];                      /*!< (@ 0x00000000) Task for writing to pin specified in CONFIG[n].PSEL.
                                                                         Action on pin is configured in CONFIG[n].POLARITY.*/
    __IM uint32_t RESERVED[4];
    __OM uint32_t TASKS_SET[8];                      /*!< (@ 0x00000030) Task for writing to pin specified in CONFIG[n].PSEL.
                                                                         Action on pin is to set it high.*/
    __IM uint32_t RESERVED1[4];
    __OM uint32_t TASKS_CLR[8];                      /*!< (@ 0x00000060) Task for writing to pin specified in CONFIG[n].PSEL.
                                                                         Action on pin is to set it low.*/
    __IOM uint32_t SUBSCRIBE_OUT[8];                 /*!< (@ 0x00000080) Subscribe configuration for task OUT[n]               */
    __IM uint32_t RESERVED2[4];
    __IOM uint32_t SUBSCRIBE_SET[8];                 /*!< (@ 0x000000B0) Subscribe configuration for task SET[n]               */
    __IM uint32_t RESERVED3[4];
    __IOM uint32_t SUBSCRIBE_CLR[8];                 /*!< (@ 0x000000E0) Subscribe configuration for task CLR[n]               */
    __IOM uint32_t EVENTS_IN[8];                     /*!< (@ 0x00000100) Event from pin specified in CONFIG[n].PSEL            */
    __IM uint32_t RESERVED4[8];
    __IOM NRF_GPIOTE_EVENTS_PORT_Type EVENTS_PORT[1]; /*!< (@ 0x00000140) Peripheral events.                                   */
    __IM uint32_t RESERVED5[14];
    __IOM uint32_t PUBLISH_IN[8];                    /*!< (@ 0x00000180) Publish configuration for event IN[n]                 */
    __IM uint32_t RESERVED6[8];
    __IOM NRF_GPIOTE_PUBLISH_PORT_Type PUBLISH_PORT[1]; /*!< (@ 0x000001C0) Publish configuration for events                   */
    __IM uint32_t RESERVED7[79];
    __IOM uint32_t INTENSET0;                        /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR0;                        /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED8[2];
    __IOM uint32_t INTENSET1;                        /*!< (@ 0x00000314) Enable interrupt                                      */
    __IOM uint32_t INTENCLR1;                        /*!< (@ 0x00000318) Disable interrupt                                     */
    __IM uint32_t RESERVED9[125];
    __IOM uint32_t CONFIG[8];                        /*!< (@ 0x00000510) Configuration for OUT[n], SET[n], and CLR[n] tasks and
                                                                         IN[n] event*/
  } NRF_GPIOTE_Type;                                 /*!< Size = 1328 (0x530)                                                  */

/* GPIOTE_TASKS_OUT: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
  #define GPIOTE_TASKS_OUT_MaxCount (8UL)            /*!< Max size of TASKS_OUT[8] array.                                      */
  #define GPIOTE_TASKS_OUT_MaxIndex (7UL)            /*!< Max index of TASKS_OUT[8] array.                                     */
  #define GPIOTE_TASKS_OUT_MinIndex (0UL)            /*!< Min index of TASKS_OUT[8] array.                                     */
  #define GPIOTE_TASKS_OUT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_OUT[8] register.                                */

/* TASKS_OUT @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
  #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL)       /*!< Position of TASKS_OUT field.                                         */
  #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field.           */
  #define GPIOTE_TASKS_OUT_TASKS_OUT_Min (0x1UL)     /*!< Min enumerator value of TASKS_OUT field.                             */
  #define GPIOTE_TASKS_OUT_TASKS_OUT_Max (0x1UL)     /*!< Max enumerator value of TASKS_OUT field.                             */
  #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task                                                         */


/* GPIOTE_TASKS_SET: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
  #define GPIOTE_TASKS_SET_MaxCount (8UL)            /*!< Max size of TASKS_SET[8] array.                                      */
  #define GPIOTE_TASKS_SET_MaxIndex (7UL)            /*!< Max index of TASKS_SET[8] array.                                     */
  #define GPIOTE_TASKS_SET_MinIndex (0UL)            /*!< Min index of TASKS_SET[8] array.                                     */
  #define GPIOTE_TASKS_SET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SET[8] register.                                */

/* TASKS_SET @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
  #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL)       /*!< Position of TASKS_SET field.                                         */
  #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field.           */
  #define GPIOTE_TASKS_SET_TASKS_SET_Min (0x1UL)     /*!< Min enumerator value of TASKS_SET field.                             */
  #define GPIOTE_TASKS_SET_TASKS_SET_Max (0x1UL)     /*!< Max enumerator value of TASKS_SET field.                             */
  #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task                                                         */


/* GPIOTE_TASKS_CLR: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
  #define GPIOTE_TASKS_CLR_MaxCount (8UL)            /*!< Max size of TASKS_CLR[8] array.                                      */
  #define GPIOTE_TASKS_CLR_MaxIndex (7UL)            /*!< Max index of TASKS_CLR[8] array.                                     */
  #define GPIOTE_TASKS_CLR_MinIndex (0UL)            /*!< Min index of TASKS_CLR[8] array.                                     */
  #define GPIOTE_TASKS_CLR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLR[8] register.                                */

/* TASKS_CLR @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
  #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL)       /*!< Position of TASKS_CLR field.                                         */
  #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field.           */
  #define GPIOTE_TASKS_CLR_TASKS_CLR_Min (0x1UL)     /*!< Min enumerator value of TASKS_CLR field.                             */
  #define GPIOTE_TASKS_CLR_TASKS_CLR_Max (0x1UL)     /*!< Max enumerator value of TASKS_CLR field.                             */
  #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task                                                         */


/* GPIOTE_SUBSCRIBE_OUT: Subscribe configuration for task OUT[n] */
  #define GPIOTE_SUBSCRIBE_OUT_MaxCount (8UL)        /*!< Max size of SUBSCRIBE_OUT[8] array.                                  */
  #define GPIOTE_SUBSCRIBE_OUT_MaxIndex (7UL)        /*!< Max index of SUBSCRIBE_OUT[8] array.                                 */
  #define GPIOTE_SUBSCRIBE_OUT_MinIndex (0UL)        /*!< Min index of SUBSCRIBE_OUT[8] array.                                 */
  #define GPIOTE_SUBSCRIBE_OUT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_OUT[8] register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task OUT[n] will subscribe to */
  #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field.                        */
  #define GPIOTE_SUBSCRIBE_OUT_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define GPIOTE_SUBSCRIBE_OUT_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* GPIOTE_SUBSCRIBE_SET: Subscribe configuration for task SET[n] */
  #define GPIOTE_SUBSCRIBE_SET_MaxCount (8UL)        /*!< Max size of SUBSCRIBE_SET[8] array.                                  */
  #define GPIOTE_SUBSCRIBE_SET_MaxIndex (7UL)        /*!< Max index of SUBSCRIBE_SET[8] array.                                 */
  #define GPIOTE_SUBSCRIBE_SET_MinIndex (0UL)        /*!< Min index of SUBSCRIBE_SET[8] array.                                 */
  #define GPIOTE_SUBSCRIBE_SET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SET[8] register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task SET[n] will subscribe to */
  #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define GPIOTE_SUBSCRIBE_SET_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define GPIOTE_SUBSCRIBE_SET_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field.                        */
  #define GPIOTE_SUBSCRIBE_SET_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define GPIOTE_SUBSCRIBE_SET_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* GPIOTE_SUBSCRIBE_CLR: Subscribe configuration for task CLR[n] */
  #define GPIOTE_SUBSCRIBE_CLR_MaxCount (8UL)        /*!< Max size of SUBSCRIBE_CLR[8] array.                                  */
  #define GPIOTE_SUBSCRIBE_CLR_MaxIndex (7UL)        /*!< Max index of SUBSCRIBE_CLR[8] array.                                 */
  #define GPIOTE_SUBSCRIBE_CLR_MinIndex (0UL)        /*!< Min index of SUBSCRIBE_CLR[8] array.                                 */
  #define GPIOTE_SUBSCRIBE_CLR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLR[8] register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task CLR[n] will subscribe to */
  #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field.                        */
  #define GPIOTE_SUBSCRIBE_CLR_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define GPIOTE_SUBSCRIBE_CLR_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* GPIOTE_EVENTS_IN: Event from pin specified in CONFIG[n].PSEL */
  #define GPIOTE_EVENTS_IN_MaxCount (8UL)            /*!< Max size of EVENTS_IN[8] array.                                      */
  #define GPIOTE_EVENTS_IN_MaxIndex (7UL)            /*!< Max index of EVENTS_IN[8] array.                                     */
  #define GPIOTE_EVENTS_IN_MinIndex (0UL)            /*!< Min index of EVENTS_IN[8] array.                                     */
  #define GPIOTE_EVENTS_IN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_IN[8] register.                                */

/* EVENTS_IN @Bit 0 : Event from pin specified in CONFIG[n].PSEL */
  #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL)       /*!< Position of EVENTS_IN field.                                         */
  #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field.           */
  #define GPIOTE_EVENTS_IN_EVENTS_IN_Min (0x0UL)     /*!< Min enumerator value of EVENTS_IN field.                             */
  #define GPIOTE_EVENTS_IN_EVENTS_IN_Max (0x1UL)     /*!< Max enumerator value of EVENTS_IN field.                             */
  #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated                                                    */


/* GPIOTE_PUBLISH_IN: Publish configuration for event IN[n] */
  #define GPIOTE_PUBLISH_IN_MaxCount (8UL)           /*!< Max size of PUBLISH_IN[8] array.                                     */
  #define GPIOTE_PUBLISH_IN_MaxIndex (7UL)           /*!< Max index of PUBLISH_IN[8] array.                                    */
  #define GPIOTE_PUBLISH_IN_MinIndex (0UL)           /*!< Min index of PUBLISH_IN[8] array.                                    */
  #define GPIOTE_PUBLISH_IN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_IN[8] register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event IN[n] will publish to */
  #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define GPIOTE_PUBLISH_IN_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define GPIOTE_PUBLISH_IN_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define GPIOTE_PUBLISH_IN_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field.                              */
  #define GPIOTE_PUBLISH_IN_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define GPIOTE_PUBLISH_IN_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* GPIOTE_INTENSET0: Enable interrupt */
  #define GPIOTE_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register.                                   */

/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
  #define GPIOTE_INTENSET0_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
  #define GPIOTE_INTENSET0_IN0_Msk (0x1UL << GPIOTE_INTENSET0_IN0_Pos) /*!< Bit mask of IN0 field.                             */
  #define GPIOTE_INTENSET0_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENSET0_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENSET0_IN0_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
  #define GPIOTE_INTENSET0_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
  #define GPIOTE_INTENSET0_IN1_Msk (0x1UL << GPIOTE_INTENSET0_IN1_Pos) /*!< Bit mask of IN1 field.                             */
  #define GPIOTE_INTENSET0_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENSET0_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENSET0_IN1_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
  #define GPIOTE_INTENSET0_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
  #define GPIOTE_INTENSET0_IN2_Msk (0x1UL << GPIOTE_INTENSET0_IN2_Pos) /*!< Bit mask of IN2 field.                             */
  #define GPIOTE_INTENSET0_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENSET0_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENSET0_IN2_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
  #define GPIOTE_INTENSET0_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
  #define GPIOTE_INTENSET0_IN3_Msk (0x1UL << GPIOTE_INTENSET0_IN3_Pos) /*!< Bit mask of IN3 field.                             */
  #define GPIOTE_INTENSET0_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENSET0_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENSET0_IN3_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
  #define GPIOTE_INTENSET0_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
  #define GPIOTE_INTENSET0_IN4_Msk (0x1UL << GPIOTE_INTENSET0_IN4_Pos) /*!< Bit mask of IN4 field.                             */
  #define GPIOTE_INTENSET0_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENSET0_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENSET0_IN4_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
  #define GPIOTE_INTENSET0_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
  #define GPIOTE_INTENSET0_IN5_Msk (0x1UL << GPIOTE_INTENSET0_IN5_Pos) /*!< Bit mask of IN5 field.                             */
  #define GPIOTE_INTENSET0_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENSET0_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENSET0_IN5_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
  #define GPIOTE_INTENSET0_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
  #define GPIOTE_INTENSET0_IN6_Msk (0x1UL << GPIOTE_INTENSET0_IN6_Pos) /*!< Bit mask of IN6 field.                             */
  #define GPIOTE_INTENSET0_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENSET0_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENSET0_IN6_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
  #define GPIOTE_INTENSET0_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
  #define GPIOTE_INTENSET0_IN7_Msk (0x1UL << GPIOTE_INTENSET0_IN7_Pos) /*!< Bit mask of IN7 field.                             */
  #define GPIOTE_INTENSET0_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENSET0_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENSET0_IN7_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET0_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
  #define GPIOTE_INTENSET0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
  #define GPIOTE_INTENSET0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
                                                                            field.*/
  #define GPIOTE_INTENSET0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENSET0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENSET0_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
  #define GPIOTE_INTENSET0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
  #define GPIOTE_INTENSET0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */

/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
  #define GPIOTE_INTENSET0_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
  #define GPIOTE_INTENSET0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
  #define GPIOTE_INTENSET0_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENSET0_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENSET0_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
  #define GPIOTE_INTENSET0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GPIOTE_INTENSET0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */


/* GPIOTE_INTENCLR0: Disable interrupt */
  #define GPIOTE_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register.                                   */

/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
  #define GPIOTE_INTENCLR0_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
  #define GPIOTE_INTENCLR0_IN0_Msk (0x1UL << GPIOTE_INTENCLR0_IN0_Pos) /*!< Bit mask of IN0 field.                             */
  #define GPIOTE_INTENCLR0_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENCLR0_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENCLR0_IN0_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
  #define GPIOTE_INTENCLR0_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
  #define GPIOTE_INTENCLR0_IN1_Msk (0x1UL << GPIOTE_INTENCLR0_IN1_Pos) /*!< Bit mask of IN1 field.                             */
  #define GPIOTE_INTENCLR0_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENCLR0_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENCLR0_IN1_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
  #define GPIOTE_INTENCLR0_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
  #define GPIOTE_INTENCLR0_IN2_Msk (0x1UL << GPIOTE_INTENCLR0_IN2_Pos) /*!< Bit mask of IN2 field.                             */
  #define GPIOTE_INTENCLR0_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENCLR0_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENCLR0_IN2_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
  #define GPIOTE_INTENCLR0_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
  #define GPIOTE_INTENCLR0_IN3_Msk (0x1UL << GPIOTE_INTENCLR0_IN3_Pos) /*!< Bit mask of IN3 field.                             */
  #define GPIOTE_INTENCLR0_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENCLR0_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENCLR0_IN3_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
  #define GPIOTE_INTENCLR0_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
  #define GPIOTE_INTENCLR0_IN4_Msk (0x1UL << GPIOTE_INTENCLR0_IN4_Pos) /*!< Bit mask of IN4 field.                             */
  #define GPIOTE_INTENCLR0_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENCLR0_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENCLR0_IN4_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
  #define GPIOTE_INTENCLR0_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
  #define GPIOTE_INTENCLR0_IN5_Msk (0x1UL << GPIOTE_INTENCLR0_IN5_Pos) /*!< Bit mask of IN5 field.                             */
  #define GPIOTE_INTENCLR0_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENCLR0_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENCLR0_IN5_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
  #define GPIOTE_INTENCLR0_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
  #define GPIOTE_INTENCLR0_IN6_Msk (0x1UL << GPIOTE_INTENCLR0_IN6_Pos) /*!< Bit mask of IN6 field.                             */
  #define GPIOTE_INTENCLR0_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENCLR0_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENCLR0_IN6_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
  #define GPIOTE_INTENCLR0_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
  #define GPIOTE_INTENCLR0_IN7_Msk (0x1UL << GPIOTE_INTENCLR0_IN7_Pos) /*!< Bit mask of IN7 field.                             */
  #define GPIOTE_INTENCLR0_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENCLR0_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENCLR0_IN7_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR0_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
  #define GPIOTE_INTENCLR0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
  #define GPIOTE_INTENCLR0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
                                                                            field.*/
  #define GPIOTE_INTENCLR0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENCLR0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENCLR0_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
  #define GPIOTE_INTENCLR0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
  #define GPIOTE_INTENCLR0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */

/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
  #define GPIOTE_INTENCLR0_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
  #define GPIOTE_INTENCLR0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
  #define GPIOTE_INTENCLR0_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENCLR0_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENCLR0_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
  #define GPIOTE_INTENCLR0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GPIOTE_INTENCLR0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */


/* GPIOTE_INTENSET1: Enable interrupt */
  #define GPIOTE_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register.                                   */

/* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
  #define GPIOTE_INTENSET1_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
  #define GPIOTE_INTENSET1_IN0_Msk (0x1UL << GPIOTE_INTENSET1_IN0_Pos) /*!< Bit mask of IN0 field.                             */
  #define GPIOTE_INTENSET1_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENSET1_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENSET1_IN0_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
  #define GPIOTE_INTENSET1_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
  #define GPIOTE_INTENSET1_IN1_Msk (0x1UL << GPIOTE_INTENSET1_IN1_Pos) /*!< Bit mask of IN1 field.                             */
  #define GPIOTE_INTENSET1_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENSET1_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENSET1_IN1_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
  #define GPIOTE_INTENSET1_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
  #define GPIOTE_INTENSET1_IN2_Msk (0x1UL << GPIOTE_INTENSET1_IN2_Pos) /*!< Bit mask of IN2 field.                             */
  #define GPIOTE_INTENSET1_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENSET1_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENSET1_IN2_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
  #define GPIOTE_INTENSET1_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
  #define GPIOTE_INTENSET1_IN3_Msk (0x1UL << GPIOTE_INTENSET1_IN3_Pos) /*!< Bit mask of IN3 field.                             */
  #define GPIOTE_INTENSET1_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENSET1_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENSET1_IN3_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
  #define GPIOTE_INTENSET1_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
  #define GPIOTE_INTENSET1_IN4_Msk (0x1UL << GPIOTE_INTENSET1_IN4_Pos) /*!< Bit mask of IN4 field.                             */
  #define GPIOTE_INTENSET1_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENSET1_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENSET1_IN4_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
  #define GPIOTE_INTENSET1_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
  #define GPIOTE_INTENSET1_IN5_Msk (0x1UL << GPIOTE_INTENSET1_IN5_Pos) /*!< Bit mask of IN5 field.                             */
  #define GPIOTE_INTENSET1_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENSET1_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENSET1_IN5_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
  #define GPIOTE_INTENSET1_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
  #define GPIOTE_INTENSET1_IN6_Msk (0x1UL << GPIOTE_INTENSET1_IN6_Pos) /*!< Bit mask of IN6 field.                             */
  #define GPIOTE_INTENSET1_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENSET1_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENSET1_IN6_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
  #define GPIOTE_INTENSET1_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
  #define GPIOTE_INTENSET1_IN7_Msk (0x1UL << GPIOTE_INTENSET1_IN7_Pos) /*!< Bit mask of IN7 field.                             */
  #define GPIOTE_INTENSET1_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENSET1_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENSET1_IN7_Set (0x1UL)           /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENSET1_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
  #define GPIOTE_INTENSET1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
  #define GPIOTE_INTENSET1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
                                                                            field.*/
  #define GPIOTE_INTENSET1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENSET1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENSET1_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
  #define GPIOTE_INTENSET1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
  #define GPIOTE_INTENSET1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */

/* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
  #define GPIOTE_INTENSET1_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
  #define GPIOTE_INTENSET1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
  #define GPIOTE_INTENSET1_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENSET1_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENSET1_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
  #define GPIOTE_INTENSET1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GPIOTE_INTENSET1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */


/* GPIOTE_INTENCLR1: Disable interrupt */
  #define GPIOTE_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register.                                   */

/* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
  #define GPIOTE_INTENCLR1_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
  #define GPIOTE_INTENCLR1_IN0_Msk (0x1UL << GPIOTE_INTENCLR1_IN0_Pos) /*!< Bit mask of IN0 field.                             */
  #define GPIOTE_INTENCLR1_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENCLR1_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
  #define GPIOTE_INTENCLR1_IN0_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
  #define GPIOTE_INTENCLR1_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
  #define GPIOTE_INTENCLR1_IN1_Msk (0x1UL << GPIOTE_INTENCLR1_IN1_Pos) /*!< Bit mask of IN1 field.                             */
  #define GPIOTE_INTENCLR1_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENCLR1_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
  #define GPIOTE_INTENCLR1_IN1_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
  #define GPIOTE_INTENCLR1_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
  #define GPIOTE_INTENCLR1_IN2_Msk (0x1UL << GPIOTE_INTENCLR1_IN2_Pos) /*!< Bit mask of IN2 field.                             */
  #define GPIOTE_INTENCLR1_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENCLR1_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
  #define GPIOTE_INTENCLR1_IN2_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
  #define GPIOTE_INTENCLR1_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
  #define GPIOTE_INTENCLR1_IN3_Msk (0x1UL << GPIOTE_INTENCLR1_IN3_Pos) /*!< Bit mask of IN3 field.                             */
  #define GPIOTE_INTENCLR1_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENCLR1_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
  #define GPIOTE_INTENCLR1_IN3_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
  #define GPIOTE_INTENCLR1_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
  #define GPIOTE_INTENCLR1_IN4_Msk (0x1UL << GPIOTE_INTENCLR1_IN4_Pos) /*!< Bit mask of IN4 field.                             */
  #define GPIOTE_INTENCLR1_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENCLR1_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
  #define GPIOTE_INTENCLR1_IN4_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
  #define GPIOTE_INTENCLR1_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
  #define GPIOTE_INTENCLR1_IN5_Msk (0x1UL << GPIOTE_INTENCLR1_IN5_Pos) /*!< Bit mask of IN5 field.                             */
  #define GPIOTE_INTENCLR1_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENCLR1_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
  #define GPIOTE_INTENCLR1_IN5_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
  #define GPIOTE_INTENCLR1_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
  #define GPIOTE_INTENCLR1_IN6_Msk (0x1UL << GPIOTE_INTENCLR1_IN6_Pos) /*!< Bit mask of IN6 field.                             */
  #define GPIOTE_INTENCLR1_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENCLR1_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
  #define GPIOTE_INTENCLR1_IN6_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
  #define GPIOTE_INTENCLR1_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
  #define GPIOTE_INTENCLR1_IN7_Msk (0x1UL << GPIOTE_INTENCLR1_IN7_Pos) /*!< Bit mask of IN7 field.                             */
  #define GPIOTE_INTENCLR1_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENCLR1_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
  #define GPIOTE_INTENCLR1_IN7_Clear (0x1UL)         /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define GPIOTE_INTENCLR1_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
  #define GPIOTE_INTENCLR1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
  #define GPIOTE_INTENCLR1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
                                                                            field.*/
  #define GPIOTE_INTENCLR1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENCLR1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
  #define GPIOTE_INTENCLR1_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
  #define GPIOTE_INTENCLR1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
  #define GPIOTE_INTENCLR1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */

/* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
  #define GPIOTE_INTENCLR1_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
  #define GPIOTE_INTENCLR1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
  #define GPIOTE_INTENCLR1_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENCLR1_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
  #define GPIOTE_INTENCLR1_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
  #define GPIOTE_INTENCLR1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GPIOTE_INTENCLR1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */


/* GPIOTE_CONFIG: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
  #define GPIOTE_CONFIG_MaxCount (8UL)               /*!< Max size of CONFIG[8] array.                                         */
  #define GPIOTE_CONFIG_MaxIndex (7UL)               /*!< Max index of CONFIG[8] array.                                        */
  #define GPIOTE_CONFIG_MinIndex (0UL)               /*!< Min index of CONFIG[8] array.                                        */
  #define GPIOTE_CONFIG_ResetValue (0x00000000UL)    /*!< Reset value of CONFIG[8] register.                                   */

/* MODE @Bits 0..1 : Mode */
  #define GPIOTE_CONFIG_MODE_Pos (0UL)               /*!< Position of MODE field.                                              */
  #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field.                                */
  #define GPIOTE_CONFIG_MODE_Min (0x0UL)             /*!< Min enumerator value of MODE field.                                  */
  #define GPIOTE_CONFIG_MODE_Max (0x3UL)             /*!< Max enumerator value of MODE field.                                  */
  #define GPIOTE_CONFIG_MODE_Disabled (0x0UL)        /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE
                                                          module.*/
  #define GPIOTE_CONFIG_MODE_Event (0x1UL)           /*!< Event mode                                                           */
  #define GPIOTE_CONFIG_MODE_Task (0x3UL)            /*!< Task mode                                                            */

/* PSEL @Bits 4..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
  #define GPIOTE_CONFIG_PSEL_Pos (4UL)               /*!< Position of PSEL field.                                              */
  #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field.                               */
  #define GPIOTE_CONFIG_PSEL_Min (0x00UL)            /*!< Min value of PSEL field.                                             */
  #define GPIOTE_CONFIG_PSEL_Max (0x1FUL)            /*!< Max size of PSEL field.                                              */

/* PORT @Bits 9..12 : Port number */
  #define GPIOTE_CONFIG_PORT_Pos (9UL)               /*!< Position of PORT field.                                              */
  #define GPIOTE_CONFIG_PORT_Msk (0xFUL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define GPIOTE_CONFIG_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define GPIOTE_CONFIG_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */

/* POLARITY @Bits 16..17 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event
                           mode: Operation on input that shall trigger IN[n] event. */

  #define GPIOTE_CONFIG_POLARITY_Pos (16UL)          /*!< Position of POLARITY field.                                          */
  #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field.                    */
  #define GPIOTE_CONFIG_POLARITY_Min (0x0UL)         /*!< Min enumerator value of POLARITY field.                              */
  #define GPIOTE_CONFIG_POLARITY_Max (0x3UL)         /*!< Max enumerator value of POLARITY field.                              */
  #define GPIOTE_CONFIG_POLARITY_None (0x0UL)        /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n]
                                                          event generated on pin activity.*/
  #define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL)      /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event
                                                          when rising edge on pin.*/
  #define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL)      /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n]
                                                          event when falling edge on pin.*/
  #define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL)      /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any
                                                          change on pin.*/

/* OUTINIT @Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode:
                     No effect. */

  #define GPIOTE_CONFIG_OUTINIT_Pos (20UL)           /*!< Position of OUTINIT field.                                           */
  #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field.                       */
  #define GPIOTE_CONFIG_OUTINIT_Min (0x0UL)          /*!< Min enumerator value of OUTINIT field.                               */
  #define GPIOTE_CONFIG_OUTINIT_Max (0x1UL)          /*!< Max enumerator value of OUTINIT field.                               */
  #define GPIOTE_CONFIG_OUTINIT_Low (0x0UL)          /*!< Task mode: Initial value of pin before task triggering is low        */
  #define GPIOTE_CONFIG_OUTINIT_High (0x1UL)         /*!< Task mode: Initial value of pin before task triggering is high       */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           GRTC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ===================================================== Struct GRTC_CC ====================================================== */
/**
  * @brief CC [GRTC_CC] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CCL;                               /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n]   */
  __IOM uint32_t  CCH;                               /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n]  */
  __IOM uint32_t  CCADD;                             /*!< (@ 0x00000008) Count to add to CC[n] when this register is written.  */
  __IOM uint32_t  CCEN;                              /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n]              */
} NRF_GRTC_CC_Type;                                  /*!< Size = 16 (0x010)                                                    */
  #define GRTC_CC_MaxCount (12UL)                    /*!< Size of CC[12] array.                                                */
  #define GRTC_CC_MaxIndex (11UL)                    /*!< Max index of CC[12] array.                                           */
  #define GRTC_CC_MinIndex (0UL)                     /*!< Min index of CC[12] array.                                           */

/* GRTC_CC_CCL: The lower 32-bits of Capture/Compare register CC[n] */
  #define GRTC_CC_CCL_ResetValue (0x00000000UL)      /*!< Reset value of CCL register.                                         */

/* CCL @Bits 0..31 : Capture/Compare low value in 1 us */
  #define GRTC_CC_CCL_CCL_Pos (0UL)                  /*!< Position of CCL field.                                               */
  #define GRTC_CC_CCL_CCL_Msk (0xFFFFFFFFUL << GRTC_CC_CCL_CCL_Pos) /*!< Bit mask of CCL field.                                */


/* GRTC_CC_CCH: The higher 32-bits of Capture/Compare register CC[n] */
  #define GRTC_CC_CCH_ResetValue (0x00000000UL)      /*!< Reset value of CCH register.                                         */

/* CCH @Bits 0..19 : Capture/Compare high value in 1 us */
  #define GRTC_CC_CCH_CCH_Pos (0UL)                  /*!< Position of CCH field.                                               */
  #define GRTC_CC_CCH_CCH_Msk (0xFFFFFUL << GRTC_CC_CCH_CCH_Pos) /*!< Bit mask of CCH field.                                   */


/* GRTC_CC_CCADD: Count to add to CC[n] when this register is written. */
  #define GRTC_CC_CCADD_ResetValue (0x00000000UL)    /*!< Reset value of CCADD register.                                       */

/* VALUE @Bits 0..30 : Count to add to CC[n] */
  #define GRTC_CC_CCADD_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
  #define GRTC_CC_CCADD_VALUE_Msk (0x7FFFFFFFUL << GRTC_CC_CCADD_VALUE_Pos) /*!< Bit mask of VALUE field.                      */

/* REFERENCE @Bit 31 : Configure the Capture/Compare register */
  #define GRTC_CC_CCADD_REFERENCE_Pos (31UL)         /*!< Position of REFERENCE field.                                         */
  #define GRTC_CC_CCADD_REFERENCE_Msk (0x1UL << GRTC_CC_CCADD_REFERENCE_Pos) /*!< Bit mask of REFERENCE field.                 */
  #define GRTC_CC_CCADD_REFERENCE_Min (0x0UL)        /*!< Min enumerator value of REFERENCE field.                             */
  #define GRTC_CC_CCADD_REFERENCE_Max (0x1UL)        /*!< Max enumerator value of REFERENCE field.                             */
  #define GRTC_CC_CCADD_REFERENCE_SYSCOUNTER (0x0UL) /*!< Adds SYSCOUNTER value.                                               */
  #define GRTC_CC_CCADD_REFERENCE_CC (0x1UL)         /*!< Adds CC value.                                                       */


/* GRTC_CC_CCEN: Configure Capture/Compare register CC[n] */
  #define GRTC_CC_CCEN_ResetValue (0x00000000UL)     /*!< Reset value of CCEN register.                                        */

/* ACTIVE @Bit 0 : Configure the Capture/Compare register */
  #define GRTC_CC_CCEN_ACTIVE_Pos (0UL)              /*!< Position of ACTIVE field.                                            */
  #define GRTC_CC_CCEN_ACTIVE_Msk (0x1UL << GRTC_CC_CCEN_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.                            */
  #define GRTC_CC_CCEN_ACTIVE_Min (0x0UL)            /*!< Min enumerator value of ACTIVE field.                                */
  #define GRTC_CC_CCEN_ACTIVE_Max (0x1UL)            /*!< Max enumerator value of ACTIVE field.                                */
  #define GRTC_CC_CCEN_ACTIVE_Disable (0x0UL)        /*!< Capture/Compare register CC[n] Disabled.                             */
  #define GRTC_CC_CCEN_ACTIVE_Enable (0x1UL)         /*!< Capture/Compare register CC[n] enabled.                              */



/* =================================================== Struct GRTC_STATUS ==================================================== */
/**
  * @brief STATUS [GRTC_STATUS] (unspecified)
  */
typedef struct {
  __IOM uint32_t  LFTIMER;                           /*!< (@ 0x00000000) Low frequency timer status.                           */
  __IOM uint32_t  PWM;                               /*!< (@ 0x00000004) PWM status.                                           */
  __IOM uint32_t  CLKOUT;                            /*!< (@ 0x00000008) CLKOUT configuration status.                          */
} NRF_GRTC_STATUS_Type;                              /*!< Size = 12 (0x00C)                                                    */

/* GRTC_STATUS_LFTIMER: Low frequency timer status. */
  #define GRTC_STATUS_LFTIMER_ResetValue (0x00000001UL) /*!< Reset value of LFTIMER register.                                  */

/* READY @Bit 0 : Low frequency timer is ready or busy. */
  #define GRTC_STATUS_LFTIMER_READY_Pos (0UL)        /*!< Position of READY field.                                             */
  #define GRTC_STATUS_LFTIMER_READY_Msk (0x1UL << GRTC_STATUS_LFTIMER_READY_Pos) /*!< Bit mask of READY field.                 */
  #define GRTC_STATUS_LFTIMER_READY_Min (0x0UL)      /*!< Min enumerator value of READY field.                                 */
  #define GRTC_STATUS_LFTIMER_READY_Max (0x1UL)      /*!< Max enumerator value of READY field.                                 */
  #define GRTC_STATUS_LFTIMER_READY_Busy (0x0UL)     /*!< Busy                                                                 */
  #define GRTC_STATUS_LFTIMER_READY_Ready (0x1UL)    /*!< Ready                                                                */


/* GRTC_STATUS_PWM: PWM status. */
  #define GRTC_STATUS_PWM_ResetValue (0x00000001UL)  /*!< Reset value of PWM register.                                         */

/* READY @Bit 0 : PWM is ready or busy. */
  #define GRTC_STATUS_PWM_READY_Pos (0UL)            /*!< Position of READY field.                                             */
  #define GRTC_STATUS_PWM_READY_Msk (0x1UL << GRTC_STATUS_PWM_READY_Pos) /*!< Bit mask of READY field.                         */
  #define GRTC_STATUS_PWM_READY_Min (0x0UL)          /*!< Min enumerator value of READY field.                                 */
  #define GRTC_STATUS_PWM_READY_Max (0x1UL)          /*!< Max enumerator value of READY field.                                 */
  #define GRTC_STATUS_PWM_READY_Busy (0x0UL)         /*!< Busy                                                                 */
  #define GRTC_STATUS_PWM_READY_Ready (0x1UL)        /*!< Ready                                                                */


/* GRTC_STATUS_CLKOUT: CLKOUT configuration status. */
  #define GRTC_STATUS_CLKOUT_ResetValue (0x00000001UL) /*!< Reset value of CLKOUT register.                                    */

/* READY @Bit 0 : CLKOUT is ready or busy. */
  #define GRTC_STATUS_CLKOUT_READY_Pos (0UL)         /*!< Position of READY field.                                             */
  #define GRTC_STATUS_CLKOUT_READY_Msk (0x1UL << GRTC_STATUS_CLKOUT_READY_Pos) /*!< Bit mask of READY field.                   */
  #define GRTC_STATUS_CLKOUT_READY_Min (0x0UL)       /*!< Min enumerator value of READY field.                                 */
  #define GRTC_STATUS_CLKOUT_READY_Max (0x1UL)       /*!< Max enumerator value of READY field.                                 */
  #define GRTC_STATUS_CLKOUT_READY_Busy (0x0UL)      /*!< Busy                                                                 */
  #define GRTC_STATUS_CLKOUT_READY_Ready (0x1UL)     /*!< Ready                                                                */



/* ================================================= Struct GRTC_SYSCOUNTER ================================================== */
/**
  * @brief SYSCOUNTER [GRTC_SYSCOUNTER] (unspecified)
  */
typedef struct {
  __IM  uint32_t  SYSCOUNTERL;                       /*!< (@ 0x00000000) The lower 32-bits of the SYSCOUNTER for index [n]     */
  __IM  uint32_t  SYSCOUNTERH;                       /*!< (@ 0x00000004) The higher 20-bits of the SYSCOUNTER for index [n]    */
  __IOM uint32_t  ACTIVE;                            /*!< (@ 0x00000008) Request to keep the SYSCOUNTER in the active state and
                                                                         prevent going to sleep for index [n]*/
  __IM  uint32_t  RESERVED;
} NRF_GRTC_SYSCOUNTER_Type;                          /*!< Size = 16 (0x010)                                                    */
  #define GRTC_SYSCOUNTER_MaxCount (4UL)             /*!< Size of SYSCOUNTER[4] array.                                         */
  #define GRTC_SYSCOUNTER_MaxIndex (3UL)             /*!< Max index of SYSCOUNTER[4] array.                                    */
  #define GRTC_SYSCOUNTER_MinIndex (0UL)             /*!< Min index of SYSCOUNTER[4] array.                                    */

/* GRTC_SYSCOUNTER_SYSCOUNTERL: The lower 32-bits of the SYSCOUNTER for index [n] */
  #define GRTC_SYSCOUNTER_SYSCOUNTERL_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTERL register.                      */

/* VALUE @Bits 0..31 : The lower 32-bits of the SYSCOUNTER value. */
  #define GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                            */
  #define GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Msk (0xFFFFFFFFUL << GRTC_SYSCOUNTER_SYSCOUNTERL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/


/* GRTC_SYSCOUNTER_SYSCOUNTERH: The higher 20-bits of the SYSCOUNTER for index [n] */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_ResetValue (0x40000000UL) /*!< Reset value of SYSCOUNTERH register.                      */

/* VALUE @Bits 0..19 : The higher 20-bits of the SYSCOUNTER value. */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Pos (0UL) /*!< Position of VALUE field.                                            */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Msk (0xFFFFFUL << GRTC_SYSCOUNTER_SYSCOUNTERH_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/

/* BUSY @Bit 30 : SYSCOUNTER busy status */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos (30UL) /*!< Position of BUSY field.                                             */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Msk (0x1UL << GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Pos) /*!< Bit mask of BUSY field.    */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field.                                */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field.                                */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Ready (0x0UL) /*!< SYSCOUNTER is ready for read                                     */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_BUSY_Busy (0x1UL) /*!< SYSCOUNTER is busy, so not ready for read (value returned in the
                                                             VALUE field of this register is not valid)*/

/* OVERFLOW @Bit 31 : The SYSCOUNTERL overflow indication after reading it. */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Pos (31UL) /*!< Position of OVERFLOW field.                                     */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Msk (0x1UL << GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW
                                                                            field.*/
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Min (0x0UL) /*!< Min enumerator value of OVERFLOW field.                        */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Max (0x1UL) /*!< Max enumerator value of OVERFLOW field.                        */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_NoOverflow (0x0UL) /*!< SYSCOUNTERL is not overflown                            */
  #define GRTC_SYSCOUNTER_SYSCOUNTERH_OVERFLOW_Overflow (0x1UL) /*!< SYSCOUNTERL overflown                                     */


/* GRTC_SYSCOUNTER_ACTIVE: Request to keep the SYSCOUNTER in the active state and prevent going to sleep for index [n] */
  #define GRTC_SYSCOUNTER_ACTIVE_ResetValue (0x00000000UL) /*!< Reset value of ACTIVE register.                                */

/* ACTIVE @Bit 0 : Keep SYSCOUNTER in active state */
  #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Pos (0UL)    /*!< Position of ACTIVE field.                                            */
  #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Msk (0x1UL << GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.        */
  #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Min (0x0UL)  /*!< Min enumerator value of ACTIVE field.                                */
  #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Max (0x1UL)  /*!< Max enumerator value of ACTIVE field.                                */
  #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                 */
  #define GRTC_SYSCOUNTER_ACTIVE_ACTIVE_Active (0x1UL) /*!< Keep SYSCOUNTER active                                             */


/* ======================================================= Struct GRTC ======================================================= */
/**
  * @brief Global Real-time counter
  */
  typedef struct {                                   /*!< GRTC Structure                                                       */
    __OM uint32_t TASKS_CAPTURE[12];                 /*!< (@ 0x00000000) Capture the counter value to CC[n] register           */
    __IM uint32_t RESERVED[12];
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000060) Start the counter                                     */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000064) Stop the counter                                      */
    __OM uint32_t TASKS_CLEAR;                       /*!< (@ 0x00000068) Clear the counter                                     */
    __OM uint32_t TASKS_PWMSTART;                    /*!< (@ 0x0000006C) Start the PWM                                         */
    __OM uint32_t TASKS_PWMSTOP;                     /*!< (@ 0x00000070) Stop the PWM                                          */
    __IM uint32_t RESERVED1[3];
    __IOM uint32_t SUBSCRIBE_CAPTURE[12];            /*!< (@ 0x00000080) Subscribe configuration for task CAPTURE[n]           */
    __IM uint32_t RESERVED2[20];
    __IOM uint32_t EVENTS_COMPARE[12];               /*!< (@ 0x00000100) Compare event on CC[n] match                          */
    __IM uint32_t RESERVED3[13];
    __IOM uint32_t EVENTS_RTCOMPARESYNC;             /*!< (@ 0x00000164) The GRTC low frequency timer is synchronized with the
                                                                         SYSCOUNTER*/
    __IM uint32_t RESERVED4;
    __IOM uint32_t EVENTS_PWMPERIODEND;              /*!< (@ 0x0000016C) Event on end of each PWM period                       */
    __IM uint32_t RESERVED5;
    __IOM uint32_t EVENTS_PWMREADY;                  /*!< (@ 0x00000174) Event on STATUS.PWM.READY status changed to ready     */
    __IOM uint32_t EVENTS_CLKOUTREADY;               /*!< (@ 0x00000178) Event on STATUS.CLKOUT.READY status changed to ready  */
    __IM uint32_t RESERVED6;
    __IOM uint32_t PUBLISH_COMPARE[12];              /*!< (@ 0x00000180) Publish configuration for event COMPARE[n]            */
    __IM uint32_t RESERVED7[17];
    __IOM uint32_t PUBLISH_PWMREADY;                 /*!< (@ 0x000001F4) Publish configuration for event PWMREADY              */
    __IOM uint32_t PUBLISH_CLKOUTREADY;              /*!< (@ 0x000001F8) Publish configuration for event CLKOUTREADY           */
    __IM uint32_t RESERVED8;
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED9[63];
    __IOM uint32_t INTEN0;                           /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET0;                        /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR0;                        /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND0;                          /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IOM uint32_t INTEN1;                           /*!< (@ 0x00000310) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET1;                        /*!< (@ 0x00000314) Enable interrupt                                      */
    __IOM uint32_t INTENCLR1;                        /*!< (@ 0x00000318) Disable interrupt                                     */
    __IM uint32_t INTPEND1;                          /*!< (@ 0x0000031C) Pending interrupts                                    */
    __IOM uint32_t INTEN2;                           /*!< (@ 0x00000320) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET2;                        /*!< (@ 0x00000324) Enable interrupt                                      */
    __IOM uint32_t INTENCLR2;                        /*!< (@ 0x00000328) Disable interrupt                                     */
    __IM uint32_t INTPEND2;                          /*!< (@ 0x0000032C) Pending interrupts                                    */
    __IOM uint32_t INTEN3;                           /*!< (@ 0x00000330) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET3;                        /*!< (@ 0x00000334) Enable interrupt                                      */
    __IOM uint32_t INTENCLR3;                        /*!< (@ 0x00000338) Disable interrupt                                     */
    __IM uint32_t INTPEND3;                          /*!< (@ 0x0000033C) Pending interrupts                                    */
    __IM uint32_t RESERVED10[48];
    __IOM uint32_t EVTEN;                            /*!< (@ 0x00000400) Enable or disable event routing                       */
    __IOM uint32_t EVTENSET;                         /*!< (@ 0x00000404) Enable event routing                                  */
    __IOM uint32_t EVTENCLR;                         /*!< (@ 0x00000408) Disable event routing                                 */
    __IM uint32_t RESERVED11[65];
    __IOM uint32_t MODE;                             /*!< (@ 0x00000510) Counter mode selection                                */
    __IM uint32_t RESERVED12[3];
    __IOM NRF_GRTC_CC_Type CC[12];                   /*!< (@ 0x00000520) (unspecified)                                         */
    __IM uint32_t RESERVED13[49];
    __IOM uint32_t TIMEOUT;                          /*!< (@ 0x000006A4) Timeout after all CPUs gone into sleep state to stop
                                                                         the SYSCOUNTER*/
    __IOM uint32_t INTERVAL;                         /*!< (@ 0x000006A8) Count to add to CC[0] when the event EVENTS_COMPARE[0]
                                                                         triggers.*/
    __IOM uint32_t WAKETIME;                         /*!< (@ 0x000006AC) GRTC wake up time.                                    */
    __IOM NRF_GRTC_STATUS_Type STATUS;               /*!< (@ 0x000006B0) (unspecified)                                         */
    __IM uint32_t RESERVED14[21];
    __IOM uint32_t PWMCONFIG;                        /*!< (@ 0x00000710) PWM configuration.                                    */
    __IOM uint32_t CLKOUT;                           /*!< (@ 0x00000714) Configuration of clock output                         */
    __IOM uint32_t CLKCFG;                           /*!< (@ 0x00000718) Clock Configuration                                   */
    __IM uint32_t RESERVED15;
    __IOM NRF_GRTC_SYSCOUNTER_Type SYSCOUNTER[4];    /*!< (@ 0x00000720) (unspecified)                                         */
  } NRF_GRTC_Type;                                   /*!< Size = 1888 (0x760)                                                  */

/* GRTC_TASKS_CAPTURE: Capture the counter value to CC[n] register */
  #define GRTC_TASKS_CAPTURE_MaxCount (12UL)         /*!< Max size of TASKS_CAPTURE[12] array.                                 */
  #define GRTC_TASKS_CAPTURE_MaxIndex (11UL)         /*!< Max index of TASKS_CAPTURE[12] array.                                */
  #define GRTC_TASKS_CAPTURE_MinIndex (0UL)          /*!< Min index of TASKS_CAPTURE[12] array.                                */
  #define GRTC_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[12] register.                         */

/* TASKS_CAPTURE @Bit 0 : Capture the counter value to CC[n] register */
  #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field.                                     */
  #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE
                                                                            field.*/
  #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field.                       */
  #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field.                       */
  #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task                                                   */


/* GRTC_TASKS_START: Start the counter */
  #define GRTC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start the counter */
  #define GRTC_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
  #define GRTC_TASKS_START_TASKS_START_Msk (0x1UL << GRTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
  #define GRTC_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
  #define GRTC_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
  #define GRTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */


/* GRTC_TASKS_STOP: Stop the counter */
  #define GRTC_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop the counter */
  #define GRTC_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
  #define GRTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << GRTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
  #define GRTC_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
  #define GRTC_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
  #define GRTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */


/* GRTC_TASKS_CLEAR: Clear the counter */
  #define GRTC_TASKS_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEAR register.                                 */

/* TASKS_CLEAR @Bit 0 : Clear the counter */
  #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)     /*!< Position of TASKS_CLEAR field.                                       */
  #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << GRTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field.     */
  #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL)   /*!< Min enumerator value of TASKS_CLEAR field.                           */
  #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL)   /*!< Max enumerator value of TASKS_CLEAR field.                           */
  #define GRTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task                                                       */


/* GRTC_TASKS_PWMSTART: Start the PWM */
  #define GRTC_TASKS_PWMSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PWMSTART register.                           */

/* TASKS_PWMSTART @Bit 0 : Start the PWM */
  #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Pos (0UL) /*!< Position of TASKS_PWMSTART field.                                  */
  #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Msk (0x1UL << GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Pos) /*!< Bit mask of
                                                                            TASKS_PWMSTART field.*/
  #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_PWMSTART field.                    */
  #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_PWMSTART field.                    */
  #define GRTC_TASKS_PWMSTART_TASKS_PWMSTART_Trigger (0x1UL) /*!< Trigger task                                                 */


/* GRTC_TASKS_PWMSTOP: Stop the PWM */
  #define GRTC_TASKS_PWMSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PWMSTOP register.                             */

/* TASKS_PWMSTOP @Bit 0 : Stop the PWM */
  #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Pos (0UL) /*!< Position of TASKS_PWMSTOP field.                                     */
  #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Msk (0x1UL << GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Pos) /*!< Bit mask of TASKS_PWMSTOP
                                                                            field.*/
  #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_PWMSTOP field.                       */
  #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_PWMSTOP field.                       */
  #define GRTC_TASKS_PWMSTOP_TASKS_PWMSTOP_Trigger (0x1UL) /*!< Trigger task                                                   */


/* GRTC_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */
  #define GRTC_SUBSCRIBE_CAPTURE_MaxCount (12UL)     /*!< Max size of SUBSCRIBE_CAPTURE[12] array.                             */
  #define GRTC_SUBSCRIBE_CAPTURE_MaxIndex (11UL)     /*!< Max index of SUBSCRIBE_CAPTURE[12] array.                            */
  #define GRTC_SUBSCRIBE_CAPTURE_MinIndex (0UL)      /*!< Min index of SUBSCRIBE_CAPTURE[12] array.                            */
  #define GRTC_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[12] register.                 */

/* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */
  #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define GRTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define GRTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << GRTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field.                    */
  #define GRTC_SUBSCRIBE_CAPTURE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define GRTC_SUBSCRIBE_CAPTURE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define GRTC_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define GRTC_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* GRTC_EVENTS_COMPARE: Compare event on CC[n] match */
  #define GRTC_EVENTS_COMPARE_MaxCount (12UL)        /*!< Max size of EVENTS_COMPARE[12] array.                                */
  #define GRTC_EVENTS_COMPARE_MaxIndex (11UL)        /*!< Max index of EVENTS_COMPARE[12] array.                               */
  #define GRTC_EVENTS_COMPARE_MinIndex (0UL)         /*!< Min index of EVENTS_COMPARE[12] array.                               */
  #define GRTC_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[12] register.                       */

/* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */
  #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field.                                  */
  #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of
                                                                            EVENTS_COMPARE field.*/
  #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field.                    */
  #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field.                    */
  #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated                                            */


/* GRTC_EVENTS_RTCOMPARESYNC: The GRTC low frequency timer is synchronized with the SYSCOUNTER */
  #define GRTC_EVENTS_RTCOMPARESYNC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RTCOMPARESYNC register.               */

/* EVENTS_RTCOMPARESYNC @Bit 0 : The GRTC low frequency timer is synchronized with the SYSCOUNTER */
  #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Pos (0UL) /*!< Position of EVENTS_RTCOMPARESYNC field.                */
  #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Msk (0x1UL << GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Pos) /*!<
                                                                            Bit mask of EVENTS_RTCOMPARESYNC field.*/
  #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Min (0x0UL) /*!< Min enumerator value of EVENTS_RTCOMPARESYNC field.  */
  #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Max (0x1UL) /*!< Max enumerator value of EVENTS_RTCOMPARESYNC field.  */
  #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_NotGenerated (0x0UL) /*!< Event not generated                         */
  #define GRTC_EVENTS_RTCOMPARESYNC_EVENTS_RTCOMPARESYNC_Generated (0x1UL) /*!< Event generated                                */


/* GRTC_EVENTS_PWMPERIODEND: Event on end of each PWM period */
  #define GRTC_EVENTS_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMPERIODEND register.                 */

/* EVENTS_PWMPERIODEND @Bit 0 : Event on end of each PWM period */
  #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field.                   */
  #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit
                                                                            mask of EVENTS_PWMPERIODEND field.*/
  #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMPERIODEND field.     */
  #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMPERIODEND field.     */
  #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated                           */
  #define GRTC_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated                                  */


/* GRTC_EVENTS_PWMREADY: Event on STATUS.PWM.READY status changed to ready */
  #define GRTC_EVENTS_PWMREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMREADY register.                         */

/* EVENTS_PWMREADY @Bit 0 : Event on STATUS.PWM.READY status changed to ready */
  #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Pos (0UL) /*!< Position of EVENTS_PWMREADY field.                               */
  #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Msk (0x1UL << GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Pos) /*!< Bit mask of
                                                                            EVENTS_PWMREADY field.*/
  #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMREADY field.                 */
  #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMREADY field.                 */
  #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define GRTC_EVENTS_PWMREADY_EVENTS_PWMREADY_Generated (0x1UL) /*!< Event generated                                          */


/* GRTC_EVENTS_CLKOUTREADY: Event on STATUS.CLKOUT.READY status changed to ready */
  #define GRTC_EVENTS_CLKOUTREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CLKOUTREADY register.                   */

/* EVENTS_CLKOUTREADY @Bit 0 : Event on STATUS.CLKOUT.READY status changed to ready */
  #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Pos (0UL) /*!< Position of EVENTS_CLKOUTREADY field.                      */
  #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Msk (0x1UL << GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Pos) /*!< Bit mask
                                                                            of EVENTS_CLKOUTREADY field.*/
  #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_CLKOUTREADY field.        */
  #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_CLKOUTREADY field.        */
  #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_NotGenerated (0x0UL) /*!< Event not generated                             */
  #define GRTC_EVENTS_CLKOUTREADY_EVENTS_CLKOUTREADY_Generated (0x1UL) /*!< Event generated                                    */


/* GRTC_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */
  #define GRTC_PUBLISH_COMPARE_MaxCount (12UL)       /*!< Max size of PUBLISH_COMPARE[12] array.                               */
  #define GRTC_PUBLISH_COMPARE_MaxIndex (11UL)       /*!< Max index of PUBLISH_COMPARE[12] array.                              */
  #define GRTC_PUBLISH_COMPARE_MinIndex (0UL)        /*!< Min index of PUBLISH_COMPARE[12] array.                              */
  #define GRTC_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[12] register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */
  #define GRTC_PUBLISH_COMPARE_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define GRTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define GRTC_PUBLISH_COMPARE_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define GRTC_PUBLISH_COMPARE_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define GRTC_PUBLISH_COMPARE_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define GRTC_PUBLISH_COMPARE_EN_Msk (0x1UL << GRTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field.                        */
  #define GRTC_PUBLISH_COMPARE_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define GRTC_PUBLISH_COMPARE_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define GRTC_PUBLISH_COMPARE_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define GRTC_PUBLISH_COMPARE_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* GRTC_PUBLISH_PWMREADY: Publish configuration for event PWMREADY */
  #define GRTC_PUBLISH_PWMREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PWMREADY register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that event PWMREADY will publish to */
  #define GRTC_PUBLISH_PWMREADY_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define GRTC_PUBLISH_PWMREADY_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_PWMREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define GRTC_PUBLISH_PWMREADY_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define GRTC_PUBLISH_PWMREADY_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define GRTC_PUBLISH_PWMREADY_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define GRTC_PUBLISH_PWMREADY_EN_Msk (0x1UL << GRTC_PUBLISH_PWMREADY_EN_Pos) /*!< Bit mask of EN field.                      */
  #define GRTC_PUBLISH_PWMREADY_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define GRTC_PUBLISH_PWMREADY_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define GRTC_PUBLISH_PWMREADY_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define GRTC_PUBLISH_PWMREADY_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* GRTC_PUBLISH_CLKOUTREADY: Publish configuration for event CLKOUTREADY */
  #define GRTC_PUBLISH_CLKOUTREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CLKOUTREADY register.                 */

/* CHIDX @Bits 0..7 : DPPI channel that event CLKOUTREADY will publish to */
  #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_CLKOUTREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define GRTC_PUBLISH_CLKOUTREADY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define GRTC_PUBLISH_CLKOUTREADY_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define GRTC_PUBLISH_CLKOUTREADY_EN_Msk (0x1UL << GRTC_PUBLISH_CLKOUTREADY_EN_Pos) /*!< Bit mask of EN field.                */
  #define GRTC_PUBLISH_CLKOUTREADY_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define GRTC_PUBLISH_CLKOUTREADY_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define GRTC_PUBLISH_CLKOUTREADY_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define GRTC_PUBLISH_CLKOUTREADY_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* GRTC_SHORTS: Shortcuts between local events and tasks */
  #define GRTC_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* RTCOMPARE_CLEAR @Bit 0 : Shortcut between event RTCOMPARE and task CLEAR */
  #define GRTC_SHORTS_RTCOMPARE_CLEAR_Pos (0UL)      /*!< Position of RTCOMPARE_CLEAR field.                                   */
  #define GRTC_SHORTS_RTCOMPARE_CLEAR_Msk (0x1UL << GRTC_SHORTS_RTCOMPARE_CLEAR_Pos) /*!< Bit mask of RTCOMPARE_CLEAR field.   */
  #define GRTC_SHORTS_RTCOMPARE_CLEAR_Min (0x0UL)    /*!< Min enumerator value of RTCOMPARE_CLEAR field.                       */
  #define GRTC_SHORTS_RTCOMPARE_CLEAR_Max (0x1UL)    /*!< Max enumerator value of RTCOMPARE_CLEAR field.                       */
  #define GRTC_SHORTS_RTCOMPARE_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define GRTC_SHORTS_RTCOMPARE_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */


/* GRTC_INTEN0: Enable or disable interrupt */
  #define GRTC_INTEN0_ResetValue (0x00000000UL)      /*!< Reset value of INTEN0 register.                                      */

/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
  #define GRTC_INTEN0_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTEN0_COMPARE0_Msk (0x1UL << GRTC_INTEN0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
  #define GRTC_INTEN0_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN0_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN0_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
  #define GRTC_INTEN0_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTEN0_COMPARE1_Msk (0x1UL << GRTC_INTEN0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
  #define GRTC_INTEN0_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN0_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN0_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
  #define GRTC_INTEN0_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTEN0_COMPARE2_Msk (0x1UL << GRTC_INTEN0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
  #define GRTC_INTEN0_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN0_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN0_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
  #define GRTC_INTEN0_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTEN0_COMPARE3_Msk (0x1UL << GRTC_INTEN0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
  #define GRTC_INTEN0_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN0_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN0_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
  #define GRTC_INTEN0_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTEN0_COMPARE4_Msk (0x1UL << GRTC_INTEN0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
  #define GRTC_INTEN0_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN0_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN0_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
  #define GRTC_INTEN0_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTEN0_COMPARE5_Msk (0x1UL << GRTC_INTEN0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
  #define GRTC_INTEN0_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN0_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN0_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
  #define GRTC_INTEN0_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTEN0_COMPARE6_Msk (0x1UL << GRTC_INTEN0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
  #define GRTC_INTEN0_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN0_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN0_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
  #define GRTC_INTEN0_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTEN0_COMPARE7_Msk (0x1UL << GRTC_INTEN0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
  #define GRTC_INTEN0_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN0_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN0_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
  #define GRTC_INTEN0_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTEN0_COMPARE8_Msk (0x1UL << GRTC_INTEN0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
  #define GRTC_INTEN0_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN0_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN0_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
  #define GRTC_INTEN0_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTEN0_COMPARE9_Msk (0x1UL << GRTC_INTEN0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
  #define GRTC_INTEN0_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN0_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN0_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
  #define GRTC_INTEN0_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTEN0_COMPARE10_Msk (0x1UL << GRTC_INTEN0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
  #define GRTC_INTEN0_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN0_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN0_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */

/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
  #define GRTC_INTEN0_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTEN0_COMPARE11_Msk (0x1UL << GRTC_INTEN0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
  #define GRTC_INTEN0_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN0_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN0_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN0_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */

/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTEN0_RTCOMPARESYNC_Pos (25UL)       /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTEN0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.         */
  #define GRTC_INTEN0_RTCOMPARESYNC_Min (0x0UL)      /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN0_RTCOMPARESYNC_Max (0x1UL)      /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable                                                              */
  #define GRTC_INTEN0_RTCOMPARESYNC_Enabled (0x1UL)  /*!< Enable                                                               */

/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */
  #define GRTC_INTEN0_PWMPERIODEND_Pos (27UL)        /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTEN0_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.            */
  #define GRTC_INTEN0_PWMPERIODEND_Min (0x0UL)       /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN0_PWMPERIODEND_Max (0x1UL)       /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN0_PWMPERIODEND_Disabled (0x0UL)  /*!< Disable                                                              */
  #define GRTC_INTEN0_PWMPERIODEND_Enabled (0x1UL)   /*!< Enable                                                               */

/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */
  #define GRTC_INTEN0_PWMREADY_Pos (29UL)            /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTEN0_PWMREADY_Msk (0x1UL << GRTC_INTEN0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                        */
  #define GRTC_INTEN0_PWMREADY_Min (0x0UL)           /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN0_PWMREADY_Max (0x1UL)           /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN0_PWMREADY_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN0_PWMREADY_Enabled (0x1UL)       /*!< Enable                                                               */

/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */
  #define GRTC_INTEN0_CLKOUTREADY_Pos (30UL)         /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTEN0_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.               */
  #define GRTC_INTEN0_CLKOUTREADY_Min (0x0UL)        /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN0_CLKOUTREADY_Max (0x1UL)        /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN0_CLKOUTREADY_Disabled (0x0UL)   /*!< Disable                                                              */
  #define GRTC_INTEN0_CLKOUTREADY_Enabled (0x1UL)    /*!< Enable                                                               */


/* GRTC_INTENSET0: Enable interrupt */
  #define GRTC_INTENSET0_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET0 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
  #define GRTC_INTENSET0_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENSET0_COMPARE0_Msk (0x1UL << GRTC_INTENSET0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENSET0_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET0_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET0_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
  #define GRTC_INTENSET0_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENSET0_COMPARE1_Msk (0x1UL << GRTC_INTENSET0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENSET0_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET0_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET0_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
  #define GRTC_INTENSET0_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENSET0_COMPARE2_Msk (0x1UL << GRTC_INTENSET0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENSET0_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET0_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET0_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
  #define GRTC_INTENSET0_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENSET0_COMPARE3_Msk (0x1UL << GRTC_INTENSET0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENSET0_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET0_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET0_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
  #define GRTC_INTENSET0_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENSET0_COMPARE4_Msk (0x1UL << GRTC_INTENSET0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENSET0_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET0_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET0_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
  #define GRTC_INTENSET0_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENSET0_COMPARE5_Msk (0x1UL << GRTC_INTENSET0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENSET0_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET0_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET0_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
  #define GRTC_INTENSET0_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENSET0_COMPARE6_Msk (0x1UL << GRTC_INTENSET0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENSET0_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET0_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET0_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
  #define GRTC_INTENSET0_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENSET0_COMPARE7_Msk (0x1UL << GRTC_INTENSET0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENSET0_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET0_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET0_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
  #define GRTC_INTENSET0_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENSET0_COMPARE8_Msk (0x1UL << GRTC_INTENSET0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENSET0_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET0_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET0_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
  #define GRTC_INTENSET0_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENSET0_COMPARE9_Msk (0x1UL << GRTC_INTENSET0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENSET0_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET0_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET0_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
  #define GRTC_INTENSET0_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENSET0_COMPARE10_Msk (0x1UL << GRTC_INTENSET0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENSET0_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET0_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET0_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
  #define GRTC_INTENSET0_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENSET0_COMPARE11_Msk (0x1UL << GRTC_INTENSET0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENSET0_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET0_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET0_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET0_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENSET0_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENSET0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENSET0_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET0_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET0_RTCOMPARESYNC_Set (0x1UL)   /*!< Enable                                                               */
  #define GRTC_INTENSET0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENSET0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */
  #define GRTC_INTENSET0_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENSET0_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENSET0_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET0_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET0_PWMPERIODEND_Set (0x1UL)    /*!< Enable                                                               */
  #define GRTC_INTENSET0_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENSET0_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */
  #define GRTC_INTENSET0_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENSET0_PWMREADY_Msk (0x1UL << GRTC_INTENSET0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENSET0_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET0_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET0_PWMREADY_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET0_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET0_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */
  #define GRTC_INTENSET0_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENSET0_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENSET0_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET0_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET0_CLKOUTREADY_Set (0x1UL)     /*!< Enable                                                               */
  #define GRTC_INTENSET0_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENSET0_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTENCLR0: Disable interrupt */
  #define GRTC_INTENCLR0_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR0 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
  #define GRTC_INTENCLR0_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENCLR0_COMPARE0_Msk (0x1UL << GRTC_INTENCLR0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENCLR0_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR0_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR0_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
  #define GRTC_INTENCLR0_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENCLR0_COMPARE1_Msk (0x1UL << GRTC_INTENCLR0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENCLR0_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR0_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR0_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
  #define GRTC_INTENCLR0_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENCLR0_COMPARE2_Msk (0x1UL << GRTC_INTENCLR0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENCLR0_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR0_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR0_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
  #define GRTC_INTENCLR0_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENCLR0_COMPARE3_Msk (0x1UL << GRTC_INTENCLR0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENCLR0_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR0_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR0_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
  #define GRTC_INTENCLR0_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENCLR0_COMPARE4_Msk (0x1UL << GRTC_INTENCLR0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENCLR0_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR0_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR0_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
  #define GRTC_INTENCLR0_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENCLR0_COMPARE5_Msk (0x1UL << GRTC_INTENCLR0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENCLR0_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR0_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR0_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
  #define GRTC_INTENCLR0_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENCLR0_COMPARE6_Msk (0x1UL << GRTC_INTENCLR0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENCLR0_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR0_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR0_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
  #define GRTC_INTENCLR0_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENCLR0_COMPARE7_Msk (0x1UL << GRTC_INTENCLR0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENCLR0_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR0_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR0_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
  #define GRTC_INTENCLR0_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENCLR0_COMPARE8_Msk (0x1UL << GRTC_INTENCLR0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENCLR0_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR0_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR0_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
  #define GRTC_INTENCLR0_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENCLR0_COMPARE9_Msk (0x1UL << GRTC_INTENCLR0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENCLR0_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR0_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR0_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
  #define GRTC_INTENCLR0_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENCLR0_COMPARE10_Msk (0x1UL << GRTC_INTENCLR0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENCLR0_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR0_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR0_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
  #define GRTC_INTENCLR0_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENCLR0_COMPARE11_Msk (0x1UL << GRTC_INTENCLR0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENCLR0_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR0_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR0_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR0_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENCLR0_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENCLR0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENCLR0_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR0_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR0_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable                                                              */
  #define GRTC_INTENCLR0_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENCLR0_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */
  #define GRTC_INTENCLR0_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENCLR0_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENCLR0_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR0_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR0_PWMPERIODEND_Clear (0x1UL)  /*!< Disable                                                              */
  #define GRTC_INTENCLR0_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENCLR0_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */
  #define GRTC_INTENCLR0_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENCLR0_PWMREADY_Msk (0x1UL << GRTC_INTENCLR0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENCLR0_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR0_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR0_PWMREADY_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR0_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR0_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */
  #define GRTC_INTENCLR0_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENCLR0_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENCLR0_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR0_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR0_CLKOUTREADY_Clear (0x1UL)   /*!< Disable                                                              */
  #define GRTC_INTENCLR0_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENCLR0_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTPEND0: Pending interrupts */
  #define GRTC_INTPEND0_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND0 register.                                    */

/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
  #define GRTC_INTPEND0_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTPEND0_COMPARE0_Msk (0x1UL << GRTC_INTPEND0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
  #define GRTC_INTPEND0_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND0_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND0_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
  #define GRTC_INTPEND0_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTPEND0_COMPARE1_Msk (0x1UL << GRTC_INTPEND0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
  #define GRTC_INTPEND0_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND0_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND0_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
  #define GRTC_INTPEND0_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTPEND0_COMPARE2_Msk (0x1UL << GRTC_INTPEND0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
  #define GRTC_INTPEND0_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND0_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND0_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
  #define GRTC_INTPEND0_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTPEND0_COMPARE3_Msk (0x1UL << GRTC_INTPEND0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
  #define GRTC_INTPEND0_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND0_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND0_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
  #define GRTC_INTPEND0_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTPEND0_COMPARE4_Msk (0x1UL << GRTC_INTPEND0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
  #define GRTC_INTPEND0_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND0_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND0_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
  #define GRTC_INTPEND0_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTPEND0_COMPARE5_Msk (0x1UL << GRTC_INTPEND0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
  #define GRTC_INTPEND0_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND0_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND0_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
  #define GRTC_INTPEND0_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTPEND0_COMPARE6_Msk (0x1UL << GRTC_INTPEND0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
  #define GRTC_INTPEND0_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND0_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND0_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
  #define GRTC_INTPEND0_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTPEND0_COMPARE7_Msk (0x1UL << GRTC_INTPEND0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
  #define GRTC_INTPEND0_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND0_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND0_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
  #define GRTC_INTPEND0_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTPEND0_COMPARE8_Msk (0x1UL << GRTC_INTPEND0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
  #define GRTC_INTPEND0_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND0_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND0_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
  #define GRTC_INTPEND0_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTPEND0_COMPARE9_Msk (0x1UL << GRTC_INTPEND0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
  #define GRTC_INTPEND0_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND0_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND0_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
  #define GRTC_INTPEND0_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTPEND0_COMPARE10_Msk (0x1UL << GRTC_INTPEND0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
  #define GRTC_INTPEND0_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND0_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND0_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
  #define GRTC_INTPEND0_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTPEND0_COMPARE11_Msk (0x1UL << GRTC_INTPEND0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
  #define GRTC_INTPEND0_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND0_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND0_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */
  #define GRTC_INTPEND0_RTCOMPARESYNC_Pos (25UL)     /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTPEND0_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND0_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.     */
  #define GRTC_INTPEND0_RTCOMPARESYNC_Min (0x0UL)    /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND0_RTCOMPARESYNC_Max (0x1UL)    /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND0_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending                                                */
  #define GRTC_INTPEND0_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending                                                       */

/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */
  #define GRTC_INTPEND0_PWMPERIODEND_Pos (27UL)      /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTPEND0_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND0_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.        */
  #define GRTC_INTPEND0_PWMPERIODEND_Min (0x0UL)     /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND0_PWMPERIODEND_Max (0x1UL)     /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND0_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending                                                 */
  #define GRTC_INTPEND0_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending                                                        */

/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */
  #define GRTC_INTPEND0_PWMREADY_Pos (29UL)          /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTPEND0_PWMREADY_Msk (0x1UL << GRTC_INTPEND0_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                    */
  #define GRTC_INTPEND0_PWMREADY_Min (0x0UL)         /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND0_PWMREADY_Max (0x1UL)         /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND0_PWMREADY_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND0_PWMREADY_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */
  #define GRTC_INTPEND0_CLKOUTREADY_Pos (30UL)       /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTPEND0_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND0_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.           */
  #define GRTC_INTPEND0_CLKOUTREADY_Min (0x0UL)      /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND0_CLKOUTREADY_Max (0x1UL)      /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND0_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define GRTC_INTPEND0_CLKOUTREADY_Pending (0x1UL)  /*!< Read: Pending                                                        */


/* GRTC_INTEN1: Enable or disable interrupt */
  #define GRTC_INTEN1_ResetValue (0x00000000UL)      /*!< Reset value of INTEN1 register.                                      */

/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
  #define GRTC_INTEN1_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTEN1_COMPARE0_Msk (0x1UL << GRTC_INTEN1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
  #define GRTC_INTEN1_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN1_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN1_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
  #define GRTC_INTEN1_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTEN1_COMPARE1_Msk (0x1UL << GRTC_INTEN1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
  #define GRTC_INTEN1_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN1_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN1_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
  #define GRTC_INTEN1_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTEN1_COMPARE2_Msk (0x1UL << GRTC_INTEN1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
  #define GRTC_INTEN1_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN1_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN1_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
  #define GRTC_INTEN1_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTEN1_COMPARE3_Msk (0x1UL << GRTC_INTEN1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
  #define GRTC_INTEN1_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN1_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN1_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
  #define GRTC_INTEN1_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTEN1_COMPARE4_Msk (0x1UL << GRTC_INTEN1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
  #define GRTC_INTEN1_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN1_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN1_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
  #define GRTC_INTEN1_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTEN1_COMPARE5_Msk (0x1UL << GRTC_INTEN1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
  #define GRTC_INTEN1_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN1_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN1_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
  #define GRTC_INTEN1_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTEN1_COMPARE6_Msk (0x1UL << GRTC_INTEN1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
  #define GRTC_INTEN1_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN1_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN1_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
  #define GRTC_INTEN1_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTEN1_COMPARE7_Msk (0x1UL << GRTC_INTEN1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
  #define GRTC_INTEN1_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN1_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN1_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
  #define GRTC_INTEN1_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTEN1_COMPARE8_Msk (0x1UL << GRTC_INTEN1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
  #define GRTC_INTEN1_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN1_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN1_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
  #define GRTC_INTEN1_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTEN1_COMPARE9_Msk (0x1UL << GRTC_INTEN1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
  #define GRTC_INTEN1_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN1_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN1_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
  #define GRTC_INTEN1_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTEN1_COMPARE10_Msk (0x1UL << GRTC_INTEN1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
  #define GRTC_INTEN1_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN1_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN1_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */

/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
  #define GRTC_INTEN1_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTEN1_COMPARE11_Msk (0x1UL << GRTC_INTEN1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
  #define GRTC_INTEN1_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN1_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN1_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN1_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */

/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTEN1_RTCOMPARESYNC_Pos (25UL)       /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTEN1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.         */
  #define GRTC_INTEN1_RTCOMPARESYNC_Min (0x0UL)      /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN1_RTCOMPARESYNC_Max (0x1UL)      /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable                                                              */
  #define GRTC_INTEN1_RTCOMPARESYNC_Enabled (0x1UL)  /*!< Enable                                                               */

/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */
  #define GRTC_INTEN1_PWMPERIODEND_Pos (27UL)        /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTEN1_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.            */
  #define GRTC_INTEN1_PWMPERIODEND_Min (0x0UL)       /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN1_PWMPERIODEND_Max (0x1UL)       /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN1_PWMPERIODEND_Disabled (0x0UL)  /*!< Disable                                                              */
  #define GRTC_INTEN1_PWMPERIODEND_Enabled (0x1UL)   /*!< Enable                                                               */

/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */
  #define GRTC_INTEN1_PWMREADY_Pos (29UL)            /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTEN1_PWMREADY_Msk (0x1UL << GRTC_INTEN1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                        */
  #define GRTC_INTEN1_PWMREADY_Min (0x0UL)           /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN1_PWMREADY_Max (0x1UL)           /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN1_PWMREADY_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN1_PWMREADY_Enabled (0x1UL)       /*!< Enable                                                               */

/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */
  #define GRTC_INTEN1_CLKOUTREADY_Pos (30UL)         /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTEN1_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.               */
  #define GRTC_INTEN1_CLKOUTREADY_Min (0x0UL)        /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN1_CLKOUTREADY_Max (0x1UL)        /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN1_CLKOUTREADY_Disabled (0x0UL)   /*!< Disable                                                              */
  #define GRTC_INTEN1_CLKOUTREADY_Enabled (0x1UL)    /*!< Enable                                                               */


/* GRTC_INTENSET1: Enable interrupt */
  #define GRTC_INTENSET1_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET1 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
  #define GRTC_INTENSET1_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENSET1_COMPARE0_Msk (0x1UL << GRTC_INTENSET1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENSET1_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET1_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET1_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
  #define GRTC_INTENSET1_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENSET1_COMPARE1_Msk (0x1UL << GRTC_INTENSET1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENSET1_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET1_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET1_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
  #define GRTC_INTENSET1_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENSET1_COMPARE2_Msk (0x1UL << GRTC_INTENSET1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENSET1_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET1_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET1_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
  #define GRTC_INTENSET1_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENSET1_COMPARE3_Msk (0x1UL << GRTC_INTENSET1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENSET1_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET1_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET1_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
  #define GRTC_INTENSET1_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENSET1_COMPARE4_Msk (0x1UL << GRTC_INTENSET1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENSET1_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET1_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET1_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
  #define GRTC_INTENSET1_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENSET1_COMPARE5_Msk (0x1UL << GRTC_INTENSET1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENSET1_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET1_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET1_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
  #define GRTC_INTENSET1_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENSET1_COMPARE6_Msk (0x1UL << GRTC_INTENSET1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENSET1_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET1_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET1_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
  #define GRTC_INTENSET1_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENSET1_COMPARE7_Msk (0x1UL << GRTC_INTENSET1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENSET1_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET1_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET1_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
  #define GRTC_INTENSET1_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENSET1_COMPARE8_Msk (0x1UL << GRTC_INTENSET1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENSET1_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET1_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET1_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
  #define GRTC_INTENSET1_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENSET1_COMPARE9_Msk (0x1UL << GRTC_INTENSET1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENSET1_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET1_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET1_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
  #define GRTC_INTENSET1_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENSET1_COMPARE10_Msk (0x1UL << GRTC_INTENSET1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENSET1_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET1_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET1_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
  #define GRTC_INTENSET1_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENSET1_COMPARE11_Msk (0x1UL << GRTC_INTENSET1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENSET1_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET1_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET1_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET1_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENSET1_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENSET1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENSET1_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET1_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET1_RTCOMPARESYNC_Set (0x1UL)   /*!< Enable                                                               */
  #define GRTC_INTENSET1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENSET1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */
  #define GRTC_INTENSET1_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENSET1_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENSET1_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET1_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET1_PWMPERIODEND_Set (0x1UL)    /*!< Enable                                                               */
  #define GRTC_INTENSET1_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENSET1_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */
  #define GRTC_INTENSET1_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENSET1_PWMREADY_Msk (0x1UL << GRTC_INTENSET1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENSET1_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET1_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET1_PWMREADY_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET1_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET1_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */
  #define GRTC_INTENSET1_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENSET1_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENSET1_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET1_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET1_CLKOUTREADY_Set (0x1UL)     /*!< Enable                                                               */
  #define GRTC_INTENSET1_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENSET1_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTENCLR1: Disable interrupt */
  #define GRTC_INTENCLR1_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR1 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
  #define GRTC_INTENCLR1_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENCLR1_COMPARE0_Msk (0x1UL << GRTC_INTENCLR1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENCLR1_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR1_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR1_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
  #define GRTC_INTENCLR1_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENCLR1_COMPARE1_Msk (0x1UL << GRTC_INTENCLR1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENCLR1_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR1_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR1_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
  #define GRTC_INTENCLR1_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENCLR1_COMPARE2_Msk (0x1UL << GRTC_INTENCLR1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENCLR1_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR1_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR1_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
  #define GRTC_INTENCLR1_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENCLR1_COMPARE3_Msk (0x1UL << GRTC_INTENCLR1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENCLR1_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR1_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR1_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
  #define GRTC_INTENCLR1_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENCLR1_COMPARE4_Msk (0x1UL << GRTC_INTENCLR1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENCLR1_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR1_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR1_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
  #define GRTC_INTENCLR1_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENCLR1_COMPARE5_Msk (0x1UL << GRTC_INTENCLR1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENCLR1_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR1_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR1_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
  #define GRTC_INTENCLR1_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENCLR1_COMPARE6_Msk (0x1UL << GRTC_INTENCLR1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENCLR1_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR1_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR1_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
  #define GRTC_INTENCLR1_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENCLR1_COMPARE7_Msk (0x1UL << GRTC_INTENCLR1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENCLR1_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR1_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR1_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
  #define GRTC_INTENCLR1_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENCLR1_COMPARE8_Msk (0x1UL << GRTC_INTENCLR1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENCLR1_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR1_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR1_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
  #define GRTC_INTENCLR1_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENCLR1_COMPARE9_Msk (0x1UL << GRTC_INTENCLR1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENCLR1_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR1_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR1_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
  #define GRTC_INTENCLR1_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENCLR1_COMPARE10_Msk (0x1UL << GRTC_INTENCLR1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENCLR1_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR1_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR1_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
  #define GRTC_INTENCLR1_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENCLR1_COMPARE11_Msk (0x1UL << GRTC_INTENCLR1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENCLR1_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR1_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR1_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR1_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENCLR1_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENCLR1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENCLR1_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR1_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR1_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable                                                              */
  #define GRTC_INTENCLR1_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENCLR1_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */
  #define GRTC_INTENCLR1_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENCLR1_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENCLR1_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR1_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR1_PWMPERIODEND_Clear (0x1UL)  /*!< Disable                                                              */
  #define GRTC_INTENCLR1_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENCLR1_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */
  #define GRTC_INTENCLR1_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENCLR1_PWMREADY_Msk (0x1UL << GRTC_INTENCLR1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENCLR1_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR1_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR1_PWMREADY_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR1_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR1_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */
  #define GRTC_INTENCLR1_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENCLR1_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENCLR1_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR1_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR1_CLKOUTREADY_Clear (0x1UL)   /*!< Disable                                                              */
  #define GRTC_INTENCLR1_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENCLR1_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTPEND1: Pending interrupts */
  #define GRTC_INTPEND1_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND1 register.                                    */

/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
  #define GRTC_INTPEND1_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTPEND1_COMPARE0_Msk (0x1UL << GRTC_INTPEND1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
  #define GRTC_INTPEND1_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND1_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND1_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
  #define GRTC_INTPEND1_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTPEND1_COMPARE1_Msk (0x1UL << GRTC_INTPEND1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
  #define GRTC_INTPEND1_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND1_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND1_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
  #define GRTC_INTPEND1_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTPEND1_COMPARE2_Msk (0x1UL << GRTC_INTPEND1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
  #define GRTC_INTPEND1_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND1_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND1_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
  #define GRTC_INTPEND1_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTPEND1_COMPARE3_Msk (0x1UL << GRTC_INTPEND1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
  #define GRTC_INTPEND1_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND1_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND1_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
  #define GRTC_INTPEND1_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTPEND1_COMPARE4_Msk (0x1UL << GRTC_INTPEND1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
  #define GRTC_INTPEND1_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND1_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND1_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
  #define GRTC_INTPEND1_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTPEND1_COMPARE5_Msk (0x1UL << GRTC_INTPEND1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
  #define GRTC_INTPEND1_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND1_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND1_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
  #define GRTC_INTPEND1_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTPEND1_COMPARE6_Msk (0x1UL << GRTC_INTPEND1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
  #define GRTC_INTPEND1_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND1_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND1_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
  #define GRTC_INTPEND1_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTPEND1_COMPARE7_Msk (0x1UL << GRTC_INTPEND1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
  #define GRTC_INTPEND1_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND1_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND1_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
  #define GRTC_INTPEND1_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTPEND1_COMPARE8_Msk (0x1UL << GRTC_INTPEND1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
  #define GRTC_INTPEND1_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND1_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND1_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
  #define GRTC_INTPEND1_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTPEND1_COMPARE9_Msk (0x1UL << GRTC_INTPEND1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
  #define GRTC_INTPEND1_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND1_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND1_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
  #define GRTC_INTPEND1_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTPEND1_COMPARE10_Msk (0x1UL << GRTC_INTPEND1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
  #define GRTC_INTPEND1_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND1_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND1_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
  #define GRTC_INTPEND1_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTPEND1_COMPARE11_Msk (0x1UL << GRTC_INTPEND1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
  #define GRTC_INTPEND1_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND1_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND1_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */
  #define GRTC_INTPEND1_RTCOMPARESYNC_Pos (25UL)     /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTPEND1_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND1_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.     */
  #define GRTC_INTPEND1_RTCOMPARESYNC_Min (0x0UL)    /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND1_RTCOMPARESYNC_Max (0x1UL)    /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND1_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending                                                */
  #define GRTC_INTPEND1_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending                                                       */

/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */
  #define GRTC_INTPEND1_PWMPERIODEND_Pos (27UL)      /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTPEND1_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND1_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.        */
  #define GRTC_INTPEND1_PWMPERIODEND_Min (0x0UL)     /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND1_PWMPERIODEND_Max (0x1UL)     /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND1_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending                                                 */
  #define GRTC_INTPEND1_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending                                                        */

/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */
  #define GRTC_INTPEND1_PWMREADY_Pos (29UL)          /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTPEND1_PWMREADY_Msk (0x1UL << GRTC_INTPEND1_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                    */
  #define GRTC_INTPEND1_PWMREADY_Min (0x0UL)         /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND1_PWMREADY_Max (0x1UL)         /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND1_PWMREADY_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND1_PWMREADY_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */
  #define GRTC_INTPEND1_CLKOUTREADY_Pos (30UL)       /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTPEND1_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND1_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.           */
  #define GRTC_INTPEND1_CLKOUTREADY_Min (0x0UL)      /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND1_CLKOUTREADY_Max (0x1UL)      /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND1_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define GRTC_INTPEND1_CLKOUTREADY_Pending (0x1UL)  /*!< Read: Pending                                                        */


/* GRTC_INTEN2: Enable or disable interrupt */
  #define GRTC_INTEN2_ResetValue (0x00000000UL)      /*!< Reset value of INTEN2 register.                                      */

/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
  #define GRTC_INTEN2_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTEN2_COMPARE0_Msk (0x1UL << GRTC_INTEN2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
  #define GRTC_INTEN2_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN2_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN2_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
  #define GRTC_INTEN2_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTEN2_COMPARE1_Msk (0x1UL << GRTC_INTEN2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
  #define GRTC_INTEN2_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN2_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN2_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
  #define GRTC_INTEN2_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTEN2_COMPARE2_Msk (0x1UL << GRTC_INTEN2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
  #define GRTC_INTEN2_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN2_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN2_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
  #define GRTC_INTEN2_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTEN2_COMPARE3_Msk (0x1UL << GRTC_INTEN2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
  #define GRTC_INTEN2_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN2_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN2_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
  #define GRTC_INTEN2_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTEN2_COMPARE4_Msk (0x1UL << GRTC_INTEN2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
  #define GRTC_INTEN2_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN2_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN2_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
  #define GRTC_INTEN2_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTEN2_COMPARE5_Msk (0x1UL << GRTC_INTEN2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
  #define GRTC_INTEN2_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN2_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN2_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
  #define GRTC_INTEN2_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTEN2_COMPARE6_Msk (0x1UL << GRTC_INTEN2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
  #define GRTC_INTEN2_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN2_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN2_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
  #define GRTC_INTEN2_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTEN2_COMPARE7_Msk (0x1UL << GRTC_INTEN2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
  #define GRTC_INTEN2_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN2_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN2_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
  #define GRTC_INTEN2_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTEN2_COMPARE8_Msk (0x1UL << GRTC_INTEN2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
  #define GRTC_INTEN2_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN2_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN2_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
  #define GRTC_INTEN2_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTEN2_COMPARE9_Msk (0x1UL << GRTC_INTEN2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
  #define GRTC_INTEN2_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN2_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN2_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
  #define GRTC_INTEN2_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTEN2_COMPARE10_Msk (0x1UL << GRTC_INTEN2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
  #define GRTC_INTEN2_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN2_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN2_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */

/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
  #define GRTC_INTEN2_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTEN2_COMPARE11_Msk (0x1UL << GRTC_INTEN2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
  #define GRTC_INTEN2_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN2_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN2_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN2_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */

/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTEN2_RTCOMPARESYNC_Pos (25UL)       /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTEN2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.         */
  #define GRTC_INTEN2_RTCOMPARESYNC_Min (0x0UL)      /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN2_RTCOMPARESYNC_Max (0x1UL)      /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable                                                              */
  #define GRTC_INTEN2_RTCOMPARESYNC_Enabled (0x1UL)  /*!< Enable                                                               */

/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */
  #define GRTC_INTEN2_PWMPERIODEND_Pos (27UL)        /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTEN2_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.            */
  #define GRTC_INTEN2_PWMPERIODEND_Min (0x0UL)       /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN2_PWMPERIODEND_Max (0x1UL)       /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN2_PWMPERIODEND_Disabled (0x0UL)  /*!< Disable                                                              */
  #define GRTC_INTEN2_PWMPERIODEND_Enabled (0x1UL)   /*!< Enable                                                               */

/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */
  #define GRTC_INTEN2_PWMREADY_Pos (29UL)            /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTEN2_PWMREADY_Msk (0x1UL << GRTC_INTEN2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                        */
  #define GRTC_INTEN2_PWMREADY_Min (0x0UL)           /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN2_PWMREADY_Max (0x1UL)           /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN2_PWMREADY_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN2_PWMREADY_Enabled (0x1UL)       /*!< Enable                                                               */

/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */
  #define GRTC_INTEN2_CLKOUTREADY_Pos (30UL)         /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTEN2_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.               */
  #define GRTC_INTEN2_CLKOUTREADY_Min (0x0UL)        /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN2_CLKOUTREADY_Max (0x1UL)        /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN2_CLKOUTREADY_Disabled (0x0UL)   /*!< Disable                                                              */
  #define GRTC_INTEN2_CLKOUTREADY_Enabled (0x1UL)    /*!< Enable                                                               */


/* GRTC_INTENSET2: Enable interrupt */
  #define GRTC_INTENSET2_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET2 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
  #define GRTC_INTENSET2_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENSET2_COMPARE0_Msk (0x1UL << GRTC_INTENSET2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENSET2_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET2_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET2_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
  #define GRTC_INTENSET2_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENSET2_COMPARE1_Msk (0x1UL << GRTC_INTENSET2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENSET2_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET2_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET2_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
  #define GRTC_INTENSET2_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENSET2_COMPARE2_Msk (0x1UL << GRTC_INTENSET2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENSET2_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET2_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET2_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
  #define GRTC_INTENSET2_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENSET2_COMPARE3_Msk (0x1UL << GRTC_INTENSET2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENSET2_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET2_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET2_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
  #define GRTC_INTENSET2_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENSET2_COMPARE4_Msk (0x1UL << GRTC_INTENSET2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENSET2_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET2_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET2_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
  #define GRTC_INTENSET2_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENSET2_COMPARE5_Msk (0x1UL << GRTC_INTENSET2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENSET2_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET2_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET2_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
  #define GRTC_INTENSET2_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENSET2_COMPARE6_Msk (0x1UL << GRTC_INTENSET2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENSET2_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET2_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET2_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
  #define GRTC_INTENSET2_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENSET2_COMPARE7_Msk (0x1UL << GRTC_INTENSET2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENSET2_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET2_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET2_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
  #define GRTC_INTENSET2_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENSET2_COMPARE8_Msk (0x1UL << GRTC_INTENSET2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENSET2_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET2_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET2_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
  #define GRTC_INTENSET2_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENSET2_COMPARE9_Msk (0x1UL << GRTC_INTENSET2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENSET2_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET2_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET2_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
  #define GRTC_INTENSET2_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENSET2_COMPARE10_Msk (0x1UL << GRTC_INTENSET2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENSET2_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET2_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET2_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
  #define GRTC_INTENSET2_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENSET2_COMPARE11_Msk (0x1UL << GRTC_INTENSET2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENSET2_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET2_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET2_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET2_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENSET2_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENSET2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENSET2_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET2_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET2_RTCOMPARESYNC_Set (0x1UL)   /*!< Enable                                                               */
  #define GRTC_INTENSET2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENSET2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */
  #define GRTC_INTENSET2_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENSET2_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENSET2_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET2_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET2_PWMPERIODEND_Set (0x1UL)    /*!< Enable                                                               */
  #define GRTC_INTENSET2_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENSET2_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */
  #define GRTC_INTENSET2_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENSET2_PWMREADY_Msk (0x1UL << GRTC_INTENSET2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENSET2_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET2_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET2_PWMREADY_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET2_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET2_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */
  #define GRTC_INTENSET2_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENSET2_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENSET2_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET2_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET2_CLKOUTREADY_Set (0x1UL)     /*!< Enable                                                               */
  #define GRTC_INTENSET2_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENSET2_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTENCLR2: Disable interrupt */
  #define GRTC_INTENCLR2_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR2 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
  #define GRTC_INTENCLR2_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENCLR2_COMPARE0_Msk (0x1UL << GRTC_INTENCLR2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENCLR2_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR2_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR2_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
  #define GRTC_INTENCLR2_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENCLR2_COMPARE1_Msk (0x1UL << GRTC_INTENCLR2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENCLR2_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR2_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR2_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
  #define GRTC_INTENCLR2_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENCLR2_COMPARE2_Msk (0x1UL << GRTC_INTENCLR2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENCLR2_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR2_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR2_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
  #define GRTC_INTENCLR2_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENCLR2_COMPARE3_Msk (0x1UL << GRTC_INTENCLR2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENCLR2_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR2_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR2_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
  #define GRTC_INTENCLR2_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENCLR2_COMPARE4_Msk (0x1UL << GRTC_INTENCLR2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENCLR2_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR2_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR2_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
  #define GRTC_INTENCLR2_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENCLR2_COMPARE5_Msk (0x1UL << GRTC_INTENCLR2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENCLR2_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR2_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR2_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
  #define GRTC_INTENCLR2_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENCLR2_COMPARE6_Msk (0x1UL << GRTC_INTENCLR2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENCLR2_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR2_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR2_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
  #define GRTC_INTENCLR2_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENCLR2_COMPARE7_Msk (0x1UL << GRTC_INTENCLR2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENCLR2_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR2_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR2_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
  #define GRTC_INTENCLR2_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENCLR2_COMPARE8_Msk (0x1UL << GRTC_INTENCLR2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENCLR2_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR2_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR2_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
  #define GRTC_INTENCLR2_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENCLR2_COMPARE9_Msk (0x1UL << GRTC_INTENCLR2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENCLR2_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR2_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR2_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
  #define GRTC_INTENCLR2_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENCLR2_COMPARE10_Msk (0x1UL << GRTC_INTENCLR2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENCLR2_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR2_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR2_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
  #define GRTC_INTENCLR2_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENCLR2_COMPARE11_Msk (0x1UL << GRTC_INTENCLR2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENCLR2_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR2_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR2_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR2_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENCLR2_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENCLR2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENCLR2_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR2_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR2_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable                                                              */
  #define GRTC_INTENCLR2_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENCLR2_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */
  #define GRTC_INTENCLR2_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENCLR2_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENCLR2_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR2_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR2_PWMPERIODEND_Clear (0x1UL)  /*!< Disable                                                              */
  #define GRTC_INTENCLR2_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENCLR2_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */
  #define GRTC_INTENCLR2_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENCLR2_PWMREADY_Msk (0x1UL << GRTC_INTENCLR2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENCLR2_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR2_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR2_PWMREADY_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR2_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR2_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */
  #define GRTC_INTENCLR2_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENCLR2_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENCLR2_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR2_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR2_CLKOUTREADY_Clear (0x1UL)   /*!< Disable                                                              */
  #define GRTC_INTENCLR2_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENCLR2_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTPEND2: Pending interrupts */
  #define GRTC_INTPEND2_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND2 register.                                    */

/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
  #define GRTC_INTPEND2_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTPEND2_COMPARE0_Msk (0x1UL << GRTC_INTPEND2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
  #define GRTC_INTPEND2_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND2_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND2_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
  #define GRTC_INTPEND2_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTPEND2_COMPARE1_Msk (0x1UL << GRTC_INTPEND2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
  #define GRTC_INTPEND2_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND2_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND2_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
  #define GRTC_INTPEND2_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTPEND2_COMPARE2_Msk (0x1UL << GRTC_INTPEND2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
  #define GRTC_INTPEND2_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND2_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND2_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
  #define GRTC_INTPEND2_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTPEND2_COMPARE3_Msk (0x1UL << GRTC_INTPEND2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
  #define GRTC_INTPEND2_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND2_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND2_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
  #define GRTC_INTPEND2_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTPEND2_COMPARE4_Msk (0x1UL << GRTC_INTPEND2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
  #define GRTC_INTPEND2_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND2_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND2_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
  #define GRTC_INTPEND2_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTPEND2_COMPARE5_Msk (0x1UL << GRTC_INTPEND2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
  #define GRTC_INTPEND2_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND2_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND2_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
  #define GRTC_INTPEND2_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTPEND2_COMPARE6_Msk (0x1UL << GRTC_INTPEND2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
  #define GRTC_INTPEND2_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND2_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND2_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
  #define GRTC_INTPEND2_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTPEND2_COMPARE7_Msk (0x1UL << GRTC_INTPEND2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
  #define GRTC_INTPEND2_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND2_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND2_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
  #define GRTC_INTPEND2_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTPEND2_COMPARE8_Msk (0x1UL << GRTC_INTPEND2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
  #define GRTC_INTPEND2_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND2_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND2_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
  #define GRTC_INTPEND2_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTPEND2_COMPARE9_Msk (0x1UL << GRTC_INTPEND2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
  #define GRTC_INTPEND2_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND2_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND2_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
  #define GRTC_INTPEND2_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTPEND2_COMPARE10_Msk (0x1UL << GRTC_INTPEND2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
  #define GRTC_INTPEND2_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND2_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND2_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
  #define GRTC_INTPEND2_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTPEND2_COMPARE11_Msk (0x1UL << GRTC_INTPEND2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
  #define GRTC_INTPEND2_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND2_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND2_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */
  #define GRTC_INTPEND2_RTCOMPARESYNC_Pos (25UL)     /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTPEND2_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND2_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.     */
  #define GRTC_INTPEND2_RTCOMPARESYNC_Min (0x0UL)    /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND2_RTCOMPARESYNC_Max (0x1UL)    /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND2_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending                                                */
  #define GRTC_INTPEND2_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending                                                       */

/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */
  #define GRTC_INTPEND2_PWMPERIODEND_Pos (27UL)      /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTPEND2_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND2_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.        */
  #define GRTC_INTPEND2_PWMPERIODEND_Min (0x0UL)     /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND2_PWMPERIODEND_Max (0x1UL)     /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND2_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending                                                 */
  #define GRTC_INTPEND2_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending                                                        */

/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */
  #define GRTC_INTPEND2_PWMREADY_Pos (29UL)          /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTPEND2_PWMREADY_Msk (0x1UL << GRTC_INTPEND2_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                    */
  #define GRTC_INTPEND2_PWMREADY_Min (0x0UL)         /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND2_PWMREADY_Max (0x1UL)         /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND2_PWMREADY_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND2_PWMREADY_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */
  #define GRTC_INTPEND2_CLKOUTREADY_Pos (30UL)       /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTPEND2_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND2_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.           */
  #define GRTC_INTPEND2_CLKOUTREADY_Min (0x0UL)      /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND2_CLKOUTREADY_Max (0x1UL)      /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND2_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define GRTC_INTPEND2_CLKOUTREADY_Pending (0x1UL)  /*!< Read: Pending                                                        */


/* GRTC_INTEN3: Enable or disable interrupt */
  #define GRTC_INTEN3_ResetValue (0x00000000UL)      /*!< Reset value of INTEN3 register.                                      */

/* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
  #define GRTC_INTEN3_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTEN3_COMPARE0_Msk (0x1UL << GRTC_INTEN3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
  #define GRTC_INTEN3_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN3_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTEN3_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
  #define GRTC_INTEN3_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTEN3_COMPARE1_Msk (0x1UL << GRTC_INTEN3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
  #define GRTC_INTEN3_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN3_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTEN3_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
  #define GRTC_INTEN3_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTEN3_COMPARE2_Msk (0x1UL << GRTC_INTEN3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
  #define GRTC_INTEN3_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN3_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTEN3_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
  #define GRTC_INTEN3_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTEN3_COMPARE3_Msk (0x1UL << GRTC_INTEN3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
  #define GRTC_INTEN3_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN3_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTEN3_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
  #define GRTC_INTEN3_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTEN3_COMPARE4_Msk (0x1UL << GRTC_INTEN3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
  #define GRTC_INTEN3_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN3_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTEN3_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
  #define GRTC_INTEN3_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTEN3_COMPARE5_Msk (0x1UL << GRTC_INTEN3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
  #define GRTC_INTEN3_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN3_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTEN3_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
  #define GRTC_INTEN3_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTEN3_COMPARE6_Msk (0x1UL << GRTC_INTEN3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
  #define GRTC_INTEN3_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN3_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTEN3_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
  #define GRTC_INTEN3_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTEN3_COMPARE7_Msk (0x1UL << GRTC_INTEN3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
  #define GRTC_INTEN3_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN3_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTEN3_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
  #define GRTC_INTEN3_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTEN3_COMPARE8_Msk (0x1UL << GRTC_INTEN3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
  #define GRTC_INTEN3_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN3_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTEN3_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
  #define GRTC_INTEN3_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTEN3_COMPARE9_Msk (0x1UL << GRTC_INTEN3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
  #define GRTC_INTEN3_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN3_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTEN3_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
  #define GRTC_INTEN3_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTEN3_COMPARE10_Msk (0x1UL << GRTC_INTEN3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
  #define GRTC_INTEN3_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN3_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTEN3_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */

/* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
  #define GRTC_INTEN3_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTEN3_COMPARE11_Msk (0x1UL << GRTC_INTEN3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
  #define GRTC_INTEN3_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN3_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTEN3_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
  #define GRTC_INTEN3_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */

/* RTCOMPARESYNC @Bit 25 : Enable or disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTEN3_RTCOMPARESYNC_Pos (25UL)       /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTEN3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTEN3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.         */
  #define GRTC_INTEN3_RTCOMPARESYNC_Min (0x0UL)      /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN3_RTCOMPARESYNC_Max (0x1UL)      /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTEN3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Disable                                                              */
  #define GRTC_INTEN3_RTCOMPARESYNC_Enabled (0x1UL)  /*!< Enable                                                               */

/* PWMPERIODEND @Bit 27 : Enable or disable interrupt for event PWMPERIODEND */
  #define GRTC_INTEN3_PWMPERIODEND_Pos (27UL)        /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTEN3_PWMPERIODEND_Msk (0x1UL << GRTC_INTEN3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.            */
  #define GRTC_INTEN3_PWMPERIODEND_Min (0x0UL)       /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN3_PWMPERIODEND_Max (0x1UL)       /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTEN3_PWMPERIODEND_Disabled (0x0UL)  /*!< Disable                                                              */
  #define GRTC_INTEN3_PWMPERIODEND_Enabled (0x1UL)   /*!< Enable                                                               */

/* PWMREADY @Bit 29 : Enable or disable interrupt for event PWMREADY */
  #define GRTC_INTEN3_PWMREADY_Pos (29UL)            /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTEN3_PWMREADY_Msk (0x1UL << GRTC_INTEN3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                        */
  #define GRTC_INTEN3_PWMREADY_Min (0x0UL)           /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN3_PWMREADY_Max (0x1UL)           /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTEN3_PWMREADY_Disabled (0x0UL)      /*!< Disable                                                              */
  #define GRTC_INTEN3_PWMREADY_Enabled (0x1UL)       /*!< Enable                                                               */

/* CLKOUTREADY @Bit 30 : Enable or disable interrupt for event CLKOUTREADY */
  #define GRTC_INTEN3_CLKOUTREADY_Pos (30UL)         /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTEN3_CLKOUTREADY_Msk (0x1UL << GRTC_INTEN3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.               */
  #define GRTC_INTEN3_CLKOUTREADY_Min (0x0UL)        /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN3_CLKOUTREADY_Max (0x1UL)        /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTEN3_CLKOUTREADY_Disabled (0x0UL)   /*!< Disable                                                              */
  #define GRTC_INTEN3_CLKOUTREADY_Enabled (0x1UL)    /*!< Enable                                                               */


/* GRTC_INTENSET3: Enable interrupt */
  #define GRTC_INTENSET3_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET3 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
  #define GRTC_INTENSET3_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENSET3_COMPARE0_Msk (0x1UL << GRTC_INTENSET3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENSET3_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET3_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENSET3_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
  #define GRTC_INTENSET3_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENSET3_COMPARE1_Msk (0x1UL << GRTC_INTENSET3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENSET3_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET3_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENSET3_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
  #define GRTC_INTENSET3_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENSET3_COMPARE2_Msk (0x1UL << GRTC_INTENSET3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENSET3_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET3_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENSET3_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
  #define GRTC_INTENSET3_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENSET3_COMPARE3_Msk (0x1UL << GRTC_INTENSET3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENSET3_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET3_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENSET3_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
  #define GRTC_INTENSET3_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENSET3_COMPARE4_Msk (0x1UL << GRTC_INTENSET3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENSET3_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET3_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENSET3_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
  #define GRTC_INTENSET3_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENSET3_COMPARE5_Msk (0x1UL << GRTC_INTENSET3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENSET3_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET3_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENSET3_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
  #define GRTC_INTENSET3_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENSET3_COMPARE6_Msk (0x1UL << GRTC_INTENSET3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENSET3_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET3_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENSET3_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
  #define GRTC_INTENSET3_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENSET3_COMPARE7_Msk (0x1UL << GRTC_INTENSET3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENSET3_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET3_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENSET3_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
  #define GRTC_INTENSET3_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENSET3_COMPARE8_Msk (0x1UL << GRTC_INTENSET3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENSET3_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET3_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENSET3_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
  #define GRTC_INTENSET3_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENSET3_COMPARE9_Msk (0x1UL << GRTC_INTENSET3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENSET3_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET3_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENSET3_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
  #define GRTC_INTENSET3_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENSET3_COMPARE10_Msk (0x1UL << GRTC_INTENSET3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENSET3_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET3_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENSET3_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
  #define GRTC_INTENSET3_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENSET3_COMPARE11_Msk (0x1UL << GRTC_INTENSET3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENSET3_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET3_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENSET3_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
  #define GRTC_INTENSET3_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to enable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENSET3_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENSET3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENSET3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENSET3_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET3_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENSET3_RTCOMPARESYNC_Set (0x1UL)   /*!< Enable                                                               */
  #define GRTC_INTENSET3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENSET3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to enable interrupt for event PWMPERIODEND */
  #define GRTC_INTENSET3_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENSET3_PWMPERIODEND_Msk (0x1UL << GRTC_INTENSET3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENSET3_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET3_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENSET3_PWMPERIODEND_Set (0x1UL)    /*!< Enable                                                               */
  #define GRTC_INTENSET3_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENSET3_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to enable interrupt for event PWMREADY */
  #define GRTC_INTENSET3_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENSET3_PWMREADY_Msk (0x1UL << GRTC_INTENSET3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENSET3_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET3_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENSET3_PWMREADY_Set (0x1UL)        /*!< Enable                                                               */
  #define GRTC_INTENSET3_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENSET3_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to enable interrupt for event CLKOUTREADY */
  #define GRTC_INTENSET3_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENSET3_CLKOUTREADY_Msk (0x1UL << GRTC_INTENSET3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENSET3_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET3_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENSET3_CLKOUTREADY_Set (0x1UL)     /*!< Enable                                                               */
  #define GRTC_INTENSET3_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENSET3_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTENCLR3: Disable interrupt */
  #define GRTC_INTENCLR3_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR3 register.                                   */

/* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
  #define GRTC_INTENCLR3_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTENCLR3_COMPARE0_Msk (0x1UL << GRTC_INTENCLR3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define GRTC_INTENCLR3_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR3_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTENCLR3_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
  #define GRTC_INTENCLR3_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTENCLR3_COMPARE1_Msk (0x1UL << GRTC_INTENCLR3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define GRTC_INTENCLR3_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR3_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTENCLR3_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
  #define GRTC_INTENCLR3_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTENCLR3_COMPARE2_Msk (0x1UL << GRTC_INTENCLR3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define GRTC_INTENCLR3_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR3_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTENCLR3_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
  #define GRTC_INTENCLR3_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTENCLR3_COMPARE3_Msk (0x1UL << GRTC_INTENCLR3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define GRTC_INTENCLR3_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR3_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTENCLR3_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
  #define GRTC_INTENCLR3_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTENCLR3_COMPARE4_Msk (0x1UL << GRTC_INTENCLR3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define GRTC_INTENCLR3_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR3_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTENCLR3_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
  #define GRTC_INTENCLR3_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTENCLR3_COMPARE5_Msk (0x1UL << GRTC_INTENCLR3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define GRTC_INTENCLR3_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR3_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTENCLR3_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
  #define GRTC_INTENCLR3_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTENCLR3_COMPARE6_Msk (0x1UL << GRTC_INTENCLR3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define GRTC_INTENCLR3_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR3_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTENCLR3_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
  #define GRTC_INTENCLR3_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTENCLR3_COMPARE7_Msk (0x1UL << GRTC_INTENCLR3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define GRTC_INTENCLR3_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR3_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTENCLR3_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
  #define GRTC_INTENCLR3_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTENCLR3_COMPARE8_Msk (0x1UL << GRTC_INTENCLR3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
  #define GRTC_INTENCLR3_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR3_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTENCLR3_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
  #define GRTC_INTENCLR3_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTENCLR3_COMPARE9_Msk (0x1UL << GRTC_INTENCLR3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
  #define GRTC_INTENCLR3_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR3_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTENCLR3_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
  #define GRTC_INTENCLR3_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTENCLR3_COMPARE10_Msk (0x1UL << GRTC_INTENCLR3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
  #define GRTC_INTENCLR3_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR3_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTENCLR3_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
  #define GRTC_INTENCLR3_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTENCLR3_COMPARE11_Msk (0x1UL << GRTC_INTENCLR3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
  #define GRTC_INTENCLR3_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR3_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTENCLR3_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
  #define GRTC_INTENCLR3_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RTCOMPARESYNC @Bit 25 : Write '1' to disable interrupt for event RTCOMPARESYNC */
  #define GRTC_INTENCLR3_RTCOMPARESYNC_Pos (25UL)    /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTENCLR3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTENCLR3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.   */
  #define GRTC_INTENCLR3_RTCOMPARESYNC_Min (0x0UL)   /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR3_RTCOMPARESYNC_Max (0x1UL)   /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTENCLR3_RTCOMPARESYNC_Clear (0x1UL) /*!< Disable                                                              */
  #define GRTC_INTENCLR3_RTCOMPARESYNC_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define GRTC_INTENCLR3_RTCOMPARESYNC_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* PWMPERIODEND @Bit 27 : Write '1' to disable interrupt for event PWMPERIODEND */
  #define GRTC_INTENCLR3_PWMPERIODEND_Pos (27UL)     /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTENCLR3_PWMPERIODEND_Msk (0x1UL << GRTC_INTENCLR3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.      */
  #define GRTC_INTENCLR3_PWMPERIODEND_Min (0x0UL)    /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR3_PWMPERIODEND_Max (0x1UL)    /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTENCLR3_PWMPERIODEND_Clear (0x1UL)  /*!< Disable                                                              */
  #define GRTC_INTENCLR3_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define GRTC_INTENCLR3_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PWMREADY @Bit 29 : Write '1' to disable interrupt for event PWMREADY */
  #define GRTC_INTENCLR3_PWMREADY_Pos (29UL)         /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTENCLR3_PWMREADY_Msk (0x1UL << GRTC_INTENCLR3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                  */
  #define GRTC_INTENCLR3_PWMREADY_Min (0x0UL)        /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR3_PWMREADY_Max (0x1UL)        /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTENCLR3_PWMREADY_Clear (0x1UL)      /*!< Disable                                                              */
  #define GRTC_INTENCLR3_PWMREADY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define GRTC_INTENCLR3_PWMREADY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* CLKOUTREADY @Bit 30 : Write '1' to disable interrupt for event CLKOUTREADY */
  #define GRTC_INTENCLR3_CLKOUTREADY_Pos (30UL)      /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTENCLR3_CLKOUTREADY_Msk (0x1UL << GRTC_INTENCLR3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.         */
  #define GRTC_INTENCLR3_CLKOUTREADY_Min (0x0UL)     /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR3_CLKOUTREADY_Max (0x1UL)     /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTENCLR3_CLKOUTREADY_Clear (0x1UL)   /*!< Disable                                                              */
  #define GRTC_INTENCLR3_CLKOUTREADY_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_INTENCLR3_CLKOUTREADY_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* GRTC_INTPEND3: Pending interrupts */
  #define GRTC_INTPEND3_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND3 register.                                    */

/* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
  #define GRTC_INTPEND3_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
  #define GRTC_INTPEND3_COMPARE0_Msk (0x1UL << GRTC_INTPEND3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
  #define GRTC_INTPEND3_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND3_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
  #define GRTC_INTPEND3_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
  #define GRTC_INTPEND3_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
  #define GRTC_INTPEND3_COMPARE1_Msk (0x1UL << GRTC_INTPEND3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
  #define GRTC_INTPEND3_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND3_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
  #define GRTC_INTPEND3_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
  #define GRTC_INTPEND3_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
  #define GRTC_INTPEND3_COMPARE2_Msk (0x1UL << GRTC_INTPEND3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
  #define GRTC_INTPEND3_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND3_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
  #define GRTC_INTPEND3_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
  #define GRTC_INTPEND3_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
  #define GRTC_INTPEND3_COMPARE3_Msk (0x1UL << GRTC_INTPEND3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
  #define GRTC_INTPEND3_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND3_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
  #define GRTC_INTPEND3_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
  #define GRTC_INTPEND3_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
  #define GRTC_INTPEND3_COMPARE4_Msk (0x1UL << GRTC_INTPEND3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
  #define GRTC_INTPEND3_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND3_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
  #define GRTC_INTPEND3_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
  #define GRTC_INTPEND3_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
  #define GRTC_INTPEND3_COMPARE5_Msk (0x1UL << GRTC_INTPEND3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
  #define GRTC_INTPEND3_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND3_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
  #define GRTC_INTPEND3_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
  #define GRTC_INTPEND3_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
  #define GRTC_INTPEND3_COMPARE6_Msk (0x1UL << GRTC_INTPEND3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
  #define GRTC_INTPEND3_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND3_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
  #define GRTC_INTPEND3_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
  #define GRTC_INTPEND3_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
  #define GRTC_INTPEND3_COMPARE7_Msk (0x1UL << GRTC_INTPEND3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
  #define GRTC_INTPEND3_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND3_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
  #define GRTC_INTPEND3_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
  #define GRTC_INTPEND3_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
  #define GRTC_INTPEND3_COMPARE8_Msk (0x1UL << GRTC_INTPEND3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
  #define GRTC_INTPEND3_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND3_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
  #define GRTC_INTPEND3_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
  #define GRTC_INTPEND3_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
  #define GRTC_INTPEND3_COMPARE9_Msk (0x1UL << GRTC_INTPEND3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
  #define GRTC_INTPEND3_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND3_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
  #define GRTC_INTPEND3_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
  #define GRTC_INTPEND3_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
  #define GRTC_INTPEND3_COMPARE10_Msk (0x1UL << GRTC_INTPEND3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
  #define GRTC_INTPEND3_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND3_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
  #define GRTC_INTPEND3_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
  #define GRTC_INTPEND3_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
  #define GRTC_INTPEND3_COMPARE11_Msk (0x1UL << GRTC_INTPEND3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
  #define GRTC_INTPEND3_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND3_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
  #define GRTC_INTPEND3_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* RTCOMPARESYNC @Bit 25 : Read pending status of interrupt for event RTCOMPARESYNC */
  #define GRTC_INTPEND3_RTCOMPARESYNC_Pos (25UL)     /*!< Position of RTCOMPARESYNC field.                                     */
  #define GRTC_INTPEND3_RTCOMPARESYNC_Msk (0x1UL << GRTC_INTPEND3_RTCOMPARESYNC_Pos) /*!< Bit mask of RTCOMPARESYNC field.     */
  #define GRTC_INTPEND3_RTCOMPARESYNC_Min (0x0UL)    /*!< Min enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND3_RTCOMPARESYNC_Max (0x1UL)    /*!< Max enumerator value of RTCOMPARESYNC field.                         */
  #define GRTC_INTPEND3_RTCOMPARESYNC_NotPending (0x0UL) /*!< Read: Not pending                                                */
  #define GRTC_INTPEND3_RTCOMPARESYNC_Pending (0x1UL) /*!< Read: Pending                                                       */

/* PWMPERIODEND @Bit 27 : Read pending status of interrupt for event PWMPERIODEND */
  #define GRTC_INTPEND3_PWMPERIODEND_Pos (27UL)      /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_INTPEND3_PWMPERIODEND_Msk (0x1UL << GRTC_INTPEND3_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.        */
  #define GRTC_INTPEND3_PWMPERIODEND_Min (0x0UL)     /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND3_PWMPERIODEND_Max (0x1UL)     /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_INTPEND3_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending                                                 */
  #define GRTC_INTPEND3_PWMPERIODEND_Pending (0x1UL) /*!< Read: Pending                                                        */

/* PWMREADY @Bit 29 : Read pending status of interrupt for event PWMREADY */
  #define GRTC_INTPEND3_PWMREADY_Pos (29UL)          /*!< Position of PWMREADY field.                                          */
  #define GRTC_INTPEND3_PWMREADY_Msk (0x1UL << GRTC_INTPEND3_PWMREADY_Pos) /*!< Bit mask of PWMREADY field.                    */
  #define GRTC_INTPEND3_PWMREADY_Min (0x0UL)         /*!< Min enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND3_PWMREADY_Max (0x1UL)         /*!< Max enumerator value of PWMREADY field.                              */
  #define GRTC_INTPEND3_PWMREADY_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define GRTC_INTPEND3_PWMREADY_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* CLKOUTREADY @Bit 30 : Read pending status of interrupt for event CLKOUTREADY */
  #define GRTC_INTPEND3_CLKOUTREADY_Pos (30UL)       /*!< Position of CLKOUTREADY field.                                       */
  #define GRTC_INTPEND3_CLKOUTREADY_Msk (0x1UL << GRTC_INTPEND3_CLKOUTREADY_Pos) /*!< Bit mask of CLKOUTREADY field.           */
  #define GRTC_INTPEND3_CLKOUTREADY_Min (0x0UL)      /*!< Min enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND3_CLKOUTREADY_Max (0x1UL)      /*!< Max enumerator value of CLKOUTREADY field.                           */
  #define GRTC_INTPEND3_CLKOUTREADY_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define GRTC_INTPEND3_CLKOUTREADY_Pending (0x1UL)  /*!< Read: Pending                                                        */


/* GRTC_EVTEN: Enable or disable event routing */
  #define GRTC_EVTEN_ResetValue (0x00000000UL)       /*!< Reset value of EVTEN register.                                       */

/* PWMPERIODEND @Bit 27 : Enable or disable event routing for event PWMPERIODEND */
  #define GRTC_EVTEN_PWMPERIODEND_Pos (27UL)         /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_EVTEN_PWMPERIODEND_Msk (0x1UL << GRTC_EVTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.              */
  #define GRTC_EVTEN_PWMPERIODEND_Min (0x0UL)        /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_EVTEN_PWMPERIODEND_Max (0x1UL)        /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_EVTEN_PWMPERIODEND_Disabled (0x0UL)   /*!< Disable                                                              */
  #define GRTC_EVTEN_PWMPERIODEND_Enabled (0x1UL)    /*!< Enable                                                               */


/* GRTC_EVTENSET: Enable event routing */
  #define GRTC_EVTENSET_ResetValue (0x00000000UL)    /*!< Reset value of EVTENSET register.                                    */

/* PWMPERIODEND @Bit 27 : Write '1' to enable event routing for event PWMPERIODEND */
  #define GRTC_EVTENSET_PWMPERIODEND_Pos (27UL)      /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_EVTENSET_PWMPERIODEND_Msk (0x1UL << GRTC_EVTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.        */
  #define GRTC_EVTENSET_PWMPERIODEND_Min (0x0UL)     /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_EVTENSET_PWMPERIODEND_Max (0x1UL)     /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_EVTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_EVTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                        */
  #define GRTC_EVTENSET_PWMPERIODEND_Set (0x1UL)     /*!< Enable                                                               */


/* GRTC_EVTENCLR: Disable event routing */
  #define GRTC_EVTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of EVTENCLR register.                                    */

/* PWMPERIODEND @Bit 27 : Write '1' to disable event routing for event PWMPERIODEND */
  #define GRTC_EVTENCLR_PWMPERIODEND_Pos (27UL)      /*!< Position of PWMPERIODEND field.                                      */
  #define GRTC_EVTENCLR_PWMPERIODEND_Msk (0x1UL << GRTC_EVTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.        */
  #define GRTC_EVTENCLR_PWMPERIODEND_Min (0x0UL)     /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define GRTC_EVTENCLR_PWMPERIODEND_Max (0x1UL)     /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define GRTC_EVTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define GRTC_EVTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled                                                        */
  #define GRTC_EVTENCLR_PWMPERIODEND_Clear (0x1UL)   /*!< Disable                                                              */


/* GRTC_MODE: Counter mode selection */
  #define GRTC_MODE_ResetValue (0x00000000UL)        /*!< Reset value of MODE register.                                        */

/* AUTOEN @Bit 0 : Automatic enable to keep the SYSCOUNTER active. */
  #define GRTC_MODE_AUTOEN_Pos (0UL)                 /*!< Position of AUTOEN field.                                            */
  #define GRTC_MODE_AUTOEN_Msk (0x1UL << GRTC_MODE_AUTOEN_Pos) /*!< Bit mask of AUTOEN field.                                  */
  #define GRTC_MODE_AUTOEN_Min (0x0UL)               /*!< Min enumerator value of AUTOEN field.                                */
  #define GRTC_MODE_AUTOEN_Max (0x1UL)               /*!< Max enumerator value of AUTOEN field.                                */
  #define GRTC_MODE_AUTOEN_Default (0x0UL)           /*!< Default configuration to keep the SYSCOUNTER active.                 */
  #define GRTC_MODE_AUTOEN_CpuActive (0x1UL)         /*!< In addition to the above mode, any local CPU that is not sleeping keep
                                                          the SYSCOUNTER active.*/

/* SYSCOUNTEREN @Bit 1 : Enable the SYSCOUNTER */
  #define GRTC_MODE_SYSCOUNTEREN_Pos (1UL)           /*!< Position of SYSCOUNTEREN field.                                      */
  #define GRTC_MODE_SYSCOUNTEREN_Msk (0x1UL << GRTC_MODE_SYSCOUNTEREN_Pos) /*!< Bit mask of SYSCOUNTEREN field.                */
  #define GRTC_MODE_SYSCOUNTEREN_Min (0x0UL)         /*!< Min enumerator value of SYSCOUNTEREN field.                          */
  #define GRTC_MODE_SYSCOUNTEREN_Max (0x1UL)         /*!< Max enumerator value of SYSCOUNTEREN field.                          */
  #define GRTC_MODE_SYSCOUNTEREN_Disabled (0x0UL)    /*!< SYSCOUNTER disabled                                                  */
  #define GRTC_MODE_SYSCOUNTEREN_Enabled (0x1UL)     /*!< SYSCOUNTER enabled                                                   */


/* GRTC_TIMEOUT: Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER */
  #define GRTC_TIMEOUT_ResetValue (0x00000000UL)     /*!< Reset value of TIMEOUT register.                                     */

/* VALUE @Bits 0..15 : Number of 32Ki cycles */
  #define GRTC_TIMEOUT_VALUE_Pos (0UL)               /*!< Position of VALUE field.                                             */
  #define GRTC_TIMEOUT_VALUE_Msk (0xFFFFUL << GRTC_TIMEOUT_VALUE_Pos) /*!< Bit mask of VALUE field.                            */


/* GRTC_INTERVAL: Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. */
  #define GRTC_INTERVAL_ResetValue (0x00000000UL)    /*!< Reset value of INTERVAL register.                                    */

/* VALUE @Bits 0..15 : Count to add to CC[0] */
  #define GRTC_INTERVAL_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
  #define GRTC_INTERVAL_VALUE_Msk (0xFFFFUL << GRTC_INTERVAL_VALUE_Pos) /*!< Bit mask of VALUE field.                          */


/* GRTC_WAKETIME: GRTC wake up time. */
  #define GRTC_WAKETIME_ResetValue (0x00000001UL)    /*!< Reset value of WAKETIME register.                                    */

/* VALUE @Bits 0..7 : Number of LFCLK clock cycles to wake up before the next scheduled EVENTS_COMPARE event */
  #define GRTC_WAKETIME_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
  #define GRTC_WAKETIME_VALUE_Msk (0xFFUL << GRTC_WAKETIME_VALUE_Pos) /*!< Bit mask of VALUE field.                            */


/* GRTC_PWMCONFIG: PWM configuration. */
  #define GRTC_PWMCONFIG_ResetValue (0x00000000UL)   /*!< Reset value of PWMCONFIG register.                                   */

/* COMPAREVALUE @Bits 0..7 : The PWM compare value */
  #define GRTC_PWMCONFIG_COMPAREVALUE_Pos (0UL)      /*!< Position of COMPAREVALUE field.                                      */
  #define GRTC_PWMCONFIG_COMPAREVALUE_Msk (0xFFUL << GRTC_PWMCONFIG_COMPAREVALUE_Pos) /*!< Bit mask of COMPAREVALUE field.     */


/* GRTC_CLKOUT: Configuration of clock output */
  #define GRTC_CLKOUT_ResetValue (0x00000000UL)      /*!< Reset value of CLKOUT register.                                      */

/* CLKOUT32K @Bit 0 : Enable 32Ki clock output on pin */
  #define GRTC_CLKOUT_CLKOUT32K_Pos (0UL)            /*!< Position of CLKOUT32K field.                                         */
  #define GRTC_CLKOUT_CLKOUT32K_Msk (0x1UL << GRTC_CLKOUT_CLKOUT32K_Pos) /*!< Bit mask of CLKOUT32K field.                     */
  #define GRTC_CLKOUT_CLKOUT32K_Min (0x0UL)          /*!< Min enumerator value of CLKOUT32K field.                             */
  #define GRTC_CLKOUT_CLKOUT32K_Max (0x1UL)          /*!< Max enumerator value of CLKOUT32K field.                             */
  #define GRTC_CLKOUT_CLKOUT32K_Disabled (0x0UL)     /*!< Disabled                                                             */
  #define GRTC_CLKOUT_CLKOUT32K_Enabled (0x1UL)      /*!< Enabled                                                              */

/* CLKOUTFAST @Bit 1 : Enable fast clock output on pin */
  #define GRTC_CLKOUT_CLKOUTFAST_Pos (1UL)           /*!< Position of CLKOUTFAST field.                                        */
  #define GRTC_CLKOUT_CLKOUTFAST_Msk (0x1UL << GRTC_CLKOUT_CLKOUTFAST_Pos) /*!< Bit mask of CLKOUTFAST field.                  */
  #define GRTC_CLKOUT_CLKOUTFAST_Min (0x0UL)         /*!< Min enumerator value of CLKOUTFAST field.                            */
  #define GRTC_CLKOUT_CLKOUTFAST_Max (0x1UL)         /*!< Max enumerator value of CLKOUTFAST field.                            */
  #define GRTC_CLKOUT_CLKOUTFAST_Disabled (0x0UL)    /*!< Disabled                                                             */
  #define GRTC_CLKOUT_CLKOUTFAST_Enabled (0x1UL)     /*!< Enabled                                                              */


/* GRTC_CLKCFG: Clock Configuration */
  #define GRTC_CLKCFG_ResetValue (0x00010001UL)      /*!< Reset value of CLKCFG register.                                      */

/* CLKFASTDIV @Bits 0..7 : Fast clock divisor value of clock output */
  #define GRTC_CLKCFG_CLKFASTDIV_Pos (0UL)           /*!< Position of CLKFASTDIV field.                                        */
  #define GRTC_CLKCFG_CLKFASTDIV_Msk (0xFFUL << GRTC_CLKCFG_CLKFASTDIV_Pos) /*!< Bit mask of CLKFASTDIV field.                 */
  #define GRTC_CLKCFG_CLKFASTDIV_Min (0x01UL)        /*!< Min value of CLKFASTDIV field.                                       */
  #define GRTC_CLKCFG_CLKFASTDIV_Max (0xFFUL)        /*!< Max size of CLKFASTDIV field.                                        */

/* CLKSEL @Bits 16..17 : GRTC LFCLK clock source selection */
  #define GRTC_CLKCFG_CLKSEL_Pos (16UL)              /*!< Position of CLKSEL field.                                            */
  #define GRTC_CLKCFG_CLKSEL_Msk (0x3UL << GRTC_CLKCFG_CLKSEL_Pos) /*!< Bit mask of CLKSEL field.                              */
  #define GRTC_CLKCFG_CLKSEL_Min (0x0UL)             /*!< Min enumerator value of CLKSEL field.                                */
  #define GRTC_CLKCFG_CLKSEL_Max (0x2UL)             /*!< Max enumerator value of CLKSEL field.                                */
  #define GRTC_CLKCFG_CLKSEL_LFXO (0x0UL)            /*!< GRTC LFCLK clock source is LFXO                                      */
  #define GRTC_CLKCFG_CLKSEL_SystemLFCLK (0x1UL)     /*!< GRTC LFCLK clock source is system LFCLK                              */
  #define GRTC_CLKCFG_CLKSEL_LFLPRC (0x2UL)          /*!< GRTC LFCLK clock source is LFLPRC                                    */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            I2S                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ==================================================== Struct I2S_CONFIG ==================================================== */
/**
  * @brief CONFIG [I2S_CONFIG] (unspecified)
  */
typedef struct {
  __IOM uint32_t  MODE;                              /*!< (@ 0x00000000) I2S mode                                              */
  __IOM uint32_t  RXEN;                              /*!< (@ 0x00000004) Reception (RX) enable                                 */
  __IOM uint32_t  TXEN;                              /*!< (@ 0x00000008) Transmission (TX) enable                              */
  __IOM uint32_t  MCKEN;                             /*!< (@ 0x0000000C) Master clock generator enable                         */
  __IOM uint32_t  MCKFREQ;                           /*!< (@ 0x00000010) I2S clock generator control                           */
  __IOM uint32_t  RATIO;                             /*!< (@ 0x00000014) MCK / LRCK ratio                                      */
  __IOM uint32_t  SWIDTH;                            /*!< (@ 0x00000018) Sample width                                          */
  __IOM uint32_t  ALIGN;                             /*!< (@ 0x0000001C) Alignment of sample within a frame                    */
  __IOM uint32_t  FORMAT;                            /*!< (@ 0x00000020) Frame format                                          */
  __IOM uint32_t  CHANNELS;                          /*!< (@ 0x00000024) Enable channels                                       */
} NRF_I2S_CONFIG_Type;                               /*!< Size = 40 (0x028)                                                    */

/* I2S_CONFIG_MODE: I2S mode */
  #define I2S_CONFIG_MODE_ResetValue (0x00000000UL)  /*!< Reset value of MODE register.                                        */

/* MODE @Bit 0 : I2S mode */
  #define I2S_CONFIG_MODE_MODE_Pos (0UL)             /*!< Position of MODE field.                                              */
  #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field.                            */
  #define I2S_CONFIG_MODE_MODE_Min (0x0UL)           /*!< Min enumerator value of MODE field.                                  */
  #define I2S_CONFIG_MODE_MODE_Max (0x1UL)           /*!< Max enumerator value of MODE field.                                  */
  #define I2S_CONFIG_MODE_MODE_Master (0x0UL)        /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK)
                                                          and output on pins defined by PSEL.xxx.*/
  #define I2S_CONFIG_MODE_MODE_Slave (0x1UL)         /*!< Slave mode. SCK and LRCK generated by external master and received on
                                                          pins defined by PSEL.xxx*/


/* I2S_CONFIG_RXEN: Reception (RX) enable */
  #define I2S_CONFIG_RXEN_ResetValue (0x00000000UL)  /*!< Reset value of RXEN register.                                        */

/* RXEN @Bit 0 : Reception (RX) enable */
  #define I2S_CONFIG_RXEN_RXEN_Pos (0UL)             /*!< Position of RXEN field.                                              */
  #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field.                            */
  #define I2S_CONFIG_RXEN_RXEN_Min (0x0UL)           /*!< Min enumerator value of RXEN field.                                  */
  #define I2S_CONFIG_RXEN_RXEN_Max (0x1UL)           /*!< Max enumerator value of RXEN field.                                  */
  #define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL)      /*!< Reception disabled and now data will be written to the RXD.PTR
                                                          address.*/
  #define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL)       /*!< Reception enabled.                                                   */


/* I2S_CONFIG_TXEN: Transmission (TX) enable */
  #define I2S_CONFIG_TXEN_ResetValue (0x00000001UL)  /*!< Reset value of TXEN register.                                        */

/* TXEN @Bit 0 : Transmission (TX) enable */
  #define I2S_CONFIG_TXEN_TXEN_Pos (0UL)             /*!< Position of TXEN field.                                              */
  #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field.                            */
  #define I2S_CONFIG_TXEN_TXEN_Min (0x0UL)           /*!< Min enumerator value of TXEN field.                                  */
  #define I2S_CONFIG_TXEN_TXEN_Max (0x1UL)           /*!< Max enumerator value of TXEN field.                                  */
  #define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL)      /*!< Transmission disabled and now data will be read from the RXD.TXD
                                                          address.*/
  #define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL)       /*!< Transmission enabled.                                                */


/* I2S_CONFIG_MCKEN: Master clock generator enable */
  #define I2S_CONFIG_MCKEN_ResetValue (0x00000001UL) /*!< Reset value of MCKEN register.                                       */

/* MCKEN @Bit 0 : Master clock generator enable */
  #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL)           /*!< Position of MCKEN field.                                             */
  #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field.                       */
  #define I2S_CONFIG_MCKEN_MCKEN_Min (0x0UL)         /*!< Min enumerator value of MCKEN field.                                 */
  #define I2S_CONFIG_MCKEN_MCKEN_Max (0x1UL)         /*!< Max enumerator value of MCKEN field.                                 */
  #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL)    /*!< Master clock generator disabled and PSEL.MCK not connected(available
                                                          as GPIO).*/
  #define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL)     /*!< Master clock generator running and MCK output on PSEL.MCK.           */


/* I2S_CONFIG_MCKFREQ: I2S clock generator control */
  #define I2S_CONFIG_MCKFREQ_ResetValue (0x20000000UL) /*!< Reset value of MCKFREQ register.                                   */

/* MCKFREQ @Bits 0..31 : I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12
                         least significant bits of the register are ignored and shall be set to zero. */

  #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL)       /*!< Position of MCKFREQ field.                                           */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field.      */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_Min (0x20C0000UL) /*!< Min enumerator value of MCKFREQ field.                             */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_Max (0x80000000UL) /*!< Max enumerator value of MCKFREQ field.                            */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation.       */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation.        */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation.        */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation.  */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation.        */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation.      */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation.      */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation.      */
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation.*/
  #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation.  */


/* I2S_CONFIG_RATIO: MCK / LRCK ratio */
  #define I2S_CONFIG_RATIO_ResetValue (0x00000006UL) /*!< Reset value of RATIO register.                                       */

/* RATIO @Bits 0..3 : MCK / LRCK ratio */
  #define I2S_CONFIG_RATIO_RATIO_Pos (0UL)           /*!< Position of RATIO field.                                             */
  #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field.                       */
  #define I2S_CONFIG_RATIO_RATIO_Min (0x0UL)         /*!< Min enumerator value of RATIO field.                                 */
  #define I2S_CONFIG_RATIO_RATIO_Max (0x8UL)         /*!< Max enumerator value of RATIO field.                                 */
  #define I2S_CONFIG_RATIO_RATIO_32X (0x0UL)         /*!< LRCK = MCK / 32                                                      */
  #define I2S_CONFIG_RATIO_RATIO_48X (0x1UL)         /*!< LRCK = MCK / 48                                                      */
  #define I2S_CONFIG_RATIO_RATIO_64X (0x2UL)         /*!< LRCK = MCK / 64                                                      */
  #define I2S_CONFIG_RATIO_RATIO_96X (0x3UL)         /*!< LRCK = MCK / 96                                                      */
  #define I2S_CONFIG_RATIO_RATIO_128X (0x4UL)        /*!< LRCK = MCK / 128                                                     */
  #define I2S_CONFIG_RATIO_RATIO_192X (0x5UL)        /*!< LRCK = MCK / 192                                                     */
  #define I2S_CONFIG_RATIO_RATIO_256X (0x6UL)        /*!< LRCK = MCK / 256                                                     */
  #define I2S_CONFIG_RATIO_RATIO_384X (0x7UL)        /*!< LRCK = MCK / 384                                                     */
  #define I2S_CONFIG_RATIO_RATIO_512X (0x8UL)        /*!< LRCK = MCK / 512                                                     */


/* I2S_CONFIG_SWIDTH: Sample width */
  #define I2S_CONFIG_SWIDTH_ResetValue (0x00000001UL) /*!< Reset value of SWIDTH register.                                     */

/* SWIDTH @Bits 0..2 : Sample and half-frame width */
  #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL)         /*!< Position of SWIDTH field.                                            */
  #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x7UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field.                  */
  #define I2S_CONFIG_SWIDTH_SWIDTH_Min (0x0UL)       /*!< Min enumerator value of SWIDTH field.                                */
  #define I2S_CONFIG_SWIDTH_SWIDTH_Max (0x7UL)       /*!< Max enumerator value of SWIDTH field.                                */
  #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL)      /*!< 8 bit sample.                                                        */
  #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL)     /*!< 16 bit sample.                                                       */
  #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL)     /*!< 24 bit sample.                                                       */
  #define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (0x3UL)     /*!< 32 bit sample.                                                       */
  #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (0x4UL)  /*!< 8 bit sample in a 16-bit half-frame.                                 */
  #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32 (0x5UL)  /*!< 8 bit sample in a 32-bit half-frame.                                 */
  #define I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32 (0x6UL) /*!< 16 bit sample in a 32-bit half-frame.                                */
  #define I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32 (0x7UL) /*!< 24 bit sample in a 32-bit half-frame.                                */


/* I2S_CONFIG_ALIGN: Alignment of sample within a frame */
  #define I2S_CONFIG_ALIGN_ResetValue (0x00000000UL) /*!< Reset value of ALIGN register.                                       */

/* ALIGN @Bit 0 : Alignment of sample within a frame */
  #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL)           /*!< Position of ALIGN field.                                             */
  #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field.                       */
  #define I2S_CONFIG_ALIGN_ALIGN_Min (0x0UL)         /*!< Min enumerator value of ALIGN field.                                 */
  #define I2S_CONFIG_ALIGN_ALIGN_Max (0x1UL)         /*!< Max enumerator value of ALIGN field.                                 */
  #define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL)        /*!< Left-aligned.                                                        */
  #define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL)       /*!< Right-aligned.                                                       */


/* I2S_CONFIG_FORMAT: Frame format */
  #define I2S_CONFIG_FORMAT_ResetValue (0x00000000UL) /*!< Reset value of FORMAT register.                                     */

/* FORMAT @Bit 0 : Frame format */
  #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL)         /*!< Position of FORMAT field.                                            */
  #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field.                  */
  #define I2S_CONFIG_FORMAT_FORMAT_Min (0x0UL)       /*!< Min enumerator value of FORMAT field.                                */
  #define I2S_CONFIG_FORMAT_FORMAT_Max (0x1UL)       /*!< Max enumerator value of FORMAT field.                                */
  #define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL)       /*!< Original I2S format.                                                 */
  #define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL)   /*!< Alternate (left- or right-aligned) format.                           */


/* I2S_CONFIG_CHANNELS: Enable channels */
  #define I2S_CONFIG_CHANNELS_ResetValue (0x00000000UL) /*!< Reset value of CHANNELS register.                                 */

/* CHANNELS @Bits 0..1 : Enable channels */
  #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL)     /*!< Position of CHANNELS field.                                          */
  #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field.        */
  #define I2S_CONFIG_CHANNELS_CHANNELS_Min (0x0UL)   /*!< Min enumerator value of CHANNELS field.                              */
  #define I2S_CONFIG_CHANNELS_CHANNELS_Max (0x2UL)   /*!< Max enumerator value of CHANNELS field.                              */
  #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo.                                                             */
  #define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL)  /*!< Left only.                                                           */
  #define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only.                                                          */



/* ===================================================== Struct I2S_RXD ====================================================== */
/**
  * @brief RXD [I2S_RXD] (unspecified)
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Receive buffer RAM start address.                     */
} NRF_I2S_RXD_Type;                                  /*!< Size = 4 (0x004)                                                     */

/* I2S_RXD_PTR: Receive buffer RAM start address. */
  #define I2S_RXD_PTR_ResetValue (0x20000000UL)      /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this
                     address. This address is a word aligned Data RAM address. */

  #define I2S_RXD_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
  #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */



/* ===================================================== Struct I2S_TXD ====================================================== */
/**
  * @brief TXD [I2S_TXD] (unspecified)
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Transmit buffer RAM start address                     */
} NRF_I2S_TXD_Type;                                  /*!< Size = 4 (0x004)                                                     */

/* I2S_TXD_PTR: Transmit buffer RAM start address */
  #define I2S_TXD_PTR_ResetValue (0x20000000UL)      /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from
                     this address. This address is a word aligned Data RAM address. */

  #define I2S_TXD_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
  #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */



/* ==================================================== Struct I2S_RXTXD ===================================================== */
/**
  * @brief RXTXD [I2S_RXTXD] (unspecified)
  */
typedef struct {
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000000) Size of RXD and TXD buffers                           */
} NRF_I2S_RXTXD_Type;                                /*!< Size = 4 (0x004)                                                     */

/* I2S_RXTXD_MAXCNT: Size of RXD and TXD buffers */
  #define I2S_RXTXD_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                      */

/* MAXCNT @Bits 0..13 : Size of RXD and TXD buffers in number of 32 bit words */
  #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL)          /*!< Position of MAXCNT field.                                            */
  #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                 */



/* ===================================================== Struct I2S_PSEL ===================================================== */
/**
  * @brief PSEL [I2S_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  MCK;                               /*!< (@ 0x00000000) Pin select for MCK signal                             */
  __IOM uint32_t  SCK;                               /*!< (@ 0x00000004) Pin select for SCK signal                             */
  __IOM uint32_t  LRCK;                              /*!< (@ 0x00000008) Pin select for LRCK signal                            */
  __IOM uint32_t  SDIN;                              /*!< (@ 0x0000000C) Pin select for SDIN signal                            */
  __IOM uint32_t  SDOUT;                             /*!< (@ 0x00000010) Pin select for SDOUT signal                           */
} NRF_I2S_PSEL_Type;                                 /*!< Size = 20 (0x014)                                                    */

/* I2S_PSEL_MCK: Pin select for MCK signal */
  #define I2S_PSEL_MCK_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of MCK register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define I2S_PSEL_MCK_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
  #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field.                                    */
  #define I2S_PSEL_MCK_PIN_Min (0x00UL)              /*!< Min value of PIN field.                                              */
  #define I2S_PSEL_MCK_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define I2S_PSEL_MCK_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
  #define I2S_PSEL_MCK_PORT_Msk (0x7UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field.                                  */
  #define I2S_PSEL_MCK_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
  #define I2S_PSEL_MCK_PORT_Max (0x7UL)              /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define I2S_PSEL_MCK_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
  #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
  #define I2S_PSEL_MCK_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
  #define I2S_PSEL_MCK_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
  #define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
  #define I2S_PSEL_MCK_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */


/* I2S_PSEL_SCK: Pin select for SCK signal */
  #define I2S_PSEL_SCK_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of SCK register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define I2S_PSEL_SCK_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
  #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field.                                    */
  #define I2S_PSEL_SCK_PIN_Min (0x00UL)              /*!< Min value of PIN field.                                              */
  #define I2S_PSEL_SCK_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define I2S_PSEL_SCK_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
  #define I2S_PSEL_SCK_PORT_Msk (0x7UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field.                                  */
  #define I2S_PSEL_SCK_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
  #define I2S_PSEL_SCK_PORT_Max (0x7UL)              /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define I2S_PSEL_SCK_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
  #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
  #define I2S_PSEL_SCK_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
  #define I2S_PSEL_SCK_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
  #define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
  #define I2S_PSEL_SCK_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */


/* I2S_PSEL_LRCK: Pin select for LRCK signal */
  #define I2S_PSEL_LRCK_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of LRCK register.                                        */

/* PIN @Bits 0..4 : Pin number */
  #define I2S_PSEL_LRCK_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define I2S_PSEL_LRCK_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define I2S_PSEL_LRCK_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define I2S_PSEL_LRCK_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define I2S_PSEL_LRCK_PORT_Msk (0x7UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define I2S_PSEL_LRCK_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define I2S_PSEL_LRCK_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define I2S_PSEL_LRCK_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define I2S_PSEL_LRCK_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define I2S_PSEL_LRCK_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* I2S_PSEL_SDIN: Pin select for SDIN signal */
  #define I2S_PSEL_SDIN_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SDIN register.                                        */

/* PIN @Bits 0..4 : Pin number */
  #define I2S_PSEL_SDIN_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define I2S_PSEL_SDIN_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define I2S_PSEL_SDIN_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define I2S_PSEL_SDIN_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define I2S_PSEL_SDIN_PORT_Msk (0x7UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define I2S_PSEL_SDIN_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define I2S_PSEL_SDIN_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define I2S_PSEL_SDIN_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define I2S_PSEL_SDIN_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define I2S_PSEL_SDIN_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* I2S_PSEL_SDOUT: Pin select for SDOUT signal */
  #define I2S_PSEL_SDOUT_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of SDOUT register.                                       */

/* PIN @Bits 0..4 : Pin number */
  #define I2S_PSEL_SDOUT_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define I2S_PSEL_SDOUT_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define I2S_PSEL_SDOUT_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define I2S_PSEL_SDOUT_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define I2S_PSEL_SDOUT_PORT_Msk (0x7UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define I2S_PSEL_SDOUT_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define I2S_PSEL_SDOUT_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define I2S_PSEL_SDOUT_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define I2S_PSEL_SDOUT_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */



/* =================================================== Struct I2S_CHANNEL ==================================================== */
/**
  * @brief CHANNEL [I2S_CHANNEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_I2S_CHANNEL_Type;                              /*!< Size = 8 (0x008)                                                     */
  #define I2S_CHANNEL_MaxCount (2UL)                 /*!< Size of CHANNEL[2] array.                                            */
  #define I2S_CHANNEL_MaxIndex (1UL)                 /*!< Max index of CHANNEL[2] array.                                       */
  #define I2S_CHANNEL_MinIndex (0UL)                 /*!< Min index of CHANNEL[2] array.                                       */

/* I2S_CHANNEL_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define I2S_CHANNEL_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define I2S_CHANNEL_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define I2S_CHANNEL_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << I2S_CHANNEL_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define I2S_CHANNEL_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define I2S_CHANNEL_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define I2S_CHANNEL_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define I2S_CHANNEL_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* I2S_CHANNEL_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define I2S_CHANNEL_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define I2S_CHANNEL_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define I2S_CHANNEL_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << I2S_CHANNEL_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/


/* ======================================================= Struct I2S ======================================================== */
/**
  * @brief Inter-IC Sound
  */
  typedef struct {                                   /*!< I2S Structure                                                        */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK
                                                                         generator when this is enabled*/
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stops I2S transfer and MCK generator. Triggering this
                                                                         task will cause the event STOPPED to be generated.*/
    __IM uint32_t RESERVED[30];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED1[31];
    __IOM uint32_t EVENTS_RXPTRUPD;                  /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal
                                                                         double-buffers. When the I2S module is started and RX
                                                                         is enabled, this event will be generated for every
                                                                         RXTXD.MAXCNT words received on the SDIN pin.*/
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000108) I2S transfer stopped.                                 */
    __IM uint32_t RESERVED2[2];
    __IOM uint32_t EVENTS_TXPTRUPD;                  /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal
                                                                         double-buffers. When the I2S module is started and TX
                                                                         is enabled, this event will be generated for every
                                                                         RXTXD.MAXCNT words that are sent on the SDOUT pin.*/
    __IM uint32_t RESERVED3;
    __IOM uint32_t EVENTS_FRAMESTART;                /*!< (@ 0x0000011C) Frame start event, generated on the active edge of
                                                                         LRCK*/
    __IM uint32_t RESERVED4[25];
    __IOM uint32_t PUBLISH_RXPTRUPD;                 /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD              */
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000188) Publish configuration for event STOPPED               */
    __IM uint32_t RESERVED5[2];
    __IOM uint32_t PUBLISH_TXPTRUPD;                 /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD              */
    __IM uint32_t RESERVED6;
    __IOM uint32_t PUBLISH_FRAMESTART;               /*!< (@ 0x0000019C) Publish configuration for event FRAMESTART            */
    __IM uint32_t RESERVED7[88];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED8[125];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable I2S module                                     */
    __IOM NRF_I2S_CONFIG_Type CONFIG;                /*!< (@ 0x00000504) (unspecified)                                         */
    __IM uint32_t RESERVED9[3];
    __IOM NRF_I2S_RXD_Type RXD;                      /*!< (@ 0x00000538) (unspecified)                                         */
    __IM uint32_t RESERVED10;
    __IOM NRF_I2S_TXD_Type TXD;                      /*!< (@ 0x00000540) (unspecified)                                         */
    __IM uint32_t RESERVED11[3];
    __IOM NRF_I2S_RXTXD_Type RXTXD;                  /*!< (@ 0x00000550) (unspecified)                                         */
    __IM uint32_t RESERVED12[3];
    __IOM NRF_I2S_PSEL_Type PSEL;                    /*!< (@ 0x00000560) (unspecified)                                         */
    __IM uint32_t RESERVED13[3];
    __IOM NRF_I2S_CHANNEL_Type CHANNEL[2];           /*!< (@ 0x00000580) (unspecified)                                         */
  } NRF_I2S_Type;                                    /*!< Size = 1424 (0x590)                                                  */

/* I2S_TASKS_START: Starts continuous I2S transfer. Also starts MCK generator when this is enabled */
  #define I2S_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled */
  #define I2S_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
  #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
  #define I2S_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
  #define I2S_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
  #define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */


/* I2S_TASKS_STOP: Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */
  #define I2S_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated.
                       */

  #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
  #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
  #define I2S_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
  #define I2S_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
  #define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* I2S_SUBSCRIBE_START: Subscribe configuration for task START */
  #define I2S_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define I2S_SUBSCRIBE_START_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define I2S_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define I2S_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
  #define I2S_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define I2S_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define I2S_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define I2S_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* I2S_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define I2S_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define I2S_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define I2S_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
  #define I2S_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define I2S_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define I2S_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
  #define I2S_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */


/* I2S_EVENTS_RXPTRUPD: The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX
                         is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */

  #define I2S_EVENTS_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXPTRUPD register.                          */

/* EVENTS_RXPTRUPD @Bit 0 : The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and
                            RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */

  #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field.                                */
  #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of
                                                                            EVENTS_RXPTRUPD field.*/
  #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXPTRUPD field.                  */
  #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXPTRUPD field.                  */
  #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated                                           */


/* I2S_EVENTS_STOPPED: I2S transfer stopped. */
  #define I2S_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */

/* EVENTS_STOPPED @Bit 0 : I2S transfer stopped. */
  #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
  #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
                                                                            field.*/
  #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
  #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
  #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */


/* I2S_EVENTS_TXPTRUPD: The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX
                         is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */

  #define I2S_EVENTS_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXPTRUPD register.                          */

/* EVENTS_TXPTRUPD @Bit 0 : The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and
                            TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT
                            pin. */

  #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field.                                */
  #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of
                                                                            EVENTS_TXPTRUPD field.*/
  #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXPTRUPD field.                  */
  #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXPTRUPD field.                  */
  #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated                                           */


/* I2S_EVENTS_FRAMESTART: Frame start event, generated on the active edge of LRCK */
  #define I2S_EVENTS_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMESTART register.                      */

/* EVENTS_FRAMESTART @Bit 0 : Frame start event, generated on the active edge of LRCK */
  #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field.                          */
  #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of
                                                                            EVENTS_FRAMESTART field.*/
  #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMESTART field.            */
  #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMESTART field.            */
  #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated                                       */


/* I2S_PUBLISH_RXPTRUPD: Publish configuration for event RXPTRUPD */
  #define I2S_PUBLISH_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXPTRUPD register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event RXPTRUPD will publish to */
  #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define I2S_PUBLISH_RXPTRUPD_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define I2S_PUBLISH_RXPTRUPD_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field.                        */
  #define I2S_PUBLISH_RXPTRUPD_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define I2S_PUBLISH_RXPTRUPD_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* I2S_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define I2S_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define I2S_PUBLISH_STOPPED_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define I2S_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define I2S_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
  #define I2S_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define I2S_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define I2S_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define I2S_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* I2S_PUBLISH_TXPTRUPD: Publish configuration for event TXPTRUPD */
  #define I2S_PUBLISH_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXPTRUPD register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event TXPTRUPD will publish to */
  #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define I2S_PUBLISH_TXPTRUPD_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define I2S_PUBLISH_TXPTRUPD_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field.                        */
  #define I2S_PUBLISH_TXPTRUPD_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define I2S_PUBLISH_TXPTRUPD_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* I2S_PUBLISH_FRAMESTART: Publish configuration for event FRAMESTART */
  #define I2S_PUBLISH_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMESTART register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that event FRAMESTART will publish to */
  #define I2S_PUBLISH_FRAMESTART_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define I2S_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << I2S_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define I2S_PUBLISH_FRAMESTART_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define I2S_PUBLISH_FRAMESTART_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define I2S_PUBLISH_FRAMESTART_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define I2S_PUBLISH_FRAMESTART_EN_Msk (0x1UL << I2S_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field.                    */
  #define I2S_PUBLISH_FRAMESTART_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define I2S_PUBLISH_FRAMESTART_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define I2S_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define I2S_PUBLISH_FRAMESTART_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* I2S_INTEN: Enable or disable interrupt */
  #define I2S_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */

/* RXPTRUPD @Bit 1 : Enable or disable interrupt for event RXPTRUPD */
  #define I2S_INTEN_RXPTRUPD_Pos (1UL)               /*!< Position of RXPTRUPD field.                                          */
  #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field.                            */
  #define I2S_INTEN_RXPTRUPD_Min (0x0UL)             /*!< Min enumerator value of RXPTRUPD field.                              */
  #define I2S_INTEN_RXPTRUPD_Max (0x1UL)             /*!< Max enumerator value of RXPTRUPD field.                              */
  #define I2S_INTEN_RXPTRUPD_Disabled (0x0UL)        /*!< Disable                                                              */
  #define I2S_INTEN_RXPTRUPD_Enabled (0x1UL)         /*!< Enable                                                               */

/* STOPPED @Bit 2 : Enable or disable interrupt for event STOPPED */
  #define I2S_INTEN_STOPPED_Pos (2UL)                /*!< Position of STOPPED field.                                           */
  #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                               */
  #define I2S_INTEN_STOPPED_Min (0x0UL)              /*!< Min enumerator value of STOPPED field.                               */
  #define I2S_INTEN_STOPPED_Max (0x1UL)              /*!< Max enumerator value of STOPPED field.                               */
  #define I2S_INTEN_STOPPED_Disabled (0x0UL)         /*!< Disable                                                              */
  #define I2S_INTEN_STOPPED_Enabled (0x1UL)          /*!< Enable                                                               */

/* TXPTRUPD @Bit 5 : Enable or disable interrupt for event TXPTRUPD */
  #define I2S_INTEN_TXPTRUPD_Pos (5UL)               /*!< Position of TXPTRUPD field.                                          */
  #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field.                            */
  #define I2S_INTEN_TXPTRUPD_Min (0x0UL)             /*!< Min enumerator value of TXPTRUPD field.                              */
  #define I2S_INTEN_TXPTRUPD_Max (0x1UL)             /*!< Max enumerator value of TXPTRUPD field.                              */
  #define I2S_INTEN_TXPTRUPD_Disabled (0x0UL)        /*!< Disable                                                              */
  #define I2S_INTEN_TXPTRUPD_Enabled (0x1UL)         /*!< Enable                                                               */

/* FRAMESTART @Bit 7 : Enable or disable interrupt for event FRAMESTART */
  #define I2S_INTEN_FRAMESTART_Pos (7UL)             /*!< Position of FRAMESTART field.                                        */
  #define I2S_INTEN_FRAMESTART_Msk (0x1UL << I2S_INTEN_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.                      */
  #define I2S_INTEN_FRAMESTART_Min (0x0UL)           /*!< Min enumerator value of FRAMESTART field.                            */
  #define I2S_INTEN_FRAMESTART_Max (0x1UL)           /*!< Max enumerator value of FRAMESTART field.                            */
  #define I2S_INTEN_FRAMESTART_Disabled (0x0UL)      /*!< Disable                                                              */
  #define I2S_INTEN_FRAMESTART_Enabled (0x1UL)       /*!< Enable                                                               */


/* I2S_INTENSET: Enable interrupt */
  #define I2S_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* RXPTRUPD @Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
  #define I2S_INTENSET_RXPTRUPD_Pos (1UL)            /*!< Position of RXPTRUPD field.                                          */
  #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field.                      */
  #define I2S_INTENSET_RXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of RXPTRUPD field.                              */
  #define I2S_INTENSET_RXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of RXPTRUPD field.                              */
  #define I2S_INTENSET_RXPTRUPD_Set (0x1UL)          /*!< Enable                                                               */
  #define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* STOPPED @Bit 2 : Write '1' to enable interrupt for event STOPPED */
  #define I2S_INTENSET_STOPPED_Pos (2UL)             /*!< Position of STOPPED field.                                           */
  #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define I2S_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define I2S_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define I2S_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
  #define I2S_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define I2S_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* TXPTRUPD @Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
  #define I2S_INTENSET_TXPTRUPD_Pos (5UL)            /*!< Position of TXPTRUPD field.                                          */
  #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field.                      */
  #define I2S_INTENSET_TXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of TXPTRUPD field.                              */
  #define I2S_INTENSET_TXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of TXPTRUPD field.                              */
  #define I2S_INTENSET_TXPTRUPD_Set (0x1UL)          /*!< Enable                                                               */
  #define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* FRAMESTART @Bit 7 : Write '1' to enable interrupt for event FRAMESTART */
  #define I2S_INTENSET_FRAMESTART_Pos (7UL)          /*!< Position of FRAMESTART field.                                        */
  #define I2S_INTENSET_FRAMESTART_Msk (0x1UL << I2S_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.                */
  #define I2S_INTENSET_FRAMESTART_Min (0x0UL)        /*!< Min enumerator value of FRAMESTART field.                            */
  #define I2S_INTENSET_FRAMESTART_Max (0x1UL)        /*!< Max enumerator value of FRAMESTART field.                            */
  #define I2S_INTENSET_FRAMESTART_Set (0x1UL)        /*!< Enable                                                               */
  #define I2S_INTENSET_FRAMESTART_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define I2S_INTENSET_FRAMESTART_Enabled (0x1UL)    /*!< Read: Enabled                                                        */


/* I2S_INTENCLR: Disable interrupt */
  #define I2S_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* RXPTRUPD @Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
  #define I2S_INTENCLR_RXPTRUPD_Pos (1UL)            /*!< Position of RXPTRUPD field.                                          */
  #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field.                      */
  #define I2S_INTENCLR_RXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of RXPTRUPD field.                              */
  #define I2S_INTENCLR_RXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of RXPTRUPD field.                              */
  #define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL)        /*!< Disable                                                              */
  #define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* STOPPED @Bit 2 : Write '1' to disable interrupt for event STOPPED */
  #define I2S_INTENCLR_STOPPED_Pos (2UL)             /*!< Position of STOPPED field.                                           */
  #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define I2S_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define I2S_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define I2S_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
  #define I2S_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define I2S_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* TXPTRUPD @Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
  #define I2S_INTENCLR_TXPTRUPD_Pos (5UL)            /*!< Position of TXPTRUPD field.                                          */
  #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field.                      */
  #define I2S_INTENCLR_TXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of TXPTRUPD field.                              */
  #define I2S_INTENCLR_TXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of TXPTRUPD field.                              */
  #define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL)        /*!< Disable                                                              */
  #define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* FRAMESTART @Bit 7 : Write '1' to disable interrupt for event FRAMESTART */
  #define I2S_INTENCLR_FRAMESTART_Pos (7UL)          /*!< Position of FRAMESTART field.                                        */
  #define I2S_INTENCLR_FRAMESTART_Msk (0x1UL << I2S_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.                */
  #define I2S_INTENCLR_FRAMESTART_Min (0x0UL)        /*!< Min enumerator value of FRAMESTART field.                            */
  #define I2S_INTENCLR_FRAMESTART_Max (0x1UL)        /*!< Max enumerator value of FRAMESTART field.                            */
  #define I2S_INTENCLR_FRAMESTART_Clear (0x1UL)      /*!< Disable                                                              */
  #define I2S_INTENCLR_FRAMESTART_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define I2S_INTENCLR_FRAMESTART_Enabled (0x1UL)    /*!< Read: Enabled                                                        */


/* I2S_ENABLE: Enable I2S module */
  #define I2S_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bit 0 : Enable I2S module */
  #define I2S_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
  #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
  #define I2S_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
  #define I2S_ENABLE_ENABLE_Max (0x1UL)              /*!< Max enumerator value of ENABLE field.                                */
  #define I2S_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
  #define I2S_ENABLE_ENABLE_Enabled (0x1UL)          /*!< Enable                                                               */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            KMU                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct KMU ======================================================== */
/**
  * @brief Key management unit
  */
  typedef struct {                                   /*!< KMU Structure                                                        */
    __OM uint32_t TASKS_PROVISION;                   /*!< (@ 0x00000000) Provision key slot                                    */
    __OM uint32_t TASKS_PUSH;                        /*!< (@ 0x00000004) Push key slot                                         */
    __OM uint32_t TASKS_REVOKE;                      /*!< (@ 0x00000008) Revoke key slot                                       */
    __OM uint32_t TASKS_READMETADATA;                /*!< (@ 0x0000000C) Read key slot metadata into METADATA register         */
    __OM uint32_t TASKS_PUSHBLOCK;                   /*!< (@ 0x00000010) Block only the PUSH operation of a key slot, preventing
                                                                         the key slot from being PUSHED until next reset. The
                                                                         task is kept for backwards compatibility.*/
    __IM uint32_t RESERVED[59];
    __IOM uint32_t EVENTS_PROVISIONED;               /*!< (@ 0x00000100) Key slot successfully provisioned                     */
    __IOM uint32_t EVENTS_PUSHED;                    /*!< (@ 0x00000104) Key slot successfully pushed                          */
    __IOM uint32_t EVENTS_REVOKED;                   /*!< (@ 0x00000108) Key slot has been revoked and can no longer be used   */
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x0000010C) Error generated during PROVISION, PUSH, READMETADATA or
                                                                         REVOKE operations. Triggering the PROVISION, PUSH and
                                                                         REVOKE tasks on a BLOCKED keyslot will also generate
                                                                         this event.*/
    __IOM uint32_t EVENTS_METADATAREAD;              /*!< (@ 0x00000110) Key slot metadata has been read into METADATA register*/
    __IOM uint32_t EVENTS_PUSHBLOCKED;               /*!< (@ 0x00000114) The PUSHBLOCK operation was successful. The event is
                                                                         kept for backwards compatibility.*/
    __IM uint32_t RESERVED1[186];
    __IM uint32_t STATUS;                            /*!< (@ 0x00000400) KMU status register                                   */
    __IM uint32_t RESERVED2[63];
    __IOM uint32_t KEYSLOT;                          /*!< (@ 0x00000500) Select key slot to operate on                         */
    __IOM uint32_t SRC;                              /*!< (@ 0x00000504) Source address for provisioning                       */
    __IOM uint32_t METADATA;                         /*!< (@ 0x00000508) Key slot metadata as read by TASKS_READMETADATA.      */
  } NRF_KMU_Type;                                    /*!< Size = 1292 (0x50C)                                                  */

/* KMU_TASKS_PROVISION: Provision key slot */
  #define KMU_TASKS_PROVISION_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PROVISION register.                          */

/* TASKS_PROVISION @Bit 0 : Provision key slot */
  #define KMU_TASKS_PROVISION_TASKS_PROVISION_Pos (0UL) /*!< Position of TASKS_PROVISION field.                                */
  #define KMU_TASKS_PROVISION_TASKS_PROVISION_Msk (0x1UL << KMU_TASKS_PROVISION_TASKS_PROVISION_Pos) /*!< Bit mask of
                                                                            TASKS_PROVISION field.*/
  #define KMU_TASKS_PROVISION_TASKS_PROVISION_Min (0x1UL) /*!< Min enumerator value of TASKS_PROVISION field.                  */
  #define KMU_TASKS_PROVISION_TASKS_PROVISION_Max (0x1UL) /*!< Max enumerator value of TASKS_PROVISION field.                  */
  #define KMU_TASKS_PROVISION_TASKS_PROVISION_Trigger (0x1UL) /*!< Trigger task                                                */


/* KMU_TASKS_PUSH: Push key slot */
  #define KMU_TASKS_PUSH_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_PUSH register.                                  */

/* TASKS_PUSH @Bit 0 : Push key slot */
  #define KMU_TASKS_PUSH_TASKS_PUSH_Pos (0UL)        /*!< Position of TASKS_PUSH field.                                        */
  #define KMU_TASKS_PUSH_TASKS_PUSH_Msk (0x1UL << KMU_TASKS_PUSH_TASKS_PUSH_Pos) /*!< Bit mask of TASKS_PUSH field.            */
  #define KMU_TASKS_PUSH_TASKS_PUSH_Min (0x1UL)      /*!< Min enumerator value of TASKS_PUSH field.                            */
  #define KMU_TASKS_PUSH_TASKS_PUSH_Max (0x1UL)      /*!< Max enumerator value of TASKS_PUSH field.                            */
  #define KMU_TASKS_PUSH_TASKS_PUSH_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* KMU_TASKS_REVOKE: Revoke key slot */
  #define KMU_TASKS_REVOKE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_REVOKE register.                                */

/* TASKS_REVOKE @Bit 0 : Revoke key slot */
  #define KMU_TASKS_REVOKE_TASKS_REVOKE_Pos (0UL)    /*!< Position of TASKS_REVOKE field.                                      */
  #define KMU_TASKS_REVOKE_TASKS_REVOKE_Msk (0x1UL << KMU_TASKS_REVOKE_TASKS_REVOKE_Pos) /*!< Bit mask of TASKS_REVOKE field.  */
  #define KMU_TASKS_REVOKE_TASKS_REVOKE_Min (0x1UL)  /*!< Min enumerator value of TASKS_REVOKE field.                          */
  #define KMU_TASKS_REVOKE_TASKS_REVOKE_Max (0x1UL)  /*!< Max enumerator value of TASKS_REVOKE field.                          */
  #define KMU_TASKS_REVOKE_TASKS_REVOKE_Trigger (0x1UL) /*!< Trigger task                                                      */


/* KMU_TASKS_READMETADATA: Read key slot metadata into METADATA register */
  #define KMU_TASKS_READMETADATA_ResetValue (0x00000000UL) /*!< Reset value of TASKS_READMETADATA register.                    */

/* TASKS_READMETADATA @Bit 0 : Read key slot metadata into METADATA register */
  #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Pos (0UL) /*!< Position of TASKS_READMETADATA field.                       */
  #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Msk (0x1UL << KMU_TASKS_READMETADATA_TASKS_READMETADATA_Pos) /*!< Bit mask
                                                                            of TASKS_READMETADATA field.*/
  #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Min (0x1UL) /*!< Min enumerator value of TASKS_READMETADATA field.         */
  #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Max (0x1UL) /*!< Max enumerator value of TASKS_READMETADATA field.         */
  #define KMU_TASKS_READMETADATA_TASKS_READMETADATA_Trigger (0x1UL) /*!< Trigger task                                          */


/* KMU_TASKS_PUSHBLOCK: Block only the PUSH operation of a key slot, preventing the key slot from being PUSHED until next reset.
                         The task is kept for backwards compatibility. */

  #define KMU_TASKS_PUSHBLOCK_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PUSHBLOCK register.                          */

/* TASKS_PUSHBLOCK @Bit 0 : Block only the PUSH operation of a key slot, preventing the key slot from being PUSHED until next
                            reset. The task is kept for backwards compatibility. */

  #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Pos (0UL) /*!< Position of TASKS_PUSHBLOCK field.                                */
  #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Msk (0x1UL << KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Pos) /*!< Bit mask of
                                                                            TASKS_PUSHBLOCK field.*/
  #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Min (0x1UL) /*!< Min enumerator value of TASKS_PUSHBLOCK field.                  */
  #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Max (0x1UL) /*!< Max enumerator value of TASKS_PUSHBLOCK field.                  */
  #define KMU_TASKS_PUSHBLOCK_TASKS_PUSHBLOCK_Trigger (0x1UL) /*!< Trigger task                                                */


/* KMU_EVENTS_PROVISIONED: Key slot successfully provisioned */
  #define KMU_EVENTS_PROVISIONED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PROVISIONED register.                    */

/* EVENTS_PROVISIONED @Bit 0 : Key slot successfully provisioned */
  #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Pos (0UL) /*!< Position of EVENTS_PROVISIONED field.                       */
  #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Msk (0x1UL << KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Pos) /*!< Bit mask
                                                                            of EVENTS_PROVISIONED field.*/
  #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PROVISIONED field.         */
  #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PROVISIONED field.         */
  #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define KMU_EVENTS_PROVISIONED_EVENTS_PROVISIONED_Generated (0x1UL) /*!< Event generated                                     */


/* KMU_EVENTS_PUSHED: Key slot successfully pushed */
  #define KMU_EVENTS_PUSHED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PUSHED register.                              */

/* EVENTS_PUSHED @Bit 0 : Key slot successfully pushed */
  #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Pos (0UL)  /*!< Position of EVENTS_PUSHED field.                                     */
  #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Msk (0x1UL << KMU_EVENTS_PUSHED_EVENTS_PUSHED_Pos) /*!< Bit mask of EVENTS_PUSHED
                                                                            field.*/
  #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PUSHED field.                        */
  #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PUSHED field.                        */
  #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define KMU_EVENTS_PUSHED_EVENTS_PUSHED_Generated (0x1UL) /*!< Event generated                                               */


/* KMU_EVENTS_REVOKED: Key slot has been revoked and can no longer be used */
  #define KMU_EVENTS_REVOKED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_REVOKED register.                            */

/* EVENTS_REVOKED @Bit 0 : Key slot has been revoked and can no longer be used */
  #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Pos (0UL) /*!< Position of EVENTS_REVOKED field.                                   */
  #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Msk (0x1UL << KMU_EVENTS_REVOKED_EVENTS_REVOKED_Pos) /*!< Bit mask of EVENTS_REVOKED
                                                                            field.*/
  #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Min (0x0UL) /*!< Min enumerator value of EVENTS_REVOKED field.                     */
  #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Max (0x1UL) /*!< Max enumerator value of EVENTS_REVOKED field.                     */
  #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define KMU_EVENTS_REVOKED_EVENTS_REVOKED_Generated (0x1UL) /*!< Event generated                                             */


/* KMU_EVENTS_ERROR: Error generated during PROVISION, PUSH, READMETADATA or REVOKE operations. Triggering the PROVISION, PUSH
                      and REVOKE tasks on a BLOCKED keyslot will also generate this event. */

  #define KMU_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                                */

/* EVENTS_ERROR @Bit 0 : Error generated during PROVISION, PUSH, READMETADATA or REVOKE operations. Triggering the PROVISION,
                         PUSH and REVOKE tasks on a BLOCKED keyslot will also generate this event. */

  #define KMU_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)    /*!< Position of EVENTS_ERROR field.                                      */
  #define KMU_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << KMU_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.  */
  #define KMU_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL)  /*!< Min enumerator value of EVENTS_ERROR field.                          */
  #define KMU_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL)  /*!< Max enumerator value of EVENTS_ERROR field.                          */
  #define KMU_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define KMU_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                 */


/* KMU_EVENTS_METADATAREAD: Key slot metadata has been read into METADATA register */
  #define KMU_EVENTS_METADATAREAD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_METADATAREAD register.                  */

/* EVENTS_METADATAREAD @Bit 0 : Key slot metadata has been read into METADATA register */
  #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Pos (0UL) /*!< Position of EVENTS_METADATAREAD field.                    */
  #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Msk (0x1UL << KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Pos) /*!< Bit
                                                                            mask of EVENTS_METADATAREAD field.*/
  #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Min (0x0UL) /*!< Min enumerator value of EVENTS_METADATAREAD field.      */
  #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Max (0x1UL) /*!< Max enumerator value of EVENTS_METADATAREAD field.      */
  #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_NotGenerated (0x0UL) /*!< Event not generated                            */
  #define KMU_EVENTS_METADATAREAD_EVENTS_METADATAREAD_Generated (0x1UL) /*!< Event generated                                   */


/* KMU_EVENTS_PUSHBLOCKED: The PUSHBLOCK operation was successful. The event is kept for backwards compatibility. */
  #define KMU_EVENTS_PUSHBLOCKED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PUSHBLOCKED register.                    */

/* EVENTS_PUSHBLOCKED @Bit 0 : The PUSHBLOCK operation was successful. The event is kept for backwards compatibility. */
  #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Pos (0UL) /*!< Position of EVENTS_PUSHBLOCKED field.                       */
  #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Msk (0x1UL << KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Pos) /*!< Bit mask
                                                                            of EVENTS_PUSHBLOCKED field.*/
  #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Min (0x0UL) /*!< Min enumerator value of EVENTS_PUSHBLOCKED field.         */
  #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Max (0x1UL) /*!< Max enumerator value of EVENTS_PUSHBLOCKED field.         */
  #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define KMU_EVENTS_PUSHBLOCKED_EVENTS_PUSHBLOCKED_Generated (0x1UL) /*!< Event generated                                     */


/* KMU_STATUS: KMU status register */
  #define KMU_STATUS_ResetValue (0x00000000UL)       /*!< Reset value of STATUS register.                                      */

/* STATUS @Bit 0 : KMU status */
  #define KMU_STATUS_STATUS_Pos (0UL)                /*!< Position of STATUS field.                                            */
  #define KMU_STATUS_STATUS_Msk (0x1UL << KMU_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field.                                */
  #define KMU_STATUS_STATUS_Min (0x0UL)              /*!< Min enumerator value of STATUS field.                                */
  #define KMU_STATUS_STATUS_Max (0x1UL)              /*!< Max enumerator value of STATUS field.                                */
  #define KMU_STATUS_STATUS_Ready (0x0UL)            /*!< KMU is ready for new operation                                       */
  #define KMU_STATUS_STATUS_Busy (0x1UL)             /*!< KMU is busy, an operation is in progress                             */


/* KMU_KEYSLOT: Select key slot to operate on */
  #define KMU_KEYSLOT_ResetValue (0x00000000UL)      /*!< Reset value of KEYSLOT register.                                     */

/* ID @Bits 0..7 : Select key slot ID to provision, push, read METADATA, revoke or block when the corresponding task is
                   triggered. */

  #define KMU_KEYSLOT_ID_Pos (0UL)                   /*!< Position of ID field.                                                */
  #define KMU_KEYSLOT_ID_Msk (0xFFUL << KMU_KEYSLOT_ID_Pos) /*!< Bit mask of ID field.                                         */
  #define KMU_KEYSLOT_ID_Min (0x00UL)                /*!< Min value of ID field.                                               */
  #define KMU_KEYSLOT_ID_Max (0xF9UL)                /*!< Max size of ID field.                                                */


/* KMU_SRC: Source address for provisioning */
  #define KMU_SRC_ResetValue (0x00000000UL)          /*!< Reset value of SRC register.                                         */

/* SRC @Bits 0..31 : Source address for TASKS_PROVISION. */
  #define KMU_SRC_SRC_Pos (0UL)                      /*!< Position of SRC field.                                               */
  #define KMU_SRC_SRC_Msk (0xFFFFFFFFUL << KMU_SRC_SRC_Pos) /*!< Bit mask of SRC field.                                        */


/* KMU_METADATA: Key slot metadata as read by TASKS_READMETADATA. */
  #define KMU_METADATA_ResetValue (0x00000000UL)     /*!< Reset value of METADATA register.                                    */

/* METADATA @Bits 0..31 : Read metadata. */
  #define KMU_METADATA_METADATA_Pos (0UL)            /*!< Position of METADATA field.                                          */
  #define KMU_METADATA_METADATA_Msk (0xFFFFFFFFUL << KMU_METADATA_METADATA_Pos) /*!< Bit mask of METADATA field.               */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                          LPCOMP                                          ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ====================================================== Struct LPCOMP ====================================================== */
/**
  * @brief Low-power comparator
  */
  typedef struct {                                   /*!< LPCOMP Structure                                                     */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start comparator                                      */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop comparator                                       */
    __OM uint32_t TASKS_SAMPLE;                      /*!< (@ 0x00000008) Sample comparator value. This task requires that LPCOMP
                                                                         has been started by the START task.*/
    __IM uint32_t RESERVED[29];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_SAMPLE;                 /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE               */
    __IM uint32_t RESERVED1[29];
    __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000100) LPCOMP is ready and output is valid                   */
    __IOM uint32_t EVENTS_DOWN;                      /*!< (@ 0x00000104) Downward crossing                                     */
    __IOM uint32_t EVENTS_UP;                        /*!< (@ 0x00000108) Upward crossing                                       */
    __IOM uint32_t EVENTS_CROSS;                     /*!< (@ 0x0000010C) Downward or upward crossing                           */
    __IM uint32_t RESERVED2[28];
    __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000180) Publish configuration for event READY                 */
    __IOM uint32_t PUBLISH_DOWN;                     /*!< (@ 0x00000184) Publish configuration for event DOWN                  */
    __IOM uint32_t PUBLISH_UP;                       /*!< (@ 0x00000188) Publish configuration for event UP                    */
    __IOM uint32_t PUBLISH_CROSS;                    /*!< (@ 0x0000018C) Publish configuration for event CROSS                 */
    __IM uint32_t RESERVED3[28];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED4[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED5[60];
    __IM uint32_t RESULT;                            /*!< (@ 0x00000400) Compare result                                        */
    __IM uint32_t RESERVED6[63];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable LPCOMP                                         */
    __IOM uint32_t PSEL;                             /*!< (@ 0x00000504) Input pin select                                      */
    __IOM uint32_t REFSEL;                           /*!< (@ 0x00000508) Reference select                                      */
    __IOM uint32_t EXTREFSEL;                        /*!< (@ 0x0000050C) External reference select                             */
    __IM uint32_t RESERVED7[4];
    __IOM uint32_t ANADETECT;                        /*!< (@ 0x00000520) Analog detect configuration                           */
    __IM uint32_t RESERVED8[5];
    __IOM uint32_t HYST;                             /*!< (@ 0x00000538) Comparator hysteresis enable                          */
  } NRF_LPCOMP_Type;                                 /*!< Size = 1340 (0x53C)                                                  */

/* LPCOMP_TASKS_START: Start comparator */
  #define LPCOMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                               */

/* TASKS_START @Bit 0 : Start comparator */
  #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL)   /*!< Position of TASKS_START field.                                       */
  #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
  #define LPCOMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field.                           */
  #define LPCOMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field.                           */
  #define LPCOMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                     */


/* LPCOMP_TASKS_STOP: Stop comparator */
  #define LPCOMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                 */

/* TASKS_STOP @Bit 0 : Stop comparator */
  #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL)     /*!< Position of TASKS_STOP field.                                        */
  #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.      */
  #define LPCOMP_TASKS_STOP_TASKS_STOP_Min (0x1UL)   /*!< Min enumerator value of TASKS_STOP field.                            */
  #define LPCOMP_TASKS_STOP_TASKS_STOP_Max (0x1UL)   /*!< Max enumerator value of TASKS_STOP field.                            */
  #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                       */


/* LPCOMP_TASKS_SAMPLE: Sample comparator value. This task requires that LPCOMP has been started by the START task. */
  #define LPCOMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register.                             */

/* TASKS_SAMPLE @Bit 0 : Sample comparator value. This task requires that LPCOMP has been started by the START task. */
  #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field.                                      */
  #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE
                                                                            field.*/
  #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field.                        */
  #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field.                        */
  #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task                                                   */


/* LPCOMP_SUBSCRIBE_START: Subscribe configuration for task START */
  #define LPCOMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define LPCOMP_SUBSCRIBE_START_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define LPCOMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define LPCOMP_SUBSCRIBE_START_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define LPCOMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define LPCOMP_SUBSCRIBE_START_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define LPCOMP_SUBSCRIBE_START_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                    */
  #define LPCOMP_SUBSCRIBE_START_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define LPCOMP_SUBSCRIBE_START_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define LPCOMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define LPCOMP_SUBSCRIBE_START_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* LPCOMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define LPCOMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define LPCOMP_SUBSCRIBE_STOP_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define LPCOMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                      */
  #define LPCOMP_SUBSCRIBE_STOP_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define LPCOMP_SUBSCRIBE_STOP_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define LPCOMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define LPCOMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* LPCOMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */
  #define LPCOMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */
  #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field.                  */
  #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* LPCOMP_EVENTS_READY: LPCOMP is ready and output is valid */
  #define LPCOMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                             */

/* EVENTS_READY @Bit 0 : LPCOMP is ready and output is valid */
  #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field.                                      */
  #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY
                                                                            field.*/
  #define LPCOMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                        */
  #define LPCOMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                        */
  #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                              */


/* LPCOMP_EVENTS_DOWN: Downward crossing */
  #define LPCOMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register.                               */

/* EVENTS_DOWN @Bit 0 : Downward crossing */
  #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL)   /*!< Position of EVENTS_DOWN field.                                       */
  #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
  #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL) /*!< Min enumerator value of EVENTS_DOWN field.                           */
  #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL) /*!< Max enumerator value of EVENTS_DOWN field.                           */
  #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated                                                */


/* LPCOMP_EVENTS_UP: Upward crossing */
  #define LPCOMP_EVENTS_UP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_UP register.                                   */

/* EVENTS_UP @Bit 0 : Upward crossing */
  #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL)       /*!< Position of EVENTS_UP field.                                         */
  #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field.           */
  #define LPCOMP_EVENTS_UP_EVENTS_UP_Min (0x0UL)     /*!< Min enumerator value of EVENTS_UP field.                             */
  #define LPCOMP_EVENTS_UP_EVENTS_UP_Max (0x1UL)     /*!< Max enumerator value of EVENTS_UP field.                             */
  #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated                                                    */


/* LPCOMP_EVENTS_CROSS: Downward or upward crossing */
  #define LPCOMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register.                             */

/* EVENTS_CROSS @Bit 0 : Downward or upward crossing */
  #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field.                                      */
  #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS
                                                                            field.*/
  #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field.                        */
  #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field.                        */
  #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated                                              */


/* LPCOMP_PUBLISH_READY: Publish configuration for event READY */
  #define LPCOMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define LPCOMP_PUBLISH_READY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define LPCOMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define LPCOMP_PUBLISH_READY_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define LPCOMP_PUBLISH_READY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define LPCOMP_PUBLISH_READY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define LPCOMP_PUBLISH_READY_EN_Msk (0x1UL << LPCOMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                        */
  #define LPCOMP_PUBLISH_READY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_READY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_READY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define LPCOMP_PUBLISH_READY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* LPCOMP_PUBLISH_DOWN: Publish configuration for event DOWN */
  #define LPCOMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */
  #define LPCOMP_PUBLISH_DOWN_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define LPCOMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define LPCOMP_PUBLISH_DOWN_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define LPCOMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define LPCOMP_PUBLISH_DOWN_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define LPCOMP_PUBLISH_DOWN_EN_Msk (0x1UL << LPCOMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field.                          */
  #define LPCOMP_PUBLISH_DOWN_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_DOWN_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_DOWN_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define LPCOMP_PUBLISH_DOWN_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* LPCOMP_PUBLISH_UP: Publish configuration for event UP */
  #define LPCOMP_PUBLISH_UP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_UP register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */
  #define LPCOMP_PUBLISH_UP_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define LPCOMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define LPCOMP_PUBLISH_UP_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define LPCOMP_PUBLISH_UP_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define LPCOMP_PUBLISH_UP_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define LPCOMP_PUBLISH_UP_EN_Msk (0x1UL << LPCOMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field.                              */
  #define LPCOMP_PUBLISH_UP_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_UP_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_UP_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define LPCOMP_PUBLISH_UP_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* LPCOMP_PUBLISH_CROSS: Publish configuration for event CROSS */
  #define LPCOMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */
  #define LPCOMP_PUBLISH_CROSS_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define LPCOMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define LPCOMP_PUBLISH_CROSS_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define LPCOMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define LPCOMP_PUBLISH_CROSS_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define LPCOMP_PUBLISH_CROSS_EN_Msk (0x1UL << LPCOMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field.                        */
  #define LPCOMP_PUBLISH_CROSS_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_CROSS_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define LPCOMP_PUBLISH_CROSS_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define LPCOMP_PUBLISH_CROSS_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* LPCOMP_SHORTS: Shortcuts between local events and tasks */
  #define LPCOMP_SHORTS_ResetValue (0x00000000UL)    /*!< Reset value of SHORTS register.                                      */

/* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */
  #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL)       /*!< Position of READY_SAMPLE field.                                      */
  #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field.        */
  #define LPCOMP_SHORTS_READY_SAMPLE_Min (0x0UL)     /*!< Min enumerator value of READY_SAMPLE field.                          */
  #define LPCOMP_SHORTS_READY_SAMPLE_Max (0x1UL)     /*!< Max enumerator value of READY_SAMPLE field.                          */
  #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */
  #define LPCOMP_SHORTS_READY_STOP_Pos (1UL)         /*!< Position of READY_STOP field.                                        */
  #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field.              */
  #define LPCOMP_SHORTS_READY_STOP_Min (0x0UL)       /*!< Min enumerator value of READY_STOP field.                            */
  #define LPCOMP_SHORTS_READY_STOP_Max (0x1UL)       /*!< Max enumerator value of READY_STOP field.                            */
  #define LPCOMP_SHORTS_READY_STOP_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
  #define LPCOMP_SHORTS_READY_STOP_Enabled (0x1UL)   /*!< Enable shortcut                                                      */

/* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */
  #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL)          /*!< Position of DOWN_STOP field.                                         */
  #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field.                 */
  #define LPCOMP_SHORTS_DOWN_STOP_Min (0x0UL)        /*!< Min enumerator value of DOWN_STOP field.                             */
  #define LPCOMP_SHORTS_DOWN_STOP_Max (0x1UL)        /*!< Max enumerator value of DOWN_STOP field.                             */
  #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
  #define LPCOMP_SHORTS_DOWN_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */

/* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */
  #define LPCOMP_SHORTS_UP_STOP_Pos (3UL)            /*!< Position of UP_STOP field.                                           */
  #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field.                       */
  #define LPCOMP_SHORTS_UP_STOP_Min (0x0UL)          /*!< Min enumerator value of UP_STOP field.                               */
  #define LPCOMP_SHORTS_UP_STOP_Max (0x1UL)          /*!< Max enumerator value of UP_STOP field.                               */
  #define LPCOMP_SHORTS_UP_STOP_Disabled (0x0UL)     /*!< Disable shortcut                                                     */
  #define LPCOMP_SHORTS_UP_STOP_Enabled (0x1UL)      /*!< Enable shortcut                                                      */

/* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */
  #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL)         /*!< Position of CROSS_STOP field.                                        */
  #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field.              */
  #define LPCOMP_SHORTS_CROSS_STOP_Min (0x0UL)       /*!< Min enumerator value of CROSS_STOP field.                            */
  #define LPCOMP_SHORTS_CROSS_STOP_Max (0x1UL)       /*!< Max enumerator value of CROSS_STOP field.                            */
  #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
  #define LPCOMP_SHORTS_CROSS_STOP_Enabled (0x1UL)   /*!< Enable shortcut                                                      */


/* LPCOMP_INTEN: Enable or disable interrupt */
  #define LPCOMP_INTEN_ResetValue (0x00000000UL)     /*!< Reset value of INTEN register.                                       */

/* READY @Bit 0 : Enable or disable interrupt for event READY */
  #define LPCOMP_INTEN_READY_Pos (0UL)               /*!< Position of READY field.                                             */
  #define LPCOMP_INTEN_READY_Msk (0x1UL << LPCOMP_INTEN_READY_Pos) /*!< Bit mask of READY field.                               */
  #define LPCOMP_INTEN_READY_Min (0x0UL)             /*!< Min enumerator value of READY field.                                 */
  #define LPCOMP_INTEN_READY_Max (0x1UL)             /*!< Max enumerator value of READY field.                                 */
  #define LPCOMP_INTEN_READY_Disabled (0x0UL)        /*!< Disable                                                              */
  #define LPCOMP_INTEN_READY_Enabled (0x1UL)         /*!< Enable                                                               */

/* DOWN @Bit 1 : Enable or disable interrupt for event DOWN */
  #define LPCOMP_INTEN_DOWN_Pos (1UL)                /*!< Position of DOWN field.                                              */
  #define LPCOMP_INTEN_DOWN_Msk (0x1UL << LPCOMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field.                                  */
  #define LPCOMP_INTEN_DOWN_Min (0x0UL)              /*!< Min enumerator value of DOWN field.                                  */
  #define LPCOMP_INTEN_DOWN_Max (0x1UL)              /*!< Max enumerator value of DOWN field.                                  */
  #define LPCOMP_INTEN_DOWN_Disabled (0x0UL)         /*!< Disable                                                              */
  #define LPCOMP_INTEN_DOWN_Enabled (0x1UL)          /*!< Enable                                                               */

/* UP @Bit 2 : Enable or disable interrupt for event UP */
  #define LPCOMP_INTEN_UP_Pos (2UL)                  /*!< Position of UP field.                                                */
  #define LPCOMP_INTEN_UP_Msk (0x1UL << LPCOMP_INTEN_UP_Pos) /*!< Bit mask of UP field.                                        */
  #define LPCOMP_INTEN_UP_Min (0x0UL)                /*!< Min enumerator value of UP field.                                    */
  #define LPCOMP_INTEN_UP_Max (0x1UL)                /*!< Max enumerator value of UP field.                                    */
  #define LPCOMP_INTEN_UP_Disabled (0x0UL)           /*!< Disable                                                              */
  #define LPCOMP_INTEN_UP_Enabled (0x1UL)            /*!< Enable                                                               */

/* CROSS @Bit 3 : Enable or disable interrupt for event CROSS */
  #define LPCOMP_INTEN_CROSS_Pos (3UL)               /*!< Position of CROSS field.                                             */
  #define LPCOMP_INTEN_CROSS_Msk (0x1UL << LPCOMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field.                               */
  #define LPCOMP_INTEN_CROSS_Min (0x0UL)             /*!< Min enumerator value of CROSS field.                                 */
  #define LPCOMP_INTEN_CROSS_Max (0x1UL)             /*!< Max enumerator value of CROSS field.                                 */
  #define LPCOMP_INTEN_CROSS_Disabled (0x0UL)        /*!< Disable                                                              */
  #define LPCOMP_INTEN_CROSS_Enabled (0x1UL)         /*!< Enable                                                               */


/* LPCOMP_INTENSET: Enable interrupt */
  #define LPCOMP_INTENSET_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET register.                                    */

/* READY @Bit 0 : Write '1' to enable interrupt for event READY */
  #define LPCOMP_INTENSET_READY_Pos (0UL)            /*!< Position of READY field.                                             */
  #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field.                         */
  #define LPCOMP_INTENSET_READY_Min (0x0UL)          /*!< Min enumerator value of READY field.                                 */
  #define LPCOMP_INTENSET_READY_Max (0x1UL)          /*!< Max enumerator value of READY field.                                 */
  #define LPCOMP_INTENSET_READY_Set (0x1UL)          /*!< Enable                                                               */
  #define LPCOMP_INTENSET_READY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENSET_READY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */
  #define LPCOMP_INTENSET_DOWN_Pos (1UL)             /*!< Position of DOWN field.                                              */
  #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field.                            */
  #define LPCOMP_INTENSET_DOWN_Min (0x0UL)           /*!< Min enumerator value of DOWN field.                                  */
  #define LPCOMP_INTENSET_DOWN_Max (0x1UL)           /*!< Max enumerator value of DOWN field.                                  */
  #define LPCOMP_INTENSET_DOWN_Set (0x1UL)           /*!< Enable                                                               */
  #define LPCOMP_INTENSET_DOWN_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENSET_DOWN_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* UP @Bit 2 : Write '1' to enable interrupt for event UP */
  #define LPCOMP_INTENSET_UP_Pos (2UL)               /*!< Position of UP field.                                                */
  #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field.                                  */
  #define LPCOMP_INTENSET_UP_Min (0x0UL)             /*!< Min enumerator value of UP field.                                    */
  #define LPCOMP_INTENSET_UP_Max (0x1UL)             /*!< Max enumerator value of UP field.                                    */
  #define LPCOMP_INTENSET_UP_Set (0x1UL)             /*!< Enable                                                               */
  #define LPCOMP_INTENSET_UP_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENSET_UP_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */
  #define LPCOMP_INTENSET_CROSS_Pos (3UL)            /*!< Position of CROSS field.                                             */
  #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field.                         */
  #define LPCOMP_INTENSET_CROSS_Min (0x0UL)          /*!< Min enumerator value of CROSS field.                                 */
  #define LPCOMP_INTENSET_CROSS_Max (0x1UL)          /*!< Max enumerator value of CROSS field.                                 */
  #define LPCOMP_INTENSET_CROSS_Set (0x1UL)          /*!< Enable                                                               */
  #define LPCOMP_INTENSET_CROSS_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENSET_CROSS_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* LPCOMP_INTENCLR: Disable interrupt */
  #define LPCOMP_INTENCLR_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR register.                                    */

/* READY @Bit 0 : Write '1' to disable interrupt for event READY */
  #define LPCOMP_INTENCLR_READY_Pos (0UL)            /*!< Position of READY field.                                             */
  #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field.                         */
  #define LPCOMP_INTENCLR_READY_Min (0x0UL)          /*!< Min enumerator value of READY field.                                 */
  #define LPCOMP_INTENCLR_READY_Max (0x1UL)          /*!< Max enumerator value of READY field.                                 */
  #define LPCOMP_INTENCLR_READY_Clear (0x1UL)        /*!< Disable                                                              */
  #define LPCOMP_INTENCLR_READY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENCLR_READY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */
  #define LPCOMP_INTENCLR_DOWN_Pos (1UL)             /*!< Position of DOWN field.                                              */
  #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field.                            */
  #define LPCOMP_INTENCLR_DOWN_Min (0x0UL)           /*!< Min enumerator value of DOWN field.                                  */
  #define LPCOMP_INTENCLR_DOWN_Max (0x1UL)           /*!< Max enumerator value of DOWN field.                                  */
  #define LPCOMP_INTENCLR_DOWN_Clear (0x1UL)         /*!< Disable                                                              */
  #define LPCOMP_INTENCLR_DOWN_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENCLR_DOWN_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* UP @Bit 2 : Write '1' to disable interrupt for event UP */
  #define LPCOMP_INTENCLR_UP_Pos (2UL)               /*!< Position of UP field.                                                */
  #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field.                                  */
  #define LPCOMP_INTENCLR_UP_Min (0x0UL)             /*!< Min enumerator value of UP field.                                    */
  #define LPCOMP_INTENCLR_UP_Max (0x1UL)             /*!< Max enumerator value of UP field.                                    */
  #define LPCOMP_INTENCLR_UP_Clear (0x1UL)           /*!< Disable                                                              */
  #define LPCOMP_INTENCLR_UP_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENCLR_UP_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */
  #define LPCOMP_INTENCLR_CROSS_Pos (3UL)            /*!< Position of CROSS field.                                             */
  #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field.                         */
  #define LPCOMP_INTENCLR_CROSS_Min (0x0UL)          /*!< Min enumerator value of CROSS field.                                 */
  #define LPCOMP_INTENCLR_CROSS_Max (0x1UL)          /*!< Max enumerator value of CROSS field.                                 */
  #define LPCOMP_INTENCLR_CROSS_Clear (0x1UL)        /*!< Disable                                                              */
  #define LPCOMP_INTENCLR_CROSS_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define LPCOMP_INTENCLR_CROSS_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* LPCOMP_INTPEND: Pending interrupts */
  #define LPCOMP_INTPEND_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND register.                                     */

/* READY @Bit 0 : Read pending status of interrupt for event READY */
  #define LPCOMP_INTPEND_READY_Pos (0UL)             /*!< Position of READY field.                                             */
  #define LPCOMP_INTPEND_READY_Msk (0x1UL << LPCOMP_INTPEND_READY_Pos) /*!< Bit mask of READY field.                           */
  #define LPCOMP_INTPEND_READY_Min (0x0UL)           /*!< Min enumerator value of READY field.                                 */
  #define LPCOMP_INTPEND_READY_Max (0x1UL)           /*!< Max enumerator value of READY field.                                 */
  #define LPCOMP_INTPEND_READY_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
  #define LPCOMP_INTPEND_READY_Pending (0x1UL)       /*!< Read: Pending                                                        */

/* DOWN @Bit 1 : Read pending status of interrupt for event DOWN */
  #define LPCOMP_INTPEND_DOWN_Pos (1UL)              /*!< Position of DOWN field.                                              */
  #define LPCOMP_INTPEND_DOWN_Msk (0x1UL << LPCOMP_INTPEND_DOWN_Pos) /*!< Bit mask of DOWN field.                              */
  #define LPCOMP_INTPEND_DOWN_Min (0x0UL)            /*!< Min enumerator value of DOWN field.                                  */
  #define LPCOMP_INTPEND_DOWN_Max (0x1UL)            /*!< Max enumerator value of DOWN field.                                  */
  #define LPCOMP_INTPEND_DOWN_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
  #define LPCOMP_INTPEND_DOWN_Pending (0x1UL)        /*!< Read: Pending                                                        */

/* UP @Bit 2 : Read pending status of interrupt for event UP */
  #define LPCOMP_INTPEND_UP_Pos (2UL)                /*!< Position of UP field.                                                */
  #define LPCOMP_INTPEND_UP_Msk (0x1UL << LPCOMP_INTPEND_UP_Pos) /*!< Bit mask of UP field.                                    */
  #define LPCOMP_INTPEND_UP_Min (0x0UL)              /*!< Min enumerator value of UP field.                                    */
  #define LPCOMP_INTPEND_UP_Max (0x1UL)              /*!< Max enumerator value of UP field.                                    */
  #define LPCOMP_INTPEND_UP_NotPending (0x0UL)       /*!< Read: Not pending                                                    */
  #define LPCOMP_INTPEND_UP_Pending (0x1UL)          /*!< Read: Pending                                                        */

/* CROSS @Bit 3 : Read pending status of interrupt for event CROSS */
  #define LPCOMP_INTPEND_CROSS_Pos (3UL)             /*!< Position of CROSS field.                                             */
  #define LPCOMP_INTPEND_CROSS_Msk (0x1UL << LPCOMP_INTPEND_CROSS_Pos) /*!< Bit mask of CROSS field.                           */
  #define LPCOMP_INTPEND_CROSS_Min (0x0UL)           /*!< Min enumerator value of CROSS field.                                 */
  #define LPCOMP_INTPEND_CROSS_Max (0x1UL)           /*!< Max enumerator value of CROSS field.                                 */
  #define LPCOMP_INTPEND_CROSS_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
  #define LPCOMP_INTPEND_CROSS_Pending (0x1UL)       /*!< Read: Pending                                                        */


/* LPCOMP_RESULT: Compare result */
  #define LPCOMP_RESULT_ResetValue (0x00000000UL)    /*!< Reset value of RESULT register.                                      */

/* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */
  #define LPCOMP_RESULT_RESULT_Pos (0UL)             /*!< Position of RESULT field.                                            */
  #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field.                          */
  #define LPCOMP_RESULT_RESULT_Min (0x0UL)           /*!< Min enumerator value of RESULT field.                                */
  #define LPCOMP_RESULT_RESULT_Max (0x1UL)           /*!< Max enumerator value of RESULT field.                                */
  #define LPCOMP_RESULT_RESULT_Below (0x0UL)         /*!< Input voltage is below the reference threshold (VIN+ < VIN-)         */
  #define LPCOMP_RESULT_RESULT_Above (0x1UL)         /*!< Input voltage is above the reference threshold (VIN+ > VIN-)         */


/* LPCOMP_ENABLE: Enable LPCOMP */
  #define LPCOMP_ENABLE_ResetValue (0x00000000UL)    /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..1 : Enable or disable LPCOMP */
  #define LPCOMP_ENABLE_ENABLE_Pos (0UL)             /*!< Position of ENABLE field.                                            */
  #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                          */
  #define LPCOMP_ENABLE_ENABLE_Min (0x0UL)           /*!< Min enumerator value of ENABLE field.                                */
  #define LPCOMP_ENABLE_ENABLE_Max (0x1UL)           /*!< Max enumerator value of ENABLE field.                                */
  #define LPCOMP_ENABLE_ENABLE_Disabled (0x0UL)      /*!< Disable                                                              */
  #define LPCOMP_ENABLE_ENABLE_Enabled (0x1UL)       /*!< Enable                                                               */


/* LPCOMP_PSEL: Input pin select */
  #define LPCOMP_PSEL_ResetValue (0x00000000UL)      /*!< Reset value of PSEL register.                                        */

/* PIN @Bits 0..4 : Analog pin select */
  #define LPCOMP_PSEL_PIN_Pos (0UL)                  /*!< Position of PIN field.                                               */
  #define LPCOMP_PSEL_PIN_Msk (0x1FUL << LPCOMP_PSEL_PIN_Pos) /*!< Bit mask of PIN field.                                      */

/* PORT @Bits 8..11 : GPIO Port selection */
  #define LPCOMP_PSEL_PORT_Pos (8UL)                 /*!< Position of PORT field.                                              */
  #define LPCOMP_PSEL_PORT_Msk (0xFUL << LPCOMP_PSEL_PORT_Pos) /*!< Bit mask of PORT field.                                    */


/* LPCOMP_REFSEL: Reference select */
  #define LPCOMP_REFSEL_ResetValue (0x00000004UL)    /*!< Reset value of REFSEL register.                                      */

/* REFSEL @Bits 0..3 : Reference select */
  #define LPCOMP_REFSEL_REFSEL_Pos (0UL)             /*!< Position of REFSEL field.                                            */
  #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field.                          */
  #define LPCOMP_REFSEL_REFSEL_Min (0x0UL)           /*!< Min enumerator value of REFSEL field.                                */
  #define LPCOMP_REFSEL_REFSEL_Max (0xFUL)           /*!< Max enumerator value of REFSEL field.                                */
  #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0x0UL)     /*!< VDD * 1/8 selected as reference                                      */
  #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (0x1UL)     /*!< VDD * 2/8 selected as reference                                      */
  #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (0x2UL)     /*!< VDD * 3/8 selected as reference                                      */
  #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (0x3UL)     /*!< VDD * 4/8 selected as reference                                      */
  #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (0x4UL)     /*!< VDD * 5/8 selected as reference                                      */
  #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (0x5UL)     /*!< VDD * 6/8 selected as reference                                      */
  #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (0x6UL)     /*!< VDD * 7/8 selected as reference                                      */
  #define LPCOMP_REFSEL_REFSEL_ARef (0x7UL)          /*!< External analog reference selected                                   */
  #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (0x8UL)    /*!< VDD * 1/16 selected as reference                                     */
  #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (0x9UL)    /*!< VDD * 3/16 selected as reference                                     */
  #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (0xAUL)    /*!< VDD * 5/16 selected as reference                                     */
  #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (0xBUL)    /*!< VDD * 7/16 selected as reference                                     */
  #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (0xCUL)    /*!< VDD * 9/16 selected as reference                                     */
  #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (0xDUL)   /*!< VDD * 11/16 selected as reference                                    */
  #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (0xEUL)   /*!< VDD * 13/16 selected as reference                                    */
  #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (0xFUL)   /*!< VDD * 15/16 selected as reference                                    */


/* LPCOMP_EXTREFSEL: External reference select */
  #define LPCOMP_EXTREFSEL_ResetValue (0x00000000UL) /*!< Reset value of EXTREFSEL register.                                   */

/* PIN @Bits 0..4 : External analog reference pin select */
  #define LPCOMP_EXTREFSEL_PIN_Pos (0UL)             /*!< Position of PIN field.                                               */
  #define LPCOMP_EXTREFSEL_PIN_Msk (0x1FUL << LPCOMP_EXTREFSEL_PIN_Pos) /*!< Bit mask of PIN field.                            */

/* PORT @Bits 8..11 : GPIO Port selection */
  #define LPCOMP_EXTREFSEL_PORT_Pos (8UL)            /*!< Position of PORT field.                                              */
  #define LPCOMP_EXTREFSEL_PORT_Msk (0xFUL << LPCOMP_EXTREFSEL_PORT_Pos) /*!< Bit mask of PORT field.                          */


/* LPCOMP_ANADETECT: Analog detect configuration */
  #define LPCOMP_ANADETECT_ResetValue (0x00000000UL) /*!< Reset value of ANADETECT register.                                   */

/* ANADETECT @Bits 0..1 : Analog detect configuration */
  #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL)       /*!< Position of ANADETECT field.                                         */
  #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field.           */
  #define LPCOMP_ANADETECT_ANADETECT_Min (0x0UL)     /*!< Min enumerator value of ANADETECT field.                             */
  #define LPCOMP_ANADETECT_ANADETECT_Max (0x2UL)     /*!< Max enumerator value of ANADETECT field.                             */
  #define LPCOMP_ANADETECT_ANADETECT_Cross (0x0UL)   /*!< Generate ANADETECT on crossing, both upward crossing and downward
                                                          crossing*/
  #define LPCOMP_ANADETECT_ANADETECT_Up (0x1UL)      /*!< Generate ANADETECT on upward crossing only                           */
  #define LPCOMP_ANADETECT_ANADETECT_Down (0x2UL)    /*!< Generate ANADETECT on downward crossing only                         */


/* LPCOMP_HYST: Comparator hysteresis enable */
  #define LPCOMP_HYST_ResetValue (0x00000000UL)      /*!< Reset value of HYST register.                                        */

/* HYST @Bit 0 : Comparator hysteresis enable */
  #define LPCOMP_HYST_HYST_Pos (0UL)                 /*!< Position of HYST field.                                              */
  #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field.                                    */
  #define LPCOMP_HYST_HYST_Min (0x0UL)               /*!< Min enumerator value of HYST field.                                  */
  #define LPCOMP_HYST_HYST_Max (0x1UL)               /*!< Max enumerator value of HYST field.                                  */
  #define LPCOMP_HYST_HYST_Disabled (0x0UL)          /*!< Comparator hysteresis disabled                                       */
  #define LPCOMP_HYST_HYST_Enabled (0x1UL)           /*!< Comparator hysteresis enabled                                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                          MEMCONF                                          ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================== Struct MEMCONF_POWER =================================================== */
/**
  * @brief POWER [MEMCONF_POWER] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CONTROL;                           /*!< (@ 0x00000000) Control memory block power.                           */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  RET;                               /*!< (@ 0x00000008) RAM retention for RAM [n].                            */
  __IOM uint32_t  RET2;                              /*!< (@ 0x0000000C) RAM retention for the second bank in the RAM block    */
} NRF_MEMCONF_POWER_Type;                            /*!< Size = 16 (0x010)                                                    */
  #define MEMCONF_POWER_MaxCount (2UL)               /*!< Size of POWER[2] array.                                              */
  #define MEMCONF_POWER_MaxIndex (1UL)               /*!< Max index of POWER[2] array.                                         */
  #define MEMCONF_POWER_MinIndex (0UL)               /*!< Min index of POWER[2] array.                                         */

/* MEMCONF_POWER_CONTROL: Control memory block power. */
  #define MEMCONF_POWER_CONTROL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONTROL register.                                */

/* MEM0 @Bit 0 : Keep the memory block MEM[0] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM0_Pos (0UL)       /*!< Position of MEM0 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM0_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM0_Pos) /*!< Bit mask of MEM0 field.                */
  #define MEMCONF_POWER_CONTROL_MEM0_Min (0x0UL)     /*!< Min enumerator value of MEM0 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM0_Max (0x1UL)     /*!< Max enumerator value of MEM0 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM0_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM0_On (0x1UL)      /*!< Power up                                                             */

/* MEM1 @Bit 1 : Keep the memory block MEM[1] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM1_Pos (1UL)       /*!< Position of MEM1 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM1_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM1_Pos) /*!< Bit mask of MEM1 field.                */
  #define MEMCONF_POWER_CONTROL_MEM1_Min (0x0UL)     /*!< Min enumerator value of MEM1 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM1_Max (0x1UL)     /*!< Max enumerator value of MEM1 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM1_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM1_On (0x1UL)      /*!< Power up                                                             */

/* MEM2 @Bit 2 : Keep the memory block MEM[2] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM2_Pos (2UL)       /*!< Position of MEM2 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM2_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM2_Pos) /*!< Bit mask of MEM2 field.                */
  #define MEMCONF_POWER_CONTROL_MEM2_Min (0x0UL)     /*!< Min enumerator value of MEM2 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM2_Max (0x1UL)     /*!< Max enumerator value of MEM2 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM2_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM2_On (0x1UL)      /*!< Power up                                                             */

/* MEM3 @Bit 3 : Keep the memory block MEM[3] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM3_Pos (3UL)       /*!< Position of MEM3 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM3_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM3_Pos) /*!< Bit mask of MEM3 field.                */
  #define MEMCONF_POWER_CONTROL_MEM3_Min (0x0UL)     /*!< Min enumerator value of MEM3 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM3_Max (0x1UL)     /*!< Max enumerator value of MEM3 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM3_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM3_On (0x1UL)      /*!< Power up                                                             */

/* MEM4 @Bit 4 : Keep the memory block MEM[4] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM4_Pos (4UL)       /*!< Position of MEM4 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM4_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM4_Pos) /*!< Bit mask of MEM4 field.                */
  #define MEMCONF_POWER_CONTROL_MEM4_Min (0x0UL)     /*!< Min enumerator value of MEM4 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM4_Max (0x1UL)     /*!< Max enumerator value of MEM4 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM4_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM4_On (0x1UL)      /*!< Power up                                                             */

/* MEM5 @Bit 5 : Keep the memory block MEM[5] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM5_Pos (5UL)       /*!< Position of MEM5 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM5_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM5_Pos) /*!< Bit mask of MEM5 field.                */
  #define MEMCONF_POWER_CONTROL_MEM5_Min (0x0UL)     /*!< Min enumerator value of MEM5 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM5_Max (0x1UL)     /*!< Max enumerator value of MEM5 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM5_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM5_On (0x1UL)      /*!< Power up                                                             */

/* MEM6 @Bit 6 : Keep the memory block MEM[6] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM6_Pos (6UL)       /*!< Position of MEM6 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM6_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM6_Pos) /*!< Bit mask of MEM6 field.                */
  #define MEMCONF_POWER_CONTROL_MEM6_Min (0x0UL)     /*!< Min enumerator value of MEM6 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM6_Max (0x1UL)     /*!< Max enumerator value of MEM6 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM6_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM6_On (0x1UL)      /*!< Power up                                                             */

/* MEM7 @Bit 7 : Keep the memory block MEM[7] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM7_Pos (7UL)       /*!< Position of MEM7 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM7_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM7_Pos) /*!< Bit mask of MEM7 field.                */
  #define MEMCONF_POWER_CONTROL_MEM7_Min (0x0UL)     /*!< Min enumerator value of MEM7 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM7_Max (0x1UL)     /*!< Max enumerator value of MEM7 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM7_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM7_On (0x1UL)      /*!< Power up                                                             */

/* MEM8 @Bit 8 : Keep the memory block MEM[8] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM8_Pos (8UL)       /*!< Position of MEM8 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM8_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM8_Pos) /*!< Bit mask of MEM8 field.                */
  #define MEMCONF_POWER_CONTROL_MEM8_Min (0x0UL)     /*!< Min enumerator value of MEM8 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM8_Max (0x1UL)     /*!< Max enumerator value of MEM8 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM8_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM8_On (0x1UL)      /*!< Power up                                                             */

/* MEM9 @Bit 9 : Keep the memory block MEM[9] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM9_Pos (9UL)       /*!< Position of MEM9 field.                                              */
  #define MEMCONF_POWER_CONTROL_MEM9_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM9_Pos) /*!< Bit mask of MEM9 field.                */
  #define MEMCONF_POWER_CONTROL_MEM9_Min (0x0UL)     /*!< Min enumerator value of MEM9 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM9_Max (0x1UL)     /*!< Max enumerator value of MEM9 field.                                  */
  #define MEMCONF_POWER_CONTROL_MEM9_Off (0x0UL)     /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM9_On (0x1UL)      /*!< Power up                                                             */

/* MEM10 @Bit 10 : Keep the memory block MEM[10] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM10_Pos (10UL)     /*!< Position of MEM10 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM10_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM10_Pos) /*!< Bit mask of MEM10 field.             */
  #define MEMCONF_POWER_CONTROL_MEM10_Min (0x0UL)    /*!< Min enumerator value of MEM10 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM10_Max (0x1UL)    /*!< Max enumerator value of MEM10 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM10_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM10_On (0x1UL)     /*!< Power up                                                             */

/* MEM11 @Bit 11 : Keep the memory block MEM[11] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM11_Pos (11UL)     /*!< Position of MEM11 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM11_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM11_Pos) /*!< Bit mask of MEM11 field.             */
  #define MEMCONF_POWER_CONTROL_MEM11_Min (0x0UL)    /*!< Min enumerator value of MEM11 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM11_Max (0x1UL)    /*!< Max enumerator value of MEM11 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM11_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM11_On (0x1UL)     /*!< Power up                                                             */

/* MEM12 @Bit 12 : Keep the memory block MEM[12] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM12_Pos (12UL)     /*!< Position of MEM12 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM12_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM12_Pos) /*!< Bit mask of MEM12 field.             */
  #define MEMCONF_POWER_CONTROL_MEM12_Min (0x0UL)    /*!< Min enumerator value of MEM12 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM12_Max (0x1UL)    /*!< Max enumerator value of MEM12 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM12_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM12_On (0x1UL)     /*!< Power up                                                             */

/* MEM13 @Bit 13 : Keep the memory block MEM[13] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM13_Pos (13UL)     /*!< Position of MEM13 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM13_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM13_Pos) /*!< Bit mask of MEM13 field.             */
  #define MEMCONF_POWER_CONTROL_MEM13_Min (0x0UL)    /*!< Min enumerator value of MEM13 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM13_Max (0x1UL)    /*!< Max enumerator value of MEM13 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM13_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM13_On (0x1UL)     /*!< Power up                                                             */

/* MEM14 @Bit 14 : Keep the memory block MEM[14] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM14_Pos (14UL)     /*!< Position of MEM14 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM14_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM14_Pos) /*!< Bit mask of MEM14 field.             */
  #define MEMCONF_POWER_CONTROL_MEM14_Min (0x0UL)    /*!< Min enumerator value of MEM14 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM14_Max (0x1UL)    /*!< Max enumerator value of MEM14 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM14_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM14_On (0x1UL)     /*!< Power up                                                             */

/* MEM15 @Bit 15 : Keep the memory block MEM[15] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM15_Pos (15UL)     /*!< Position of MEM15 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM15_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM15_Pos) /*!< Bit mask of MEM15 field.             */
  #define MEMCONF_POWER_CONTROL_MEM15_Min (0x0UL)    /*!< Min enumerator value of MEM15 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM15_Max (0x1UL)    /*!< Max enumerator value of MEM15 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM15_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM15_On (0x1UL)     /*!< Power up                                                             */

/* MEM16 @Bit 16 : Keep the memory block MEM[16] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM16_Pos (16UL)     /*!< Position of MEM16 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM16_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM16_Pos) /*!< Bit mask of MEM16 field.             */
  #define MEMCONF_POWER_CONTROL_MEM16_Min (0x0UL)    /*!< Min enumerator value of MEM16 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM16_Max (0x1UL)    /*!< Max enumerator value of MEM16 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM16_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM16_On (0x1UL)     /*!< Power up                                                             */

/* MEM17 @Bit 17 : Keep the memory block MEM[17] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM17_Pos (17UL)     /*!< Position of MEM17 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM17_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM17_Pos) /*!< Bit mask of MEM17 field.             */
  #define MEMCONF_POWER_CONTROL_MEM17_Min (0x0UL)    /*!< Min enumerator value of MEM17 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM17_Max (0x1UL)    /*!< Max enumerator value of MEM17 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM17_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM17_On (0x1UL)     /*!< Power up                                                             */

/* MEM18 @Bit 18 : Keep the memory block MEM[18] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM18_Pos (18UL)     /*!< Position of MEM18 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM18_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM18_Pos) /*!< Bit mask of MEM18 field.             */
  #define MEMCONF_POWER_CONTROL_MEM18_Min (0x0UL)    /*!< Min enumerator value of MEM18 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM18_Max (0x1UL)    /*!< Max enumerator value of MEM18 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM18_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM18_On (0x1UL)     /*!< Power up                                                             */

/* MEM19 @Bit 19 : Keep the memory block MEM[19] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM19_Pos (19UL)     /*!< Position of MEM19 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM19_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM19_Pos) /*!< Bit mask of MEM19 field.             */
  #define MEMCONF_POWER_CONTROL_MEM19_Min (0x0UL)    /*!< Min enumerator value of MEM19 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM19_Max (0x1UL)    /*!< Max enumerator value of MEM19 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM19_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM19_On (0x1UL)     /*!< Power up                                                             */

/* MEM20 @Bit 20 : Keep the memory block MEM[20] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM20_Pos (20UL)     /*!< Position of MEM20 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM20_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM20_Pos) /*!< Bit mask of MEM20 field.             */
  #define MEMCONF_POWER_CONTROL_MEM20_Min (0x0UL)    /*!< Min enumerator value of MEM20 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM20_Max (0x1UL)    /*!< Max enumerator value of MEM20 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM20_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM20_On (0x1UL)     /*!< Power up                                                             */

/* MEM21 @Bit 21 : Keep the memory block MEM[21] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM21_Pos (21UL)     /*!< Position of MEM21 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM21_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM21_Pos) /*!< Bit mask of MEM21 field.             */
  #define MEMCONF_POWER_CONTROL_MEM21_Min (0x0UL)    /*!< Min enumerator value of MEM21 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM21_Max (0x1UL)    /*!< Max enumerator value of MEM21 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM21_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM21_On (0x1UL)     /*!< Power up                                                             */

/* MEM22 @Bit 22 : Keep the memory block MEM[22] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM22_Pos (22UL)     /*!< Position of MEM22 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM22_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM22_Pos) /*!< Bit mask of MEM22 field.             */
  #define MEMCONF_POWER_CONTROL_MEM22_Min (0x0UL)    /*!< Min enumerator value of MEM22 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM22_Max (0x1UL)    /*!< Max enumerator value of MEM22 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM22_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM22_On (0x1UL)     /*!< Power up                                                             */

/* MEM23 @Bit 23 : Keep the memory block MEM[23] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM23_Pos (23UL)     /*!< Position of MEM23 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM23_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM23_Pos) /*!< Bit mask of MEM23 field.             */
  #define MEMCONF_POWER_CONTROL_MEM23_Min (0x0UL)    /*!< Min enumerator value of MEM23 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM23_Max (0x1UL)    /*!< Max enumerator value of MEM23 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM23_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM23_On (0x1UL)     /*!< Power up                                                             */

/* MEM24 @Bit 24 : Keep the memory block MEM[24] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM24_Pos (24UL)     /*!< Position of MEM24 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM24_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM24_Pos) /*!< Bit mask of MEM24 field.             */
  #define MEMCONF_POWER_CONTROL_MEM24_Min (0x0UL)    /*!< Min enumerator value of MEM24 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM24_Max (0x1UL)    /*!< Max enumerator value of MEM24 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM24_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM24_On (0x1UL)     /*!< Power up                                                             */

/* MEM25 @Bit 25 : Keep the memory block MEM[25] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM25_Pos (25UL)     /*!< Position of MEM25 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM25_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM25_Pos) /*!< Bit mask of MEM25 field.             */
  #define MEMCONF_POWER_CONTROL_MEM25_Min (0x0UL)    /*!< Min enumerator value of MEM25 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM25_Max (0x1UL)    /*!< Max enumerator value of MEM25 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM25_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM25_On (0x1UL)     /*!< Power up                                                             */

/* MEM26 @Bit 26 : Keep the memory block MEM[26] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM26_Pos (26UL)     /*!< Position of MEM26 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM26_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM26_Pos) /*!< Bit mask of MEM26 field.             */
  #define MEMCONF_POWER_CONTROL_MEM26_Min (0x0UL)    /*!< Min enumerator value of MEM26 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM26_Max (0x1UL)    /*!< Max enumerator value of MEM26 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM26_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM26_On (0x1UL)     /*!< Power up                                                             */

/* MEM27 @Bit 27 : Keep the memory block MEM[27] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM27_Pos (27UL)     /*!< Position of MEM27 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM27_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM27_Pos) /*!< Bit mask of MEM27 field.             */
  #define MEMCONF_POWER_CONTROL_MEM27_Min (0x0UL)    /*!< Min enumerator value of MEM27 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM27_Max (0x1UL)    /*!< Max enumerator value of MEM27 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM27_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM27_On (0x1UL)     /*!< Power up                                                             */

/* MEM28 @Bit 28 : Keep the memory block MEM[28] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM28_Pos (28UL)     /*!< Position of MEM28 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM28_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM28_Pos) /*!< Bit mask of MEM28 field.             */
  #define MEMCONF_POWER_CONTROL_MEM28_Min (0x0UL)    /*!< Min enumerator value of MEM28 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM28_Max (0x1UL)    /*!< Max enumerator value of MEM28 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM28_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM28_On (0x1UL)     /*!< Power up                                                             */

/* MEM29 @Bit 29 : Keep the memory block MEM[29] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM29_Pos (29UL)     /*!< Position of MEM29 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM29_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM29_Pos) /*!< Bit mask of MEM29 field.             */
  #define MEMCONF_POWER_CONTROL_MEM29_Min (0x0UL)    /*!< Min enumerator value of MEM29 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM29_Max (0x1UL)    /*!< Max enumerator value of MEM29 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM29_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM29_On (0x1UL)     /*!< Power up                                                             */

/* MEM30 @Bit 30 : Keep the memory block MEM[30] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM30_Pos (30UL)     /*!< Position of MEM30 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM30_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM30_Pos) /*!< Bit mask of MEM30 field.             */
  #define MEMCONF_POWER_CONTROL_MEM30_Min (0x0UL)    /*!< Min enumerator value of MEM30 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM30_Max (0x1UL)    /*!< Max enumerator value of MEM30 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM30_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM30_On (0x1UL)     /*!< Power up                                                             */

/* MEM31 @Bit 31 : Keep the memory block MEM[31] on or off when in System ON mode. */
  #define MEMCONF_POWER_CONTROL_MEM31_Pos (31UL)     /*!< Position of MEM31 field.                                             */
  #define MEMCONF_POWER_CONTROL_MEM31_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM31_Pos) /*!< Bit mask of MEM31 field.             */
  #define MEMCONF_POWER_CONTROL_MEM31_Min (0x0UL)    /*!< Min enumerator value of MEM31 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM31_Max (0x1UL)    /*!< Max enumerator value of MEM31 field.                                 */
  #define MEMCONF_POWER_CONTROL_MEM31_Off (0x0UL)    /*!< Power down                                                           */
  #define MEMCONF_POWER_CONTROL_MEM31_On (0x1UL)     /*!< Power up                                                             */


/* MEMCONF_POWER_RET: RAM retention for RAM [n]. */
  #define MEMCONF_POWER_RET_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RET register.                                        */

/* MEM0 @Bit 0 : Keep the RAM block MEM[0] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM0_Pos (0UL)           /*!< Position of MEM0 field.                                              */
  #define MEMCONF_POWER_RET_MEM0_Msk (0x1UL << MEMCONF_POWER_RET_MEM0_Pos) /*!< Bit mask of MEM0 field.                        */
  #define MEMCONF_POWER_RET_MEM0_Min (0x0UL)         /*!< Min enumerator value of MEM0 field.                                  */
  #define MEMCONF_POWER_RET_MEM0_Max (0x1UL)         /*!< Max enumerator value of MEM0 field.                                  */
  #define MEMCONF_POWER_RET_MEM0_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM0_On (0x1UL)          /*!< Retention on                                                         */

/* MEM1 @Bit 1 : Keep the RAM block MEM[1] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM1_Pos (1UL)           /*!< Position of MEM1 field.                                              */
  #define MEMCONF_POWER_RET_MEM1_Msk (0x1UL << MEMCONF_POWER_RET_MEM1_Pos) /*!< Bit mask of MEM1 field.                        */
  #define MEMCONF_POWER_RET_MEM1_Min (0x0UL)         /*!< Min enumerator value of MEM1 field.                                  */
  #define MEMCONF_POWER_RET_MEM1_Max (0x1UL)         /*!< Max enumerator value of MEM1 field.                                  */
  #define MEMCONF_POWER_RET_MEM1_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM1_On (0x1UL)          /*!< Retention on                                                         */

/* MEM2 @Bit 2 : Keep the RAM block MEM[2] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM2_Pos (2UL)           /*!< Position of MEM2 field.                                              */
  #define MEMCONF_POWER_RET_MEM2_Msk (0x1UL << MEMCONF_POWER_RET_MEM2_Pos) /*!< Bit mask of MEM2 field.                        */
  #define MEMCONF_POWER_RET_MEM2_Min (0x0UL)         /*!< Min enumerator value of MEM2 field.                                  */
  #define MEMCONF_POWER_RET_MEM2_Max (0x1UL)         /*!< Max enumerator value of MEM2 field.                                  */
  #define MEMCONF_POWER_RET_MEM2_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM2_On (0x1UL)          /*!< Retention on                                                         */

/* MEM3 @Bit 3 : Keep the RAM block MEM[3] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM3_Pos (3UL)           /*!< Position of MEM3 field.                                              */
  #define MEMCONF_POWER_RET_MEM3_Msk (0x1UL << MEMCONF_POWER_RET_MEM3_Pos) /*!< Bit mask of MEM3 field.                        */
  #define MEMCONF_POWER_RET_MEM3_Min (0x0UL)         /*!< Min enumerator value of MEM3 field.                                  */
  #define MEMCONF_POWER_RET_MEM3_Max (0x1UL)         /*!< Max enumerator value of MEM3 field.                                  */
  #define MEMCONF_POWER_RET_MEM3_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM3_On (0x1UL)          /*!< Retention on                                                         */

/* MEM4 @Bit 4 : Keep the RAM block MEM[4] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM4_Pos (4UL)           /*!< Position of MEM4 field.                                              */
  #define MEMCONF_POWER_RET_MEM4_Msk (0x1UL << MEMCONF_POWER_RET_MEM4_Pos) /*!< Bit mask of MEM4 field.                        */
  #define MEMCONF_POWER_RET_MEM4_Min (0x0UL)         /*!< Min enumerator value of MEM4 field.                                  */
  #define MEMCONF_POWER_RET_MEM4_Max (0x1UL)         /*!< Max enumerator value of MEM4 field.                                  */
  #define MEMCONF_POWER_RET_MEM4_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM4_On (0x1UL)          /*!< Retention on                                                         */

/* MEM5 @Bit 5 : Keep the RAM block MEM[5] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM5_Pos (5UL)           /*!< Position of MEM5 field.                                              */
  #define MEMCONF_POWER_RET_MEM5_Msk (0x1UL << MEMCONF_POWER_RET_MEM5_Pos) /*!< Bit mask of MEM5 field.                        */
  #define MEMCONF_POWER_RET_MEM5_Min (0x0UL)         /*!< Min enumerator value of MEM5 field.                                  */
  #define MEMCONF_POWER_RET_MEM5_Max (0x1UL)         /*!< Max enumerator value of MEM5 field.                                  */
  #define MEMCONF_POWER_RET_MEM5_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM5_On (0x1UL)          /*!< Retention on                                                         */

/* MEM6 @Bit 6 : Keep the RAM block MEM[6] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM6_Pos (6UL)           /*!< Position of MEM6 field.                                              */
  #define MEMCONF_POWER_RET_MEM6_Msk (0x1UL << MEMCONF_POWER_RET_MEM6_Pos) /*!< Bit mask of MEM6 field.                        */
  #define MEMCONF_POWER_RET_MEM6_Min (0x0UL)         /*!< Min enumerator value of MEM6 field.                                  */
  #define MEMCONF_POWER_RET_MEM6_Max (0x1UL)         /*!< Max enumerator value of MEM6 field.                                  */
  #define MEMCONF_POWER_RET_MEM6_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM6_On (0x1UL)          /*!< Retention on                                                         */

/* MEM7 @Bit 7 : Keep the RAM block MEM[7] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM7_Pos (7UL)           /*!< Position of MEM7 field.                                              */
  #define MEMCONF_POWER_RET_MEM7_Msk (0x1UL << MEMCONF_POWER_RET_MEM7_Pos) /*!< Bit mask of MEM7 field.                        */
  #define MEMCONF_POWER_RET_MEM7_Min (0x0UL)         /*!< Min enumerator value of MEM7 field.                                  */
  #define MEMCONF_POWER_RET_MEM7_Max (0x1UL)         /*!< Max enumerator value of MEM7 field.                                  */
  #define MEMCONF_POWER_RET_MEM7_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM7_On (0x1UL)          /*!< Retention on                                                         */

/* MEM8 @Bit 8 : Keep the RAM block MEM[8] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM8_Pos (8UL)           /*!< Position of MEM8 field.                                              */
  #define MEMCONF_POWER_RET_MEM8_Msk (0x1UL << MEMCONF_POWER_RET_MEM8_Pos) /*!< Bit mask of MEM8 field.                        */
  #define MEMCONF_POWER_RET_MEM8_Min (0x0UL)         /*!< Min enumerator value of MEM8 field.                                  */
  #define MEMCONF_POWER_RET_MEM8_Max (0x1UL)         /*!< Max enumerator value of MEM8 field.                                  */
  #define MEMCONF_POWER_RET_MEM8_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM8_On (0x1UL)          /*!< Retention on                                                         */

/* MEM9 @Bit 9 : Keep the RAM block MEM[9] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM9_Pos (9UL)           /*!< Position of MEM9 field.                                              */
  #define MEMCONF_POWER_RET_MEM9_Msk (0x1UL << MEMCONF_POWER_RET_MEM9_Pos) /*!< Bit mask of MEM9 field.                        */
  #define MEMCONF_POWER_RET_MEM9_Min (0x0UL)         /*!< Min enumerator value of MEM9 field.                                  */
  #define MEMCONF_POWER_RET_MEM9_Max (0x1UL)         /*!< Max enumerator value of MEM9 field.                                  */
  #define MEMCONF_POWER_RET_MEM9_Off (0x0UL)         /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM9_On (0x1UL)          /*!< Retention on                                                         */

/* MEM10 @Bit 10 : Keep the RAM block MEM[10] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM10_Pos (10UL)         /*!< Position of MEM10 field.                                             */
  #define MEMCONF_POWER_RET_MEM10_Msk (0x1UL << MEMCONF_POWER_RET_MEM10_Pos) /*!< Bit mask of MEM10 field.                     */
  #define MEMCONF_POWER_RET_MEM10_Min (0x0UL)        /*!< Min enumerator value of MEM10 field.                                 */
  #define MEMCONF_POWER_RET_MEM10_Max (0x1UL)        /*!< Max enumerator value of MEM10 field.                                 */
  #define MEMCONF_POWER_RET_MEM10_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM10_On (0x1UL)         /*!< Retention on                                                         */

/* MEM11 @Bit 11 : Keep the RAM block MEM[11] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM11_Pos (11UL)         /*!< Position of MEM11 field.                                             */
  #define MEMCONF_POWER_RET_MEM11_Msk (0x1UL << MEMCONF_POWER_RET_MEM11_Pos) /*!< Bit mask of MEM11 field.                     */
  #define MEMCONF_POWER_RET_MEM11_Min (0x0UL)        /*!< Min enumerator value of MEM11 field.                                 */
  #define MEMCONF_POWER_RET_MEM11_Max (0x1UL)        /*!< Max enumerator value of MEM11 field.                                 */
  #define MEMCONF_POWER_RET_MEM11_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM11_On (0x1UL)         /*!< Retention on                                                         */

/* MEM12 @Bit 12 : Keep the RAM block MEM[12] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM12_Pos (12UL)         /*!< Position of MEM12 field.                                             */
  #define MEMCONF_POWER_RET_MEM12_Msk (0x1UL << MEMCONF_POWER_RET_MEM12_Pos) /*!< Bit mask of MEM12 field.                     */
  #define MEMCONF_POWER_RET_MEM12_Min (0x0UL)        /*!< Min enumerator value of MEM12 field.                                 */
  #define MEMCONF_POWER_RET_MEM12_Max (0x1UL)        /*!< Max enumerator value of MEM12 field.                                 */
  #define MEMCONF_POWER_RET_MEM12_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM12_On (0x1UL)         /*!< Retention on                                                         */

/* MEM13 @Bit 13 : Keep the RAM block MEM[13] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM13_Pos (13UL)         /*!< Position of MEM13 field.                                             */
  #define MEMCONF_POWER_RET_MEM13_Msk (0x1UL << MEMCONF_POWER_RET_MEM13_Pos) /*!< Bit mask of MEM13 field.                     */
  #define MEMCONF_POWER_RET_MEM13_Min (0x0UL)        /*!< Min enumerator value of MEM13 field.                                 */
  #define MEMCONF_POWER_RET_MEM13_Max (0x1UL)        /*!< Max enumerator value of MEM13 field.                                 */
  #define MEMCONF_POWER_RET_MEM13_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM13_On (0x1UL)         /*!< Retention on                                                         */

/* MEM14 @Bit 14 : Keep the RAM block MEM[14] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM14_Pos (14UL)         /*!< Position of MEM14 field.                                             */
  #define MEMCONF_POWER_RET_MEM14_Msk (0x1UL << MEMCONF_POWER_RET_MEM14_Pos) /*!< Bit mask of MEM14 field.                     */
  #define MEMCONF_POWER_RET_MEM14_Min (0x0UL)        /*!< Min enumerator value of MEM14 field.                                 */
  #define MEMCONF_POWER_RET_MEM14_Max (0x1UL)        /*!< Max enumerator value of MEM14 field.                                 */
  #define MEMCONF_POWER_RET_MEM14_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM14_On (0x1UL)         /*!< Retention on                                                         */

/* MEM15 @Bit 15 : Keep the RAM block MEM[15] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM15_Pos (15UL)         /*!< Position of MEM15 field.                                             */
  #define MEMCONF_POWER_RET_MEM15_Msk (0x1UL << MEMCONF_POWER_RET_MEM15_Pos) /*!< Bit mask of MEM15 field.                     */
  #define MEMCONF_POWER_RET_MEM15_Min (0x0UL)        /*!< Min enumerator value of MEM15 field.                                 */
  #define MEMCONF_POWER_RET_MEM15_Max (0x1UL)        /*!< Max enumerator value of MEM15 field.                                 */
  #define MEMCONF_POWER_RET_MEM15_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM15_On (0x1UL)         /*!< Retention on                                                         */

/* MEM16 @Bit 16 : Keep the RAM block MEM[16] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM16_Pos (16UL)         /*!< Position of MEM16 field.                                             */
  #define MEMCONF_POWER_RET_MEM16_Msk (0x1UL << MEMCONF_POWER_RET_MEM16_Pos) /*!< Bit mask of MEM16 field.                     */
  #define MEMCONF_POWER_RET_MEM16_Min (0x0UL)        /*!< Min enumerator value of MEM16 field.                                 */
  #define MEMCONF_POWER_RET_MEM16_Max (0x1UL)        /*!< Max enumerator value of MEM16 field.                                 */
  #define MEMCONF_POWER_RET_MEM16_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM16_On (0x1UL)         /*!< Retention on                                                         */

/* MEM17 @Bit 17 : Keep the RAM block MEM[17] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM17_Pos (17UL)         /*!< Position of MEM17 field.                                             */
  #define MEMCONF_POWER_RET_MEM17_Msk (0x1UL << MEMCONF_POWER_RET_MEM17_Pos) /*!< Bit mask of MEM17 field.                     */
  #define MEMCONF_POWER_RET_MEM17_Min (0x0UL)        /*!< Min enumerator value of MEM17 field.                                 */
  #define MEMCONF_POWER_RET_MEM17_Max (0x1UL)        /*!< Max enumerator value of MEM17 field.                                 */
  #define MEMCONF_POWER_RET_MEM17_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM17_On (0x1UL)         /*!< Retention on                                                         */

/* MEM18 @Bit 18 : Keep the RAM block MEM[18] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM18_Pos (18UL)         /*!< Position of MEM18 field.                                             */
  #define MEMCONF_POWER_RET_MEM18_Msk (0x1UL << MEMCONF_POWER_RET_MEM18_Pos) /*!< Bit mask of MEM18 field.                     */
  #define MEMCONF_POWER_RET_MEM18_Min (0x0UL)        /*!< Min enumerator value of MEM18 field.                                 */
  #define MEMCONF_POWER_RET_MEM18_Max (0x1UL)        /*!< Max enumerator value of MEM18 field.                                 */
  #define MEMCONF_POWER_RET_MEM18_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM18_On (0x1UL)         /*!< Retention on                                                         */

/* MEM19 @Bit 19 : Keep the RAM block MEM[19] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM19_Pos (19UL)         /*!< Position of MEM19 field.                                             */
  #define MEMCONF_POWER_RET_MEM19_Msk (0x1UL << MEMCONF_POWER_RET_MEM19_Pos) /*!< Bit mask of MEM19 field.                     */
  #define MEMCONF_POWER_RET_MEM19_Min (0x0UL)        /*!< Min enumerator value of MEM19 field.                                 */
  #define MEMCONF_POWER_RET_MEM19_Max (0x1UL)        /*!< Max enumerator value of MEM19 field.                                 */
  #define MEMCONF_POWER_RET_MEM19_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM19_On (0x1UL)         /*!< Retention on                                                         */

/* MEM20 @Bit 20 : Keep the RAM block MEM[20] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM20_Pos (20UL)         /*!< Position of MEM20 field.                                             */
  #define MEMCONF_POWER_RET_MEM20_Msk (0x1UL << MEMCONF_POWER_RET_MEM20_Pos) /*!< Bit mask of MEM20 field.                     */
  #define MEMCONF_POWER_RET_MEM20_Min (0x0UL)        /*!< Min enumerator value of MEM20 field.                                 */
  #define MEMCONF_POWER_RET_MEM20_Max (0x1UL)        /*!< Max enumerator value of MEM20 field.                                 */
  #define MEMCONF_POWER_RET_MEM20_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM20_On (0x1UL)         /*!< Retention on                                                         */

/* MEM21 @Bit 21 : Keep the RAM block MEM[21] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM21_Pos (21UL)         /*!< Position of MEM21 field.                                             */
  #define MEMCONF_POWER_RET_MEM21_Msk (0x1UL << MEMCONF_POWER_RET_MEM21_Pos) /*!< Bit mask of MEM21 field.                     */
  #define MEMCONF_POWER_RET_MEM21_Min (0x0UL)        /*!< Min enumerator value of MEM21 field.                                 */
  #define MEMCONF_POWER_RET_MEM21_Max (0x1UL)        /*!< Max enumerator value of MEM21 field.                                 */
  #define MEMCONF_POWER_RET_MEM21_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM21_On (0x1UL)         /*!< Retention on                                                         */

/* MEM22 @Bit 22 : Keep the RAM block MEM[22] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM22_Pos (22UL)         /*!< Position of MEM22 field.                                             */
  #define MEMCONF_POWER_RET_MEM22_Msk (0x1UL << MEMCONF_POWER_RET_MEM22_Pos) /*!< Bit mask of MEM22 field.                     */
  #define MEMCONF_POWER_RET_MEM22_Min (0x0UL)        /*!< Min enumerator value of MEM22 field.                                 */
  #define MEMCONF_POWER_RET_MEM22_Max (0x1UL)        /*!< Max enumerator value of MEM22 field.                                 */
  #define MEMCONF_POWER_RET_MEM22_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM22_On (0x1UL)         /*!< Retention on                                                         */

/* MEM23 @Bit 23 : Keep the RAM block MEM[23] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM23_Pos (23UL)         /*!< Position of MEM23 field.                                             */
  #define MEMCONF_POWER_RET_MEM23_Msk (0x1UL << MEMCONF_POWER_RET_MEM23_Pos) /*!< Bit mask of MEM23 field.                     */
  #define MEMCONF_POWER_RET_MEM23_Min (0x0UL)        /*!< Min enumerator value of MEM23 field.                                 */
  #define MEMCONF_POWER_RET_MEM23_Max (0x1UL)        /*!< Max enumerator value of MEM23 field.                                 */
  #define MEMCONF_POWER_RET_MEM23_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM23_On (0x1UL)         /*!< Retention on                                                         */

/* MEM24 @Bit 24 : Keep the RAM block MEM[24] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM24_Pos (24UL)         /*!< Position of MEM24 field.                                             */
  #define MEMCONF_POWER_RET_MEM24_Msk (0x1UL << MEMCONF_POWER_RET_MEM24_Pos) /*!< Bit mask of MEM24 field.                     */
  #define MEMCONF_POWER_RET_MEM24_Min (0x0UL)        /*!< Min enumerator value of MEM24 field.                                 */
  #define MEMCONF_POWER_RET_MEM24_Max (0x1UL)        /*!< Max enumerator value of MEM24 field.                                 */
  #define MEMCONF_POWER_RET_MEM24_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM24_On (0x1UL)         /*!< Retention on                                                         */

/* MEM25 @Bit 25 : Keep the RAM block MEM[25] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM25_Pos (25UL)         /*!< Position of MEM25 field.                                             */
  #define MEMCONF_POWER_RET_MEM25_Msk (0x1UL << MEMCONF_POWER_RET_MEM25_Pos) /*!< Bit mask of MEM25 field.                     */
  #define MEMCONF_POWER_RET_MEM25_Min (0x0UL)        /*!< Min enumerator value of MEM25 field.                                 */
  #define MEMCONF_POWER_RET_MEM25_Max (0x1UL)        /*!< Max enumerator value of MEM25 field.                                 */
  #define MEMCONF_POWER_RET_MEM25_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM25_On (0x1UL)         /*!< Retention on                                                         */

/* MEM26 @Bit 26 : Keep the RAM block MEM[26] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM26_Pos (26UL)         /*!< Position of MEM26 field.                                             */
  #define MEMCONF_POWER_RET_MEM26_Msk (0x1UL << MEMCONF_POWER_RET_MEM26_Pos) /*!< Bit mask of MEM26 field.                     */
  #define MEMCONF_POWER_RET_MEM26_Min (0x0UL)        /*!< Min enumerator value of MEM26 field.                                 */
  #define MEMCONF_POWER_RET_MEM26_Max (0x1UL)        /*!< Max enumerator value of MEM26 field.                                 */
  #define MEMCONF_POWER_RET_MEM26_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM26_On (0x1UL)         /*!< Retention on                                                         */

/* MEM27 @Bit 27 : Keep the RAM block MEM[27] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM27_Pos (27UL)         /*!< Position of MEM27 field.                                             */
  #define MEMCONF_POWER_RET_MEM27_Msk (0x1UL << MEMCONF_POWER_RET_MEM27_Pos) /*!< Bit mask of MEM27 field.                     */
  #define MEMCONF_POWER_RET_MEM27_Min (0x0UL)        /*!< Min enumerator value of MEM27 field.                                 */
  #define MEMCONF_POWER_RET_MEM27_Max (0x1UL)        /*!< Max enumerator value of MEM27 field.                                 */
  #define MEMCONF_POWER_RET_MEM27_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM27_On (0x1UL)         /*!< Retention on                                                         */

/* MEM28 @Bit 28 : Keep the RAM block MEM[28] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM28_Pos (28UL)         /*!< Position of MEM28 field.                                             */
  #define MEMCONF_POWER_RET_MEM28_Msk (0x1UL << MEMCONF_POWER_RET_MEM28_Pos) /*!< Bit mask of MEM28 field.                     */
  #define MEMCONF_POWER_RET_MEM28_Min (0x0UL)        /*!< Min enumerator value of MEM28 field.                                 */
  #define MEMCONF_POWER_RET_MEM28_Max (0x1UL)        /*!< Max enumerator value of MEM28 field.                                 */
  #define MEMCONF_POWER_RET_MEM28_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM28_On (0x1UL)         /*!< Retention on                                                         */

/* MEM29 @Bit 29 : Keep the RAM block MEM[29] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM29_Pos (29UL)         /*!< Position of MEM29 field.                                             */
  #define MEMCONF_POWER_RET_MEM29_Msk (0x1UL << MEMCONF_POWER_RET_MEM29_Pos) /*!< Bit mask of MEM29 field.                     */
  #define MEMCONF_POWER_RET_MEM29_Min (0x0UL)        /*!< Min enumerator value of MEM29 field.                                 */
  #define MEMCONF_POWER_RET_MEM29_Max (0x1UL)        /*!< Max enumerator value of MEM29 field.                                 */
  #define MEMCONF_POWER_RET_MEM29_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM29_On (0x1UL)         /*!< Retention on                                                         */

/* MEM30 @Bit 30 : Keep the RAM block MEM[30] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM30_Pos (30UL)         /*!< Position of MEM30 field.                                             */
  #define MEMCONF_POWER_RET_MEM30_Msk (0x1UL << MEMCONF_POWER_RET_MEM30_Pos) /*!< Bit mask of MEM30 field.                     */
  #define MEMCONF_POWER_RET_MEM30_Min (0x0UL)        /*!< Min enumerator value of MEM30 field.                                 */
  #define MEMCONF_POWER_RET_MEM30_Max (0x1UL)        /*!< Max enumerator value of MEM30 field.                                 */
  #define MEMCONF_POWER_RET_MEM30_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM30_On (0x1UL)         /*!< Retention on                                                         */

/* MEM31 @Bit 31 : Keep the RAM block MEM[31] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET_MEM31_Pos (31UL)         /*!< Position of MEM31 field.                                             */
  #define MEMCONF_POWER_RET_MEM31_Msk (0x1UL << MEMCONF_POWER_RET_MEM31_Pos) /*!< Bit mask of MEM31 field.                     */
  #define MEMCONF_POWER_RET_MEM31_Min (0x0UL)        /*!< Min enumerator value of MEM31 field.                                 */
  #define MEMCONF_POWER_RET_MEM31_Max (0x1UL)        /*!< Max enumerator value of MEM31 field.                                 */
  #define MEMCONF_POWER_RET_MEM31_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET_MEM31_On (0x1UL)         /*!< Retention on                                                         */


/* MEMCONF_POWER_RET2: RAM retention for the second bank in the RAM block */
  #define MEMCONF_POWER_RET2_ResetValue (0x00000000UL) /*!< Reset value of RET2 register.                                      */

/* MEM0 @Bit 0 : Keep the second bank in RAM block MEM[0] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM0_Pos (0UL)          /*!< Position of MEM0 field.                                              */
  #define MEMCONF_POWER_RET2_MEM0_Msk (0x1UL << MEMCONF_POWER_RET2_MEM0_Pos) /*!< Bit mask of MEM0 field.                      */
  #define MEMCONF_POWER_RET2_MEM0_Min (0x0UL)        /*!< Min enumerator value of MEM0 field.                                  */
  #define MEMCONF_POWER_RET2_MEM0_Max (0x1UL)        /*!< Max enumerator value of MEM0 field.                                  */
  #define MEMCONF_POWER_RET2_MEM0_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM0_On (0x1UL)         /*!< Retention on                                                         */

/* MEM1 @Bit 1 : Keep the second bank in RAM block MEM[1] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM1_Pos (1UL)          /*!< Position of MEM1 field.                                              */
  #define MEMCONF_POWER_RET2_MEM1_Msk (0x1UL << MEMCONF_POWER_RET2_MEM1_Pos) /*!< Bit mask of MEM1 field.                      */
  #define MEMCONF_POWER_RET2_MEM1_Min (0x0UL)        /*!< Min enumerator value of MEM1 field.                                  */
  #define MEMCONF_POWER_RET2_MEM1_Max (0x1UL)        /*!< Max enumerator value of MEM1 field.                                  */
  #define MEMCONF_POWER_RET2_MEM1_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM1_On (0x1UL)         /*!< Retention on                                                         */

/* MEM2 @Bit 2 : Keep the second bank in RAM block MEM[2] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM2_Pos (2UL)          /*!< Position of MEM2 field.                                              */
  #define MEMCONF_POWER_RET2_MEM2_Msk (0x1UL << MEMCONF_POWER_RET2_MEM2_Pos) /*!< Bit mask of MEM2 field.                      */
  #define MEMCONF_POWER_RET2_MEM2_Min (0x0UL)        /*!< Min enumerator value of MEM2 field.                                  */
  #define MEMCONF_POWER_RET2_MEM2_Max (0x1UL)        /*!< Max enumerator value of MEM2 field.                                  */
  #define MEMCONF_POWER_RET2_MEM2_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM2_On (0x1UL)         /*!< Retention on                                                         */

/* MEM3 @Bit 3 : Keep the second bank in RAM block MEM[3] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM3_Pos (3UL)          /*!< Position of MEM3 field.                                              */
  #define MEMCONF_POWER_RET2_MEM3_Msk (0x1UL << MEMCONF_POWER_RET2_MEM3_Pos) /*!< Bit mask of MEM3 field.                      */
  #define MEMCONF_POWER_RET2_MEM3_Min (0x0UL)        /*!< Min enumerator value of MEM3 field.                                  */
  #define MEMCONF_POWER_RET2_MEM3_Max (0x1UL)        /*!< Max enumerator value of MEM3 field.                                  */
  #define MEMCONF_POWER_RET2_MEM3_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM3_On (0x1UL)         /*!< Retention on                                                         */

/* MEM4 @Bit 4 : Keep the second bank in RAM block MEM[4] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM4_Pos (4UL)          /*!< Position of MEM4 field.                                              */
  #define MEMCONF_POWER_RET2_MEM4_Msk (0x1UL << MEMCONF_POWER_RET2_MEM4_Pos) /*!< Bit mask of MEM4 field.                      */
  #define MEMCONF_POWER_RET2_MEM4_Min (0x0UL)        /*!< Min enumerator value of MEM4 field.                                  */
  #define MEMCONF_POWER_RET2_MEM4_Max (0x1UL)        /*!< Max enumerator value of MEM4 field.                                  */
  #define MEMCONF_POWER_RET2_MEM4_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM4_On (0x1UL)         /*!< Retention on                                                         */

/* MEM5 @Bit 5 : Keep the second bank in RAM block MEM[5] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM5_Pos (5UL)          /*!< Position of MEM5 field.                                              */
  #define MEMCONF_POWER_RET2_MEM5_Msk (0x1UL << MEMCONF_POWER_RET2_MEM5_Pos) /*!< Bit mask of MEM5 field.                      */
  #define MEMCONF_POWER_RET2_MEM5_Min (0x0UL)        /*!< Min enumerator value of MEM5 field.                                  */
  #define MEMCONF_POWER_RET2_MEM5_Max (0x1UL)        /*!< Max enumerator value of MEM5 field.                                  */
  #define MEMCONF_POWER_RET2_MEM5_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM5_On (0x1UL)         /*!< Retention on                                                         */

/* MEM6 @Bit 6 : Keep the second bank in RAM block MEM[6] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM6_Pos (6UL)          /*!< Position of MEM6 field.                                              */
  #define MEMCONF_POWER_RET2_MEM6_Msk (0x1UL << MEMCONF_POWER_RET2_MEM6_Pos) /*!< Bit mask of MEM6 field.                      */
  #define MEMCONF_POWER_RET2_MEM6_Min (0x0UL)        /*!< Min enumerator value of MEM6 field.                                  */
  #define MEMCONF_POWER_RET2_MEM6_Max (0x1UL)        /*!< Max enumerator value of MEM6 field.                                  */
  #define MEMCONF_POWER_RET2_MEM6_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM6_On (0x1UL)         /*!< Retention on                                                         */

/* MEM7 @Bit 7 : Keep the second bank in RAM block MEM[7] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM7_Pos (7UL)          /*!< Position of MEM7 field.                                              */
  #define MEMCONF_POWER_RET2_MEM7_Msk (0x1UL << MEMCONF_POWER_RET2_MEM7_Pos) /*!< Bit mask of MEM7 field.                      */
  #define MEMCONF_POWER_RET2_MEM7_Min (0x0UL)        /*!< Min enumerator value of MEM7 field.                                  */
  #define MEMCONF_POWER_RET2_MEM7_Max (0x1UL)        /*!< Max enumerator value of MEM7 field.                                  */
  #define MEMCONF_POWER_RET2_MEM7_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM7_On (0x1UL)         /*!< Retention on                                                         */

/* MEM8 @Bit 8 : Keep the second bank in RAM block MEM[8] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM8_Pos (8UL)          /*!< Position of MEM8 field.                                              */
  #define MEMCONF_POWER_RET2_MEM8_Msk (0x1UL << MEMCONF_POWER_RET2_MEM8_Pos) /*!< Bit mask of MEM8 field.                      */
  #define MEMCONF_POWER_RET2_MEM8_Min (0x0UL)        /*!< Min enumerator value of MEM8 field.                                  */
  #define MEMCONF_POWER_RET2_MEM8_Max (0x1UL)        /*!< Max enumerator value of MEM8 field.                                  */
  #define MEMCONF_POWER_RET2_MEM8_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM8_On (0x1UL)         /*!< Retention on                                                         */

/* MEM9 @Bit 9 : Keep the second bank in RAM block MEM[9] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM9_Pos (9UL)          /*!< Position of MEM9 field.                                              */
  #define MEMCONF_POWER_RET2_MEM9_Msk (0x1UL << MEMCONF_POWER_RET2_MEM9_Pos) /*!< Bit mask of MEM9 field.                      */
  #define MEMCONF_POWER_RET2_MEM9_Min (0x0UL)        /*!< Min enumerator value of MEM9 field.                                  */
  #define MEMCONF_POWER_RET2_MEM9_Max (0x1UL)        /*!< Max enumerator value of MEM9 field.                                  */
  #define MEMCONF_POWER_RET2_MEM9_Off (0x0UL)        /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM9_On (0x1UL)         /*!< Retention on                                                         */

/* MEM10 @Bit 10 : Keep the second bank in RAM block MEM[10] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM10_Pos (10UL)        /*!< Position of MEM10 field.                                             */
  #define MEMCONF_POWER_RET2_MEM10_Msk (0x1UL << MEMCONF_POWER_RET2_MEM10_Pos) /*!< Bit mask of MEM10 field.                   */
  #define MEMCONF_POWER_RET2_MEM10_Min (0x0UL)       /*!< Min enumerator value of MEM10 field.                                 */
  #define MEMCONF_POWER_RET2_MEM10_Max (0x1UL)       /*!< Max enumerator value of MEM10 field.                                 */
  #define MEMCONF_POWER_RET2_MEM10_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM10_On (0x1UL)        /*!< Retention on                                                         */

/* MEM11 @Bit 11 : Keep the second bank in RAM block MEM[11] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM11_Pos (11UL)        /*!< Position of MEM11 field.                                             */
  #define MEMCONF_POWER_RET2_MEM11_Msk (0x1UL << MEMCONF_POWER_RET2_MEM11_Pos) /*!< Bit mask of MEM11 field.                   */
  #define MEMCONF_POWER_RET2_MEM11_Min (0x0UL)       /*!< Min enumerator value of MEM11 field.                                 */
  #define MEMCONF_POWER_RET2_MEM11_Max (0x1UL)       /*!< Max enumerator value of MEM11 field.                                 */
  #define MEMCONF_POWER_RET2_MEM11_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM11_On (0x1UL)        /*!< Retention on                                                         */

/* MEM12 @Bit 12 : Keep the second bank in RAM block MEM[12] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM12_Pos (12UL)        /*!< Position of MEM12 field.                                             */
  #define MEMCONF_POWER_RET2_MEM12_Msk (0x1UL << MEMCONF_POWER_RET2_MEM12_Pos) /*!< Bit mask of MEM12 field.                   */
  #define MEMCONF_POWER_RET2_MEM12_Min (0x0UL)       /*!< Min enumerator value of MEM12 field.                                 */
  #define MEMCONF_POWER_RET2_MEM12_Max (0x1UL)       /*!< Max enumerator value of MEM12 field.                                 */
  #define MEMCONF_POWER_RET2_MEM12_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM12_On (0x1UL)        /*!< Retention on                                                         */

/* MEM13 @Bit 13 : Keep the second bank in RAM block MEM[13] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM13_Pos (13UL)        /*!< Position of MEM13 field.                                             */
  #define MEMCONF_POWER_RET2_MEM13_Msk (0x1UL << MEMCONF_POWER_RET2_MEM13_Pos) /*!< Bit mask of MEM13 field.                   */
  #define MEMCONF_POWER_RET2_MEM13_Min (0x0UL)       /*!< Min enumerator value of MEM13 field.                                 */
  #define MEMCONF_POWER_RET2_MEM13_Max (0x1UL)       /*!< Max enumerator value of MEM13 field.                                 */
  #define MEMCONF_POWER_RET2_MEM13_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM13_On (0x1UL)        /*!< Retention on                                                         */

/* MEM14 @Bit 14 : Keep the second bank in RAM block MEM[14] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM14_Pos (14UL)        /*!< Position of MEM14 field.                                             */
  #define MEMCONF_POWER_RET2_MEM14_Msk (0x1UL << MEMCONF_POWER_RET2_MEM14_Pos) /*!< Bit mask of MEM14 field.                   */
  #define MEMCONF_POWER_RET2_MEM14_Min (0x0UL)       /*!< Min enumerator value of MEM14 field.                                 */
  #define MEMCONF_POWER_RET2_MEM14_Max (0x1UL)       /*!< Max enumerator value of MEM14 field.                                 */
  #define MEMCONF_POWER_RET2_MEM14_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM14_On (0x1UL)        /*!< Retention on                                                         */

/* MEM15 @Bit 15 : Keep the second bank in RAM block MEM[15] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM15_Pos (15UL)        /*!< Position of MEM15 field.                                             */
  #define MEMCONF_POWER_RET2_MEM15_Msk (0x1UL << MEMCONF_POWER_RET2_MEM15_Pos) /*!< Bit mask of MEM15 field.                   */
  #define MEMCONF_POWER_RET2_MEM15_Min (0x0UL)       /*!< Min enumerator value of MEM15 field.                                 */
  #define MEMCONF_POWER_RET2_MEM15_Max (0x1UL)       /*!< Max enumerator value of MEM15 field.                                 */
  #define MEMCONF_POWER_RET2_MEM15_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM15_On (0x1UL)        /*!< Retention on                                                         */

/* MEM16 @Bit 16 : Keep the second bank in RAM block MEM[16] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM16_Pos (16UL)        /*!< Position of MEM16 field.                                             */
  #define MEMCONF_POWER_RET2_MEM16_Msk (0x1UL << MEMCONF_POWER_RET2_MEM16_Pos) /*!< Bit mask of MEM16 field.                   */
  #define MEMCONF_POWER_RET2_MEM16_Min (0x0UL)       /*!< Min enumerator value of MEM16 field.                                 */
  #define MEMCONF_POWER_RET2_MEM16_Max (0x1UL)       /*!< Max enumerator value of MEM16 field.                                 */
  #define MEMCONF_POWER_RET2_MEM16_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM16_On (0x1UL)        /*!< Retention on                                                         */

/* MEM17 @Bit 17 : Keep the second bank in RAM block MEM[17] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM17_Pos (17UL)        /*!< Position of MEM17 field.                                             */
  #define MEMCONF_POWER_RET2_MEM17_Msk (0x1UL << MEMCONF_POWER_RET2_MEM17_Pos) /*!< Bit mask of MEM17 field.                   */
  #define MEMCONF_POWER_RET2_MEM17_Min (0x0UL)       /*!< Min enumerator value of MEM17 field.                                 */
  #define MEMCONF_POWER_RET2_MEM17_Max (0x1UL)       /*!< Max enumerator value of MEM17 field.                                 */
  #define MEMCONF_POWER_RET2_MEM17_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM17_On (0x1UL)        /*!< Retention on                                                         */

/* MEM18 @Bit 18 : Keep the second bank in RAM block MEM[18] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM18_Pos (18UL)        /*!< Position of MEM18 field.                                             */
  #define MEMCONF_POWER_RET2_MEM18_Msk (0x1UL << MEMCONF_POWER_RET2_MEM18_Pos) /*!< Bit mask of MEM18 field.                   */
  #define MEMCONF_POWER_RET2_MEM18_Min (0x0UL)       /*!< Min enumerator value of MEM18 field.                                 */
  #define MEMCONF_POWER_RET2_MEM18_Max (0x1UL)       /*!< Max enumerator value of MEM18 field.                                 */
  #define MEMCONF_POWER_RET2_MEM18_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM18_On (0x1UL)        /*!< Retention on                                                         */

/* MEM19 @Bit 19 : Keep the second bank in RAM block MEM[19] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM19_Pos (19UL)        /*!< Position of MEM19 field.                                             */
  #define MEMCONF_POWER_RET2_MEM19_Msk (0x1UL << MEMCONF_POWER_RET2_MEM19_Pos) /*!< Bit mask of MEM19 field.                   */
  #define MEMCONF_POWER_RET2_MEM19_Min (0x0UL)       /*!< Min enumerator value of MEM19 field.                                 */
  #define MEMCONF_POWER_RET2_MEM19_Max (0x1UL)       /*!< Max enumerator value of MEM19 field.                                 */
  #define MEMCONF_POWER_RET2_MEM19_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM19_On (0x1UL)        /*!< Retention on                                                         */

/* MEM20 @Bit 20 : Keep the second bank in RAM block MEM[20] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM20_Pos (20UL)        /*!< Position of MEM20 field.                                             */
  #define MEMCONF_POWER_RET2_MEM20_Msk (0x1UL << MEMCONF_POWER_RET2_MEM20_Pos) /*!< Bit mask of MEM20 field.                   */
  #define MEMCONF_POWER_RET2_MEM20_Min (0x0UL)       /*!< Min enumerator value of MEM20 field.                                 */
  #define MEMCONF_POWER_RET2_MEM20_Max (0x1UL)       /*!< Max enumerator value of MEM20 field.                                 */
  #define MEMCONF_POWER_RET2_MEM20_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM20_On (0x1UL)        /*!< Retention on                                                         */

/* MEM21 @Bit 21 : Keep the second bank in RAM block MEM[21] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM21_Pos (21UL)        /*!< Position of MEM21 field.                                             */
  #define MEMCONF_POWER_RET2_MEM21_Msk (0x1UL << MEMCONF_POWER_RET2_MEM21_Pos) /*!< Bit mask of MEM21 field.                   */
  #define MEMCONF_POWER_RET2_MEM21_Min (0x0UL)       /*!< Min enumerator value of MEM21 field.                                 */
  #define MEMCONF_POWER_RET2_MEM21_Max (0x1UL)       /*!< Max enumerator value of MEM21 field.                                 */
  #define MEMCONF_POWER_RET2_MEM21_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM21_On (0x1UL)        /*!< Retention on                                                         */

/* MEM22 @Bit 22 : Keep the second bank in RAM block MEM[22] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM22_Pos (22UL)        /*!< Position of MEM22 field.                                             */
  #define MEMCONF_POWER_RET2_MEM22_Msk (0x1UL << MEMCONF_POWER_RET2_MEM22_Pos) /*!< Bit mask of MEM22 field.                   */
  #define MEMCONF_POWER_RET2_MEM22_Min (0x0UL)       /*!< Min enumerator value of MEM22 field.                                 */
  #define MEMCONF_POWER_RET2_MEM22_Max (0x1UL)       /*!< Max enumerator value of MEM22 field.                                 */
  #define MEMCONF_POWER_RET2_MEM22_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM22_On (0x1UL)        /*!< Retention on                                                         */

/* MEM23 @Bit 23 : Keep the second bank in RAM block MEM[23] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM23_Pos (23UL)        /*!< Position of MEM23 field.                                             */
  #define MEMCONF_POWER_RET2_MEM23_Msk (0x1UL << MEMCONF_POWER_RET2_MEM23_Pos) /*!< Bit mask of MEM23 field.                   */
  #define MEMCONF_POWER_RET2_MEM23_Min (0x0UL)       /*!< Min enumerator value of MEM23 field.                                 */
  #define MEMCONF_POWER_RET2_MEM23_Max (0x1UL)       /*!< Max enumerator value of MEM23 field.                                 */
  #define MEMCONF_POWER_RET2_MEM23_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM23_On (0x1UL)        /*!< Retention on                                                         */

/* MEM24 @Bit 24 : Keep the second bank in RAM block MEM[24] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM24_Pos (24UL)        /*!< Position of MEM24 field.                                             */
  #define MEMCONF_POWER_RET2_MEM24_Msk (0x1UL << MEMCONF_POWER_RET2_MEM24_Pos) /*!< Bit mask of MEM24 field.                   */
  #define MEMCONF_POWER_RET2_MEM24_Min (0x0UL)       /*!< Min enumerator value of MEM24 field.                                 */
  #define MEMCONF_POWER_RET2_MEM24_Max (0x1UL)       /*!< Max enumerator value of MEM24 field.                                 */
  #define MEMCONF_POWER_RET2_MEM24_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM24_On (0x1UL)        /*!< Retention on                                                         */

/* MEM25 @Bit 25 : Keep the second bank in RAM block MEM[25] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM25_Pos (25UL)        /*!< Position of MEM25 field.                                             */
  #define MEMCONF_POWER_RET2_MEM25_Msk (0x1UL << MEMCONF_POWER_RET2_MEM25_Pos) /*!< Bit mask of MEM25 field.                   */
  #define MEMCONF_POWER_RET2_MEM25_Min (0x0UL)       /*!< Min enumerator value of MEM25 field.                                 */
  #define MEMCONF_POWER_RET2_MEM25_Max (0x1UL)       /*!< Max enumerator value of MEM25 field.                                 */
  #define MEMCONF_POWER_RET2_MEM25_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM25_On (0x1UL)        /*!< Retention on                                                         */

/* MEM26 @Bit 26 : Keep the second bank in RAM block MEM[26] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM26_Pos (26UL)        /*!< Position of MEM26 field.                                             */
  #define MEMCONF_POWER_RET2_MEM26_Msk (0x1UL << MEMCONF_POWER_RET2_MEM26_Pos) /*!< Bit mask of MEM26 field.                   */
  #define MEMCONF_POWER_RET2_MEM26_Min (0x0UL)       /*!< Min enumerator value of MEM26 field.                                 */
  #define MEMCONF_POWER_RET2_MEM26_Max (0x1UL)       /*!< Max enumerator value of MEM26 field.                                 */
  #define MEMCONF_POWER_RET2_MEM26_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM26_On (0x1UL)        /*!< Retention on                                                         */

/* MEM27 @Bit 27 : Keep the second bank in RAM block MEM[27] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM27_Pos (27UL)        /*!< Position of MEM27 field.                                             */
  #define MEMCONF_POWER_RET2_MEM27_Msk (0x1UL << MEMCONF_POWER_RET2_MEM27_Pos) /*!< Bit mask of MEM27 field.                   */
  #define MEMCONF_POWER_RET2_MEM27_Min (0x0UL)       /*!< Min enumerator value of MEM27 field.                                 */
  #define MEMCONF_POWER_RET2_MEM27_Max (0x1UL)       /*!< Max enumerator value of MEM27 field.                                 */
  #define MEMCONF_POWER_RET2_MEM27_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM27_On (0x1UL)        /*!< Retention on                                                         */

/* MEM28 @Bit 28 : Keep the second bank in RAM block MEM[28] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM28_Pos (28UL)        /*!< Position of MEM28 field.                                             */
  #define MEMCONF_POWER_RET2_MEM28_Msk (0x1UL << MEMCONF_POWER_RET2_MEM28_Pos) /*!< Bit mask of MEM28 field.                   */
  #define MEMCONF_POWER_RET2_MEM28_Min (0x0UL)       /*!< Min enumerator value of MEM28 field.                                 */
  #define MEMCONF_POWER_RET2_MEM28_Max (0x1UL)       /*!< Max enumerator value of MEM28 field.                                 */
  #define MEMCONF_POWER_RET2_MEM28_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM28_On (0x1UL)        /*!< Retention on                                                         */

/* MEM29 @Bit 29 : Keep the second bank in RAM block MEM[29] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM29_Pos (29UL)        /*!< Position of MEM29 field.                                             */
  #define MEMCONF_POWER_RET2_MEM29_Msk (0x1UL << MEMCONF_POWER_RET2_MEM29_Pos) /*!< Bit mask of MEM29 field.                   */
  #define MEMCONF_POWER_RET2_MEM29_Min (0x0UL)       /*!< Min enumerator value of MEM29 field.                                 */
  #define MEMCONF_POWER_RET2_MEM29_Max (0x1UL)       /*!< Max enumerator value of MEM29 field.                                 */
  #define MEMCONF_POWER_RET2_MEM29_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM29_On (0x1UL)        /*!< Retention on                                                         */

/* MEM30 @Bit 30 : Keep the second bank in RAM block MEM[30] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM30_Pos (30UL)        /*!< Position of MEM30 field.                                             */
  #define MEMCONF_POWER_RET2_MEM30_Msk (0x1UL << MEMCONF_POWER_RET2_MEM30_Pos) /*!< Bit mask of MEM30 field.                   */
  #define MEMCONF_POWER_RET2_MEM30_Min (0x0UL)       /*!< Min enumerator value of MEM30 field.                                 */
  #define MEMCONF_POWER_RET2_MEM30_Max (0x1UL)       /*!< Max enumerator value of MEM30 field.                                 */
  #define MEMCONF_POWER_RET2_MEM30_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM30_On (0x1UL)        /*!< Retention on                                                         */

/* MEM31 @Bit 31 : Keep the second bank in RAM block MEM[31] retained when in System OFF mode. */
  #define MEMCONF_POWER_RET2_MEM31_Pos (31UL)        /*!< Position of MEM31 field.                                             */
  #define MEMCONF_POWER_RET2_MEM31_Msk (0x1UL << MEMCONF_POWER_RET2_MEM31_Pos) /*!< Bit mask of MEM31 field.                   */
  #define MEMCONF_POWER_RET2_MEM31_Min (0x0UL)       /*!< Min enumerator value of MEM31 field.                                 */
  #define MEMCONF_POWER_RET2_MEM31_Max (0x1UL)       /*!< Max enumerator value of MEM31 field.                                 */
  #define MEMCONF_POWER_RET2_MEM31_Off (0x0UL)       /*!< Retention off                                                        */
  #define MEMCONF_POWER_RET2_MEM31_On (0x1UL)        /*!< Retention on                                                         */


/* ===================================================== Struct MEMCONF ====================================================== */
/**
  * @brief Memory configuration
  */
  typedef struct {                                   /*!< MEMCONF Structure                                                    */
    __IM uint32_t RESERVED[320];
    __IOM NRF_MEMCONF_POWER_Type POWER[2];           /*!< (@ 0x00000500) (unspecified)                                         */
  } NRF_MEMCONF_Type;                                /*!< Size = 1312 (0x520)                                                  */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            MPC                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================== Struct MPC_MEMACCERR =================================================== */
/**
  * @brief MEMACCERR [MPC_MEMACCERR] Memory Access Error status registers
  */
typedef struct {
  __IM  uint32_t  ADDRESS;                           /*!< (@ 0x00000000) Target Address of Memory Access Error. Register content
                                                                         won't be changed as long as MEMACCERR event is active.*/
  __IM  uint32_t  INFO;                              /*!< (@ 0x00000004) Access information for the transaction that triggered a
                                                                         memory access error. Register content won't be changed
                                                                         as long as MEMACCERR event is active.*/
} NRF_MPC_MEMACCERR_Type;                            /*!< Size = 8 (0x008)                                                     */

/* MPC_MEMACCERR_ADDRESS: Target Address of Memory Access Error. Register content won't be changed as long as MEMACCERR event is
                           active. */

  #define MPC_MEMACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register.                                */

/* ADDRESS @Bits 0..31 : Target address for erroneous access */
  #define MPC_MEMACCERR_ADDRESS_ADDRESS_Pos (0UL)    /*!< Position of ADDRESS field.                                           */
  #define MPC_MEMACCERR_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MPC_MEMACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.*/


/* MPC_MEMACCERR_INFO: Access information for the transaction that triggered a memory access error. Register content won't be
                        changed as long as MEMACCERR event is active. */

  #define MPC_MEMACCERR_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register.                                      */

/* READ @Bit 12 : Read bit of bus access */
  #define MPC_MEMACCERR_INFO_READ_Pos (12UL)         /*!< Position of READ field.                                              */
  #define MPC_MEMACCERR_INFO_READ_Msk (0x1UL << MPC_MEMACCERR_INFO_READ_Pos) /*!< Bit mask of READ field.                      */
  #define MPC_MEMACCERR_INFO_READ_Min (0x0UL)        /*!< Min enumerator value of READ field.                                  */
  #define MPC_MEMACCERR_INFO_READ_Max (0x1UL)        /*!< Max enumerator value of READ field.                                  */
  #define MPC_MEMACCERR_INFO_READ_Set (0x1UL)        /*!< Read access bit was set                                              */
  #define MPC_MEMACCERR_INFO_READ_NotSet (0x0UL)     /*!< Read access bit was not set                                          */

/* WRITE @Bit 13 : Write bit of bus access */
  #define MPC_MEMACCERR_INFO_WRITE_Pos (13UL)        /*!< Position of WRITE field.                                             */
  #define MPC_MEMACCERR_INFO_WRITE_Msk (0x1UL << MPC_MEMACCERR_INFO_WRITE_Pos) /*!< Bit mask of WRITE field.                   */
  #define MPC_MEMACCERR_INFO_WRITE_Min (0x0UL)       /*!< Min enumerator value of WRITE field.                                 */
  #define MPC_MEMACCERR_INFO_WRITE_Max (0x1UL)       /*!< Max enumerator value of WRITE field.                                 */
  #define MPC_MEMACCERR_INFO_WRITE_Set (0x1UL)       /*!< Write access bit was set                                             */
  #define MPC_MEMACCERR_INFO_WRITE_NotSet (0x0UL)    /*!< Write access bit was not set                                         */

/* EXECUTE @Bit 14 : Execute bit of bus access */
  #define MPC_MEMACCERR_INFO_EXECUTE_Pos (14UL)      /*!< Position of EXECUTE field.                                           */
  #define MPC_MEMACCERR_INFO_EXECUTE_Msk (0x1UL << MPC_MEMACCERR_INFO_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.             */
  #define MPC_MEMACCERR_INFO_EXECUTE_Min (0x0UL)     /*!< Min enumerator value of EXECUTE field.                               */
  #define MPC_MEMACCERR_INFO_EXECUTE_Max (0x1UL)     /*!< Max enumerator value of EXECUTE field.                               */
  #define MPC_MEMACCERR_INFO_EXECUTE_Set (0x1UL)     /*!< Execute access bit was set                                           */
  #define MPC_MEMACCERR_INFO_EXECUTE_NotSet (0x0UL)  /*!< Execute access bit was not set                                       */

/* SECURE @Bit 15 : Secure bit of bus access */
  #define MPC_MEMACCERR_INFO_SECURE_Pos (15UL)       /*!< Position of SECURE field.                                            */
  #define MPC_MEMACCERR_INFO_SECURE_Msk (0x1UL << MPC_MEMACCERR_INFO_SECURE_Pos) /*!< Bit mask of SECURE field.                */
  #define MPC_MEMACCERR_INFO_SECURE_Min (0x0UL)      /*!< Min enumerator value of SECURE field.                                */
  #define MPC_MEMACCERR_INFO_SECURE_Max (0x1UL)      /*!< Max enumerator value of SECURE field.                                */
  #define MPC_MEMACCERR_INFO_SECURE_Set (0x1UL)      /*!< Secure access bit was set                                            */
  #define MPC_MEMACCERR_INFO_SECURE_NotSet (0x0UL)   /*!< Secure access bit was not set                                        */

/* ERRORSOURCE @Bit 16 : Source of memory access error */
  #define MPC_MEMACCERR_INFO_ERRORSOURCE_Pos (16UL)  /*!< Position of ERRORSOURCE field.                                       */
  #define MPC_MEMACCERR_INFO_ERRORSOURCE_Msk (0x1UL << MPC_MEMACCERR_INFO_ERRORSOURCE_Pos) /*!< Bit mask of ERRORSOURCE field. */
  #define MPC_MEMACCERR_INFO_ERRORSOURCE_Min (0x0UL) /*!< Min enumerator value of ERRORSOURCE field.                           */
  #define MPC_MEMACCERR_INFO_ERRORSOURCE_Max (0x1UL) /*!< Max enumerator value of ERRORSOURCE field.                           */
  #define MPC_MEMACCERR_INFO_ERRORSOURCE_MPC (0x1UL) /*!< Error was triggered by MPC module                                    */
  #define MPC_MEMACCERR_INFO_ERRORSOURCE_Slave (0x0UL) /*!< Error was triggered by a Subordinate                               */



/* =================================================== Struct MPC_OVERRIDE =================================================== */
/**
  * @brief OVERRIDE [MPC_OVERRIDE] Special privilege tables
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Override region n Configuration register              */
  __IOM uint32_t  STARTADDR;                         /*!< (@ 0x00000004) Override region n Start Address                       */
  __IOM uint32_t  ENDADDR;                           /*!< (@ 0x00000008) Override region n End Address                         */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PERM;                              /*!< (@ 0x00000010) Permission settings for override region n             */
  __IOM uint32_t  PERMMASK;                          /*!< (@ 0x00000014) Masks permission setting fields from register
                                                                         OVERRIDE.PERM*/
  __IM  uint32_t  RESERVED1[2];
} NRF_MPC_OVERRIDE_Type;                             /*!< Size = 32 (0x020)                                                    */
  #define MPC_OVERRIDE_MaxCount (7UL)                /*!< Size of OVERRIDE[7] array.                                           */
  #define MPC_OVERRIDE_MaxIndex (6UL)                /*!< Max index of OVERRIDE[7] array.                                      */
  #define MPC_OVERRIDE_MinIndex (0UL)                /*!< Min index of OVERRIDE[7] array.                                      */

/* MPC_OVERRIDE_CONFIG: Override region n Configuration register */
  #define MPC_OVERRIDE_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                                   */

/* LOCK @Bit 8 : Lock Override region n */
  #define MPC_OVERRIDE_CONFIG_LOCK_Pos (8UL)         /*!< Position of LOCK field.                                              */
  #define MPC_OVERRIDE_CONFIG_LOCK_Msk (0x1UL << MPC_OVERRIDE_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field.                    */
  #define MPC_OVERRIDE_CONFIG_LOCK_Min (0x0UL)       /*!< Min enumerator value of LOCK field.                                  */
  #define MPC_OVERRIDE_CONFIG_LOCK_Max (0x1UL)       /*!< Max enumerator value of LOCK field.                                  */
  #define MPC_OVERRIDE_CONFIG_LOCK_Unlocked (0x0UL)  /*!< Override region n settings can be updated                            */
  #define MPC_OVERRIDE_CONFIG_LOCK_Locked (0x1UL)    /*!< Override region n settings can't be updated until next reset         */

/* ENABLE @Bit 9 : Enable Override region n */
  #define MPC_OVERRIDE_CONFIG_ENABLE_Pos (9UL)       /*!< Position of ENABLE field.                                            */
  #define MPC_OVERRIDE_CONFIG_ENABLE_Msk (0x1UL << MPC_OVERRIDE_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field.              */
  #define MPC_OVERRIDE_CONFIG_ENABLE_Min (0x0UL)     /*!< Min enumerator value of ENABLE field.                                */
  #define MPC_OVERRIDE_CONFIG_ENABLE_Max (0x1UL)     /*!< Max enumerator value of ENABLE field.                                */
  #define MPC_OVERRIDE_CONFIG_ENABLE_Disabled (0x0UL) /*!< Override region n is not used                                       */
  #define MPC_OVERRIDE_CONFIG_ENABLE_Enabled (0x1UL) /*!< Override region n is used                                            */


/* MPC_OVERRIDE_STARTADDR: Override region n Start Address */
  #define MPC_OVERRIDE_STARTADDR_ResetValue (0x00000000UL) /*!< Reset value of STARTADDR register.                             */

/* STARTADDR @Bits 0..31 : Start address for override region n */
  #define MPC_OVERRIDE_STARTADDR_STARTADDR_Pos (0UL) /*!< Position of STARTADDR field.                                         */
  #define MPC_OVERRIDE_STARTADDR_STARTADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_STARTADDR_STARTADDR_Pos) /*!< Bit mask of STARTADDR
                                                                            field.*/


/* MPC_OVERRIDE_ENDADDR: Override region n End Address */
  #define MPC_OVERRIDE_ENDADDR_ResetValue (0x00000000UL) /*!< Reset value of ENDADDR register.                                 */

/* ENDADDR @Bits 0..31 : End address for override region n */
  #define MPC_OVERRIDE_ENDADDR_ENDADDR_Pos (0UL)     /*!< Position of ENDADDR field.                                           */
  #define MPC_OVERRIDE_ENDADDR_ENDADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_ENDADDR_ENDADDR_Pos) /*!< Bit mask of ENDADDR field.  */


/* MPC_OVERRIDE_PERM: Permission settings for override region n */
  #define MPC_OVERRIDE_PERM_ResetValue (0x00000000UL) /*!< Reset value of PERM register.                                       */

/* READ @Bit 0 : Read access */
  #define MPC_OVERRIDE_PERM_READ_Pos (0UL)           /*!< Position of READ field.                                              */
  #define MPC_OVERRIDE_PERM_READ_Msk (0x1UL << MPC_OVERRIDE_PERM_READ_Pos) /*!< Bit mask of READ field.                        */
  #define MPC_OVERRIDE_PERM_READ_Min (0x0UL)         /*!< Min enumerator value of READ field.                                  */
  #define MPC_OVERRIDE_PERM_READ_Max (0x1UL)         /*!< Max enumerator value of READ field.                                  */
  #define MPC_OVERRIDE_PERM_READ_NotAllowed (0x0UL)  /*!< Read access to override region n is not allowed                      */
  #define MPC_OVERRIDE_PERM_READ_Allowed (0x1UL)     /*!< Read access to override region n is allowed                          */

/* WRITE @Bit 1 : Write access */
  #define MPC_OVERRIDE_PERM_WRITE_Pos (1UL)          /*!< Position of WRITE field.                                             */
  #define MPC_OVERRIDE_PERM_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERM_WRITE_Pos) /*!< Bit mask of WRITE field.                     */
  #define MPC_OVERRIDE_PERM_WRITE_Min (0x0UL)        /*!< Min enumerator value of WRITE field.                                 */
  #define MPC_OVERRIDE_PERM_WRITE_Max (0x1UL)        /*!< Max enumerator value of WRITE field.                                 */
  #define MPC_OVERRIDE_PERM_WRITE_NotAllowed (0x0UL) /*!< Write access to override region n is not allowed                     */
  #define MPC_OVERRIDE_PERM_WRITE_Allowed (0x1UL)    /*!< Write access to override region n is allowed                         */

/* EXECUTE @Bit 2 : Software execute */
  #define MPC_OVERRIDE_PERM_EXECUTE_Pos (2UL)        /*!< Position of EXECUTE field.                                           */
  #define MPC_OVERRIDE_PERM_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.               */
  #define MPC_OVERRIDE_PERM_EXECUTE_Min (0x0UL)      /*!< Min enumerator value of EXECUTE field.                               */
  #define MPC_OVERRIDE_PERM_EXECUTE_Max (0x1UL)      /*!< Max enumerator value of EXECUTE field.                               */
  #define MPC_OVERRIDE_PERM_EXECUTE_NotAllowed (0x0UL) /*!< Software execution from override region n is not allowed           */
  #define MPC_OVERRIDE_PERM_EXECUTE_Allowed (0x1UL)  /*!< Software execution from override region n is allowed                 */

/* SECATTR @Bit 3 : Security mapping */
  #define MPC_OVERRIDE_PERM_SECATTR_Pos (3UL)        /*!< Position of SECATTR field.                                           */
  #define MPC_OVERRIDE_PERM_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field.               */
  #define MPC_OVERRIDE_PERM_SECATTR_Min (0x0UL)      /*!< Min enumerator value of SECATTR field.                               */
  #define MPC_OVERRIDE_PERM_SECATTR_Max (0x1UL)      /*!< Max enumerator value of SECATTR field.                               */
  #define MPC_OVERRIDE_PERM_SECATTR_Secure (0x1UL)   /*!< Override region n is mapped in secure memory address space           */
  #define MPC_OVERRIDE_PERM_SECATTR_NonSecure (0x0UL) /*!< Override region n is mapped in non-secure memory address space      */


/* MPC_OVERRIDE_PERMMASK: Masks permission setting fields from register OVERRIDE.PERM */
  #define MPC_OVERRIDE_PERMMASK_ResetValue (0x00000000UL) /*!< Reset value of PERMMASK register.                               */

/* READ @Bit 0 : Read mask */
  #define MPC_OVERRIDE_PERMMASK_READ_Pos (0UL)       /*!< Position of READ field.                                              */
  #define MPC_OVERRIDE_PERMMASK_READ_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_READ_Pos) /*!< Bit mask of READ field.                */
  #define MPC_OVERRIDE_PERMMASK_READ_Min (0x0UL)     /*!< Min enumerator value of READ field.                                  */
  #define MPC_OVERRIDE_PERMMASK_READ_Max (0x1UL)     /*!< Max enumerator value of READ field.                                  */
  #define MPC_OVERRIDE_PERMMASK_READ_Masked (0x0UL)  /*!< Permission setting READ in OVERRIDE register will not be applied     */
  #define MPC_OVERRIDE_PERMMASK_READ_UnMasked (0x1UL) /*!< Permission setting READ in OVERRIDE register will be applied        */

/* WRITE @Bit 1 : Write mask */
  #define MPC_OVERRIDE_PERMMASK_WRITE_Pos (1UL)      /*!< Position of WRITE field.                                             */
  #define MPC_OVERRIDE_PERMMASK_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_WRITE_Pos) /*!< Bit mask of WRITE field.             */
  #define MPC_OVERRIDE_PERMMASK_WRITE_Min (0x0UL)    /*!< Min enumerator value of WRITE field.                                 */
  #define MPC_OVERRIDE_PERMMASK_WRITE_Max (0x1UL)    /*!< Max enumerator value of WRITE field.                                 */
  #define MPC_OVERRIDE_PERMMASK_WRITE_Masked (0x0UL) /*!< Permission setting WRITE in OVERRIDE register will not be applied    */
  #define MPC_OVERRIDE_PERMMASK_WRITE_UnMasked (0x1UL) /*!< Permission setting WRITE in OVERRIDE register will be applied      */

/* EXECUTE @Bit 2 : Execute mask */
  #define MPC_OVERRIDE_PERMMASK_EXECUTE_Pos (2UL)    /*!< Position of EXECUTE field.                                           */
  #define MPC_OVERRIDE_PERMMASK_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.       */
  #define MPC_OVERRIDE_PERMMASK_EXECUTE_Min (0x0UL)  /*!< Min enumerator value of EXECUTE field.                               */
  #define MPC_OVERRIDE_PERMMASK_EXECUTE_Max (0x1UL)  /*!< Max enumerator value of EXECUTE field.                               */
  #define MPC_OVERRIDE_PERMMASK_EXECUTE_Masked (0x0UL) /*!< Permission setting EXECUTE in OVERRIDE register will not be applied*/
  #define MPC_OVERRIDE_PERMMASK_EXECUTE_UnMasked (0x1UL) /*!< Permission setting EXECUTE in OVERRIDE register will be applied  */

/* SECATTR @Bit 3 : Security mapping mask */
  #define MPC_OVERRIDE_PERMMASK_SECATTR_Pos (3UL)    /*!< Position of SECATTR field.                                           */
  #define MPC_OVERRIDE_PERMMASK_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_SECATTR_Pos) /*!< Bit mask of SECATTR field.       */
  #define MPC_OVERRIDE_PERMMASK_SECATTR_Min (0x0UL)  /*!< Min enumerator value of SECATTR field.                               */
  #define MPC_OVERRIDE_PERMMASK_SECATTR_Max (0x1UL)  /*!< Max enumerator value of SECATTR field.                               */
  #define MPC_OVERRIDE_PERMMASK_SECATTR_Masked (0x0UL) /*!< Permission setting SECATTR in OVERRIDE register will not be applied*/
  #define MPC_OVERRIDE_PERMMASK_SECATTR_UnMasked (0x1UL) /*!< Permission setting SECATTR in OVERRIDE register will be applied  */


/* ======================================================= Struct MPC ======================================================== */
/**
  * @brief Memory Privilege Controller
  */
  typedef struct {                                   /*!< MPC Structure                                                        */
    __IM uint32_t RESERVED[64];
    __IOM uint32_t EVENTS_MEMACCERR;                 /*!< (@ 0x00000100) Memory Access Error event                             */
    __IM uint32_t RESERVED1[127];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED2[61];
    __IOM NRF_MPC_MEMACCERR_Type MEMACCERR;          /*!< (@ 0x00000400) Memory Access Error status registers                  */
    __IM uint32_t RESERVED3[254];
    __IOM NRF_MPC_OVERRIDE_Type OVERRIDE[7];         /*!< (@ 0x00000800) Special privilege tables                              */
  } NRF_MPC_Type;                                    /*!< Size = 2272 (0x8E0)                                                  */

/* MPC_EVENTS_MEMACCERR: Memory Access Error event */
  #define MPC_EVENTS_MEMACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MEMACCERR register.                        */

/* EVENTS_MEMACCERR @Bit 0 : Memory Access Error event */
  #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos (0UL) /*!< Position of EVENTS_MEMACCERR field.                             */
  #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Msk (0x1UL << MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos) /*!< Bit mask of
                                                                            EVENTS_MEMACCERR field.*/
  #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_MEMACCERR field.               */
  #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_MEMACCERR field.               */
  #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Generated (0x1UL) /*!< Event generated                                         */


/* MPC_INTEN: Enable or disable interrupt */
  #define MPC_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */

/* MEMACCERR @Bit 0 : Enable or disable interrupt for event MEMACCERR */
  #define MPC_INTEN_MEMACCERR_Pos (0UL)              /*!< Position of MEMACCERR field.                                         */
  #define MPC_INTEN_MEMACCERR_Msk (0x1UL << MPC_INTEN_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field.                         */
  #define MPC_INTEN_MEMACCERR_Min (0x0UL)            /*!< Min enumerator value of MEMACCERR field.                             */
  #define MPC_INTEN_MEMACCERR_Max (0x1UL)            /*!< Max enumerator value of MEMACCERR field.                             */
  #define MPC_INTEN_MEMACCERR_Disabled (0x0UL)       /*!< Disable                                                              */
  #define MPC_INTEN_MEMACCERR_Enabled (0x1UL)        /*!< Enable                                                               */


/* MPC_INTENSET: Enable interrupt */
  #define MPC_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* MEMACCERR @Bit 0 : Write '1' to enable interrupt for event MEMACCERR */
  #define MPC_INTENSET_MEMACCERR_Pos (0UL)           /*!< Position of MEMACCERR field.                                         */
  #define MPC_INTENSET_MEMACCERR_Msk (0x1UL << MPC_INTENSET_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field.                   */
  #define MPC_INTENSET_MEMACCERR_Min (0x0UL)         /*!< Min enumerator value of MEMACCERR field.                             */
  #define MPC_INTENSET_MEMACCERR_Max (0x1UL)         /*!< Max enumerator value of MEMACCERR field.                             */
  #define MPC_INTENSET_MEMACCERR_Set (0x1UL)         /*!< Enable                                                               */
  #define MPC_INTENSET_MEMACCERR_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define MPC_INTENSET_MEMACCERR_Enabled (0x1UL)     /*!< Read: Enabled                                                        */


/* MPC_INTENCLR: Disable interrupt */
  #define MPC_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* MEMACCERR @Bit 0 : Write '1' to disable interrupt for event MEMACCERR */
  #define MPC_INTENCLR_MEMACCERR_Pos (0UL)           /*!< Position of MEMACCERR field.                                         */
  #define MPC_INTENCLR_MEMACCERR_Msk (0x1UL << MPC_INTENCLR_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field.                   */
  #define MPC_INTENCLR_MEMACCERR_Min (0x0UL)         /*!< Min enumerator value of MEMACCERR field.                             */
  #define MPC_INTENCLR_MEMACCERR_Max (0x1UL)         /*!< Max enumerator value of MEMACCERR field.                             */
  #define MPC_INTENCLR_MEMACCERR_Clear (0x1UL)       /*!< Disable                                                              */
  #define MPC_INTENCLR_MEMACCERR_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define MPC_INTENCLR_MEMACCERR_Enabled (0x1UL)     /*!< Read: Enabled                                                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           NFCT                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================= Struct NFCT_FRAMESTATUS ================================================= */
/**
  * @brief FRAMESTATUS [NFCT_FRAMESTATUS] (unspecified)
  */
typedef struct {
  __IOM uint32_t  RX;                                /*!< (@ 0x00000000) Result of last incoming frame                         */
} NRF_NFCT_FRAMESTATUS_Type;                         /*!< Size = 4 (0x004)                                                     */

/* NFCT_FRAMESTATUS_RX: Result of last incoming frame */
  #define NFCT_FRAMESTATUS_RX_ResetValue (0x00000000UL) /*!< Reset value of RX register.                                       */

/* CRCERROR @Bit 0 : No valid end of frame (EoF) detected */
  #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL)     /*!< Position of CRCERROR field.                                          */
  #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.        */
  #define NFCT_FRAMESTATUS_RX_CRCERROR_Min (0x0UL)   /*!< Min enumerator value of CRCERROR field.                              */
  #define NFCT_FRAMESTATUS_RX_CRCERROR_Max (0x1UL)   /*!< Max enumerator value of CRCERROR field.                              */
  #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0x0UL) /*!< Valid CRC detected                                              */
  #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (0x1UL) /*!< CRC received does not match local check                           */

/* PARITYSTATUS @Bit 2 : Parity status of received frame */
  #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field.                                      */
  #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS
                                                                            field.*/
  #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Min (0x0UL) /*!< Min enumerator value of PARITYSTATUS field.                        */
  #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Max (0x1UL) /*!< Max enumerator value of PARITYSTATUS field.                        */
  #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0x0UL) /*!< Frame received with parity OK                                 */
  #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (0x1UL) /*!< Frame received with parity error                           */

/* OVERRUN @Bit 3 : Overrun detected */
  #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL)      /*!< Position of OVERRUN field.                                           */
  #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field.           */
  #define NFCT_FRAMESTATUS_RX_OVERRUN_Min (0x0UL)    /*!< Min enumerator value of OVERRUN field.                               */
  #define NFCT_FRAMESTATUS_RX_OVERRUN_Max (0x1UL)    /*!< Max enumerator value of OVERRUN field.                               */
  #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0x0UL) /*!< No overrun detected                                               */
  #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (0x1UL) /*!< Overrun error                                                       */



/* ===================================================== Struct NFCT_TXD ===================================================== */
/**
  * @brief TXD [NFCT_TXD] (unspecified)
  */
typedef struct {
  __IOM uint32_t  FRAMECONFIG;                       /*!< (@ 0x00000000) Configuration of outgoing frames                      */
  __IOM uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Size of outgoing frame                                */
} NRF_NFCT_TXD_Type;                                 /*!< Size = 8 (0x008)                                                     */

/* NFCT_TXD_FRAMECONFIG: Configuration of outgoing frames */
  #define NFCT_TXD_FRAMECONFIG_ResetValue (0x00000017UL) /*!< Reset value of FRAMECONFIG register.                             */

/* PARITY @Bit 0 : Indicates if parity is added to the frame */
  #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL)      /*!< Position of PARITY field.                                            */
  #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field.            */
  #define NFCT_TXD_FRAMECONFIG_PARITY_Min (0x0UL)    /*!< Min enumerator value of PARITY field.                                */
  #define NFCT_TXD_FRAMECONFIG_PARITY_Max (0x1UL)    /*!< Max enumerator value of PARITY field.                                */
  #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not added to TX frames                                   */
  #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is added to TX frames                                         */

/* DISCARDMODE @Bit 1 : Discarding unused bits at start or end of a frame */
  #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field.                                       */
  #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE
                                                                            field.*/
  #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Min (0x0UL) /*!< Min enumerator value of DISCARDMODE field.                         */
  #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Max (0x1UL) /*!< Max enumerator value of DISCARDMODE field.                         */
  #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0x0UL) /*!< Unused bits are discarded at end of frame (EoF)             */
  #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (0x1UL) /*!< Unused bits are discarded at start of frame (SoF)         */

/* SOF @Bit 2 : Adding SoF or not in TX frames */
  #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL)         /*!< Position of SOF field.                                               */
  #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field.                     */
  #define NFCT_TXD_FRAMECONFIG_SOF_Min (0x0UL)       /*!< Min enumerator value of SOF field.                                   */
  #define NFCT_TXD_FRAMECONFIG_SOF_Max (0x1UL)       /*!< Max enumerator value of SOF field.                                   */
  #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0x0UL)     /*!< SoF symbol not added                                                 */
  #define NFCT_TXD_FRAMECONFIG_SOF_SoF (0x1UL)       /*!< SoF symbol added                                                     */

/* CRCMODETX @Bit 4 : CRC mode for outgoing frames */
  #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL)   /*!< Position of CRCMODETX field.                                         */
  #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field.   */
  #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Min (0x0UL) /*!< Min enumerator value of CRCMODETX field.                             */
  #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Max (0x1UL) /*!< Max enumerator value of CRCMODETX field.                             */
  #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0x0UL) /*!< CRC is not added to the frame                                    */
  #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (0x1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM
                                                              that is used in the frame*/


/* NFCT_TXD_AMOUNT: Size of outgoing frame */
  #define NFCT_TXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */

/* TXDATABITS @Bits 0..2 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding
                           parity bit). */

  #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL)       /*!< Position of TXDATABITS field.                                        */
  #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field.          */
  #define NFCT_TXD_AMOUNT_TXDATABITS_Min (0x0UL)     /*!< Min value of TXDATABITS field.                                       */
  #define NFCT_TXD_AMOUNT_TXDATABITS_Max (0x7UL)     /*!< Max size of TXDATABITS field.                                        */

/* TXDATABYTES @Bits 3..11 : Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. */
  #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL)      /*!< Position of TXDATABYTES field.                                       */
  #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field.     */
  #define NFCT_TXD_AMOUNT_TXDATABYTES_Min (0x000UL)  /*!< Min value of TXDATABYTES field.                                      */
  #define NFCT_TXD_AMOUNT_TXDATABYTES_Max (0x101UL)  /*!< Max size of TXDATABYTES field.                                       */



/* ===================================================== Struct NFCT_RXD ===================================================== */
/**
  * @brief RXD [NFCT_RXD] (unspecified)
  */
typedef struct {
  __IOM uint32_t  FRAMECONFIG;                       /*!< (@ 0x00000000) Configuration of incoming frames                      */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Size of last incoming frame                           */
} NRF_NFCT_RXD_Type;                                 /*!< Size = 8 (0x008)                                                     */

/* NFCT_RXD_FRAMECONFIG: Configuration of incoming frames */
  #define NFCT_RXD_FRAMECONFIG_ResetValue (0x00000015UL) /*!< Reset value of FRAMECONFIG register.                             */

/* PARITY @Bit 0 : Indicates if parity expected in RX frame */
  #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL)      /*!< Position of PARITY field.                                            */
  #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field.            */
  #define NFCT_RXD_FRAMECONFIG_PARITY_Min (0x0UL)    /*!< Min enumerator value of PARITY field.                                */
  #define NFCT_RXD_FRAMECONFIG_PARITY_Max (0x1UL)    /*!< Max enumerator value of PARITY field.                                */
  #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not expected in RX frames                                */
  #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is expected in RX frames                                      */

/* SOF @Bit 2 : SoF expected or not in RX frames */
  #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL)         /*!< Position of SOF field.                                               */
  #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field.                     */
  #define NFCT_RXD_FRAMECONFIG_SOF_Min (0x0UL)       /*!< Min enumerator value of SOF field.                                   */
  #define NFCT_RXD_FRAMECONFIG_SOF_Max (0x1UL)       /*!< Max enumerator value of SOF field.                                   */
  #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0x0UL)     /*!< SoF symbol is not expected in RX frames                              */
  #define NFCT_RXD_FRAMECONFIG_SOF_SoF (0x1UL)       /*!< SoF symbol is expected in RX frames                                  */

/* CRCMODERX @Bit 4 : CRC mode for incoming frames */
  #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL)   /*!< Position of CRCMODERX field.                                         */
  #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field.   */
  #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Min (0x0UL) /*!< Min enumerator value of CRCMODERX field.                             */
  #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Max (0x1UL) /*!< Max enumerator value of CRCMODERX field.                             */
  #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0x0UL) /*!< CRC is not expected in RX frames                                 */
  #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (0x1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS
                                                              updated*/


/* NFCT_RXD_AMOUNT: Size of last incoming frame */
  #define NFCT_RXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */

/* RXDATABITS @Bits 0..2 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and
                           SoF/EoF framing). */

  #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL)       /*!< Position of RXDATABITS field.                                        */
  #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field.          */

/* RXDATABYTES @Bits 3..11 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF
                             framing) */

  #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL)      /*!< Position of RXDATABYTES field.                                       */
  #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field.     */



/* =================================================== Struct NFCT_NFCID1 ==================================================== */
/**
  * @brief NFCID1 [NFCT_NFCID1] (unspecified)
  */
typedef struct {
  __IOM uint32_t  LAST;                              /*!< (@ 0x00000000) Last NFCID1 part (4, 7 or 10 bytes ID)                */
  __IOM uint32_t  SECONDLAST;                        /*!< (@ 0x00000004) Second last NFCID1 part (7 or 10 bytes ID)            */
  __IOM uint32_t  THIRDLAST;                         /*!< (@ 0x00000008) Third last NFCID1 part (10 bytes ID)                  */
} NRF_NFCT_NFCID1_Type;                              /*!< Size = 12 (0x00C)                                                    */

/* NFCT_NFCID1_LAST: Last NFCID1 part (4, 7 or 10 bytes ID) */
  #define NFCT_NFCID1_LAST_ResetValue (0x00006363UL) /*!< Reset value of LAST register.                                        */

/* Z @Bits 0..7 : NFCID1 byte Z (very last byte sent) */
  #define NFCT_NFCID1_LAST_Z_Pos (0UL)               /*!< Position of Z field.                                                 */
  #define NFCT_NFCID1_LAST_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_Z_Pos) /*!< Bit mask of Z field.                                  */

/* Y @Bits 8..15 : NFCID1 byte Y */
  #define NFCT_NFCID1_LAST_Y_Pos (8UL)               /*!< Position of Y field.                                                 */
  #define NFCT_NFCID1_LAST_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_Y_Pos) /*!< Bit mask of Y field.                                  */

/* X @Bits 16..23 : NFCID1 byte X */
  #define NFCT_NFCID1_LAST_X_Pos (16UL)              /*!< Position of X field.                                                 */
  #define NFCT_NFCID1_LAST_X_Msk (0xFFUL << NFCT_NFCID1_LAST_X_Pos) /*!< Bit mask of X field.                                  */

/* W @Bits 24..31 : NFCID1 byte W */
  #define NFCT_NFCID1_LAST_W_Pos (24UL)              /*!< Position of W field.                                                 */
  #define NFCT_NFCID1_LAST_W_Msk (0xFFUL << NFCT_NFCID1_LAST_W_Pos) /*!< Bit mask of W field.                                  */


/* NFCT_NFCID1_SECONDLAST: Second last NFCID1 part (7 or 10 bytes ID) */
  #define NFCT_NFCID1_SECONDLAST_ResetValue (0x00000000UL) /*!< Reset value of SECONDLAST register.                            */

/* V @Bits 0..7 : NFCID1 byte V */
  #define NFCT_NFCID1_SECONDLAST_V_Pos (0UL)         /*!< Position of V field.                                                 */
  #define NFCT_NFCID1_SECONDLAST_V_Msk (0xFFUL << NFCT_NFCID1_SECONDLAST_V_Pos) /*!< Bit mask of V field.                      */

/* U @Bits 8..15 : NFCID1 byte U */
  #define NFCT_NFCID1_SECONDLAST_U_Pos (8UL)         /*!< Position of U field.                                                 */
  #define NFCT_NFCID1_SECONDLAST_U_Msk (0xFFUL << NFCT_NFCID1_SECONDLAST_U_Pos) /*!< Bit mask of U field.                      */

/* T @Bits 16..23 : NFCID1 byte T */
  #define NFCT_NFCID1_SECONDLAST_T_Pos (16UL)        /*!< Position of T field.                                                 */
  #define NFCT_NFCID1_SECONDLAST_T_Msk (0xFFUL << NFCT_NFCID1_SECONDLAST_T_Pos) /*!< Bit mask of T field.                      */


/* NFCT_NFCID1_THIRDLAST: Third last NFCID1 part (10 bytes ID) */
  #define NFCT_NFCID1_THIRDLAST_ResetValue (0x00000000UL) /*!< Reset value of THIRDLAST register.                              */

/* S @Bits 0..7 : NFCID1 byte S */
  #define NFCT_NFCID1_THIRDLAST_S_Pos (0UL)          /*!< Position of S field.                                                 */
  #define NFCT_NFCID1_THIRDLAST_S_Msk (0xFFUL << NFCT_NFCID1_THIRDLAST_S_Pos) /*!< Bit mask of S field.                        */

/* R @Bits 8..15 : NFCID1 byte R */
  #define NFCT_NFCID1_THIRDLAST_R_Pos (8UL)          /*!< Position of R field.                                                 */
  #define NFCT_NFCID1_THIRDLAST_R_Msk (0xFFUL << NFCT_NFCID1_THIRDLAST_R_Pos) /*!< Bit mask of R field.                        */

/* Q @Bits 16..23 : NFCID1 byte Q */
  #define NFCT_NFCID1_THIRDLAST_Q_Pos (16UL)         /*!< Position of Q field.                                                 */
  #define NFCT_NFCID1_THIRDLAST_Q_Msk (0xFFUL << NFCT_NFCID1_THIRDLAST_Q_Pos) /*!< Bit mask of Q field.                        */


/* ======================================================= Struct NFCT ======================================================= */
/**
  * @brief NFC-A compatible radio NFC-A compatible radio
  */
  typedef struct {                                   /*!< NFCT Structure                                                       */
    __OM uint32_t TASKS_ACTIVATE;                    /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing
                                                                         frames, change state to activated*/
    __OM uint32_t TASKS_DISABLE;                     /*!< (@ 0x00000004) Disable NFCT peripheral                               */
    __OM uint32_t TASKS_SENSE;                       /*!< (@ 0x00000008) Enable NFC sense field mode, change state to sense
                                                                         mode*/
    __OM uint32_t TASKS_STARTTX;                     /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change state
                                                                         to transmit*/
    __OM uint32_t TASKS_STOPTX;                      /*!< (@ 0x00000010) Stops an issued transmission of a frame               */
    __IM uint32_t RESERVED[2];
    __OM uint32_t TASKS_ENABLERXDATA;                /*!< (@ 0x0000001C) Initializes the EasyDMA for receive.                  */
    __IM uint32_t RESERVED1;
    __OM uint32_t TASKS_GOIDLE;                      /*!< (@ 0x00000024) Force state machine to IDLE state                     */
    __OM uint32_t TASKS_GOSLEEP;                     /*!< (@ 0x00000028) Force state machine to SLEEP_A state                  */
    __IM uint32_t RESERVED2[21];
    __IOM uint32_t SUBSCRIBE_ACTIVATE;               /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE             */
    __IOM uint32_t SUBSCRIBE_DISABLE;                /*!< (@ 0x00000084) Subscribe configuration for task DISABLE              */
    __IOM uint32_t SUBSCRIBE_SENSE;                  /*!< (@ 0x00000088) Subscribe configuration for task SENSE                */
    __IOM uint32_t SUBSCRIBE_STARTTX;                /*!< (@ 0x0000008C) Subscribe configuration for task STARTTX              */
    __IOM uint32_t SUBSCRIBE_STOPTX;                 /*!< (@ 0x00000090) Subscribe configuration for task STOPTX               */
    __IM uint32_t RESERVED3[2];
    __IOM uint32_t SUBSCRIBE_ENABLERXDATA;           /*!< (@ 0x0000009C) Subscribe configuration for task ENABLERXDATA         */
    __IM uint32_t RESERVED4;
    __IOM uint32_t SUBSCRIBE_GOIDLE;                 /*!< (@ 0x000000A4) Subscribe configuration for task GOIDLE               */
    __IOM uint32_t SUBSCRIBE_GOSLEEP;                /*!< (@ 0x000000A8) Subscribe configuration for task GOSLEEP              */
    __IM uint32_t RESERVED5[21];
    __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send
                                                                         frames*/
    __IOM uint32_t EVENTS_FIELDDETECTED;             /*!< (@ 0x00000104) Remote NFC field detected                             */
    __IOM uint32_t EVENTS_FIELDLOST;                 /*!< (@ 0x00000108) Remote NFC field lost                                 */
    __IOM uint32_t EVENTS_TXFRAMESTART;              /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted
                                                                         frame*/
    __IOM uint32_t EVENTS_TXFRAMEEND;                /*!< (@ 0x00000110) Marks the end of the last transmitted on-air symbol of
                                                                         a frame*/
    __IOM uint32_t EVENTS_RXFRAMESTART;              /*!< (@ 0x00000114) Marks the end of the first symbol of a received frame */
    __IOM uint32_t EVENTS_RXFRAMEEND;                /*!< (@ 0x00000118) Received data has been checked (CRC, parity) and
                                                                         transferred to RAM, and EasyDMA has ended accessing the
                                                                         RX buffer*/
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register contains
                                                                         details on the source of the error.*/
    __IM uint32_t RESERVED6[2];
    __IOM uint32_t EVENTS_RXERROR;                   /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX
                                                                         register contains details on the source of the error.*/
    __IOM uint32_t EVENTS_ENDRX;                     /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) in Data
                                                                         RAM full.*/
    __IOM uint32_t EVENTS_ENDTX;                     /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA has
                                                                         ended accessing the TX buffer*/
    __IM uint32_t RESERVED7;
    __IOM uint32_t EVENTS_AUTOCOLRESSTARTED;         /*!< (@ 0x00000138) Auto collision resolution process has started         */
    __IM uint32_t RESERVED8[3];
    __IOM uint32_t EVENTS_COLLISION;                 /*!< (@ 0x00000148) NFC auto collision resolution error reported.         */
    __IOM uint32_t EVENTS_SELECTED;                  /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed  */
    __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames.           */
    __IM uint32_t RESERVED9[11];
    __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000180) Publish configuration for event READY                 */
    __IOM uint32_t PUBLISH_FIELDDETECTED;            /*!< (@ 0x00000184) Publish configuration for event FIELDDETECTED         */
    __IOM uint32_t PUBLISH_FIELDLOST;                /*!< (@ 0x00000188) Publish configuration for event FIELDLOST             */
    __IOM uint32_t PUBLISH_TXFRAMESTART;             /*!< (@ 0x0000018C) Publish configuration for event TXFRAMESTART          */
    __IOM uint32_t PUBLISH_TXFRAMEEND;               /*!< (@ 0x00000190) Publish configuration for event TXFRAMEEND            */
    __IOM uint32_t PUBLISH_RXFRAMESTART;             /*!< (@ 0x00000194) Publish configuration for event RXFRAMESTART          */
    __IOM uint32_t PUBLISH_RXFRAMEEND;               /*!< (@ 0x00000198) Publish configuration for event RXFRAMEEND            */
    __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x0000019C) Publish configuration for event ERROR                 */
    __IM uint32_t RESERVED10[2];
    __IOM uint32_t PUBLISH_RXERROR;                  /*!< (@ 0x000001A8) Publish configuration for event RXERROR               */
    __IOM uint32_t PUBLISH_ENDRX;                    /*!< (@ 0x000001AC) Publish configuration for event ENDRX                 */
    __IOM uint32_t PUBLISH_ENDTX;                    /*!< (@ 0x000001B0) Publish configuration for event ENDTX                 */
    __IM uint32_t RESERVED11;
    __IOM uint32_t PUBLISH_AUTOCOLRESSTARTED;        /*!< (@ 0x000001B8) Publish configuration for event AUTOCOLRESSTARTED     */
    __IM uint32_t RESERVED12[3];
    __IOM uint32_t PUBLISH_COLLISION;                /*!< (@ 0x000001C8) Publish configuration for event COLLISION             */
    __IOM uint32_t PUBLISH_SELECTED;                 /*!< (@ 0x000001CC) Publish configuration for event SELECTED              */
    __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x000001D0) Publish configuration for event STARTED               */
    __IM uint32_t RESERVED13[11];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED14[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED15[62];
    __IOM uint32_t ERRORSTATUS;                      /*!< (@ 0x00000404) NFC Error Status register                             */
    __IM uint32_t RESERVED16;
    __IOM NRF_NFCT_FRAMESTATUS_Type FRAMESTATUS;     /*!< (@ 0x0000040C) (unspecified)                                         */
    __IM uint32_t NFCTAGSTATE;                       /*!< (@ 0x00000410) Current operating state of NFC tag                    */
    __IM uint32_t RESERVED17[3];
    __IM uint32_t SLEEPSTATE;                        /*!< (@ 0x00000420) Sleep state during automatic collision resolution     */
    __IM uint32_t RESERVED18[6];
    __IM uint32_t FIELDPRESENT;                      /*!< (@ 0x0000043C) Indicates the presence or not of a valid field        */
    __IM uint32_t RESERVED19[49];
    __IOM uint32_t FRAMEDELAYMIN;                    /*!< (@ 0x00000504) Minimum frame delay                                   */
    __IOM uint32_t FRAMEDELAYMAX;                    /*!< (@ 0x00000508) Maximum frame delay                                   */
    __IOM uint32_t FRAMEDELAYMODE;                   /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer      */
    __IOM uint32_t PACKETPTR;                        /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in Data
                                                                         RAM*/
    __IOM uint32_t MAXLEN;                           /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD data
                                                                         storage each*/
    __IOM NRF_NFCT_TXD_Type TXD;                     /*!< (@ 0x00000518) (unspecified)                                         */
    __IOM NRF_NFCT_RXD_Type RXD;                     /*!< (@ 0x00000520) (unspecified)                                         */
    __IM uint32_t RESERVED20;
    __IOM uint32_t MODULATIONCTRL;                   /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which can
                                                                         be connected to a second external antenna.*/
    __IM uint32_t RESERVED21[2];
    __IOM uint32_t MODULATIONPSEL;                   /*!< (@ 0x00000538) Pin select for Modulation control                     */
    __IM uint32_t RESERVED22[5];
    __IOM uint32_t MODE;                             /*!< (@ 0x00000550) Configure EasyDMA mode                                */
    __IM uint32_t RESERVED23[15];
    __IOM NRF_NFCT_NFCID1_Type NFCID1;               /*!< (@ 0x00000590) (unspecified)                                         */
    __IOM uint32_t AUTOCOLRESCONFIG;                 /*!< (@ 0x0000059C) Controls the auto collision resolution function. This
                                                                         setting must be done before the NFCT peripheral is
                                                                         activated.*/
    __IOM uint32_t SENSRES;                          /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings                 */
    __IOM uint32_t SELRES;                           /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings                  */
    __IM uint32_t RESERVED24[75];
    __IOM uint32_t PADCONFIG;                        /*!< (@ 0x000006D4) NFC pad configuration                                 */
  } NRF_NFCT_Type;                                   /*!< Size = 1752 (0x6D8)                                                  */

/* NFCT_TASKS_ACTIVATE: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
  #define NFCT_TASKS_ACTIVATE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ACTIVATE register.                           */

/* TASKS_ACTIVATE @Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
  #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field.                                  */
  #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of
                                                                            TASKS_ACTIVATE field.*/
  #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Min (0x1UL) /*!< Min enumerator value of TASKS_ACTIVATE field.                    */
  #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Max (0x1UL) /*!< Max enumerator value of TASKS_ACTIVATE field.                    */
  #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (0x1UL) /*!< Trigger task                                                 */


/* NFCT_TASKS_DISABLE: Disable NFCT peripheral */
  #define NFCT_TASKS_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_DISABLE register.                             */

/* TASKS_DISABLE @Bit 0 : Disable NFCT peripheral */
  #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field.                                     */
  #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE
                                                                            field.*/
  #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Min (0x1UL) /*!< Min enumerator value of TASKS_DISABLE field.                       */
  #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Max (0x1UL) /*!< Max enumerator value of TASKS_DISABLE field.                       */
  #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task                                                   */


/* NFCT_TASKS_SENSE: Enable NFC sense field mode, change state to sense mode */
  #define NFCT_TASKS_SENSE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SENSE register.                                 */

/* TASKS_SENSE @Bit 0 : Enable NFC sense field mode, change state to sense mode */
  #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL)     /*!< Position of TASKS_SENSE field.                                       */
  #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field.     */
  #define NFCT_TASKS_SENSE_TASKS_SENSE_Min (0x1UL)   /*!< Min enumerator value of TASKS_SENSE field.                           */
  #define NFCT_TASKS_SENSE_TASKS_SENSE_Max (0x1UL)   /*!< Max enumerator value of TASKS_SENSE field.                           */
  #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (0x1UL) /*!< Trigger task                                                       */


/* NFCT_TASKS_STARTTX: Start transmission of an outgoing frame, change state to transmit */
  #define NFCT_TASKS_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STARTTX register.                             */

/* TASKS_STARTTX @Bit 0 : Start transmission of an outgoing frame, change state to transmit */
  #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field.                                     */
  #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX
                                                                            field.*/
  #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STARTTX field.                       */
  #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STARTTX field.                       */
  #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task                                                   */


/* NFCT_TASKS_STOPTX: Stops an issued transmission of a frame */
  #define NFCT_TASKS_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPTX register.                               */

/* TASKS_STOPTX @Bit 0 : Stops an issued transmission of a frame */
  #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL)   /*!< Position of TASKS_STOPTX field.                                      */
  #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << NFCT_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field.*/
  #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPTX field.                          */
  #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPTX field.                          */
  #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task                                                     */


/* NFCT_TASKS_ENABLERXDATA: Initializes the EasyDMA for receive. */
  #define NFCT_TASKS_ENABLERXDATA_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ENABLERXDATA register.                   */

/* TASKS_ENABLERXDATA @Bit 0 : Initializes the EasyDMA for receive. */
  #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field.                      */
  #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask
                                                                            of TASKS_ENABLERXDATA field.*/
  #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Min (0x1UL) /*!< Min enumerator value of TASKS_ENABLERXDATA field.        */
  #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Max (0x1UL) /*!< Max enumerator value of TASKS_ENABLERXDATA field.        */
  #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (0x1UL) /*!< Trigger task                                         */


/* NFCT_TASKS_GOIDLE: Force state machine to IDLE state */
  #define NFCT_TASKS_GOIDLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_GOIDLE register.                               */

/* TASKS_GOIDLE @Bit 0 : Force state machine to IDLE state */
  #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL)   /*!< Position of TASKS_GOIDLE field.                                      */
  #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field.*/
  #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Min (0x1UL) /*!< Min enumerator value of TASKS_GOIDLE field.                          */
  #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Max (0x1UL) /*!< Max enumerator value of TASKS_GOIDLE field.                          */
  #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (0x1UL) /*!< Trigger task                                                     */


/* NFCT_TASKS_GOSLEEP: Force state machine to SLEEP_A state */
  #define NFCT_TASKS_GOSLEEP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_GOSLEEP register.                             */

/* TASKS_GOSLEEP @Bit 0 : Force state machine to SLEEP_A state */
  #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field.                                     */
  #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP
                                                                            field.*/
  #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Min (0x1UL) /*!< Min enumerator value of TASKS_GOSLEEP field.                       */
  #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Max (0x1UL) /*!< Max enumerator value of TASKS_GOSLEEP field.                       */
  #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (0x1UL) /*!< Trigger task                                                   */


/* NFCT_SUBSCRIBE_ACTIVATE: Subscribe configuration for task ACTIVATE */
  #define NFCT_SUBSCRIBE_ACTIVATE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACTIVATE register.                   */

/* CHIDX @Bits 0..7 : DPPI channel that task ACTIVATE will subscribe to */
  #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_ACTIVATE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ACTIVATE_EN_Pos) /*!< Bit mask of EN field.                  */
  #define NFCT_SUBSCRIBE_ACTIVATE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_ACTIVATE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_ACTIVATE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define NFCT_SUBSCRIBE_ACTIVATE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* NFCT_SUBSCRIBE_DISABLE: Subscribe configuration for task DISABLE */
  #define NFCT_SUBSCRIBE_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_DISABLE register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task DISABLE will subscribe to */
  #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_DISABLE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field.                    */
  #define NFCT_SUBSCRIBE_DISABLE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_DISABLE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define NFCT_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* NFCT_SUBSCRIBE_SENSE: Subscribe configuration for task SENSE */
  #define NFCT_SUBSCRIBE_SENSE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SENSE register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that task SENSE will subscribe to */
  #define NFCT_SUBSCRIBE_SENSE_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define NFCT_SUBSCRIBE_SENSE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_SENSE_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define NFCT_SUBSCRIBE_SENSE_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_SENSE_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_SENSE_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_SENSE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_SENSE_EN_Pos) /*!< Bit mask of EN field.                        */
  #define NFCT_SUBSCRIBE_SENSE_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_SENSE_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_SENSE_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define NFCT_SUBSCRIBE_SENSE_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* NFCT_SUBSCRIBE_STARTTX: Subscribe configuration for task STARTTX */
  #define NFCT_SUBSCRIBE_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STARTTX register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task STARTTX will subscribe to */
  #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_STARTTX_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field.                    */
  #define NFCT_SUBSCRIBE_STARTTX_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_STARTTX_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define NFCT_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* NFCT_SUBSCRIBE_STOPTX: Subscribe configuration for task STOPTX */
  #define NFCT_SUBSCRIBE_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOPTX register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task STOPTX will subscribe to */
  #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_STOPTX_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field.                      */
  #define NFCT_SUBSCRIBE_STOPTX_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_STOPTX_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define NFCT_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* NFCT_SUBSCRIBE_ENABLERXDATA: Subscribe configuration for task ENABLERXDATA */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ENABLERXDATA register.           */

/* CHIDX @Bits 0..7 : DPPI channel that task ENABLERXDATA will subscribe to */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
  #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                        */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos (31UL)  /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos) /*!< Bit mask of EN field.          */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Disabled (0x0UL) /*!< Disable subscription                                            */
  #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Enabled (0x1UL) /*!< Enable subscription                                              */


/* NFCT_SUBSCRIBE_GOIDLE: Subscribe configuration for task GOIDLE */
  #define NFCT_SUBSCRIBE_GOIDLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_GOIDLE register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task GOIDLE will subscribe to */
  #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_GOIDLE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_GOIDLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOIDLE_EN_Pos) /*!< Bit mask of EN field.                      */
  #define NFCT_SUBSCRIBE_GOIDLE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_GOIDLE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_GOIDLE_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define NFCT_SUBSCRIBE_GOIDLE_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* NFCT_SUBSCRIBE_GOSLEEP: Subscribe configuration for task GOSLEEP */
  #define NFCT_SUBSCRIBE_GOSLEEP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_GOSLEEP register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task GOSLEEP will subscribe to */
  #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_SUBSCRIBE_GOSLEEP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define NFCT_SUBSCRIBE_GOSLEEP_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOSLEEP_EN_Pos) /*!< Bit mask of EN field.                    */
  #define NFCT_SUBSCRIBE_GOSLEEP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_GOSLEEP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define NFCT_SUBSCRIBE_GOSLEEP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define NFCT_SUBSCRIBE_GOSLEEP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* NFCT_EVENTS_READY: The NFCT peripheral is ready to receive and send frames */
  #define NFCT_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                               */

/* EVENTS_READY @Bit 0 : The NFCT peripheral is ready to receive and send frames */
  #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL)   /*!< Position of EVENTS_READY field.                                      */
  #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/
  #define NFCT_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                          */
  #define NFCT_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                          */
  #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define NFCT_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                                */


/* NFCT_EVENTS_FIELDDETECTED: Remote NFC field detected */
  #define NFCT_EVENTS_FIELDDETECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FIELDDETECTED register.               */

/* EVENTS_FIELDDETECTED @Bit 0 : Remote NFC field detected */
  #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field.                */
  #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!<
                                                                            Bit mask of EVENTS_FIELDDETECTED field.*/
  #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_FIELDDETECTED field.  */
  #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_FIELDDETECTED field.  */
  #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0x0UL) /*!< Event not generated                         */
  #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (0x1UL) /*!< Event generated                                */


/* NFCT_EVENTS_FIELDLOST: Remote NFC field lost */
  #define NFCT_EVENTS_FIELDLOST_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FIELDLOST register.                       */

/* EVENTS_FIELDLOST @Bit 0 : Remote NFC field lost */
  #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field.                            */
  #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of
                                                                            EVENTS_FIELDLOST field.*/
  #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Min (0x0UL) /*!< Min enumerator value of EVENTS_FIELDLOST field.              */
  #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Max (0x1UL) /*!< Max enumerator value of EVENTS_FIELDLOST field.              */
  #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0x0UL) /*!< Event not generated                                 */
  #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (0x1UL) /*!< Event generated                                        */


/* NFCT_EVENTS_TXFRAMESTART: Marks the start of the first symbol of a transmitted frame */
  #define NFCT_EVENTS_TXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXFRAMESTART register.                 */

/* EVENTS_TXFRAMESTART @Bit 0 : Marks the start of the first symbol of a transmitted frame */
  #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field.                   */
  #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit
                                                                            mask of EVENTS_TXFRAMESTART field.*/
  #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXFRAMESTART field.     */
  #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXFRAMESTART field.     */
  #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                           */
  #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (0x1UL) /*!< Event generated                                  */


/* NFCT_EVENTS_TXFRAMEEND: Marks the end of the last transmitted on-air symbol of a frame */
  #define NFCT_EVENTS_TXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXFRAMEEND register.                     */

/* EVENTS_TXFRAMEEND @Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
  #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field.                         */
  #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of
                                                                            EVENTS_TXFRAMEEND field.*/
  #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXFRAMEEND field.           */
  #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXFRAMEEND field.           */
  #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated                               */
  #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (0x1UL) /*!< Event generated                                      */


/* NFCT_EVENTS_RXFRAMESTART: Marks the end of the first symbol of a received frame */
  #define NFCT_EVENTS_RXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXFRAMESTART register.                 */

/* EVENTS_RXFRAMESTART @Bit 0 : Marks the end of the first symbol of a received frame */
  #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field.                   */
  #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit
                                                                            mask of EVENTS_RXFRAMESTART field.*/
  #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXFRAMESTART field.     */
  #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXFRAMESTART field.     */
  #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                           */
  #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (0x1UL) /*!< Event generated                                  */


/* NFCT_EVENTS_RXFRAMEEND: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing
                            the RX buffer */

  #define NFCT_EVENTS_RXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXFRAMEEND register.                     */

/* EVENTS_RXFRAMEEND @Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended
                              accessing the RX buffer */

  #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field.                         */
  #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of
                                                                            EVENTS_RXFRAMEEND field.*/
  #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXFRAMEEND field.           */
  #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXFRAMEEND field.           */
  #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated                               */
  #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (0x1UL) /*!< Event generated                                      */


/* NFCT_EVENTS_ERROR: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
  #define NFCT_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                               */

/* EVENTS_ERROR @Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
  #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)   /*!< Position of EVENTS_ERROR field.                                      */
  #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/
  #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                          */
  #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                          */
  #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                */


/* NFCT_EVENTS_RXERROR: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
  #define NFCT_EVENTS_RXERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXERROR register.                           */

/* EVENTS_RXERROR @Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
                           */

  #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field.                                  */
  #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of
                                                                            EVENTS_RXERROR field.*/
  #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXERROR field.                    */
  #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXERROR field.                    */
  #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (0x1UL) /*!< Event generated                                            */


/* NFCT_EVENTS_ENDRX: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
  #define NFCT_EVENTS_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDRX register.                               */

/* EVENTS_ENDRX @Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
  #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)   /*!< Position of EVENTS_ENDRX field.                                      */
  #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field.*/
  #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDRX field.                          */
  #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDRX field.                          */
  #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated                                                */


/* NFCT_EVENTS_ENDTX: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
  #define NFCT_EVENTS_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDTX register.                               */

/* EVENTS_ENDTX @Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
  #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)   /*!< Position of EVENTS_ENDTX field.                                      */
  #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field.*/
  #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDTX field.                          */
  #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDTX field.                          */
  #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated                                                */


/* NFCT_EVENTS_AUTOCOLRESSTARTED: Auto collision resolution process has started */
  #define NFCT_EVENTS_AUTOCOLRESSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_AUTOCOLRESSTARTED register.       */

/* EVENTS_AUTOCOLRESSTARTED @Bit 0 : Auto collision resolution process has started */
  #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field.    */
  #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos)
                                                                            /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field.*/
  #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of
                                                                            EVENTS_AUTOCOLRESSTARTED field.*/
  #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of
                                                                            EVENTS_AUTOCOLRESSTARTED field.*/
  #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0x0UL) /*!< Event not generated                 */
  #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (0x1UL) /*!< Event generated                        */


/* NFCT_EVENTS_COLLISION: NFC auto collision resolution error reported. */
  #define NFCT_EVENTS_COLLISION_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COLLISION register.                       */

/* EVENTS_COLLISION @Bit 0 : NFC auto collision resolution error reported. */
  #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field.                            */
  #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of
                                                                            EVENTS_COLLISION field.*/
  #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Min (0x0UL) /*!< Min enumerator value of EVENTS_COLLISION field.              */
  #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Max (0x1UL) /*!< Max enumerator value of EVENTS_COLLISION field.              */
  #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0x0UL) /*!< Event not generated                                 */
  #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (0x1UL) /*!< Event generated                                        */


/* NFCT_EVENTS_SELECTED: NFC auto collision resolution successfully completed */
  #define NFCT_EVENTS_SELECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SELECTED register.                         */

/* EVENTS_SELECTED @Bit 0 : NFC auto collision resolution successfully completed */
  #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field.                               */
  #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of
                                                                            EVENTS_SELECTED field.*/
  #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SELECTED field.                 */
  #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SELECTED field.                 */
  #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (0x1UL) /*!< Event generated                                          */


/* NFCT_EVENTS_STARTED: EasyDMA is ready to receive or send frames. */
  #define NFCT_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                           */

/* EVENTS_STARTED @Bit 0 : EasyDMA is ready to receive or send frames. */
  #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                  */
  #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
                                                                            EVENTS_STARTED field.*/
  #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                    */
  #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                    */
  #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                            */


/* NFCT_PUBLISH_READY: Publish configuration for event READY */
  #define NFCT_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define NFCT_PUBLISH_READY_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_READY_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define NFCT_PUBLISH_READY_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_READY_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_READY_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_READY_EN_Msk (0x1UL << NFCT_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                            */
  #define NFCT_PUBLISH_READY_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_READY_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_READY_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_READY_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_FIELDDETECTED: Publish configuration for event FIELDDETECTED */
  #define NFCT_PUBLISH_FIELDDETECTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FIELDDETECTED register.             */

/* CHIDX @Bits 0..7 : DPPI channel that event FIELDDETECTED will publish to */
  #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_FIELDDETECTED_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_FIELDDETECTED_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDDETECTED_EN_Pos) /*!< Bit mask of EN field.            */
  #define NFCT_PUBLISH_FIELDDETECTED_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_FIELDDETECTED_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_FIELDDETECTED_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
  #define NFCT_PUBLISH_FIELDDETECTED_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */


/* NFCT_PUBLISH_FIELDLOST: Publish configuration for event FIELDLOST */
  #define NFCT_PUBLISH_FIELDLOST_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FIELDLOST register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event FIELDLOST will publish to */
  #define NFCT_PUBLISH_FIELDLOST_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_FIELDLOST_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDLOST_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define NFCT_PUBLISH_FIELDLOST_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_FIELDLOST_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_FIELDLOST_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_FIELDLOST_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDLOST_EN_Pos) /*!< Bit mask of EN field.                    */
  #define NFCT_PUBLISH_FIELDLOST_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_FIELDLOST_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_FIELDLOST_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_FIELDLOST_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_TXFRAMESTART: Publish configuration for event TXFRAMESTART */
  #define NFCT_PUBLISH_TXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXFRAMESTART register.               */

/* CHIDX @Bits 0..7 : DPPI channel that event TXFRAMESTART will publish to */
  #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_TXFRAMESTART_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_TXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMESTART_EN_Pos) /*!< Bit mask of EN field.              */
  #define NFCT_PUBLISH_TXFRAMESTART_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_TXFRAMESTART_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_TXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define NFCT_PUBLISH_TXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* NFCT_PUBLISH_TXFRAMEEND: Publish configuration for event TXFRAMEEND */
  #define NFCT_PUBLISH_TXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXFRAMEEND register.                   */

/* CHIDX @Bits 0..7 : DPPI channel that event TXFRAMEEND will publish to */
  #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_TXFRAMEEND_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_TXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMEEND_EN_Pos) /*!< Bit mask of EN field.                  */
  #define NFCT_PUBLISH_TXFRAMEEND_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_TXFRAMEEND_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_TXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define NFCT_PUBLISH_TXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_RXFRAMESTART: Publish configuration for event RXFRAMESTART */
  #define NFCT_PUBLISH_RXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXFRAMESTART register.               */

/* CHIDX @Bits 0..7 : DPPI channel that event RXFRAMESTART will publish to */
  #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_RXFRAMESTART_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_RXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMESTART_EN_Pos) /*!< Bit mask of EN field.              */
  #define NFCT_PUBLISH_RXFRAMESTART_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_RXFRAMESTART_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_RXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define NFCT_PUBLISH_RXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* NFCT_PUBLISH_RXFRAMEEND: Publish configuration for event RXFRAMEEND */
  #define NFCT_PUBLISH_RXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXFRAMEEND register.                   */

/* CHIDX @Bits 0..7 : DPPI channel that event RXFRAMEEND will publish to */
  #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_RXFRAMEEND_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_RXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMEEND_EN_Pos) /*!< Bit mask of EN field.                  */
  #define NFCT_PUBLISH_RXFRAMEEND_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_RXFRAMEEND_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_RXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define NFCT_PUBLISH_RXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_ERROR: Publish configuration for event ERROR */
  #define NFCT_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
  #define NFCT_PUBLISH_ERROR_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define NFCT_PUBLISH_ERROR_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_ERROR_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_ERROR_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_ERROR_EN_Msk (0x1UL << NFCT_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                            */
  #define NFCT_PUBLISH_ERROR_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_ERROR_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_ERROR_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_ERROR_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_RXERROR: Publish configuration for event RXERROR */
  #define NFCT_PUBLISH_RXERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXERROR register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event RXERROR will publish to */
  #define NFCT_PUBLISH_RXERROR_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_RXERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define NFCT_PUBLISH_RXERROR_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_RXERROR_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_RXERROR_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_RXERROR_EN_Msk (0x1UL << NFCT_PUBLISH_RXERROR_EN_Pos) /*!< Bit mask of EN field.                        */
  #define NFCT_PUBLISH_RXERROR_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_RXERROR_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_RXERROR_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_RXERROR_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_ENDRX: Publish configuration for event ENDRX */
  #define NFCT_PUBLISH_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDRX register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event ENDRX will publish to */
  #define NFCT_PUBLISH_ENDRX_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define NFCT_PUBLISH_ENDRX_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_ENDRX_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_ENDRX_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_ENDRX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field.                            */
  #define NFCT_PUBLISH_ENDRX_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_ENDRX_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_ENDRX_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_ENDRX_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_ENDTX: Publish configuration for event ENDTX */
  #define NFCT_PUBLISH_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDTX register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event ENDTX will publish to */
  #define NFCT_PUBLISH_ENDTX_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define NFCT_PUBLISH_ENDTX_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_ENDTX_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_ENDTX_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_ENDTX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field.                            */
  #define NFCT_PUBLISH_ENDTX_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_ENDTX_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_ENDTX_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_ENDTX_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_AUTOCOLRESSTARTED: Publish configuration for event AUTOCOLRESSTARTED */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_AUTOCOLRESSTARTED register.     */

/* CHIDX @Bits 0..7 : DPPI channel that event AUTOCOLRESSTARTED will publish to */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                         */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                     */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                      */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos (31UL) /*!< Position of EN field.                                              */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Msk (0x1UL << NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos) /*!< Bit mask of EN field.    */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                 */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                 */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                           */
  #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing                                             */


/* NFCT_PUBLISH_COLLISION: Publish configuration for event COLLISION */
  #define NFCT_PUBLISH_COLLISION_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COLLISION register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event COLLISION will publish to */
  #define NFCT_PUBLISH_COLLISION_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_COLLISION_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_COLLISION_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define NFCT_PUBLISH_COLLISION_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_COLLISION_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_COLLISION_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_COLLISION_EN_Msk (0x1UL << NFCT_PUBLISH_COLLISION_EN_Pos) /*!< Bit mask of EN field.                    */
  #define NFCT_PUBLISH_COLLISION_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_COLLISION_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_COLLISION_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_COLLISION_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_SELECTED: Publish configuration for event SELECTED */
  #define NFCT_PUBLISH_SELECTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SELECTED register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that event SELECTED will publish to */
  #define NFCT_PUBLISH_SELECTED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_SELECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_SELECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define NFCT_PUBLISH_SELECTED_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_SELECTED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_SELECTED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_SELECTED_EN_Msk (0x1UL << NFCT_PUBLISH_SELECTED_EN_Pos) /*!< Bit mask of EN field.                      */
  #define NFCT_PUBLISH_SELECTED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_SELECTED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_SELECTED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_SELECTED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* NFCT_PUBLISH_STARTED: Publish configuration for event STARTED */
  #define NFCT_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
  #define NFCT_PUBLISH_STARTED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define NFCT_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define NFCT_PUBLISH_STARTED_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define NFCT_PUBLISH_STARTED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define NFCT_PUBLISH_STARTED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define NFCT_PUBLISH_STARTED_EN_Msk (0x1UL << NFCT_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                        */
  #define NFCT_PUBLISH_STARTED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_STARTED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define NFCT_PUBLISH_STARTED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define NFCT_PUBLISH_STARTED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* NFCT_SHORTS: Shortcuts between local events and tasks */
  #define NFCT_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* FIELDDETECTED_ACTIVATE @Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
  #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field.                          */
  #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of
                                                                            FIELDDETECTED_ACTIVATE field.*/
  #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Min (0x0UL) /*!< Min enumerator value of FIELDDETECTED_ACTIVATE field.            */
  #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Max (0x1UL) /*!< Max enumerator value of FIELDDETECTED_ACTIVATE field.            */
  #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0x0UL) /*!< Disable shortcut                                            */
  #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (0x1UL) /*!< Enable shortcut                                              */

/* FIELDLOST_SENSE @Bit 1 : Shortcut between event FIELDLOST and task SENSE */
  #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL)      /*!< Position of FIELDLOST_SENSE field.                                   */
  #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field.   */
  #define NFCT_SHORTS_FIELDLOST_SENSE_Min (0x0UL)    /*!< Min enumerator value of FIELDLOST_SENSE field.                       */
  #define NFCT_SHORTS_FIELDLOST_SENSE_Max (0x1UL)    /*!< Max enumerator value of FIELDLOST_SENSE field.                       */
  #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* TXFRAMEEND_ENABLERXDATA @Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
  #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field.                        */
  #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of
                                                                            TXFRAMEEND_ENABLERXDATA field.*/
  #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Min (0x0UL) /*!< Min enumerator value of TXFRAMEEND_ENABLERXDATA field.          */
  #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Max (0x1UL) /*!< Max enumerator value of TXFRAMEEND_ENABLERXDATA field.          */
  #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0x0UL) /*!< Disable shortcut                                           */
  #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (0x1UL) /*!< Enable shortcut                                             */


/* NFCT_INTEN: Enable or disable interrupt */
  #define NFCT_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */

/* READY @Bit 0 : Enable or disable interrupt for event READY */
  #define NFCT_INTEN_READY_Pos (0UL)                 /*!< Position of READY field.                                             */
  #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field.                                   */
  #define NFCT_INTEN_READY_Min (0x0UL)               /*!< Min enumerator value of READY field.                                 */
  #define NFCT_INTEN_READY_Max (0x1UL)               /*!< Max enumerator value of READY field.                                 */
  #define NFCT_INTEN_READY_Disabled (0x0UL)          /*!< Disable                                                              */
  #define NFCT_INTEN_READY_Enabled (0x1UL)           /*!< Enable                                                               */

/* FIELDDETECTED @Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
  #define NFCT_INTEN_FIELDDETECTED_Pos (1UL)         /*!< Position of FIELDDETECTED field.                                     */
  #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field.           */
  #define NFCT_INTEN_FIELDDETECTED_Min (0x0UL)       /*!< Min enumerator value of FIELDDETECTED field.                         */
  #define NFCT_INTEN_FIELDDETECTED_Max (0x1UL)       /*!< Max enumerator value of FIELDDETECTED field.                         */
  #define NFCT_INTEN_FIELDDETECTED_Disabled (0x0UL)  /*!< Disable                                                              */
  #define NFCT_INTEN_FIELDDETECTED_Enabled (0x1UL)   /*!< Enable                                                               */

/* FIELDLOST @Bit 2 : Enable or disable interrupt for event FIELDLOST */
  #define NFCT_INTEN_FIELDLOST_Pos (2UL)             /*!< Position of FIELDLOST field.                                         */
  #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field.                       */
  #define NFCT_INTEN_FIELDLOST_Min (0x0UL)           /*!< Min enumerator value of FIELDLOST field.                             */
  #define NFCT_INTEN_FIELDLOST_Max (0x1UL)           /*!< Max enumerator value of FIELDLOST field.                             */
  #define NFCT_INTEN_FIELDLOST_Disabled (0x0UL)      /*!< Disable                                                              */
  #define NFCT_INTEN_FIELDLOST_Enabled (0x1UL)       /*!< Enable                                                               */

/* TXFRAMESTART @Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
  #define NFCT_INTEN_TXFRAMESTART_Pos (3UL)          /*!< Position of TXFRAMESTART field.                                      */
  #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field.              */
  #define NFCT_INTEN_TXFRAMESTART_Min (0x0UL)        /*!< Min enumerator value of TXFRAMESTART field.                          */
  #define NFCT_INTEN_TXFRAMESTART_Max (0x1UL)        /*!< Max enumerator value of TXFRAMESTART field.                          */
  #define NFCT_INTEN_TXFRAMESTART_Disabled (0x0UL)   /*!< Disable                                                              */
  #define NFCT_INTEN_TXFRAMESTART_Enabled (0x1UL)    /*!< Enable                                                               */

/* TXFRAMEEND @Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
  #define NFCT_INTEN_TXFRAMEEND_Pos (4UL)            /*!< Position of TXFRAMEEND field.                                        */
  #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field.                    */
  #define NFCT_INTEN_TXFRAMEEND_Min (0x0UL)          /*!< Min enumerator value of TXFRAMEEND field.                            */
  #define NFCT_INTEN_TXFRAMEEND_Max (0x1UL)          /*!< Max enumerator value of TXFRAMEEND field.                            */
  #define NFCT_INTEN_TXFRAMEEND_Disabled (0x0UL)     /*!< Disable                                                              */
  #define NFCT_INTEN_TXFRAMEEND_Enabled (0x1UL)      /*!< Enable                                                               */

/* RXFRAMESTART @Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
  #define NFCT_INTEN_RXFRAMESTART_Pos (5UL)          /*!< Position of RXFRAMESTART field.                                      */
  #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field.              */
  #define NFCT_INTEN_RXFRAMESTART_Min (0x0UL)        /*!< Min enumerator value of RXFRAMESTART field.                          */
  #define NFCT_INTEN_RXFRAMESTART_Max (0x1UL)        /*!< Max enumerator value of RXFRAMESTART field.                          */
  #define NFCT_INTEN_RXFRAMESTART_Disabled (0x0UL)   /*!< Disable                                                              */
  #define NFCT_INTEN_RXFRAMESTART_Enabled (0x1UL)    /*!< Enable                                                               */

/* RXFRAMEEND @Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
  #define NFCT_INTEN_RXFRAMEEND_Pos (6UL)            /*!< Position of RXFRAMEEND field.                                        */
  #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field.                    */
  #define NFCT_INTEN_RXFRAMEEND_Min (0x0UL)          /*!< Min enumerator value of RXFRAMEEND field.                            */
  #define NFCT_INTEN_RXFRAMEEND_Max (0x1UL)          /*!< Max enumerator value of RXFRAMEEND field.                            */
  #define NFCT_INTEN_RXFRAMEEND_Disabled (0x0UL)     /*!< Disable                                                              */
  #define NFCT_INTEN_RXFRAMEEND_Enabled (0x1UL)      /*!< Enable                                                               */

/* ERROR @Bit 7 : Enable or disable interrupt for event ERROR */
  #define NFCT_INTEN_ERROR_Pos (7UL)                 /*!< Position of ERROR field.                                             */
  #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                   */
  #define NFCT_INTEN_ERROR_Min (0x0UL)               /*!< Min enumerator value of ERROR field.                                 */
  #define NFCT_INTEN_ERROR_Max (0x1UL)               /*!< Max enumerator value of ERROR field.                                 */
  #define NFCT_INTEN_ERROR_Disabled (0x0UL)          /*!< Disable                                                              */
  #define NFCT_INTEN_ERROR_Enabled (0x1UL)           /*!< Enable                                                               */

/* RXERROR @Bit 10 : Enable or disable interrupt for event RXERROR */
  #define NFCT_INTEN_RXERROR_Pos (10UL)              /*!< Position of RXERROR field.                                           */
  #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field.                             */
  #define NFCT_INTEN_RXERROR_Min (0x0UL)             /*!< Min enumerator value of RXERROR field.                               */
  #define NFCT_INTEN_RXERROR_Max (0x1UL)             /*!< Max enumerator value of RXERROR field.                               */
  #define NFCT_INTEN_RXERROR_Disabled (0x0UL)        /*!< Disable                                                              */
  #define NFCT_INTEN_RXERROR_Enabled (0x1UL)         /*!< Enable                                                               */

/* ENDRX @Bit 11 : Enable or disable interrupt for event ENDRX */
  #define NFCT_INTEN_ENDRX_Pos (11UL)                /*!< Position of ENDRX field.                                             */
  #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field.                                   */
  #define NFCT_INTEN_ENDRX_Min (0x0UL)               /*!< Min enumerator value of ENDRX field.                                 */
  #define NFCT_INTEN_ENDRX_Max (0x1UL)               /*!< Max enumerator value of ENDRX field.                                 */
  #define NFCT_INTEN_ENDRX_Disabled (0x0UL)          /*!< Disable                                                              */
  #define NFCT_INTEN_ENDRX_Enabled (0x1UL)           /*!< Enable                                                               */

/* ENDTX @Bit 12 : Enable or disable interrupt for event ENDTX */
  #define NFCT_INTEN_ENDTX_Pos (12UL)                /*!< Position of ENDTX field.                                             */
  #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field.                                   */
  #define NFCT_INTEN_ENDTX_Min (0x0UL)               /*!< Min enumerator value of ENDTX field.                                 */
  #define NFCT_INTEN_ENDTX_Max (0x1UL)               /*!< Max enumerator value of ENDTX field.                                 */
  #define NFCT_INTEN_ENDTX_Disabled (0x0UL)          /*!< Disable                                                              */
  #define NFCT_INTEN_ENDTX_Enabled (0x1UL)           /*!< Enable                                                               */

/* AUTOCOLRESSTARTED @Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
  #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL)    /*!< Position of AUTOCOLRESSTARTED field.                                 */
  #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED
                                                                            field.*/
  #define NFCT_INTEN_AUTOCOLRESSTARTED_Min (0x0UL)   /*!< Min enumerator value of AUTOCOLRESSTARTED field.                     */
  #define NFCT_INTEN_AUTOCOLRESSTARTED_Max (0x1UL)   /*!< Max enumerator value of AUTOCOLRESSTARTED field.                     */
  #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Disable                                                           */
  #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Enable                                                             */

/* COLLISION @Bit 18 : Enable or disable interrupt for event COLLISION */
  #define NFCT_INTEN_COLLISION_Pos (18UL)            /*!< Position of COLLISION field.                                         */
  #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field.                       */
  #define NFCT_INTEN_COLLISION_Min (0x0UL)           /*!< Min enumerator value of COLLISION field.                             */
  #define NFCT_INTEN_COLLISION_Max (0x1UL)           /*!< Max enumerator value of COLLISION field.                             */
  #define NFCT_INTEN_COLLISION_Disabled (0x0UL)      /*!< Disable                                                              */
  #define NFCT_INTEN_COLLISION_Enabled (0x1UL)       /*!< Enable                                                               */

/* SELECTED @Bit 19 : Enable or disable interrupt for event SELECTED */
  #define NFCT_INTEN_SELECTED_Pos (19UL)             /*!< Position of SELECTED field.                                          */
  #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field.                          */
  #define NFCT_INTEN_SELECTED_Min (0x0UL)            /*!< Min enumerator value of SELECTED field.                              */
  #define NFCT_INTEN_SELECTED_Max (0x1UL)            /*!< Max enumerator value of SELECTED field.                              */
  #define NFCT_INTEN_SELECTED_Disabled (0x0UL)       /*!< Disable                                                              */
  #define NFCT_INTEN_SELECTED_Enabled (0x1UL)        /*!< Enable                                                               */

/* STARTED @Bit 20 : Enable or disable interrupt for event STARTED */
  #define NFCT_INTEN_STARTED_Pos (20UL)              /*!< Position of STARTED field.                                           */
  #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field.                             */
  #define NFCT_INTEN_STARTED_Min (0x0UL)             /*!< Min enumerator value of STARTED field.                               */
  #define NFCT_INTEN_STARTED_Max (0x1UL)             /*!< Max enumerator value of STARTED field.                               */
  #define NFCT_INTEN_STARTED_Disabled (0x0UL)        /*!< Disable                                                              */
  #define NFCT_INTEN_STARTED_Enabled (0x1UL)         /*!< Enable                                                               */


/* NFCT_INTENSET: Enable interrupt */
  #define NFCT_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* READY @Bit 0 : Write '1' to enable interrupt for event READY */
  #define NFCT_INTENSET_READY_Pos (0UL)              /*!< Position of READY field.                                             */
  #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field.                             */
  #define NFCT_INTENSET_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
  #define NFCT_INTENSET_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
  #define NFCT_INTENSET_READY_Set (0x1UL)            /*!< Enable                                                               */
  #define NFCT_INTENSET_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* FIELDDETECTED @Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
  #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL)      /*!< Position of FIELDDETECTED field.                                     */
  #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field.     */
  #define NFCT_INTENSET_FIELDDETECTED_Min (0x0UL)    /*!< Min enumerator value of FIELDDETECTED field.                         */
  #define NFCT_INTENSET_FIELDDETECTED_Max (0x1UL)    /*!< Max enumerator value of FIELDDETECTED field.                         */
  #define NFCT_INTENSET_FIELDDETECTED_Set (0x1UL)    /*!< Enable                                                               */
  #define NFCT_INTENSET_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define NFCT_INTENSET_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* FIELDLOST @Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
  #define NFCT_INTENSET_FIELDLOST_Pos (2UL)          /*!< Position of FIELDLOST field.                                         */
  #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field.                 */
  #define NFCT_INTENSET_FIELDLOST_Min (0x0UL)        /*!< Min enumerator value of FIELDLOST field.                             */
  #define NFCT_INTENSET_FIELDLOST_Max (0x1UL)        /*!< Max enumerator value of FIELDLOST field.                             */
  #define NFCT_INTENSET_FIELDLOST_Set (0x1UL)        /*!< Enable                                                               */
  #define NFCT_INTENSET_FIELDLOST_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_FIELDLOST_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TXFRAMESTART @Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
  #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL)       /*!< Position of TXFRAMESTART field.                                      */
  #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field.        */
  #define NFCT_INTENSET_TXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of TXFRAMESTART field.                          */
  #define NFCT_INTENSET_TXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of TXFRAMESTART field.                          */
  #define NFCT_INTENSET_TXFRAMESTART_Set (0x1UL)     /*!< Enable                                                               */
  #define NFCT_INTENSET_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define NFCT_INTENSET_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* TXFRAMEEND @Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
  #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL)         /*!< Position of TXFRAMEEND field.                                        */
  #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field.              */
  #define NFCT_INTENSET_TXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of TXFRAMEEND field.                            */
  #define NFCT_INTENSET_TXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of TXFRAMEEND field.                            */
  #define NFCT_INTENSET_TXFRAMEEND_Set (0x1UL)       /*!< Enable                                                               */
  #define NFCT_INTENSET_TXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_TXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RXFRAMESTART @Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
  #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL)       /*!< Position of RXFRAMESTART field.                                      */
  #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field.        */
  #define NFCT_INTENSET_RXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of RXFRAMESTART field.                          */
  #define NFCT_INTENSET_RXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of RXFRAMESTART field.                          */
  #define NFCT_INTENSET_RXFRAMESTART_Set (0x1UL)     /*!< Enable                                                               */
  #define NFCT_INTENSET_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define NFCT_INTENSET_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* RXFRAMEEND @Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
  #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL)         /*!< Position of RXFRAMEEND field.                                        */
  #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field.              */
  #define NFCT_INTENSET_RXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of RXFRAMEEND field.                            */
  #define NFCT_INTENSET_RXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of RXFRAMEEND field.                            */
  #define NFCT_INTENSET_RXFRAMEEND_Set (0x1UL)       /*!< Enable                                                               */
  #define NFCT_INTENSET_RXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_RXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ERROR @Bit 7 : Write '1' to enable interrupt for event ERROR */
  #define NFCT_INTENSET_ERROR_Pos (7UL)              /*!< Position of ERROR field.                                             */
  #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
  #define NFCT_INTENSET_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
  #define NFCT_INTENSET_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
  #define NFCT_INTENSET_ERROR_Set (0x1UL)            /*!< Enable                                                               */
  #define NFCT_INTENSET_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* RXERROR @Bit 10 : Write '1' to enable interrupt for event RXERROR */
  #define NFCT_INTENSET_RXERROR_Pos (10UL)           /*!< Position of RXERROR field.                                           */
  #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field.                       */
  #define NFCT_INTENSET_RXERROR_Min (0x0UL)          /*!< Min enumerator value of RXERROR field.                               */
  #define NFCT_INTENSET_RXERROR_Max (0x1UL)          /*!< Max enumerator value of RXERROR field.                               */
  #define NFCT_INTENSET_RXERROR_Set (0x1UL)          /*!< Enable                                                               */
  #define NFCT_INTENSET_RXERROR_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_RXERROR_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ENDRX @Bit 11 : Write '1' to enable interrupt for event ENDRX */
  #define NFCT_INTENSET_ENDRX_Pos (11UL)             /*!< Position of ENDRX field.                                             */
  #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
  #define NFCT_INTENSET_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
  #define NFCT_INTENSET_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
  #define NFCT_INTENSET_ENDRX_Set (0x1UL)            /*!< Enable                                                               */
  #define NFCT_INTENSET_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* ENDTX @Bit 12 : Write '1' to enable interrupt for event ENDTX */
  #define NFCT_INTENSET_ENDTX_Pos (12UL)             /*!< Position of ENDTX field.                                             */
  #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field.                             */
  #define NFCT_INTENSET_ENDTX_Min (0x0UL)            /*!< Min enumerator value of ENDTX field.                                 */
  #define NFCT_INTENSET_ENDTX_Max (0x1UL)            /*!< Max enumerator value of ENDTX field.                                 */
  #define NFCT_INTENSET_ENDTX_Set (0x1UL)            /*!< Enable                                                               */
  #define NFCT_INTENSET_ENDTX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_ENDTX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* AUTOCOLRESSTARTED @Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
  #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field.                                 */
  #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED
                                                                            field.*/
  #define NFCT_INTENSET_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of AUTOCOLRESSTARTED field.                    */
  #define NFCT_INTENSET_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of AUTOCOLRESSTARTED field.                    */
  #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (0x1UL) /*!< Enable                                                              */
  #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                 */
  #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled                                                   */

/* COLLISION @Bit 18 : Write '1' to enable interrupt for event COLLISION */
  #define NFCT_INTENSET_COLLISION_Pos (18UL)         /*!< Position of COLLISION field.                                         */
  #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field.                 */
  #define NFCT_INTENSET_COLLISION_Min (0x0UL)        /*!< Min enumerator value of COLLISION field.                             */
  #define NFCT_INTENSET_COLLISION_Max (0x1UL)        /*!< Max enumerator value of COLLISION field.                             */
  #define NFCT_INTENSET_COLLISION_Set (0x1UL)        /*!< Enable                                                               */
  #define NFCT_INTENSET_COLLISION_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_COLLISION_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* SELECTED @Bit 19 : Write '1' to enable interrupt for event SELECTED */
  #define NFCT_INTENSET_SELECTED_Pos (19UL)          /*!< Position of SELECTED field.                                          */
  #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field.                    */
  #define NFCT_INTENSET_SELECTED_Min (0x0UL)         /*!< Min enumerator value of SELECTED field.                              */
  #define NFCT_INTENSET_SELECTED_Max (0x1UL)         /*!< Max enumerator value of SELECTED field.                              */
  #define NFCT_INTENSET_SELECTED_Set (0x1UL)         /*!< Enable                                                               */
  #define NFCT_INTENSET_SELECTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_SELECTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* STARTED @Bit 20 : Write '1' to enable interrupt for event STARTED */
  #define NFCT_INTENSET_STARTED_Pos (20UL)           /*!< Position of STARTED field.                                           */
  #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
  #define NFCT_INTENSET_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
  #define NFCT_INTENSET_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
  #define NFCT_INTENSET_STARTED_Set (0x1UL)          /*!< Enable                                                               */
  #define NFCT_INTENSET_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define NFCT_INTENSET_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* NFCT_INTENCLR: Disable interrupt */
  #define NFCT_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* READY @Bit 0 : Write '1' to disable interrupt for event READY */
  #define NFCT_INTENCLR_READY_Pos (0UL)              /*!< Position of READY field.                                             */
  #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field.                             */
  #define NFCT_INTENCLR_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
  #define NFCT_INTENCLR_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
  #define NFCT_INTENCLR_READY_Clear (0x1UL)          /*!< Disable                                                              */
  #define NFCT_INTENCLR_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* FIELDDETECTED @Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
  #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL)      /*!< Position of FIELDDETECTED field.                                     */
  #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field.     */
  #define NFCT_INTENCLR_FIELDDETECTED_Min (0x0UL)    /*!< Min enumerator value of FIELDDETECTED field.                         */
  #define NFCT_INTENCLR_FIELDDETECTED_Max (0x1UL)    /*!< Max enumerator value of FIELDDETECTED field.                         */
  #define NFCT_INTENCLR_FIELDDETECTED_Clear (0x1UL)  /*!< Disable                                                              */
  #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define NFCT_INTENCLR_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* FIELDLOST @Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
  #define NFCT_INTENCLR_FIELDLOST_Pos (2UL)          /*!< Position of FIELDLOST field.                                         */
  #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field.                 */
  #define NFCT_INTENCLR_FIELDLOST_Min (0x0UL)        /*!< Min enumerator value of FIELDLOST field.                             */
  #define NFCT_INTENCLR_FIELDLOST_Max (0x1UL)        /*!< Max enumerator value of FIELDLOST field.                             */
  #define NFCT_INTENCLR_FIELDLOST_Clear (0x1UL)      /*!< Disable                                                              */
  #define NFCT_INTENCLR_FIELDLOST_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_FIELDLOST_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* TXFRAMESTART @Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
  #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL)       /*!< Position of TXFRAMESTART field.                                      */
  #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field.        */
  #define NFCT_INTENCLR_TXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of TXFRAMESTART field.                          */
  #define NFCT_INTENCLR_TXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of TXFRAMESTART field.                          */
  #define NFCT_INTENCLR_TXFRAMESTART_Clear (0x1UL)   /*!< Disable                                                              */
  #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define NFCT_INTENCLR_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* TXFRAMEEND @Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
  #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL)         /*!< Position of TXFRAMEEND field.                                        */
  #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field.              */
  #define NFCT_INTENCLR_TXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of TXFRAMEEND field.                            */
  #define NFCT_INTENCLR_TXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of TXFRAMEEND field.                            */
  #define NFCT_INTENCLR_TXFRAMEEND_Clear (0x1UL)     /*!< Disable                                                              */
  #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_TXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RXFRAMESTART @Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
  #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL)       /*!< Position of RXFRAMESTART field.                                      */
  #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field.        */
  #define NFCT_INTENCLR_RXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of RXFRAMESTART field.                          */
  #define NFCT_INTENCLR_RXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of RXFRAMESTART field.                          */
  #define NFCT_INTENCLR_RXFRAMESTART_Clear (0x1UL)   /*!< Disable                                                              */
  #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define NFCT_INTENCLR_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* RXFRAMEEND @Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
  #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL)         /*!< Position of RXFRAMEEND field.                                        */
  #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field.              */
  #define NFCT_INTENCLR_RXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of RXFRAMEEND field.                            */
  #define NFCT_INTENCLR_RXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of RXFRAMEEND field.                            */
  #define NFCT_INTENCLR_RXFRAMEEND_Clear (0x1UL)     /*!< Disable                                                              */
  #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_RXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ERROR @Bit 7 : Write '1' to disable interrupt for event ERROR */
  #define NFCT_INTENCLR_ERROR_Pos (7UL)              /*!< Position of ERROR field.                                             */
  #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
  #define NFCT_INTENCLR_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
  #define NFCT_INTENCLR_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
  #define NFCT_INTENCLR_ERROR_Clear (0x1UL)          /*!< Disable                                                              */
  #define NFCT_INTENCLR_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* RXERROR @Bit 10 : Write '1' to disable interrupt for event RXERROR */
  #define NFCT_INTENCLR_RXERROR_Pos (10UL)           /*!< Position of RXERROR field.                                           */
  #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field.                       */
  #define NFCT_INTENCLR_RXERROR_Min (0x0UL)          /*!< Min enumerator value of RXERROR field.                               */
  #define NFCT_INTENCLR_RXERROR_Max (0x1UL)          /*!< Max enumerator value of RXERROR field.                               */
  #define NFCT_INTENCLR_RXERROR_Clear (0x1UL)        /*!< Disable                                                              */
  #define NFCT_INTENCLR_RXERROR_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_RXERROR_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ENDRX @Bit 11 : Write '1' to disable interrupt for event ENDRX */
  #define NFCT_INTENCLR_ENDRX_Pos (11UL)             /*!< Position of ENDRX field.                                             */
  #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
  #define NFCT_INTENCLR_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
  #define NFCT_INTENCLR_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
  #define NFCT_INTENCLR_ENDRX_Clear (0x1UL)          /*!< Disable                                                              */
  #define NFCT_INTENCLR_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* ENDTX @Bit 12 : Write '1' to disable interrupt for event ENDTX */
  #define NFCT_INTENCLR_ENDTX_Pos (12UL)             /*!< Position of ENDTX field.                                             */
  #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field.                             */
  #define NFCT_INTENCLR_ENDTX_Min (0x0UL)            /*!< Min enumerator value of ENDTX field.                                 */
  #define NFCT_INTENCLR_ENDTX_Max (0x1UL)            /*!< Max enumerator value of ENDTX field.                                 */
  #define NFCT_INTENCLR_ENDTX_Clear (0x1UL)          /*!< Disable                                                              */
  #define NFCT_INTENCLR_ENDTX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_ENDTX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* AUTOCOLRESSTARTED @Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
  #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field.                                 */
  #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED
                                                                            field.*/
  #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of AUTOCOLRESSTARTED field.                    */
  #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of AUTOCOLRESSTARTED field.                    */
  #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (0x1UL) /*!< Disable                                                           */
  #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                 */
  #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled                                                   */

/* COLLISION @Bit 18 : Write '1' to disable interrupt for event COLLISION */
  #define NFCT_INTENCLR_COLLISION_Pos (18UL)         /*!< Position of COLLISION field.                                         */
  #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field.                 */
  #define NFCT_INTENCLR_COLLISION_Min (0x0UL)        /*!< Min enumerator value of COLLISION field.                             */
  #define NFCT_INTENCLR_COLLISION_Max (0x1UL)        /*!< Max enumerator value of COLLISION field.                             */
  #define NFCT_INTENCLR_COLLISION_Clear (0x1UL)      /*!< Disable                                                              */
  #define NFCT_INTENCLR_COLLISION_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_COLLISION_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* SELECTED @Bit 19 : Write '1' to disable interrupt for event SELECTED */
  #define NFCT_INTENCLR_SELECTED_Pos (19UL)          /*!< Position of SELECTED field.                                          */
  #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field.                    */
  #define NFCT_INTENCLR_SELECTED_Min (0x0UL)         /*!< Min enumerator value of SELECTED field.                              */
  #define NFCT_INTENCLR_SELECTED_Max (0x1UL)         /*!< Max enumerator value of SELECTED field.                              */
  #define NFCT_INTENCLR_SELECTED_Clear (0x1UL)       /*!< Disable                                                              */
  #define NFCT_INTENCLR_SELECTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_SELECTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* STARTED @Bit 20 : Write '1' to disable interrupt for event STARTED */
  #define NFCT_INTENCLR_STARTED_Pos (20UL)           /*!< Position of STARTED field.                                           */
  #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
  #define NFCT_INTENCLR_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
  #define NFCT_INTENCLR_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
  #define NFCT_INTENCLR_STARTED_Clear (0x1UL)        /*!< Disable                                                              */
  #define NFCT_INTENCLR_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define NFCT_INTENCLR_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* NFCT_ERRORSTATUS: NFC Error Status register */
  #define NFCT_ERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of ERRORSTATUS register.                                 */

/* FRAMEDELAYTIMEOUT @Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
  #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field.                               */
  #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of
                                                                            FRAMEDELAYTIMEOUT field.*/


/* NFCT_NFCTAGSTATE: Current operating state of NFC tag */
  #define NFCT_NFCTAGSTATE_ResetValue (0x00000000UL) /*!< Reset value of NFCTAGSTATE register.                                 */

/* NFCTAGSTATE @Bits 0..2 : NfcTag state */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL)     /*!< Position of NFCTAGSTATE field.                                       */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field.     */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Min (0x0UL)   /*!< Min enumerator value of NFCTAGSTATE field.                           */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Max (0x6UL)   /*!< Max enumerator value of NFCTAGSTATE field.                           */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0x0UL) /*!< Disabled or sense                                                 */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (0x2UL) /*!< RampUp                                                              */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (0x3UL)  /*!< Idle                                                                 */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (0x4UL) /*!< Receive                                                            */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (0x5UL) /*!< FrameDelay                                                      */
  #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (0x6UL) /*!< Transmit                                                          */


/* NFCT_SLEEPSTATE: Sleep state during automatic collision resolution */
  #define NFCT_SLEEPSTATE_ResetValue (0x00000000UL)  /*!< Reset value of SLEEPSTATE register.                                  */

/* SLEEPSTATE @Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to
                       SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. */

  #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL)       /*!< Position of SLEEPSTATE field.                                        */
  #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field.          */
  #define NFCT_SLEEPSTATE_SLEEPSTATE_Min (0x0UL)     /*!< Min enumerator value of SLEEPSTATE field.                            */
  #define NFCT_SLEEPSTATE_SLEEPSTATE_Max (0x1UL)     /*!< Max enumerator value of SLEEPSTATE field.                            */
  #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0x0UL)    /*!< State is IDLE.                                                       */
  #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (0x1UL)  /*!< State is SLEEP_A.                                                    */


/* NFCT_FIELDPRESENT: Indicates the presence or not of a valid field */
  #define NFCT_FIELDPRESENT_ResetValue (0x00000000UL) /*!< Reset value of FIELDPRESENT register.                               */

/* FIELDPRESENT @Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
  #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL)   /*!< Position of FIELDPRESENT field.                                      */
  #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field.*/
  #define NFCT_FIELDPRESENT_FIELDPRESENT_Min (0x0UL) /*!< Min enumerator value of FIELDPRESENT field.                          */
  #define NFCT_FIELDPRESENT_FIELDPRESENT_Max (0x1UL) /*!< Max enumerator value of FIELDPRESENT field.                          */
  #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0x0UL) /*!< No valid field detected                                          */
  #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (0x1UL) /*!< Valid field detected                                        */

/* LOCKDETECT @Bit 1 : Indicates if the low level has locked to the field */
  #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL)     /*!< Position of LOCKDETECT field.                                        */
  #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field.      */
  #define NFCT_FIELDPRESENT_LOCKDETECT_Min (0x0UL)   /*!< Min enumerator value of LOCKDETECT field.                            */
  #define NFCT_FIELDPRESENT_LOCKDETECT_Max (0x1UL)   /*!< Max enumerator value of LOCKDETECT field.                            */
  #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0x0UL) /*!< Not locked to field                                              */
  #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (0x1UL) /*!< Locked to field                                                     */


/* NFCT_FRAMEDELAYMIN: Minimum frame delay */
  #define NFCT_FRAMEDELAYMIN_ResetValue (0x00000480UL) /*!< Reset value of FRAMEDELAYMIN register.                             */

/* FRAMEDELAYMIN @Bits 0..15 : Minimum frame delay in number of 13.56 MHz clock cycles */
  #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field.                                     */
  #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN
                                                                            field.*/


/* NFCT_FRAMEDELAYMAX: Maximum frame delay */
  #define NFCT_FRAMEDELAYMAX_ResetValue (0x00001000UL) /*!< Reset value of FRAMEDELAYMAX register.                             */

/* FRAMEDELAYMAX @Bits 0..19 : Maximum frame delay in number of 13.56 MHz clock cycles */
  #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field.                                     */
  #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of
                                                                            FRAMEDELAYMAX field.*/


/* NFCT_FRAMEDELAYMODE: Configuration register for the Frame Delay Timer */
  #define NFCT_FRAMEDELAYMODE_ResetValue (0x00000001UL) /*!< Reset value of FRAMEDELAYMODE register.                           */

/* FRAMEDELAYMODE @Bits 0..1 : Configuration register for the Frame Delay Timer */
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field.                                  */
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of
                                                                            FRAMEDELAYMODE field.*/
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Min (0x0UL) /*!< Min enumerator value of FRAMEDELAYMODE field.                    */
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Max (0x3UL) /*!< Max enumerator value of FRAMEDELAYMODE field.                    */
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0x0UL) /*!< Transmission is independent of frame timer and will start when
                                                                  the STARTTX task is triggered. No timeout.*/
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (0x1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX  */
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (0x2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX               */
  #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (0x3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN
                                                                     and FRAMEDELAYMAX*/


/* NFCT_PACKETPTR: Packet pointer for TXD and RXD data storage in Data RAM */
  #define NFCT_PACKETPTR_ResetValue (0x00000000UL)   /*!< Reset value of PACKETPTR register.                                   */

/* PTR @Bits 0..31 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
  #define NFCT_PACKETPTR_PTR_Pos (0UL)               /*!< Position of PTR field.                                               */
  #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field.                          */


/* NFCT_MAXLEN: Size of the RAM buffer allocated to TXD and RXD data storage each */
  #define NFCT_MAXLEN_ResetValue (0x00000000UL)      /*!< Reset value of MAXLEN register.                                      */

/* MAXLEN @Bits 0..8 : Size of the RAM buffer allocated to TXD and RXD data storage each */
  #define NFCT_MAXLEN_MAXLEN_Pos (0UL)               /*!< Position of MAXLEN field.                                            */
  #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field.                            */
  #define NFCT_MAXLEN_MAXLEN_Min (0x000UL)           /*!< Min value of MAXLEN field.                                           */
  #define NFCT_MAXLEN_MAXLEN_Max (0x101UL)           /*!< Max size of MAXLEN field.                                            */


/* NFCT_MODULATIONCTRL: Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */
  #define NFCT_MODULATIONCTRL_ResetValue (0x00000001UL) /*!< Reset value of MODULATIONCTRL register.                           */

/* MODULATIONCTRL @Bits 0..1 : Configuration of modulation control. */
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL) /*!< Position of MODULATIONCTRL field.                                  */
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos) /*!< Bit mask of
                                                                            MODULATIONCTRL field.*/
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Min (0x0UL) /*!< Min enumerator value of MODULATIONCTRL field.                    */
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Max (0x3UL) /*!< Max enumerator value of MODULATIONCTRL field.                    */
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL) /*!< Invalid, defaults to same behaviour as for Internal          */
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL) /*!< Use internal modulator only                                 */
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL) /*!< Output digital modulation signal to a GPIO pin.            */
  #define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital
                                                                            modulation signal to a GPIO pin.*/


/* NFCT_MODULATIONPSEL: Pin select for Modulation control */
  #define NFCT_MODULATIONPSEL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MODULATIONPSEL register.                           */

/* PIN @Bits 0..4 : Pin number */
  #define NFCT_MODULATIONPSEL_PIN_Pos (0UL)          /*!< Position of PIN field.                                               */
  #define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos) /*!< Bit mask of PIN field.                      */
  #define NFCT_MODULATIONPSEL_PIN_Min (0x00UL)       /*!< Min value of PIN field.                                              */
  #define NFCT_MODULATIONPSEL_PIN_Max (0x1FUL)       /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..6 : Port number */
  #define NFCT_MODULATIONPSEL_PORT_Pos (5UL)         /*!< Position of PORT field.                                              */
  #define NFCT_MODULATIONPSEL_PORT_Msk (0x3UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field.                    */
  #define NFCT_MODULATIONPSEL_PORT_Min (0x0UL)       /*!< Min value of PORT field.                                             */
  #define NFCT_MODULATIONPSEL_PORT_Max (0x3UL)       /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL)     /*!< Position of CONNECT field.                                           */
  #define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos) /*!< Bit mask of CONNECT field.           */
  #define NFCT_MODULATIONPSEL_CONNECT_Min (0x0UL)    /*!< Min enumerator value of CONNECT field.                               */
  #define NFCT_MODULATIONPSEL_CONNECT_Max (0x1UL)    /*!< Max enumerator value of CONNECT field.                               */
  #define NFCT_MODULATIONPSEL_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                     */
  #define NFCT_MODULATIONPSEL_CONNECT_Connected (0x0UL) /*!< Connect                                                           */


/* NFCT_MODE: Configure EasyDMA mode */
  #define NFCT_MODE_ResetValue (0x00000001UL)        /*!< Reset value of MODE register.                                        */

/* LPOP @Bits 0..1 : Enable low-power operation, or use low-latency */
  #define NFCT_MODE_LPOP_Pos (0UL)                   /*!< Position of LPOP field.                                              */
  #define NFCT_MODE_LPOP_Msk (0x3UL << NFCT_MODE_LPOP_Pos) /*!< Bit mask of LPOP field.                                        */
  #define NFCT_MODE_LPOP_Min (0x0UL)                 /*!< Min enumerator value of LPOP field.                                  */
  #define NFCT_MODE_LPOP_Max (0x3UL)                 /*!< Max enumerator value of LPOP field.                                  */
  #define NFCT_MODE_LPOP_LowLat (0x0UL)              /*!< Low-latency operation                                                */
  #define NFCT_MODE_LPOP_LowPower (0x1UL)            /*!< Low-power operation                                                  */
  #define NFCT_MODE_LPOP_FullLowPower (0x3UL)        /*!< Full Low-power operation                                             */


/* NFCT_AUTOCOLRESCONFIG: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral
                           is activated. */

  #define NFCT_AUTOCOLRESCONFIG_ResetValue (0x00000002UL) /*!< Reset value of AUTOCOLRESCONFIG register.                       */

/* MODE @Bit 0 : Enables/disables auto collision resolution */
  #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL)       /*!< Position of MODE field.                                              */
  #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field.                */
  #define NFCT_AUTOCOLRESCONFIG_MODE_Min (0x0UL)     /*!< Min enumerator value of MODE field.                                  */
  #define NFCT_AUTOCOLRESCONFIG_MODE_Max (0x1UL)     /*!< Max enumerator value of MODE field.                                  */
  #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0x0UL) /*!< Auto collision resolution enabled                                    */
  #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (0x1UL) /*!< Auto collision resolution disabled                                  */


/* NFCT_SENSRES: NFC-A SENS_RES auto-response settings */
  #define NFCT_SENSRES_ResetValue (0x00000001UL)     /*!< Reset value of SENSRES register.                                     */

/* BITFRAMESDD @Bits 0..4 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital
                            Protocol Technical Specification */

  #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL)         /*!< Position of BITFRAMESDD field.                                       */
  #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field.            */
  #define NFCT_SENSRES_BITFRAMESDD_Min (0x0UL)       /*!< Min enumerator value of BITFRAMESDD field.                           */
  #define NFCT_SENSRES_BITFRAMESDD_Max (0x10UL)      /*!< Max enumerator value of BITFRAMESDD field.                           */
  #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0x00UL) /*!< SDD pattern 00000                                                    */
  #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (0x01UL) /*!< SDD pattern 00001                                                    */
  #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (0x02UL) /*!< SDD pattern 00010                                                    */
  #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (0x04UL) /*!< SDD pattern 00100                                                    */
  #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (0x08UL) /*!< SDD pattern 01000                                                    */
  #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (0x10UL) /*!< SDD pattern 10000                                                    */

/* RFU5 @Bit 5 : Reserved for future use. Shall be 0. */
  #define NFCT_SENSRES_RFU5_Pos (5UL)                /*!< Position of RFU5 field.                                              */
  #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field.                                  */

/* NFCIDSIZE @Bits 6..7 : NFCID1 size. This value is used by the auto collision resolution engine. */
  #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL)           /*!< Position of NFCIDSIZE field.                                         */
  #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field.                   */
  #define NFCT_SENSRES_NFCIDSIZE_Min (0x0UL)         /*!< Min enumerator value of NFCIDSIZE field.                             */
  #define NFCT_SENSRES_NFCIDSIZE_Max (0x2UL)         /*!< Max enumerator value of NFCIDSIZE field.                             */
  #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0x0UL) /*!< NFCID1 size: single (4 bytes)                                       */
  #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (0x1UL) /*!< NFCID1 size: double (7 bytes)                                       */
  #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (0x2UL) /*!< NFCID1 size: triple (10 bytes)                                      */

/* PLATFCONFIG @Bits 8..11 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum,
                             NFC Digital Protocol Technical Specification */

  #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL)         /*!< Position of PLATFCONFIG field.                                       */
  #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field.             */

/* RFU74 @Bits 12..15 : Reserved for future use. Shall be 0. */
  #define NFCT_SENSRES_RFU74_Pos (12UL)              /*!< Position of RFU74 field.                                             */
  #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field.                               */


/* NFCT_SELRES: NFC-A SEL_RES auto-response settings */
  #define NFCT_SELRES_ResetValue (0x00000000UL)      /*!< Reset value of SELRES register.                                      */

/* RFU10 @Bits 0..1 : Reserved for future use. Shall be 0. */
  #define NFCT_SELRES_RFU10_Pos (0UL)                /*!< Position of RFU10 field.                                             */
  #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field.                                 */

/* CASCADE @Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical
                    Specification (controlled by hardware, shall be 0) */

  #define NFCT_SELRES_CASCADE_Pos (2UL)              /*!< Position of CASCADE field.                                           */
  #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field.                           */

/* RFU43 @Bits 3..4 : Reserved for future use. Shall be 0. */
  #define NFCT_SELRES_RFU43_Pos (3UL)                /*!< Position of RFU43 field.                                             */
  #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field.                                 */

/* PROTOCOL @Bits 5..6 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical
                         Specification */

  #define NFCT_SELRES_PROTOCOL_Pos (5UL)             /*!< Position of PROTOCOL field.                                          */
  #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field.                        */

/* RFU7 @Bit 7 : Reserved for future use. Shall be 0. */
  #define NFCT_SELRES_RFU7_Pos (7UL)                 /*!< Position of RFU7 field.                                              */
  #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field.                                    */


/* NFCT_PADCONFIG: NFC pad configuration */
  #define NFCT_PADCONFIG_ResetValue (0x00000001UL)   /*!< Reset value of PADCONFIG register.                                   */

/* ENABLE @Bit 0 : Enable NFC pads */
  #define NFCT_PADCONFIG_ENABLE_Pos (0UL)            /*!< Position of ENABLE field.                                            */
  #define NFCT_PADCONFIG_ENABLE_Msk (0x1UL << NFCT_PADCONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field.                        */
  #define NFCT_PADCONFIG_ENABLE_Min (0x0UL)          /*!< Min enumerator value of ENABLE field.                                */
  #define NFCT_PADCONFIG_ENABLE_Max (0x1UL)          /*!< Max enumerator value of ENABLE field.                                */
  #define NFCT_PADCONFIG_ENABLE_Disabled (0x0UL)     /*!< NFC pads are used as GPIO pins                                       */
  #define NFCT_PADCONFIG_ENABLE_Enabled (0x1UL)      /*!< The NFC pads are configured as NFC antenna pins                      */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                        OSCILLATORS                                        ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ============================================ Struct OSCILLATORS_XOSC32M_CONFIG ============================================ */
/**
  * @brief CONFIG [OSCILLATORS_XOSC32M_CONFIG] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  INTCAP;                            /*!< (@ 0x00000008) Crystal load capacitor as seen by the crystal across
                                                                         its terminals, including pin capacitance but excluding
                                                                         PCB stray capacitance.*/
} NRF_OSCILLATORS_XOSC32M_CONFIG_Type;               /*!< Size = 12 (0x00C)                                                    */

/* OSCILLATORS_XOSC32M_CONFIG_INTCAP: Crystal load capacitor as seen by the crystal across its terminals, including pin
                                       capacitance but excluding PCB stray capacitance. */

  #define OSCILLATORS_XOSC32M_CONFIG_INTCAP_ResetValue (0x00000020UL) /*!< Reset value of INTCAP register.                     */

/* VAL @Bits 0..5 : Crystal load capacitor value */
  #define OSCILLATORS_XOSC32M_CONFIG_INTCAP_VAL_Pos (0UL) /*!< Position of VAL field.                                          */
  #define OSCILLATORS_XOSC32M_CONFIG_INTCAP_VAL_Msk (0x3FUL << OSCILLATORS_XOSC32M_CONFIG_INTCAP_VAL_Pos) /*!< Bit mask of VAL
                                                                            field.*/



/* =============================================== Struct OSCILLATORS_XOSC32M ================================================ */
/**
  * @brief XOSC32M [OSCILLATORS_XOSC32M] 32 MHz oscillator control
  */
typedef struct {
  __IM  uint32_t  RESERVED[5];
  __IOM NRF_OSCILLATORS_XOSC32M_CONFIG_Type CONFIG;  /*!< (@ 0x00000014) (unspecified)                                         */
} NRF_OSCILLATORS_XOSC32M_Type;                      /*!< Size = 32 (0x020)                                                    */


/* ================================================= Struct OSCILLATORS_PLL ================================================== */
/**
  * @brief PLL [OSCILLATORS_PLL] Oscillator control
  */
typedef struct {
  __IOM uint32_t  FREQ;                              /*!< (@ 0x00000000) Set speed of MCU power domain, including CPU          */
  __IM  uint32_t  CURRENTFREQ;                       /*!< (@ 0x00000004) Current speed of MCU power domain, including CPU      */
} NRF_OSCILLATORS_PLL_Type;                          /*!< Size = 8 (0x008)                                                     */

/* OSCILLATORS_PLL_FREQ: Set speed of MCU power domain, including CPU */
  #define OSCILLATORS_PLL_FREQ_ResetValue (0x00000003UL) /*!< Reset value of FREQ register.                                    */

/* FREQ @Bits 0..1 : Select CPU speed */
  #define OSCILLATORS_PLL_FREQ_FREQ_Pos (0UL)        /*!< Position of FREQ field.                                              */
  #define OSCILLATORS_PLL_FREQ_FREQ_Msk (0x3UL << OSCILLATORS_PLL_FREQ_FREQ_Pos) /*!< Bit mask of FREQ field.                  */
  #define OSCILLATORS_PLL_FREQ_FREQ_Min (0x1UL)      /*!< Min enumerator value of FREQ field.                                  */
  #define OSCILLATORS_PLL_FREQ_FREQ_Max (0x3UL)      /*!< Max enumerator value of FREQ field.                                  */
  #define OSCILLATORS_PLL_FREQ_FREQ_CK128M (0x1UL)   /*!< 128 MHz                                                              */
  #define OSCILLATORS_PLL_FREQ_FREQ_CK64M (0x3UL)    /*!< 64 MHz                                                               */


/* OSCILLATORS_PLL_CURRENTFREQ: Current speed of MCU power domain, including CPU */
  #define OSCILLATORS_PLL_CURRENTFREQ_ResetValue (0x00000003UL) /*!< Reset value of CURRENTFREQ register.                      */

/* CURRENTFREQ @Bits 0..1 : Active CPU speed */
  #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Pos (0UL) /*!< Position of CURRENTFREQ field.                                */
  #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Msk (0x3UL << OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Pos) /*!< Bit mask of
                                                                            CURRENTFREQ field.*/
  #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Min (0x1UL) /*!< Min enumerator value of CURRENTFREQ field.                  */
  #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_Max (0x3UL) /*!< Max enumerator value of CURRENTFREQ field.                  */
  #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK128M (0x1UL) /*!< 128 MHz                                                  */
  #define OSCILLATORS_PLL_CURRENTFREQ_CURRENTFREQ_CK64M (0x3UL) /*!< 64 MHz                                                    */



/* =============================================== Struct OSCILLATORS_XOSC32KI =============================================== */
/**
  * @brief XOSC32KI [OSCILLATORS_XOSC32KI] 32.768 kHz oscillator control
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  INTCAP;                            /*!< (@ 0x00000004) Programmable capacitance of XL1 and XL2               */
} NRF_OSCILLATORS_XOSC32KI_Type;                     /*!< Size = 8 (0x008)                                                     */

/* OSCILLATORS_XOSC32KI_INTCAP: Programmable capacitance of XL1 and XL2 */
  #define OSCILLATORS_XOSC32KI_INTCAP_ResetValue (0x00000017UL) /*!< Reset value of INTCAP register.                           */

/* VAL @Bits 0..4 : Crystal load capacitor as seen by the crystal across its terminals, including pin capacitance but excluding
                    PCB stray capacitance. */

  #define OSCILLATORS_XOSC32KI_INTCAP_VAL_Pos (0UL)  /*!< Position of VAL field.                                               */
  #define OSCILLATORS_XOSC32KI_INTCAP_VAL_Msk (0x1FUL << OSCILLATORS_XOSC32KI_INTCAP_VAL_Pos) /*!< Bit mask of VAL field.      */


/* =================================================== Struct OSCILLATORS ==================================================== */
/**
  * @brief Oscillator control
  */
  typedef struct {                                   /*!< OSCILLATORS Structure                                                */
    __IM uint32_t RESERVED[448];
    __IOM NRF_OSCILLATORS_XOSC32M_Type XOSC32M;      /*!< (@ 0x00000700) 32 MHz oscillator control                             */
    __IM uint32_t RESERVED1[56];
    __IOM NRF_OSCILLATORS_PLL_Type PLL;              /*!< (@ 0x00000800) Oscillator control                                    */
    __IM uint32_t RESERVED2[62];
    __IOM NRF_OSCILLATORS_XOSC32KI_Type XOSC32KI;    /*!< (@ 0x00000900) 32.768 kHz oscillator control                         */
  } NRF_OSCILLATORS_Type;                            /*!< Size = 2312 (0x908)                                                  */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            PDM                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================== Struct PDM_EVENTS_DMA ================================================== */
/**
  * @brief EVENTS_DMA [PDM_EVENTS_DMA] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000000) This event is generated if an error occurs during the
                                                                         bus transfer.*/
} NRF_PDM_EVENTS_DMA_Type;                           /*!< Size = 4 (0x004)                                                     */

/* PDM_EVENTS_DMA_BUSERROR: This event is generated if an error occurs during the bus transfer. */
  #define PDM_EVENTS_DMA_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                             */

/* BUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
  #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                          */
  #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Msk (0x1UL << PDM_EVENTS_DMA_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR field.*/
  #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                            */
  #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                            */
  #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define PDM_EVENTS_DMA_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                              */



/* ================================================= Struct PDM_PUBLISH_DMA ================================================== */
/**
  * @brief PUBLISH_DMA [PDM_PUBLISH_DMA] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000000) Publish configuration for event DMA.BUSERROR          */
} NRF_PDM_PUBLISH_DMA_Type;                          /*!< Size = 4 (0x004)                                                     */

/* PDM_PUBLISH_DMA_BUSERROR: Publish configuration for event DMA.BUSERROR */
  #define PDM_PUBLISH_DMA_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that event DMA.BUSERROR will publish to */
  #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Msk (0xFFUL << PDM_PUBLISH_DMA_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define PDM_PUBLISH_DMA_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define PDM_PUBLISH_DMA_BUSERROR_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define PDM_PUBLISH_DMA_BUSERROR_EN_Msk (0x1UL << PDM_PUBLISH_DMA_BUSERROR_EN_Pos) /*!< Bit mask of EN field.                */
  #define PDM_PUBLISH_DMA_BUSERROR_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define PDM_PUBLISH_DMA_BUSERROR_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define PDM_PUBLISH_DMA_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define PDM_PUBLISH_DMA_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */



/* ===================================================== Struct PDM_PSEL ===================================================== */
/**
  * @brief PSEL [PDM_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CLK;                               /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal           */
  __IOM uint32_t  DIN;                               /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal           */
} NRF_PDM_PSEL_Type;                                 /*!< Size = 8 (0x008)                                                     */

/* PDM_PSEL_CLK: Pin number configuration for PDM CLK signal */
  #define PDM_PSEL_CLK_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of CLK register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define PDM_PSEL_CLK_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
  #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field.                                    */
  #define PDM_PSEL_CLK_PIN_Min (0x00UL)              /*!< Min value of PIN field.                                              */
  #define PDM_PSEL_CLK_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define PDM_PSEL_CLK_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
  #define PDM_PSEL_CLK_PORT_Msk (0x7UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field.                                  */
  #define PDM_PSEL_CLK_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
  #define PDM_PSEL_CLK_PORT_Max (0x7UL)              /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define PDM_PSEL_CLK_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
  #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
  #define PDM_PSEL_CLK_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
  #define PDM_PSEL_CLK_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
  #define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
  #define PDM_PSEL_CLK_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */


/* PDM_PSEL_DIN: Pin number configuration for PDM DIN signal */
  #define PDM_PSEL_DIN_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of DIN register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define PDM_PSEL_DIN_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
  #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field.                                    */
  #define PDM_PSEL_DIN_PIN_Min (0x00UL)              /*!< Min value of PIN field.                                              */
  #define PDM_PSEL_DIN_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define PDM_PSEL_DIN_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
  #define PDM_PSEL_DIN_PORT_Msk (0x7UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field.                                  */
  #define PDM_PSEL_DIN_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
  #define PDM_PSEL_DIN_PORT_Max (0x7UL)              /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define PDM_PSEL_DIN_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
  #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
  #define PDM_PSEL_DIN_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
  #define PDM_PSEL_DIN_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
  #define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
  #define PDM_PSEL_DIN_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */



/* ==================================================== Struct PDM_SAMPLE ==================================================== */
/**
  * @brief SAMPLE [PDM_SAMPLE] (unspecified)
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) RAM address pointer to write samples to with EasyDMA  */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Number of bytes to allocate memory for in EasyDMA mode*/
} NRF_PDM_SAMPLE_Type;                               /*!< Size = 8 (0x008)                                                     */

/* PDM_SAMPLE_PTR: RAM address pointer to write samples to with EasyDMA */
  #define PDM_SAMPLE_PTR_ResetValue (0x00000000UL)   /*!< Reset value of PTR register.                                         */

/* SAMPLEPTR @Bits 0..31 : Address to write PCM samples to over DMA */
  #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL)         /*!< Position of SAMPLEPTR field.                                         */
  #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field.        */


/* PDM_SAMPLE_MAXCNT: Number of bytes to allocate memory for in EasyDMA mode */
  #define PDM_SAMPLE_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                     */

/* BUFFSIZE @Bits 0..14 : Length of DMA RAM allocation in number of bytes */
  #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL)       /*!< Position of BUFFSIZE field.                                          */
  #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field.         */
  #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Min (0x0000UL)  /*!< Min value of BUFFSIZE field.                                         */
  #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Max (0x7FFFUL)  /*!< Max size of BUFFSIZE field.                                          */



/* ===================================================== Struct PDM_DMA ====================================================== */
/**
  * @brief DMA [PDM_DMA] (unspecified)
  */
typedef struct {
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_PDM_DMA_Type;                                  /*!< Size = 8 (0x008)                                                     */

/* PDM_DMA_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define PDM_DMA_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.              */

/* ENABLE @Bit 0 : (unspecified) */
  #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                          */
  #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of ENABLE
                                                                            field.*/
  #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                            */
  #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                            */
  #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                     */
  #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                       */


/* PDM_DMA_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define PDM_DMA_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                      */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos (0UL)  /*!< Position of ADDRESS field.                                           */
  #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS
                                                                            field.*/


/* ======================================================= Struct PDM ======================================================== */
/**
  * @brief Pulse Density Modulation (Digital Microphone) Interface
  */
  typedef struct {                                   /*!< PDM Structure                                                        */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Starts continuous PDM transfer                        */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stops PDM transfer                                    */
    __IM uint32_t RESERVED[30];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED1[30];
    __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000100) PDM transfer has started                              */
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) PDM transfer has finished                             */
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000108) The PDM has written the last sample specified by
                                                                         SAMPLE.MAXCNT (or the last sample after a STOP task has
                                                                         been received) to Data RAM*/
    __IM uint32_t RESERVED2;
    __IOM NRF_PDM_EVENTS_DMA_Type EVENTS_DMA;        /*!< (@ 0x00000110) Peripheral events.                                    */
    __IM uint32_t RESERVED3[27];
    __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x00000180) Publish configuration for event STARTED               */
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000188) Publish configuration for event END                   */
    __IM uint32_t RESERVED4;
    __IOM NRF_PDM_PUBLISH_DMA_Type PUBLISH_DMA;      /*!< (@ 0x00000190) Publish configuration for events                      */
    __IM uint32_t RESERVED5[91];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED6[124];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) PDM module enable register                            */
    __IM uint32_t RESERVED7;
    __IOM uint32_t MODE;                             /*!< (@ 0x00000508) Defines the routing of the connected PDM microphone
                                                                         signals*/
    __IM uint32_t RESERVED8[3];
    __IOM uint32_t GAINL;                            /*!< (@ 0x00000518) Left output gain adjustment                           */
    __IOM uint32_t GAINR;                            /*!< (@ 0x0000051C) Right output gain adjustment                          */
    __IOM uint32_t RATIO;                            /*!< (@ 0x00000520) Selects the decimation ratio between PDM_CLK and output
                                                                         sample rate. Change PRESCALER accordingly.*/
    __IM uint32_t RESERVED9[7];
    __IOM NRF_PDM_PSEL_Type PSEL;                    /*!< (@ 0x00000540) (unspecified)                                         */
    __IM uint32_t RESERVED10[6];
    __IOM NRF_PDM_SAMPLE_Type SAMPLE;                /*!< (@ 0x00000560) (unspecified)                                         */
    __IM uint32_t RESERVED11[6];
    __IOM uint32_t PRESCALER;                        /*!< (@ 0x00000580) The prescaler is used to set the PDM frequency        */
    __IM uint32_t RESERVED12[95];
    __IOM NRF_PDM_DMA_Type DMA;                      /*!< (@ 0x00000700) (unspecified)                                         */
  } NRF_PDM_Type;                                    /*!< Size = 1800 (0x708)                                                  */

/* PDM_TASKS_START: Starts continuous PDM transfer */
  #define PDM_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Starts continuous PDM transfer */
  #define PDM_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
  #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
  #define PDM_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
  #define PDM_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
  #define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */


/* PDM_TASKS_STOP: Stops PDM transfer */
  #define PDM_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stops PDM transfer */
  #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
  #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
  #define PDM_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
  #define PDM_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
  #define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* PDM_SUBSCRIBE_START: Subscribe configuration for task START */
  #define PDM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define PDM_SUBSCRIBE_START_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define PDM_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PDM_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
  #define PDM_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define PDM_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* PDM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define PDM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define PDM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define PDM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
  #define PDM_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define PDM_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
  #define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */


/* PDM_EVENTS_STARTED: PDM transfer has started */
  #define PDM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                            */

/* EVENTS_STARTED @Bit 0 : PDM transfer has started */
  #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                   */
  #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED
                                                                            field.*/
  #define PDM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                     */
  #define PDM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                     */
  #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                             */


/* PDM_EVENTS_STOPPED: PDM transfer has finished */
  #define PDM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */

/* EVENTS_STOPPED @Bit 0 : PDM transfer has finished */
  #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
  #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
                                                                            field.*/
  #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
  #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
  #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */


/* PDM_EVENTS_END: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been
                    received) to Data RAM */

  #define PDM_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has
                       been received) to Data RAM */

  #define PDM_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
  #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
  #define PDM_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
  #define PDM_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
  #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
  #define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */


/* PDM_PUBLISH_STARTED: Publish configuration for event STARTED */
  #define PDM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
  #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define PDM_PUBLISH_STARTED_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define PDM_PUBLISH_STARTED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PDM_PUBLISH_STARTED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                          */
  #define PDM_PUBLISH_STARTED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define PDM_PUBLISH_STARTED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* PDM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define PDM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define PDM_PUBLISH_STOPPED_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define PDM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PDM_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
  #define PDM_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define PDM_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* PDM_PUBLISH_END: Publish configuration for event END */
  #define PDM_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define PDM_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
  #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
  #define PDM_PUBLISH_END_CHIDX_Min (0x00UL)         /*!< Min value of CHIDX field.                                            */
  #define PDM_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PDM_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
  #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
  #define PDM_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
  #define PDM_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
  #define PDM_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
  #define PDM_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */


/* PDM_INTEN: Enable or disable interrupt */
  #define PDM_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */

/* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */
  #define PDM_INTEN_STARTED_Pos (0UL)                /*!< Position of STARTED field.                                           */
  #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field.                               */
  #define PDM_INTEN_STARTED_Min (0x0UL)              /*!< Min enumerator value of STARTED field.                               */
  #define PDM_INTEN_STARTED_Max (0x1UL)              /*!< Max enumerator value of STARTED field.                               */
  #define PDM_INTEN_STARTED_Disabled (0x0UL)         /*!< Disable                                                              */
  #define PDM_INTEN_STARTED_Enabled (0x1UL)          /*!< Enable                                                               */

/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
  #define PDM_INTEN_STOPPED_Pos (1UL)                /*!< Position of STOPPED field.                                           */
  #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                               */
  #define PDM_INTEN_STOPPED_Min (0x0UL)              /*!< Min enumerator value of STOPPED field.                               */
  #define PDM_INTEN_STOPPED_Max (0x1UL)              /*!< Max enumerator value of STOPPED field.                               */
  #define PDM_INTEN_STOPPED_Disabled (0x0UL)         /*!< Disable                                                              */
  #define PDM_INTEN_STOPPED_Enabled (0x1UL)          /*!< Enable                                                               */

/* END @Bit 2 : Enable or disable interrupt for event END */
  #define PDM_INTEN_END_Pos (2UL)                    /*!< Position of END field.                                               */
  #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field.                                           */
  #define PDM_INTEN_END_Min (0x0UL)                  /*!< Min enumerator value of END field.                                   */
  #define PDM_INTEN_END_Max (0x1UL)                  /*!< Max enumerator value of END field.                                   */
  #define PDM_INTEN_END_Disabled (0x0UL)             /*!< Disable                                                              */
  #define PDM_INTEN_END_Enabled (0x1UL)              /*!< Enable                                                               */

/* DMABUSERROR @Bit 4 : Enable or disable interrupt for event DMABUSERROR */
  #define PDM_INTEN_DMABUSERROR_Pos (4UL)            /*!< Position of DMABUSERROR field.                                       */
  #define PDM_INTEN_DMABUSERROR_Msk (0x1UL << PDM_INTEN_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field.                   */
  #define PDM_INTEN_DMABUSERROR_Min (0x0UL)          /*!< Min enumerator value of DMABUSERROR field.                           */
  #define PDM_INTEN_DMABUSERROR_Max (0x1UL)          /*!< Max enumerator value of DMABUSERROR field.                           */
  #define PDM_INTEN_DMABUSERROR_Disabled (0x0UL)     /*!< Disable                                                              */
  #define PDM_INTEN_DMABUSERROR_Enabled (0x1UL)      /*!< Enable                                                               */


/* PDM_INTENSET: Enable interrupt */
  #define PDM_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */
  #define PDM_INTENSET_STARTED_Pos (0UL)             /*!< Position of STARTED field.                                           */
  #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                         */
  #define PDM_INTENSET_STARTED_Min (0x0UL)           /*!< Min enumerator value of STARTED field.                               */
  #define PDM_INTENSET_STARTED_Max (0x1UL)           /*!< Max enumerator value of STARTED field.                               */
  #define PDM_INTENSET_STARTED_Set (0x1UL)           /*!< Enable                                                               */
  #define PDM_INTENSET_STARTED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PDM_INTENSET_STARTED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
  #define PDM_INTENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define PDM_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define PDM_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define PDM_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
  #define PDM_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PDM_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* END @Bit 2 : Write '1' to enable interrupt for event END */
  #define PDM_INTENSET_END_Pos (2UL)                 /*!< Position of END field.                                               */
  #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
  #define PDM_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define PDM_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define PDM_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
  #define PDM_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define PDM_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* DMABUSERROR @Bit 4 : Write '1' to enable interrupt for event DMABUSERROR */
  #define PDM_INTENSET_DMABUSERROR_Pos (4UL)         /*!< Position of DMABUSERROR field.                                       */
  #define PDM_INTENSET_DMABUSERROR_Msk (0x1UL << PDM_INTENSET_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field.             */
  #define PDM_INTENSET_DMABUSERROR_Min (0x0UL)       /*!< Min enumerator value of DMABUSERROR field.                           */
  #define PDM_INTENSET_DMABUSERROR_Max (0x1UL)       /*!< Max enumerator value of DMABUSERROR field.                           */
  #define PDM_INTENSET_DMABUSERROR_Set (0x1UL)       /*!< Enable                                                               */
  #define PDM_INTENSET_DMABUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define PDM_INTENSET_DMABUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* PDM_INTENCLR: Disable interrupt */
  #define PDM_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */
  #define PDM_INTENCLR_STARTED_Pos (0UL)             /*!< Position of STARTED field.                                           */
  #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                         */
  #define PDM_INTENCLR_STARTED_Min (0x0UL)           /*!< Min enumerator value of STARTED field.                               */
  #define PDM_INTENCLR_STARTED_Max (0x1UL)           /*!< Max enumerator value of STARTED field.                               */
  #define PDM_INTENCLR_STARTED_Clear (0x1UL)         /*!< Disable                                                              */
  #define PDM_INTENCLR_STARTED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PDM_INTENCLR_STARTED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
  #define PDM_INTENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define PDM_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define PDM_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define PDM_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
  #define PDM_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PDM_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* END @Bit 2 : Write '1' to disable interrupt for event END */
  #define PDM_INTENCLR_END_Pos (2UL)                 /*!< Position of END field.                                               */
  #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
  #define PDM_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
  #define PDM_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
  #define PDM_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
  #define PDM_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
  #define PDM_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */

/* DMABUSERROR @Bit 4 : Write '1' to disable interrupt for event DMABUSERROR */
  #define PDM_INTENCLR_DMABUSERROR_Pos (4UL)         /*!< Position of DMABUSERROR field.                                       */
  #define PDM_INTENCLR_DMABUSERROR_Msk (0x1UL << PDM_INTENCLR_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field.             */
  #define PDM_INTENCLR_DMABUSERROR_Min (0x0UL)       /*!< Min enumerator value of DMABUSERROR field.                           */
  #define PDM_INTENCLR_DMABUSERROR_Max (0x1UL)       /*!< Max enumerator value of DMABUSERROR field.                           */
  #define PDM_INTENCLR_DMABUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
  #define PDM_INTENCLR_DMABUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define PDM_INTENCLR_DMABUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* PDM_INTPEND: Pending interrupts */
  #define PDM_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */

/* STARTED @Bit 0 : Read pending status of interrupt for event STARTED */
  #define PDM_INTPEND_STARTED_Pos (0UL)              /*!< Position of STARTED field.                                           */
  #define PDM_INTPEND_STARTED_Msk (0x1UL << PDM_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field.                           */
  #define PDM_INTPEND_STARTED_Min (0x0UL)            /*!< Min enumerator value of STARTED field.                               */
  #define PDM_INTPEND_STARTED_Max (0x1UL)            /*!< Max enumerator value of STARTED field.                               */
  #define PDM_INTPEND_STARTED_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
  #define PDM_INTPEND_STARTED_Pending (0x1UL)        /*!< Read: Pending                                                        */

/* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */
  #define PDM_INTPEND_STOPPED_Pos (1UL)              /*!< Position of STOPPED field.                                           */
  #define PDM_INTPEND_STOPPED_Msk (0x1UL << PDM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field.                           */
  #define PDM_INTPEND_STOPPED_Min (0x0UL)            /*!< Min enumerator value of STOPPED field.                               */
  #define PDM_INTPEND_STOPPED_Max (0x1UL)            /*!< Max enumerator value of STOPPED field.                               */
  #define PDM_INTPEND_STOPPED_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
  #define PDM_INTPEND_STOPPED_Pending (0x1UL)        /*!< Read: Pending                                                        */

/* END @Bit 2 : Read pending status of interrupt for event END */
  #define PDM_INTPEND_END_Pos (2UL)                  /*!< Position of END field.                                               */
  #define PDM_INTPEND_END_Msk (0x1UL << PDM_INTPEND_END_Pos) /*!< Bit mask of END field.                                       */
  #define PDM_INTPEND_END_Min (0x0UL)                /*!< Min enumerator value of END field.                                   */
  #define PDM_INTPEND_END_Max (0x1UL)                /*!< Max enumerator value of END field.                                   */
  #define PDM_INTPEND_END_NotPending (0x0UL)         /*!< Read: Not pending                                                    */
  #define PDM_INTPEND_END_Pending (0x1UL)            /*!< Read: Pending                                                        */

/* DMABUSERROR @Bit 4 : Read pending status of interrupt for event DMABUSERROR */
  #define PDM_INTPEND_DMABUSERROR_Pos (4UL)          /*!< Position of DMABUSERROR field.                                       */
  #define PDM_INTPEND_DMABUSERROR_Msk (0x1UL << PDM_INTPEND_DMABUSERROR_Pos) /*!< Bit mask of DMABUSERROR field.               */
  #define PDM_INTPEND_DMABUSERROR_Min (0x0UL)        /*!< Min enumerator value of DMABUSERROR field.                           */
  #define PDM_INTPEND_DMABUSERROR_Max (0x1UL)        /*!< Max enumerator value of DMABUSERROR field.                           */
  #define PDM_INTPEND_DMABUSERROR_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define PDM_INTPEND_DMABUSERROR_Pending (0x1UL)    /*!< Read: Pending                                                        */


/* PDM_ENABLE: PDM module enable register */
  #define PDM_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bit 0 : Enable or disable PDM module */
  #define PDM_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
  #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
  #define PDM_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
  #define PDM_ENABLE_ENABLE_Max (0x1UL)              /*!< Max enumerator value of ENABLE field.                                */
  #define PDM_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
  #define PDM_ENABLE_ENABLE_Enabled (0x1UL)          /*!< Enable                                                               */


/* PDM_MODE: Defines the routing of the connected PDM microphone signals */
  #define PDM_MODE_ResetValue (0x00000000UL)         /*!< Reset value of MODE register.                                        */

/* OPERATION @Bit 0 : Mono or stereo operation */
  #define PDM_MODE_OPERATION_Pos (0UL)               /*!< Position of OPERATION field.                                         */
  #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field.                           */
  #define PDM_MODE_OPERATION_Min (0x0UL)             /*!< Min enumerator value of OPERATION field.                             */
  #define PDM_MODE_OPERATION_Max (0x1UL)             /*!< Max enumerator value of OPERATION field.                             */
  #define PDM_MODE_OPERATION_Stereo (0x0UL)          /*!< Sample and store one pair (left + right) of 16-bit samples per RAM
                                                          word R=[31:16]; L=[15:0]*/
  #define PDM_MODE_OPERATION_Mono (0x1UL)            /*!< Sample and store two successive left samples (16 bits each) per RAM
                                                          word L1=[31:16]; L0=[15:0]*/

/* EDGE @Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled. */
  #define PDM_MODE_EDGE_Pos (1UL)                    /*!< Position of EDGE field.                                              */
  #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field.                                          */
  #define PDM_MODE_EDGE_Min (0x0UL)                  /*!< Min enumerator value of EDGE field.                                  */
  #define PDM_MODE_EDGE_Max (0x1UL)                  /*!< Max enumerator value of EDGE field.                                  */
  #define PDM_MODE_EDGE_LeftFalling (0x1UL)          /*!< Left (or mono) is sampled on falling edge of PDM_CLK                 */
  #define PDM_MODE_EDGE_LeftRising (0x0UL)           /*!< Left (or mono) is sampled on rising edge of PDM_CLK                  */


/* PDM_GAINL: Left output gain adjustment */
  #define PDM_GAINL_ResetValue (0x00000028UL)        /*!< Reset value of GAINL register.                                       */

/* GAINL @Bits 0..6 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
                      0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust
                      0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */

  #define PDM_GAINL_GAINL_Pos (0UL)                  /*!< Position of GAINL field.                                             */
  #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field.                                    */
  #define PDM_GAINL_GAINL_Min (0x0UL)                /*!< Min enumerator value of GAINL field.                                 */
  #define PDM_GAINL_GAINL_Max (0x50UL)               /*!< Max enumerator value of GAINL field.                                 */
  #define PDM_GAINL_GAINL_MinGain (0x00UL)           /*!< -20 dB gain adjustment (minimum)                                     */
  #define PDM_GAINL_GAINL_DefaultGain (0x28UL)       /*!< 0 dB gain adjustment                                                 */
  #define PDM_GAINL_GAINL_MaxGain (0x50UL)           /*!< +20 dB gain adjustment (maximum)                                     */


/* PDM_GAINR: Right output gain adjustment */
  #define PDM_GAINR_ResetValue (0x00000028UL)        /*!< Reset value of GAINR register.                                       */

/* GAINR @Bits 0..6 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
                      */

  #define PDM_GAINR_GAINR_Pos (0UL)                  /*!< Position of GAINR field.                                             */
  #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field.                                    */
  #define PDM_GAINR_GAINR_Min (0x0UL)                /*!< Min enumerator value of GAINR field.                                 */
  #define PDM_GAINR_GAINR_Max (0x50UL)               /*!< Max enumerator value of GAINR field.                                 */
  #define PDM_GAINR_GAINR_MinGain (0x00UL)           /*!< -20 dB gain adjustment (minimum)                                     */
  #define PDM_GAINR_GAINR_DefaultGain (0x28UL)       /*!< 0 dB gain adjustment                                                 */
  #define PDM_GAINR_GAINR_MaxGain (0x50UL)           /*!< +20 dB gain adjustment (maximum)                                     */


/* PDM_RATIO: Selects the decimation ratio between PDM_CLK and output sample rate. Change PRESCALER accordingly. */
  #define PDM_RATIO_ResetValue (0x00000002UL)        /*!< Reset value of RATIO register.                                       */

/* RATIO @Bits 0..2 : Selects the decimation ratio between PDM_CLK and output sample rate */
  #define PDM_RATIO_RATIO_Pos (0UL)                  /*!< Position of RATIO field.                                             */
  #define PDM_RATIO_RATIO_Msk (0x7UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field.                                     */
  #define PDM_RATIO_RATIO_Min (0x0UL)                /*!< Min enumerator value of RATIO field.                                 */
  #define PDM_RATIO_RATIO_Max (0x7UL)                /*!< Max enumerator value of RATIO field.                                 */
  #define PDM_RATIO_RATIO_Ratio32 (0x0UL)            /*!< Ratio of 32                                                          */
  #define PDM_RATIO_RATIO_Ratio48 (0x1UL)            /*!< Ratio of 48                                                          */
  #define PDM_RATIO_RATIO_Ratio50 (0x2UL)            /*!< Ratio of 50                                                          */
  #define PDM_RATIO_RATIO_Ratio64 (0x3UL)            /*!< Ratio of 64                                                          */
  #define PDM_RATIO_RATIO_Ratio80 (0x4UL)            /*!< Ratio of 80                                                          */
  #define PDM_RATIO_RATIO_Ratio96 (0x5UL)            /*!< Ratio of 96                                                          */
  #define PDM_RATIO_RATIO_Ratio100 (0x6UL)           /*!< Ratio of 100                                                         */
  #define PDM_RATIO_RATIO_Ratio128 (0x7UL)           /*!< Ratio of 128                                                         */


/* PDM_PRESCALER: The prescaler is used to set the PDM frequency */
  #define PDM_PRESCALER_ResetValue (0x00000004UL)    /*!< Reset value of PRESCALER register.                                   */

/* DIVISOR @Bits 0..7 : Core clock to PDM divisor */
  #define PDM_PRESCALER_DIVISOR_Pos (0UL)            /*!< Position of DIVISOR field.                                           */
  #define PDM_PRESCALER_DIVISOR_Msk (0xFFUL << PDM_PRESCALER_DIVISOR_Pos) /*!< Bit mask of DIVISOR field.                      */
  #define PDM_PRESCALER_DIVISOR_Min (0x04UL)         /*!< Min value of DIVISOR field.                                          */
  #define PDM_PRESCALER_DIVISOR_Max (0x7EUL)         /*!< Max size of DIVISOR field.                                           */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           POWER                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ====================================================== Struct POWER ======================================================= */
/**
  * @brief Power control
  */
  typedef struct {                                   /*!< POWER Structure                                                      */
    __IM uint32_t RESERVED[12];
    __OM uint32_t TASKS_CONSTLAT;                    /*!< (@ 0x00000030) Enable Constant Latency mode                          */
    __OM uint32_t TASKS_LOWPWR;                      /*!< (@ 0x00000034) Enable Low-power mode (variable latency)              */
    __IM uint32_t RESERVED1[30];
    __IOM uint32_t SUBSCRIBE_CONSTLAT;               /*!< (@ 0x000000B0) Subscribe configuration for task CONSTLAT             */
    __IOM uint32_t SUBSCRIBE_LOWPWR;                 /*!< (@ 0x000000B4) Subscribe configuration for task LOWPWR               */
    __IM uint32_t RESERVED2[30];
    __IOM uint32_t EVENTS_POFWARN;                   /*!< (@ 0x00000130) Power failure warning                                 */
    __IOM uint32_t EVENTS_SLEEPENTER;                /*!< (@ 0x00000134) CPU entered WFI/WFE sleep                             */
    __IOM uint32_t EVENTS_SLEEPEXIT;                 /*!< (@ 0x00000138) CPU exited WFI/WFE sleep                              */
    __IM uint32_t RESERVED3[30];
    __IOM uint32_t PUBLISH_SLEEPENTER;               /*!< (@ 0x000001B4) Publish configuration for event SLEEPENTER            */
    __IOM uint32_t PUBLISH_SLEEPEXIT;                /*!< (@ 0x000001B8) Publish configuration for event SLEEPEXIT             */
    __IM uint32_t RESERVED4[81];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED5[125];
    __IOM uint32_t GPREGRET[2];                      /*!< (@ 0x00000500) General purpose retention register                    */
    __IM uint32_t RESERVED6[6];
    __IM uint32_t CONSTLATSTAT;                      /*!< (@ 0x00000520) Status of constant latency                            */
  } NRF_POWER_Type;                                  /*!< Size = 1316 (0x524)                                                  */

/* POWER_TASKS_CONSTLAT: Enable Constant Latency mode */
  #define POWER_TASKS_CONSTLAT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CONSTLAT register.                          */

/* TASKS_CONSTLAT @Bit 0 : Enable Constant Latency mode */
  #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field.                                 */
  #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of
                                                                            TASKS_CONSTLAT field.*/
  #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Min (0x1UL) /*!< Min enumerator value of TASKS_CONSTLAT field.                   */
  #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Max (0x1UL) /*!< Max enumerator value of TASKS_CONSTLAT field.                   */
  #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (0x1UL) /*!< Trigger task                                                */


/* POWER_TASKS_LOWPWR: Enable Low-power mode (variable latency) */
  #define POWER_TASKS_LOWPWR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_LOWPWR register.                              */

/* TASKS_LOWPWR @Bit 0 : Enable Low-power mode (variable latency) */
  #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL)  /*!< Position of TASKS_LOWPWR field.                                      */
  #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR
                                                                            field.*/
  #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Min (0x1UL) /*!< Min enumerator value of TASKS_LOWPWR field.                         */
  #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Max (0x1UL) /*!< Max enumerator value of TASKS_LOWPWR field.                         */
  #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (0x1UL) /*!< Trigger task                                                    */


/* POWER_SUBSCRIBE_CONSTLAT: Subscribe configuration for task CONSTLAT */
  #define POWER_SUBSCRIBE_CONSTLAT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CONSTLAT register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that task CONSTLAT will subscribe to */
  #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field.                */
  #define POWER_SUBSCRIBE_CONSTLAT_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define POWER_SUBSCRIBE_CONSTLAT_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
  #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */


/* POWER_SUBSCRIBE_LOWPWR: Subscribe configuration for task LOWPWR */
  #define POWER_SUBSCRIBE_LOWPWR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_LOWPWR register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that task LOWPWR will subscribe to */
  #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field.                    */
  #define POWER_SUBSCRIBE_LOWPWR_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define POWER_SUBSCRIBE_LOWPWR_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* POWER_EVENTS_POFWARN: Power failure warning */
  #define POWER_EVENTS_POFWARN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_POFWARN register.                          */

/* EVENTS_POFWARN @Bit 0 : Power failure warning */
  #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field.                                 */
  #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of
                                                                            EVENTS_POFWARN field.*/
  #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Min (0x0UL) /*!< Min enumerator value of EVENTS_POFWARN field.                   */
  #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Max (0x1UL) /*!< Max enumerator value of EVENTS_POFWARN field.                   */
  #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (0x1UL) /*!< Event generated                                           */


/* POWER_EVENTS_SLEEPENTER: CPU entered WFI/WFE sleep */
  #define POWER_EVENTS_SLEEPENTER_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SLEEPENTER register.                    */

/* EVENTS_SLEEPENTER @Bit 0 : CPU entered WFI/WFE sleep */
  #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field.                        */
  #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask
                                                                            of EVENTS_SLEEPENTER field.*/
  #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Min (0x0UL) /*!< Min enumerator value of EVENTS_SLEEPENTER field.          */
  #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Max (0x1UL) /*!< Max enumerator value of EVENTS_SLEEPENTER field.          */
  #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (0x1UL) /*!< Event generated                                     */


/* POWER_EVENTS_SLEEPEXIT: CPU exited WFI/WFE sleep */
  #define POWER_EVENTS_SLEEPEXIT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SLEEPEXIT register.                      */

/* EVENTS_SLEEPEXIT @Bit 0 : CPU exited WFI/WFE sleep */
  #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field.                           */
  #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of
                                                                            EVENTS_SLEEPEXIT field.*/
  #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Min (0x0UL) /*!< Min enumerator value of EVENTS_SLEEPEXIT field.             */
  #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Max (0x1UL) /*!< Max enumerator value of EVENTS_SLEEPEXIT field.             */
  #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (0x1UL) /*!< Event generated                                       */


/* POWER_PUBLISH_SLEEPENTER: Publish configuration for event SLEEPENTER */
  #define POWER_PUBLISH_SLEEPENTER_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SLEEPENTER register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that event SLEEPENTER will publish to */
  #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define POWER_PUBLISH_SLEEPENTER_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define POWER_PUBLISH_SLEEPENTER_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field.                */
  #define POWER_PUBLISH_SLEEPENTER_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define POWER_PUBLISH_SLEEPENTER_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* POWER_PUBLISH_SLEEPEXIT: Publish configuration for event SLEEPEXIT */
  #define POWER_PUBLISH_SLEEPEXIT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SLEEPEXIT register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that event SLEEPEXIT will publish to */
  #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field.                  */
  #define POWER_PUBLISH_SLEEPEXIT_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define POWER_PUBLISH_SLEEPEXIT_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* POWER_INTEN: Enable or disable interrupt */
  #define POWER_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */

/* POFWARN @Bit 12 : Enable or disable interrupt for event POFWARN */
  #define POWER_INTEN_POFWARN_Pos (12UL)             /*!< Position of POFWARN field.                                           */
  #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field.                           */
  #define POWER_INTEN_POFWARN_Min (0x0UL)            /*!< Min enumerator value of POFWARN field.                               */
  #define POWER_INTEN_POFWARN_Max (0x1UL)            /*!< Max enumerator value of POFWARN field.                               */
  #define POWER_INTEN_POFWARN_Disabled (0x0UL)       /*!< Disable                                                              */
  #define POWER_INTEN_POFWARN_Enabled (0x1UL)        /*!< Enable                                                               */

/* SLEEPENTER @Bit 13 : Enable or disable interrupt for event SLEEPENTER */
  #define POWER_INTEN_SLEEPENTER_Pos (13UL)          /*!< Position of SLEEPENTER field.                                        */
  #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field.                  */
  #define POWER_INTEN_SLEEPENTER_Min (0x0UL)         /*!< Min enumerator value of SLEEPENTER field.                            */
  #define POWER_INTEN_SLEEPENTER_Max (0x1UL)         /*!< Max enumerator value of SLEEPENTER field.                            */
  #define POWER_INTEN_SLEEPENTER_Disabled (0x0UL)    /*!< Disable                                                              */
  #define POWER_INTEN_SLEEPENTER_Enabled (0x1UL)     /*!< Enable                                                               */

/* SLEEPEXIT @Bit 14 : Enable or disable interrupt for event SLEEPEXIT */
  #define POWER_INTEN_SLEEPEXIT_Pos (14UL)           /*!< Position of SLEEPEXIT field.                                         */
  #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field.                     */
  #define POWER_INTEN_SLEEPEXIT_Min (0x0UL)          /*!< Min enumerator value of SLEEPEXIT field.                             */
  #define POWER_INTEN_SLEEPEXIT_Max (0x1UL)          /*!< Max enumerator value of SLEEPEXIT field.                             */
  #define POWER_INTEN_SLEEPEXIT_Disabled (0x0UL)     /*!< Disable                                                              */
  #define POWER_INTEN_SLEEPEXIT_Enabled (0x1UL)      /*!< Enable                                                               */


/* POWER_INTENSET: Enable interrupt */
  #define POWER_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */

/* POFWARN @Bit 12 : Write '1' to enable interrupt for event POFWARN */
  #define POWER_INTENSET_POFWARN_Pos (12UL)          /*!< Position of POFWARN field.                                           */
  #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field.                     */
  #define POWER_INTENSET_POFWARN_Min (0x0UL)         /*!< Min enumerator value of POFWARN field.                               */
  #define POWER_INTENSET_POFWARN_Max (0x1UL)         /*!< Max enumerator value of POFWARN field.                               */
  #define POWER_INTENSET_POFWARN_Set (0x1UL)         /*!< Enable                                                               */
  #define POWER_INTENSET_POFWARN_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define POWER_INTENSET_POFWARN_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* SLEEPENTER @Bit 13 : Write '1' to enable interrupt for event SLEEPENTER */
  #define POWER_INTENSET_SLEEPENTER_Pos (13UL)       /*!< Position of SLEEPENTER field.                                        */
  #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field.            */
  #define POWER_INTENSET_SLEEPENTER_Min (0x0UL)      /*!< Min enumerator value of SLEEPENTER field.                            */
  #define POWER_INTENSET_SLEEPENTER_Max (0x1UL)      /*!< Max enumerator value of SLEEPENTER field.                            */
  #define POWER_INTENSET_SLEEPENTER_Set (0x1UL)      /*!< Enable                                                               */
  #define POWER_INTENSET_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define POWER_INTENSET_SLEEPENTER_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* SLEEPEXIT @Bit 14 : Write '1' to enable interrupt for event SLEEPEXIT */
  #define POWER_INTENSET_SLEEPEXIT_Pos (14UL)        /*!< Position of SLEEPEXIT field.                                         */
  #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field.               */
  #define POWER_INTENSET_SLEEPEXIT_Min (0x0UL)       /*!< Min enumerator value of SLEEPEXIT field.                             */
  #define POWER_INTENSET_SLEEPEXIT_Max (0x1UL)       /*!< Max enumerator value of SLEEPEXIT field.                             */
  #define POWER_INTENSET_SLEEPEXIT_Set (0x1UL)       /*!< Enable                                                               */
  #define POWER_INTENSET_SLEEPEXIT_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define POWER_INTENSET_SLEEPEXIT_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* POWER_INTENCLR: Disable interrupt */
  #define POWER_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */

/* POFWARN @Bit 12 : Write '1' to disable interrupt for event POFWARN */
  #define POWER_INTENCLR_POFWARN_Pos (12UL)          /*!< Position of POFWARN field.                                           */
  #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field.                     */
  #define POWER_INTENCLR_POFWARN_Min (0x0UL)         /*!< Min enumerator value of POFWARN field.                               */
  #define POWER_INTENCLR_POFWARN_Max (0x1UL)         /*!< Max enumerator value of POFWARN field.                               */
  #define POWER_INTENCLR_POFWARN_Clear (0x1UL)       /*!< Disable                                                              */
  #define POWER_INTENCLR_POFWARN_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define POWER_INTENCLR_POFWARN_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* SLEEPENTER @Bit 13 : Write '1' to disable interrupt for event SLEEPENTER */
  #define POWER_INTENCLR_SLEEPENTER_Pos (13UL)       /*!< Position of SLEEPENTER field.                                        */
  #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field.            */
  #define POWER_INTENCLR_SLEEPENTER_Min (0x0UL)      /*!< Min enumerator value of SLEEPENTER field.                            */
  #define POWER_INTENCLR_SLEEPENTER_Max (0x1UL)      /*!< Max enumerator value of SLEEPENTER field.                            */
  #define POWER_INTENCLR_SLEEPENTER_Clear (0x1UL)    /*!< Disable                                                              */
  #define POWER_INTENCLR_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define POWER_INTENCLR_SLEEPENTER_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* SLEEPEXIT @Bit 14 : Write '1' to disable interrupt for event SLEEPEXIT */
  #define POWER_INTENCLR_SLEEPEXIT_Pos (14UL)        /*!< Position of SLEEPEXIT field.                                         */
  #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field.               */
  #define POWER_INTENCLR_SLEEPEXIT_Min (0x0UL)       /*!< Min enumerator value of SLEEPEXIT field.                             */
  #define POWER_INTENCLR_SLEEPEXIT_Max (0x1UL)       /*!< Max enumerator value of SLEEPEXIT field.                             */
  #define POWER_INTENCLR_SLEEPEXIT_Clear (0x1UL)     /*!< Disable                                                              */
  #define POWER_INTENCLR_SLEEPEXIT_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define POWER_INTENCLR_SLEEPEXIT_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* POWER_GPREGRET: General purpose retention register */
  #define POWER_GPREGRET_MaxCount (2UL)              /*!< Max size of GPREGRET[2] array.                                       */
  #define POWER_GPREGRET_MaxIndex (1UL)              /*!< Max index of GPREGRET[2] array.                                      */
  #define POWER_GPREGRET_MinIndex (0UL)              /*!< Min index of GPREGRET[2] array.                                      */
  #define POWER_GPREGRET_ResetValue (0x00000000UL)   /*!< Reset value of GPREGRET[2] register.                                 */

/* GPREGRET @Bits 0..7 : General purpose retention register */
  #define POWER_GPREGRET_GPREGRET_Pos (0UL)          /*!< Position of GPREGRET field.                                          */
  #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field.                 */


/* POWER_CONSTLATSTAT: Status of constant latency */
  #define POWER_CONSTLATSTAT_ResetValue (0x00000000UL) /*!< Reset value of CONSTLATSTAT register.                              */

/* STATUS @Bit 0 : Status */
  #define POWER_CONSTLATSTAT_STATUS_Pos (0UL)        /*!< Position of STATUS field.                                            */
  #define POWER_CONSTLATSTAT_STATUS_Msk (0x1UL << POWER_CONSTLATSTAT_STATUS_Pos) /*!< Bit mask of STATUS field.                */
  #define POWER_CONSTLATSTAT_STATUS_Min (0x0UL)      /*!< Min enumerator value of STATUS field.                                */
  #define POWER_CONSTLATSTAT_STATUS_Max (0x1UL)      /*!< Max enumerator value of STATUS field.                                */
  #define POWER_CONSTLATSTAT_STATUS_Disable (0x0UL)  /*!< Constant latency disabled                                            */
  #define POWER_CONSTLATSTAT_STATUS_Enable (0x1UL)   /*!< Constant latency enabled                                             */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           PPIB                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================== Struct PPIB_OVERFLOW =================================================== */
/**
  * @brief OVERFLOW [PPIB_OVERFLOW] (unspecified)
  */
typedef struct {
  __IOM uint32_t  SEND;                              /*!< (@ 0x00000000) The task overflow for SEND tasks using SUBSCRIBE_SEND.
                                                                         Write 0 to clear.*/
} NRF_PPIB_OVERFLOW_Type;                            /*!< Size = 4 (0x004)                                                     */

/* PPIB_OVERFLOW_SEND: The task overflow for SEND tasks using SUBSCRIBE_SEND. Write 0 to clear. */
  #define PPIB_OVERFLOW_SEND_ResetValue (0x00000000UL) /*!< Reset value of SEND register.                                      */

/* SEND0 @Bit 0 : The status for tasks overflow at SUBSCRIBE_SEND[0]. */
  #define PPIB_OVERFLOW_SEND_SEND0_Pos (0UL)         /*!< Position of SEND0 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND0_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND0_Pos) /*!< Bit mask of SEND0 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND0_Min (0x0UL)       /*!< Min enumerator value of SEND0 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND0_Max (0x1UL)       /*!< Max enumerator value of SEND0 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND0_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND0_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND1 @Bit 1 : The status for tasks overflow at SUBSCRIBE_SEND[1]. */
  #define PPIB_OVERFLOW_SEND_SEND1_Pos (1UL)         /*!< Position of SEND1 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND1_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND1_Pos) /*!< Bit mask of SEND1 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND1_Min (0x0UL)       /*!< Min enumerator value of SEND1 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND1_Max (0x1UL)       /*!< Max enumerator value of SEND1 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND1_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND1_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND2 @Bit 2 : The status for tasks overflow at SUBSCRIBE_SEND[2]. */
  #define PPIB_OVERFLOW_SEND_SEND2_Pos (2UL)         /*!< Position of SEND2 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND2_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND2_Pos) /*!< Bit mask of SEND2 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND2_Min (0x0UL)       /*!< Min enumerator value of SEND2 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND2_Max (0x1UL)       /*!< Max enumerator value of SEND2 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND2_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND2_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND3 @Bit 3 : The status for tasks overflow at SUBSCRIBE_SEND[3]. */
  #define PPIB_OVERFLOW_SEND_SEND3_Pos (3UL)         /*!< Position of SEND3 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND3_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND3_Pos) /*!< Bit mask of SEND3 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND3_Min (0x0UL)       /*!< Min enumerator value of SEND3 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND3_Max (0x1UL)       /*!< Max enumerator value of SEND3 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND3_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND3_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND4 @Bit 4 : The status for tasks overflow at SUBSCRIBE_SEND[4]. */
  #define PPIB_OVERFLOW_SEND_SEND4_Pos (4UL)         /*!< Position of SEND4 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND4_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND4_Pos) /*!< Bit mask of SEND4 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND4_Min (0x0UL)       /*!< Min enumerator value of SEND4 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND4_Max (0x1UL)       /*!< Max enumerator value of SEND4 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND4_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND4_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND5 @Bit 5 : The status for tasks overflow at SUBSCRIBE_SEND[5]. */
  #define PPIB_OVERFLOW_SEND_SEND5_Pos (5UL)         /*!< Position of SEND5 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND5_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND5_Pos) /*!< Bit mask of SEND5 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND5_Min (0x0UL)       /*!< Min enumerator value of SEND5 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND5_Max (0x1UL)       /*!< Max enumerator value of SEND5 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND5_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND5_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND6 @Bit 6 : The status for tasks overflow at SUBSCRIBE_SEND[6]. */
  #define PPIB_OVERFLOW_SEND_SEND6_Pos (6UL)         /*!< Position of SEND6 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND6_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND6_Pos) /*!< Bit mask of SEND6 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND6_Min (0x0UL)       /*!< Min enumerator value of SEND6 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND6_Max (0x1UL)       /*!< Max enumerator value of SEND6 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND6_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND6_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND7 @Bit 7 : The status for tasks overflow at SUBSCRIBE_SEND[7]. */
  #define PPIB_OVERFLOW_SEND_SEND7_Pos (7UL)         /*!< Position of SEND7 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND7_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND7_Pos) /*!< Bit mask of SEND7 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND7_Min (0x0UL)       /*!< Min enumerator value of SEND7 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND7_Max (0x1UL)       /*!< Max enumerator value of SEND7 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND7_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND7_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND8 @Bit 8 : The status for tasks overflow at SUBSCRIBE_SEND[8]. */
  #define PPIB_OVERFLOW_SEND_SEND8_Pos (8UL)         /*!< Position of SEND8 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND8_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND8_Pos) /*!< Bit mask of SEND8 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND8_Min (0x0UL)       /*!< Min enumerator value of SEND8 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND8_Max (0x1UL)       /*!< Max enumerator value of SEND8 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND8_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND8_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND9 @Bit 9 : The status for tasks overflow at SUBSCRIBE_SEND[9]. */
  #define PPIB_OVERFLOW_SEND_SEND9_Pos (9UL)         /*!< Position of SEND9 field.                                             */
  #define PPIB_OVERFLOW_SEND_SEND9_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND9_Pos) /*!< Bit mask of SEND9 field.                   */
  #define PPIB_OVERFLOW_SEND_SEND9_Min (0x0UL)       /*!< Min enumerator value of SEND9 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND9_Max (0x1UL)       /*!< Max enumerator value of SEND9 field.                                 */
  #define PPIB_OVERFLOW_SEND_SEND9_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND9_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */

/* SEND10 @Bit 10 : The status for tasks overflow at SUBSCRIBE_SEND[10]. */
  #define PPIB_OVERFLOW_SEND_SEND10_Pos (10UL)       /*!< Position of SEND10 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND10_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND10_Pos) /*!< Bit mask of SEND10 field.                */
  #define PPIB_OVERFLOW_SEND_SEND10_Min (0x0UL)      /*!< Min enumerator value of SEND10 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND10_Max (0x1UL)      /*!< Max enumerator value of SEND10 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND10_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND10_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND11 @Bit 11 : The status for tasks overflow at SUBSCRIBE_SEND[11]. */
  #define PPIB_OVERFLOW_SEND_SEND11_Pos (11UL)       /*!< Position of SEND11 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND11_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND11_Pos) /*!< Bit mask of SEND11 field.                */
  #define PPIB_OVERFLOW_SEND_SEND11_Min (0x0UL)      /*!< Min enumerator value of SEND11 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND11_Max (0x1UL)      /*!< Max enumerator value of SEND11 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND11_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND11_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND12 @Bit 12 : The status for tasks overflow at SUBSCRIBE_SEND[12]. */
  #define PPIB_OVERFLOW_SEND_SEND12_Pos (12UL)       /*!< Position of SEND12 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND12_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND12_Pos) /*!< Bit mask of SEND12 field.                */
  #define PPIB_OVERFLOW_SEND_SEND12_Min (0x0UL)      /*!< Min enumerator value of SEND12 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND12_Max (0x1UL)      /*!< Max enumerator value of SEND12 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND12_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND12_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND13 @Bit 13 : The status for tasks overflow at SUBSCRIBE_SEND[13]. */
  #define PPIB_OVERFLOW_SEND_SEND13_Pos (13UL)       /*!< Position of SEND13 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND13_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND13_Pos) /*!< Bit mask of SEND13 field.                */
  #define PPIB_OVERFLOW_SEND_SEND13_Min (0x0UL)      /*!< Min enumerator value of SEND13 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND13_Max (0x1UL)      /*!< Max enumerator value of SEND13 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND13_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND13_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND14 @Bit 14 : The status for tasks overflow at SUBSCRIBE_SEND[14]. */
  #define PPIB_OVERFLOW_SEND_SEND14_Pos (14UL)       /*!< Position of SEND14 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND14_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND14_Pos) /*!< Bit mask of SEND14 field.                */
  #define PPIB_OVERFLOW_SEND_SEND14_Min (0x0UL)      /*!< Min enumerator value of SEND14 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND14_Max (0x1UL)      /*!< Max enumerator value of SEND14 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND14_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND14_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND15 @Bit 15 : The status for tasks overflow at SUBSCRIBE_SEND[15]. */
  #define PPIB_OVERFLOW_SEND_SEND15_Pos (15UL)       /*!< Position of SEND15 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND15_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND15_Pos) /*!< Bit mask of SEND15 field.                */
  #define PPIB_OVERFLOW_SEND_SEND15_Min (0x0UL)      /*!< Min enumerator value of SEND15 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND15_Max (0x1UL)      /*!< Max enumerator value of SEND15 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND15_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND15_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND16 @Bit 16 : The status for tasks overflow at SUBSCRIBE_SEND[16]. */
  #define PPIB_OVERFLOW_SEND_SEND16_Pos (16UL)       /*!< Position of SEND16 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND16_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND16_Pos) /*!< Bit mask of SEND16 field.                */
  #define PPIB_OVERFLOW_SEND_SEND16_Min (0x0UL)      /*!< Min enumerator value of SEND16 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND16_Max (0x1UL)      /*!< Max enumerator value of SEND16 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND16_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND16_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND17 @Bit 17 : The status for tasks overflow at SUBSCRIBE_SEND[17]. */
  #define PPIB_OVERFLOW_SEND_SEND17_Pos (17UL)       /*!< Position of SEND17 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND17_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND17_Pos) /*!< Bit mask of SEND17 field.                */
  #define PPIB_OVERFLOW_SEND_SEND17_Min (0x0UL)      /*!< Min enumerator value of SEND17 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND17_Max (0x1UL)      /*!< Max enumerator value of SEND17 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND17_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND17_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND18 @Bit 18 : The status for tasks overflow at SUBSCRIBE_SEND[18]. */
  #define PPIB_OVERFLOW_SEND_SEND18_Pos (18UL)       /*!< Position of SEND18 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND18_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND18_Pos) /*!< Bit mask of SEND18 field.                */
  #define PPIB_OVERFLOW_SEND_SEND18_Min (0x0UL)      /*!< Min enumerator value of SEND18 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND18_Max (0x1UL)      /*!< Max enumerator value of SEND18 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND18_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND18_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND19 @Bit 19 : The status for tasks overflow at SUBSCRIBE_SEND[19]. */
  #define PPIB_OVERFLOW_SEND_SEND19_Pos (19UL)       /*!< Position of SEND19 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND19_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND19_Pos) /*!< Bit mask of SEND19 field.                */
  #define PPIB_OVERFLOW_SEND_SEND19_Min (0x0UL)      /*!< Min enumerator value of SEND19 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND19_Max (0x1UL)      /*!< Max enumerator value of SEND19 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND19_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND19_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND20 @Bit 20 : The status for tasks overflow at SUBSCRIBE_SEND[20]. */
  #define PPIB_OVERFLOW_SEND_SEND20_Pos (20UL)       /*!< Position of SEND20 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND20_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND20_Pos) /*!< Bit mask of SEND20 field.                */
  #define PPIB_OVERFLOW_SEND_SEND20_Min (0x0UL)      /*!< Min enumerator value of SEND20 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND20_Max (0x1UL)      /*!< Max enumerator value of SEND20 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND20_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND20_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND21 @Bit 21 : The status for tasks overflow at SUBSCRIBE_SEND[21]. */
  #define PPIB_OVERFLOW_SEND_SEND21_Pos (21UL)       /*!< Position of SEND21 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND21_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND21_Pos) /*!< Bit mask of SEND21 field.                */
  #define PPIB_OVERFLOW_SEND_SEND21_Min (0x0UL)      /*!< Min enumerator value of SEND21 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND21_Max (0x1UL)      /*!< Max enumerator value of SEND21 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND21_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND21_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND22 @Bit 22 : The status for tasks overflow at SUBSCRIBE_SEND[22]. */
  #define PPIB_OVERFLOW_SEND_SEND22_Pos (22UL)       /*!< Position of SEND22 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND22_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND22_Pos) /*!< Bit mask of SEND22 field.                */
  #define PPIB_OVERFLOW_SEND_SEND22_Min (0x0UL)      /*!< Min enumerator value of SEND22 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND22_Max (0x1UL)      /*!< Max enumerator value of SEND22 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND22_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND22_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND23 @Bit 23 : The status for tasks overflow at SUBSCRIBE_SEND[23]. */
  #define PPIB_OVERFLOW_SEND_SEND23_Pos (23UL)       /*!< Position of SEND23 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND23_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND23_Pos) /*!< Bit mask of SEND23 field.                */
  #define PPIB_OVERFLOW_SEND_SEND23_Min (0x0UL)      /*!< Min enumerator value of SEND23 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND23_Max (0x1UL)      /*!< Max enumerator value of SEND23 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND23_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND23_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND24 @Bit 24 : The status for tasks overflow at SUBSCRIBE_SEND[24]. */
  #define PPIB_OVERFLOW_SEND_SEND24_Pos (24UL)       /*!< Position of SEND24 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND24_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND24_Pos) /*!< Bit mask of SEND24 field.                */
  #define PPIB_OVERFLOW_SEND_SEND24_Min (0x0UL)      /*!< Min enumerator value of SEND24 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND24_Max (0x1UL)      /*!< Max enumerator value of SEND24 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND24_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND24_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND25 @Bit 25 : The status for tasks overflow at SUBSCRIBE_SEND[25]. */
  #define PPIB_OVERFLOW_SEND_SEND25_Pos (25UL)       /*!< Position of SEND25 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND25_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND25_Pos) /*!< Bit mask of SEND25 field.                */
  #define PPIB_OVERFLOW_SEND_SEND25_Min (0x0UL)      /*!< Min enumerator value of SEND25 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND25_Max (0x1UL)      /*!< Max enumerator value of SEND25 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND25_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND25_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND26 @Bit 26 : The status for tasks overflow at SUBSCRIBE_SEND[26]. */
  #define PPIB_OVERFLOW_SEND_SEND26_Pos (26UL)       /*!< Position of SEND26 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND26_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND26_Pos) /*!< Bit mask of SEND26 field.                */
  #define PPIB_OVERFLOW_SEND_SEND26_Min (0x0UL)      /*!< Min enumerator value of SEND26 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND26_Max (0x1UL)      /*!< Max enumerator value of SEND26 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND26_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND26_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND27 @Bit 27 : The status for tasks overflow at SUBSCRIBE_SEND[27]. */
  #define PPIB_OVERFLOW_SEND_SEND27_Pos (27UL)       /*!< Position of SEND27 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND27_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND27_Pos) /*!< Bit mask of SEND27 field.                */
  #define PPIB_OVERFLOW_SEND_SEND27_Min (0x0UL)      /*!< Min enumerator value of SEND27 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND27_Max (0x1UL)      /*!< Max enumerator value of SEND27 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND27_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND27_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND28 @Bit 28 : The status for tasks overflow at SUBSCRIBE_SEND[28]. */
  #define PPIB_OVERFLOW_SEND_SEND28_Pos (28UL)       /*!< Position of SEND28 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND28_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND28_Pos) /*!< Bit mask of SEND28 field.                */
  #define PPIB_OVERFLOW_SEND_SEND28_Min (0x0UL)      /*!< Min enumerator value of SEND28 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND28_Max (0x1UL)      /*!< Max enumerator value of SEND28 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND28_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND28_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND29 @Bit 29 : The status for tasks overflow at SUBSCRIBE_SEND[29]. */
  #define PPIB_OVERFLOW_SEND_SEND29_Pos (29UL)       /*!< Position of SEND29 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND29_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND29_Pos) /*!< Bit mask of SEND29 field.                */
  #define PPIB_OVERFLOW_SEND_SEND29_Min (0x0UL)      /*!< Min enumerator value of SEND29 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND29_Max (0x1UL)      /*!< Max enumerator value of SEND29 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND29_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND29_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND30 @Bit 30 : The status for tasks overflow at SUBSCRIBE_SEND[30]. */
  #define PPIB_OVERFLOW_SEND_SEND30_Pos (30UL)       /*!< Position of SEND30 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND30_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND30_Pos) /*!< Bit mask of SEND30 field.                */
  #define PPIB_OVERFLOW_SEND_SEND30_Min (0x0UL)      /*!< Min enumerator value of SEND30 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND30_Max (0x1UL)      /*!< Max enumerator value of SEND30 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND30_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND30_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */

/* SEND31 @Bit 31 : The status for tasks overflow at SUBSCRIBE_SEND[31]. */
  #define PPIB_OVERFLOW_SEND_SEND31_Pos (31UL)       /*!< Position of SEND31 field.                                            */
  #define PPIB_OVERFLOW_SEND_SEND31_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND31_Pos) /*!< Bit mask of SEND31 field.                */
  #define PPIB_OVERFLOW_SEND_SEND31_Min (0x0UL)      /*!< Min enumerator value of SEND31 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND31_Max (0x1UL)      /*!< Max enumerator value of SEND31 field.                                */
  #define PPIB_OVERFLOW_SEND_SEND31_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
  #define PPIB_OVERFLOW_SEND_SEND31_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */


/* ======================================================= Struct PPIB ======================================================= */
/**
  * @brief PPIB APB registers
  */
  typedef struct {                                   /*!< PPIB Structure                                                       */
    __OM uint32_t TASKS_SEND[32];                    /*!< (@ 0x00000000) This task is unused, but the PPIB provides the
                                                                         SUBSCRIBE task to connect SEND [n] task.*/
    __IOM uint32_t SUBSCRIBE_SEND[32];               /*!< (@ 0x00000080) Subscribe configuration for task SEND[n]              */
    __IOM uint32_t EVENTS_RECEIVE[32];               /*!< (@ 0x00000100) This event is unused, but the PPIB provides the PUBLISH
                                                                         event to connect RECEIVE [n] event.*/
    __IOM uint32_t PUBLISH_RECEIVE[32];              /*!< (@ 0x00000180) Publish configuration for event RECEIVE[n]            */
    __IM uint32_t RESERVED[128];
    __IOM NRF_PPIB_OVERFLOW_Type OVERFLOW;           /*!< (@ 0x00000400) (unspecified)                                         */
  } NRF_PPIB_Type;                                   /*!< Size = 1028 (0x404)                                                  */

/* PPIB_TASKS_SEND: This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */
  #define PPIB_TASKS_SEND_MaxCount (32UL)            /*!< Max size of TASKS_SEND[32] array.                                    */
  #define PPIB_TASKS_SEND_MaxIndex (31UL)            /*!< Max index of TASKS_SEND[32] array.                                   */
  #define PPIB_TASKS_SEND_MinIndex (0UL)             /*!< Min index of TASKS_SEND[32] array.                                   */
  #define PPIB_TASKS_SEND_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_SEND[32] register.                              */

/* TASKS_SEND @Bit 0 : This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */
  #define PPIB_TASKS_SEND_TASKS_SEND_Pos (0UL)       /*!< Position of TASKS_SEND field.                                        */
  #define PPIB_TASKS_SEND_TASKS_SEND_Msk (0x1UL << PPIB_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field.          */
  #define PPIB_TASKS_SEND_TASKS_SEND_Min (0x1UL)     /*!< Min enumerator value of TASKS_SEND field.                            */
  #define PPIB_TASKS_SEND_TASKS_SEND_Max (0x1UL)     /*!< Max enumerator value of TASKS_SEND field.                            */
  #define PPIB_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task                                                         */


/* PPIB_SUBSCRIBE_SEND: Subscribe configuration for task SEND[n] */
  #define PPIB_SUBSCRIBE_SEND_MaxCount (32UL)        /*!< Max size of SUBSCRIBE_SEND[32] array.                                */
  #define PPIB_SUBSCRIBE_SEND_MaxIndex (31UL)        /*!< Max index of SUBSCRIBE_SEND[32] array.                               */
  #define PPIB_SUBSCRIBE_SEND_MinIndex (0UL)         /*!< Min index of SUBSCRIBE_SEND[32] array.                               */
  #define PPIB_SUBSCRIBE_SEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SEND[32] register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task SEND[n] will subscribe to */
  #define PPIB_SUBSCRIBE_SEND_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define PPIB_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << PPIB_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define PPIB_SUBSCRIBE_SEND_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define PPIB_SUBSCRIBE_SEND_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PPIB_SUBSCRIBE_SEND_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define PPIB_SUBSCRIBE_SEND_EN_Msk (0x1UL << PPIB_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field.                          */
  #define PPIB_SUBSCRIBE_SEND_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define PPIB_SUBSCRIBE_SEND_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define PPIB_SUBSCRIBE_SEND_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define PPIB_SUBSCRIBE_SEND_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* PPIB_EVENTS_RECEIVE: This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */
  #define PPIB_EVENTS_RECEIVE_MaxCount (32UL)        /*!< Max size of EVENTS_RECEIVE[32] array.                                */
  #define PPIB_EVENTS_RECEIVE_MaxIndex (31UL)        /*!< Max index of EVENTS_RECEIVE[32] array.                               */
  #define PPIB_EVENTS_RECEIVE_MinIndex (0UL)         /*!< Min index of EVENTS_RECEIVE[32] array.                               */
  #define PPIB_EVENTS_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RECEIVE[32] register.                       */

/* EVENTS_RECEIVE @Bit 0 : This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */
  #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field.                                  */
  #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of
                                                                            EVENTS_RECEIVE field.*/
  #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RECEIVE field.                    */
  #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RECEIVE field.                    */
  #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated                                            */


/* PPIB_PUBLISH_RECEIVE: Publish configuration for event RECEIVE[n] */
  #define PPIB_PUBLISH_RECEIVE_MaxCount (32UL)       /*!< Max size of PUBLISH_RECEIVE[32] array.                               */
  #define PPIB_PUBLISH_RECEIVE_MaxIndex (31UL)       /*!< Max index of PUBLISH_RECEIVE[32] array.                              */
  #define PPIB_PUBLISH_RECEIVE_MinIndex (0UL)        /*!< Min index of PUBLISH_RECEIVE[32] array.                              */
  #define PPIB_PUBLISH_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RECEIVE[32] register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event RECEIVE[n] will publish to */
  #define PPIB_PUBLISH_RECEIVE_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define PPIB_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << PPIB_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define PPIB_PUBLISH_RECEIVE_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define PPIB_PUBLISH_RECEIVE_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PPIB_PUBLISH_RECEIVE_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define PPIB_PUBLISH_RECEIVE_EN_Msk (0x1UL << PPIB_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field.                        */
  #define PPIB_PUBLISH_RECEIVE_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define PPIB_PUBLISH_RECEIVE_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define PPIB_PUBLISH_RECEIVE_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define PPIB_PUBLISH_RECEIVE_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            PWM                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct PWM_TASKS_DMA_SEQ ================================================= */
/**
  * @brief SEQ [PWM_TASKS_DMA_SEQ] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  START;                             /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See
                                                                         peripheral description for operation using easyDMA.*/
  __OM  uint32_t  STOP;                              /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an
                                                                         END event.*/
} NRF_PWM_TASKS_DMA_SEQ_Type;                        /*!< Size = 8 (0x008)                                                     */
  #define PWM_TASKS_DMA_SEQ_MaxCount (2UL)           /*!< Size of SEQ[2] array.                                                */
  #define PWM_TASKS_DMA_SEQ_MaxIndex (1UL)           /*!< Max index of SEQ[2] array.                                           */
  #define PWM_TASKS_DMA_SEQ_MinIndex (0UL)           /*!< Min index of SEQ[2] array.                                           */

/* PWM_TASKS_DMA_SEQ_START: Starts operation using easyDMA to load the values. See peripheral description for operation using
                             easyDMA. */

  #define PWM_TASKS_DMA_SEQ_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                                */

/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */
  #define PWM_TASKS_DMA_SEQ_START_START_Pos (0UL)    /*!< Position of START field.                                             */
  #define PWM_TASKS_DMA_SEQ_START_START_Msk (0x1UL << PWM_TASKS_DMA_SEQ_START_START_Pos) /*!< Bit mask of START field.         */
  #define PWM_TASKS_DMA_SEQ_START_START_Min (0x1UL)  /*!< Min enumerator value of START field.                                 */
  #define PWM_TASKS_DMA_SEQ_START_START_Max (0x1UL)  /*!< Max enumerator value of START field.                                 */
  #define PWM_TASKS_DMA_SEQ_START_START_Trigger (0x1UL) /*!< Trigger task                                                      */


/* PWM_TASKS_DMA_SEQ_STOP: Stops operation using easyDMA. This does not trigger an END event. */
  #define PWM_TASKS_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                                  */

/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */
  #define PWM_TASKS_DMA_SEQ_STOP_STOP_Pos (0UL)      /*!< Position of STOP field.                                              */
  #define PWM_TASKS_DMA_SEQ_STOP_STOP_Msk (0x1UL << PWM_TASKS_DMA_SEQ_STOP_STOP_Pos) /*!< Bit mask of STOP field.              */
  #define PWM_TASKS_DMA_SEQ_STOP_STOP_Min (0x1UL)    /*!< Min enumerator value of STOP field.                                  */
  #define PWM_TASKS_DMA_SEQ_STOP_STOP_Max (0x1UL)    /*!< Max enumerator value of STOP field.                                  */
  #define PWM_TASKS_DMA_SEQ_STOP_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */



/* ================================================== Struct PWM_TASKS_DMA =================================================== */
/**
  * @brief TASKS_DMA [PWM_TASKS_DMA] Peripheral tasks.
  */
typedef struct {
  __OM  NRF_PWM_TASKS_DMA_SEQ_Type SEQ[2];           /*!< (@ 0x00000000) Peripheral tasks.                                     */
} NRF_PWM_TASKS_DMA_Type;                            /*!< Size = 16 (0x010)                                                    */


/* ============================================== Struct PWM_SUBSCRIBE_DMA_SEQ =============================================== */
/**
  * @brief SEQ [PWM_SUBSCRIBE_DMA_SEQ] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  START;                             /*!< (@ 0x00000000) Subscribe configuration for task START                */
  __IOM uint32_t  STOP;                              /*!< (@ 0x00000004) Subscribe configuration for task STOP                 */
} NRF_PWM_SUBSCRIBE_DMA_SEQ_Type;                    /*!< Size = 8 (0x008)                                                     */
  #define PWM_SUBSCRIBE_DMA_SEQ_MaxCount (2UL)       /*!< Size of SEQ[2] array.                                                */
  #define PWM_SUBSCRIBE_DMA_SEQ_MaxIndex (1UL)       /*!< Max index of SEQ[2] array.                                           */
  #define PWM_SUBSCRIBE_DMA_SEQ_MinIndex (0UL)       /*!< Min index of SEQ[2] array.                                           */

/* PWM_SUBSCRIBE_DMA_SEQ_START: Subscribe configuration for task START */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
  #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                        */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */

/* EN @Bit 31 : (unspecified) */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Pos (31UL)  /*!< Position of EN field.                                                */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_START_EN_Pos) /*!< Bit mask of EN field.          */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Disabled (0x0UL) /*!< Disable subscription                                            */
  #define PWM_SUBSCRIBE_DMA_SEQ_START_EN_Enabled (0x1UL) /*!< Enable subscription                                              */


/* PWM_SUBSCRIBE_DMA_SEQ_STOP: Subscribe configuration for task STOP */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Pos) /*!< Bit mask of EN field.            */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Disabled (0x0UL) /*!< Disable subscription                                             */
  #define PWM_SUBSCRIBE_DMA_SEQ_STOP_EN_Enabled (0x1UL) /*!< Enable subscription                                               */



/* ================================================ Struct PWM_SUBSCRIBE_DMA ================================================= */
/**
  * @brief SUBSCRIBE_DMA [PWM_SUBSCRIBE_DMA] Subscribe configuration for tasks
  */
typedef struct {
  __IOM NRF_PWM_SUBSCRIBE_DMA_SEQ_Type SEQ[2];       /*!< (@ 0x00000000) Subscribe configuration for tasks                     */
} NRF_PWM_SUBSCRIBE_DMA_Type;                        /*!< Size = 16 (0x010)                                                    */


/* ================================================ Struct PWM_EVENTS_DMA_SEQ ================================================ */
/**
  * @brief SEQ [PWM_EVENTS_DMA_SEQ] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
} NRF_PWM_EVENTS_DMA_SEQ_Type;                       /*!< Size = 12 (0x00C)                                                    */
  #define PWM_EVENTS_DMA_SEQ_MaxCount (2UL)          /*!< Size of SEQ[2] array.                                                */
  #define PWM_EVENTS_DMA_SEQ_MaxIndex (1UL)          /*!< Max index of SEQ[2] array.                                           */
  #define PWM_EVENTS_DMA_SEQ_MinIndex (0UL)          /*!< Min index of SEQ[2] array.                                           */

/* PWM_EVENTS_DMA_SEQ_END: Generated after all MAXCNT bytes have been transferred */
  #define PWM_EVENTS_DMA_SEQ_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define PWM_EVENTS_DMA_SEQ_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define PWM_EVENTS_DMA_SEQ_END_END_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_END_END_Pos) /*!< Bit mask of END field.                 */
  #define PWM_EVENTS_DMA_SEQ_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define PWM_EVENTS_DMA_SEQ_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define PWM_EVENTS_DMA_SEQ_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define PWM_EVENTS_DMA_SEQ_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* PWM_EVENTS_DMA_SEQ_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define PWM_EVENTS_DMA_SEQ_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define PWM_EVENTS_DMA_SEQ_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define PWM_EVENTS_DMA_SEQ_READY_READY_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define PWM_EVENTS_DMA_SEQ_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define PWM_EVENTS_DMA_SEQ_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define PWM_EVENTS_DMA_SEQ_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define PWM_EVENTS_DMA_SEQ_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* PWM_EVENTS_DMA_SEQ_BUSERROR: An error occured during the bus transfer. */
  #define PWM_EVENTS_DMA_SEQ_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Msk (0x1UL << PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define PWM_EVENTS_DMA_SEQ_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */



/* ================================================== Struct PWM_EVENTS_DMA ================================================== */
/**
  * @brief EVENTS_DMA [PWM_EVENTS_DMA] Peripheral events.
  */
typedef struct {
  __IOM NRF_PWM_EVENTS_DMA_SEQ_Type SEQ[2];          /*!< (@ 0x00000000) Peripheral events.                                    */
} NRF_PWM_EVENTS_DMA_Type;                           /*!< Size = 24 (0x018)                                                    */


/* =============================================== Struct PWM_PUBLISH_DMA_SEQ ================================================ */
/**
  * @brief SEQ [PWM_PUBLISH_DMA_SEQ] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
} NRF_PWM_PUBLISH_DMA_SEQ_Type;                      /*!< Size = 12 (0x00C)                                                    */
  #define PWM_PUBLISH_DMA_SEQ_MaxCount (2UL)         /*!< Size of SEQ[2] array.                                                */
  #define PWM_PUBLISH_DMA_SEQ_MaxIndex (1UL)         /*!< Max index of SEQ[2] array.                                           */
  #define PWM_PUBLISH_DMA_SEQ_MinIndex (0UL)         /*!< Min index of SEQ[2] array.                                           */

/* PWM_PUBLISH_DMA_SEQ_END: Publish configuration for event END */
  #define PWM_PUBLISH_DMA_SEQ_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define PWM_PUBLISH_DMA_SEQ_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_DMA_SEQ_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_DMA_SEQ_END_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define PWM_PUBLISH_DMA_SEQ_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_DMA_SEQ_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_DMA_SEQ_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define PWM_PUBLISH_DMA_SEQ_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* PWM_PUBLISH_DMA_SEQ_READY: Publish configuration for event READY */
  #define PWM_PUBLISH_DMA_SEQ_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define PWM_PUBLISH_DMA_SEQ_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_DMA_SEQ_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_DMA_SEQ_READY_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define PWM_PUBLISH_DMA_SEQ_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_DMA_SEQ_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_DMA_SEQ_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define PWM_PUBLISH_DMA_SEQ_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* PWM_PUBLISH_DMA_SEQ_BUSERROR: Publish configuration for event BUSERROR */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Msk (0xFFUL << PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Msk (0x1UL << PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define PWM_PUBLISH_DMA_SEQ_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */



/* ================================================= Struct PWM_PUBLISH_DMA ================================================== */
/**
  * @brief PUBLISH_DMA [PWM_PUBLISH_DMA] Publish configuration for events
  */
typedef struct {
  __IOM NRF_PWM_PUBLISH_DMA_SEQ_Type SEQ[2];         /*!< (@ 0x00000000) Publish configuration for events                      */
} NRF_PWM_PUBLISH_DMA_Type;                          /*!< Size = 24 (0x018)                                                    */


/* ===================================================== Struct PWM_SEQ ====================================================== */
/**
  * @brief SEQ [PWM_SEQ] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  REFRESH;                           /*!< (@ 0x00000008) Number of additional PWM periods between samples loaded
                                                                         into compare register*/
  __IOM uint32_t  ENDDELAY;                          /*!< (@ 0x0000000C) Time added after the sequence                         */
  __IM  uint32_t  RESERVED1[4];
} NRF_PWM_SEQ_Type;                                  /*!< Size = 32 (0x020)                                                    */
  #define PWM_SEQ_MaxCount (2UL)                     /*!< Size of SEQ[2] array.                                                */
  #define PWM_SEQ_MaxIndex (1UL)                     /*!< Max index of SEQ[2] array.                                           */
  #define PWM_SEQ_MinIndex (0UL)                     /*!< Min index of SEQ[2] array.                                           */

/* PWM_SEQ_REFRESH: Number of additional PWM periods between samples loaded into compare register */
  #define PWM_SEQ_REFRESH_ResetValue (0x00000001UL)  /*!< Reset value of REFRESH register.                                     */

/* CNT @Bits 0..23 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM
                     periods) */

  #define PWM_SEQ_REFRESH_CNT_Pos (0UL)              /*!< Position of CNT field.                                               */
  #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field.                          */
  #define PWM_SEQ_REFRESH_CNT_Min (0x0UL)            /*!< Min enumerator value of CNT field.                                   */
  #define PWM_SEQ_REFRESH_CNT_Max (0x0UL)            /*!< Max enumerator value of CNT field.                                   */
  #define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period                                             */


/* PWM_SEQ_ENDDELAY: Time added after the sequence */
  #define PWM_SEQ_ENDDELAY_ResetValue (0x00000000UL) /*!< Reset value of ENDDELAY register.                                    */

/* CNT @Bits 0..23 : Time added after the sequence in PWM periods */
  #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL)             /*!< Position of CNT field.                                               */
  #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field.                        */



/* ===================================================== Struct PWM_PSEL ===================================================== */
/**
  * @brief PSEL [PWM_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  OUT[4];                            /*!< (@ 0x00000000) Output pin select for PWM channel n                   */
} NRF_PWM_PSEL_Type;                                 /*!< Size = 16 (0x010)                                                    */

/* PWM_PSEL_OUT: Output pin select for PWM channel n */
  #define PWM_PSEL_OUT_MaxCount (4UL)                /*!< Max size of OUT[4] array.                                            */
  #define PWM_PSEL_OUT_MaxIndex (3UL)                /*!< Max index of OUT[4] array.                                           */
  #define PWM_PSEL_OUT_MinIndex (0UL)                /*!< Min index of OUT[4] array.                                           */
  #define PWM_PSEL_OUT_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of OUT[4] register.                                      */

/* PIN @Bits 0..4 : Pin number */
  #define PWM_PSEL_OUT_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
  #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field.                                    */
  #define PWM_PSEL_OUT_PIN_Min (0x00UL)              /*!< Min value of PIN field.                                              */
  #define PWM_PSEL_OUT_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define PWM_PSEL_OUT_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
  #define PWM_PSEL_OUT_PORT_Msk (0x7UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field.                                  */
  #define PWM_PSEL_OUT_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
  #define PWM_PSEL_OUT_PORT_Max (0x7UL)              /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define PWM_PSEL_OUT_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
  #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
  #define PWM_PSEL_OUT_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
  #define PWM_PSEL_OUT_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
  #define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
  #define PWM_PSEL_OUT_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */



/* =================================================== Struct PWM_DMA_SEQ ==================================================== */
/**
  * @brief SEQ [PWM_DMA_SEQ] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event.*/
  __IM  uint32_t  CURRENTAMOUNT;                     /*!< (@ 0x00000010) Number of bytes transferred in the current transaction*/
  __IM  uint32_t  RESERVED1[2];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_PWM_DMA_SEQ_Type;                              /*!< Size = 36 (0x024)                                                    */
  #define PWM_DMA_SEQ_MaxCount (2UL)                 /*!< Size of SEQ[2] array.                                                */
  #define PWM_DMA_SEQ_MaxIndex (1UL)                 /*!< Max index of SEQ[2] array.                                           */
  #define PWM_DMA_SEQ_MinIndex (0UL)                 /*!< Min index of SEQ[2] array.                                           */

/* PWM_DMA_SEQ_PTR: RAM buffer start address */
  #define PWM_DMA_SEQ_PTR_ResetValue (0x00000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define PWM_DMA_SEQ_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define PWM_DMA_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_DMA_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* PWM_DMA_SEQ_MAXCNT: Maximum number of bytes in channel buffer */
  #define PWM_DMA_SEQ_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..14 : Maximum number of bytes in channel buffer */
  #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Msk (0x7FFFUL << PWM_DMA_SEQ_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define PWM_DMA_SEQ_MAXCNT_MAXCNT_Max (0x7FFFUL)   /*!< Max size of MAXCNT field.                                            */


/* PWM_DMA_SEQ_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. */
  #define PWM_DMA_SEQ_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Msk (0x7FFFUL << PWM_DMA_SEQ_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define PWM_DMA_SEQ_AMOUNT_AMOUNT_Max (0x7FFFUL)   /*!< Max size of AMOUNT field.                                            */


/* PWM_DMA_SEQ_CURRENTAMOUNT: Number of bytes transferred in the current transaction */
  #define PWM_DMA_SEQ_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register.                      */

/* AMOUNT @Bits 0..14 : Number of bytes transferred in the current transaction. Continuously updated. */
  #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field.                                            */
  #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT
                                                                            field.*/
  #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Min (0x0001UL) /*!< Min value of AMOUNT field.                                      */
  #define PWM_DMA_SEQ_CURRENTAMOUNT_AMOUNT_Max (0x7FFFUL) /*!< Max size of AMOUNT field.                                       */


/* PWM_DMA_SEQ_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define PWM_DMA_SEQ_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* PWM_DMA_SEQ_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define PWM_DMA_SEQ_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << PWM_DMA_SEQ_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* ===================================================== Struct PWM_DMA ====================================================== */
/**
  * @brief DMA [PWM_DMA] (unspecified)
  */
typedef struct {
  __IOM NRF_PWM_DMA_SEQ_Type SEQ[2];                 /*!< (@ 0x00000000) (unspecified)                                         */
} NRF_PWM_DMA_Type;                                  /*!< Size = 72 (0x048)                                                    */

/* ======================================================= Struct PWM ======================================================== */
/**
  * @brief Pulse width modulation unit
  */
  typedef struct {                                   /*!< PWM Structure                                                        */
    __IM uint32_t RESERVED;
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at the end
                                                                         of current PWM period, and stops sequence playback*/
    __OM uint32_t TASKS_NEXTSTEP;                    /*!< (@ 0x00000008) Steps by one value in the current sequence on all
                                                                         enabled channels if DECODER.MODE=NextStep. Does not
                                                                         cause PWM generation to start if not running.*/
    __IM uint32_t RESERVED1;
    __OM NRF_PWM_TASKS_DMA_Type TASKS_DMA;           /*!< (@ 0x00000010) Peripheral tasks.                                     */
    __IM uint32_t RESERVED2[25];
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_NEXTSTEP;               /*!< (@ 0x00000088) Subscribe configuration for task NEXTSTEP             */
    __IM uint32_t RESERVED3;
    __IOM NRF_PWM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA;  /*!< (@ 0x00000090) Subscribe configuration for tasks                     */
    __IM uint32_t RESERVED4[25];
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no
                                                                         longer generated*/
    __IOM uint32_t EVENTS_SEQSTARTED[2];             /*!< (@ 0x00000108) First PWM period started on sequence n                */
    __IOM uint32_t EVENTS_SEQEND[2];                 /*!< (@ 0x00000110) Emitted at end of every sequence n, when last value
                                                                         from RAM has been applied to wave counter*/
    __IOM uint32_t EVENTS_PWMPERIODEND;              /*!< (@ 0x00000118) Emitted at the end of each PWM period                 */
    __IOM uint32_t EVENTS_LOOPSDONE;                 /*!< (@ 0x0000011C) Concatenated sequences have been played the amount of
                                                                         times defined in LOOP.CNT*/
    __IOM uint32_t EVENTS_RAMUNDERFLOW;              /*!< (@ 0x00000120) Emitted when retrieving from RAM does not complete in
                                                                         time for the PWM module*/
    __IOM NRF_PWM_EVENTS_DMA_Type EVENTS_DMA;        /*!< (@ 0x00000124) Peripheral events.                                    */
    __IOM uint32_t EVENTS_COMPAREMATCH[4];           /*!< (@ 0x0000013C) This event is generated when the compare matches for
                                                                         the compare channel [n].*/
    __IM uint32_t RESERVED5[14];
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
    __IOM uint32_t PUBLISH_SEQSTARTED[2];            /*!< (@ 0x00000188) Publish configuration for event SEQSTARTED[n]         */
    __IOM uint32_t PUBLISH_SEQEND[2];                /*!< (@ 0x00000190) Publish configuration for event SEQEND[n]             */
    __IOM uint32_t PUBLISH_PWMPERIODEND;             /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND          */
    __IOM uint32_t PUBLISH_LOOPSDONE;                /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE             */
    __IOM uint32_t PUBLISH_RAMUNDERFLOW;             /*!< (@ 0x000001A0) Publish configuration for event RAMUNDERFLOW          */
    __IOM NRF_PWM_PUBLISH_DMA_Type PUBLISH_DMA;      /*!< (@ 0x000001A4) Publish configuration for events                      */
    __IOM uint32_t PUBLISH_COMPAREMATCH[4];          /*!< (@ 0x000001BC) Publish configuration for event COMPAREMATCH[n]       */
    __IM uint32_t RESERVED6[13];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED7[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED8[124];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) PWM module enable register                            */
    __IOM uint32_t MODE;                             /*!< (@ 0x00000504) Selects operating mode of the wave counter            */
    __IOM uint32_t COUNTERTOP;                       /*!< (@ 0x00000508) Value up to which the pulse generator counter counts  */
    __IOM uint32_t PRESCALER;                        /*!< (@ 0x0000050C) Configuration for PWM_CLK                             */
    __IOM uint32_t DECODER;                          /*!< (@ 0x00000510) Configuration of the decoder                          */
    __IOM uint32_t LOOP;                             /*!< (@ 0x00000514) Number of playbacks of a loop                         */
    __IOM uint32_t IDLEOUT;                          /*!< (@ 0x00000518) Configure the output value on the PWM channel during
                                                                         idle*/
    __IM uint32_t RESERVED9;
    __IOM NRF_PWM_SEQ_Type SEQ[2];                   /*!< (@ 0x00000520) (unspecified)                                         */
    __IOM NRF_PWM_PSEL_Type PSEL;                    /*!< (@ 0x00000560) (unspecified)                                         */
    __IM uint32_t RESERVED10[100];
    __IOM NRF_PWM_DMA_Type DMA;                      /*!< (@ 0x00000700) (unspecified)                                         */
  } NRF_PWM_Type;                                    /*!< Size = 1864 (0x748)                                                  */

/* PWM_TASKS_STOP: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
  #define PWM_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
                       */

  #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
  #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
  #define PWM_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
  #define PWM_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
  #define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* PWM_TASKS_NEXTSTEP: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not
                        cause PWM generation to start if not running. */

  #define PWM_TASKS_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_NEXTSTEP register.                            */

/* TASKS_NEXTSTEP @Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not
                           cause PWM generation to start if not running. */

  #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field.                                   */
  #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP
                                                                            field.*/
  #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Min (0x1UL) /*!< Min enumerator value of TASKS_NEXTSTEP field.                     */
  #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Max (0x1UL) /*!< Max enumerator value of TASKS_NEXTSTEP field.                     */
  #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task                                                  */


/* PWM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define PWM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define PWM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define PWM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
  #define PWM_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
  #define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */


/* PWM_SUBSCRIBE_NEXTSTEP: Subscribe configuration for task NEXTSTEP */
  #define PWM_SUBSCRIBE_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_NEXTSTEP register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task NEXTSTEP will subscribe to */
  #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field.                    */
  #define PWM_SUBSCRIBE_NEXTSTEP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_NEXTSTEP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* PWM_EVENTS_STOPPED: Response to STOP task, emitted when PWM pulses are no longer generated */
  #define PWM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */

/* EVENTS_STOPPED @Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
  #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
  #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
                                                                            field.*/
  #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
  #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
  #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */


/* PWM_EVENTS_SEQSTARTED: First PWM period started on sequence n */
  #define PWM_EVENTS_SEQSTARTED_MaxCount (2UL)       /*!< Max size of EVENTS_SEQSTARTED[2] array.                              */
  #define PWM_EVENTS_SEQSTARTED_MaxIndex (1UL)       /*!< Max index of EVENTS_SEQSTARTED[2] array.                             */
  #define PWM_EVENTS_SEQSTARTED_MinIndex (0UL)       /*!< Min index of EVENTS_SEQSTARTED[2] array.                             */
  #define PWM_EVENTS_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQSTARTED[2] register.                   */

/* EVENTS_SEQSTARTED @Bit 0 : First PWM period started on sequence n */
  #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field.                          */
  #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of
                                                                            EVENTS_SEQSTARTED field.*/
  #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQSTARTED field.            */
  #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQSTARTED field.            */
  #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated                                       */


/* PWM_EVENTS_SEQEND: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
  #define PWM_EVENTS_SEQEND_MaxCount (2UL)           /*!< Max size of EVENTS_SEQEND[2] array.                                  */
  #define PWM_EVENTS_SEQEND_MaxIndex (1UL)           /*!< Max index of EVENTS_SEQEND[2] array.                                 */
  #define PWM_EVENTS_SEQEND_MinIndex (0UL)           /*!< Min index of EVENTS_SEQEND[2] array.                                 */
  #define PWM_EVENTS_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQEND[2] register.                           */

/* EVENTS_SEQEND @Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
  #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL)  /*!< Position of EVENTS_SEQEND field.                                     */
  #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND
                                                                            field.*/
  #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQEND field.                        */
  #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQEND field.                        */
  #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated                                               */


/* PWM_EVENTS_PWMPERIODEND: Emitted at the end of each PWM period */
  #define PWM_EVENTS_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMPERIODEND register.                  */

/* EVENTS_PWMPERIODEND @Bit 0 : Emitted at the end of each PWM period */
  #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field.                    */
  #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit
                                                                            mask of EVENTS_PWMPERIODEND field.*/
  #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMPERIODEND field.      */
  #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMPERIODEND field.      */
  #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated                            */
  #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated                                   */


/* PWM_EVENTS_LOOPSDONE: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
  #define PWM_EVENTS_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LOOPSDONE register.                        */

/* EVENTS_LOOPSDONE @Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
  #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field.                             */
  #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of
                                                                            EVENTS_LOOPSDONE field.*/
  #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_LOOPSDONE field.               */
  #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_LOOPSDONE field.               */
  #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated                                         */


/* PWM_EVENTS_RAMUNDERFLOW: Emitted when retrieving from RAM does not complete in time for the PWM module */
  #define PWM_EVENTS_RAMUNDERFLOW_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RAMUNDERFLOW register.                  */

/* EVENTS_RAMUNDERFLOW @Bit 0 : Emitted when retrieving from RAM does not complete in time for the PWM module */
  #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Pos (0UL) /*!< Position of EVENTS_RAMUNDERFLOW field.                    */
  #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Msk (0x1UL << PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Pos) /*!< Bit
                                                                            mask of EVENTS_RAMUNDERFLOW field.*/
  #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of EVENTS_RAMUNDERFLOW field.      */
  #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of EVENTS_RAMUNDERFLOW field.      */
  #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_NotGenerated (0x0UL) /*!< Event not generated                            */
  #define PWM_EVENTS_RAMUNDERFLOW_EVENTS_RAMUNDERFLOW_Generated (0x1UL) /*!< Event generated                                   */


/* PWM_EVENTS_COMPAREMATCH: This event is generated when the compare matches for the compare channel [n]. */
  #define PWM_EVENTS_COMPAREMATCH_MaxCount (4UL)     /*!< Max size of EVENTS_COMPAREMATCH[4] array.                            */
  #define PWM_EVENTS_COMPAREMATCH_MaxIndex (3UL)     /*!< Max index of EVENTS_COMPAREMATCH[4] array.                           */
  #define PWM_EVENTS_COMPAREMATCH_MinIndex (0UL)     /*!< Min index of EVENTS_COMPAREMATCH[4] array.                           */
  #define PWM_EVENTS_COMPAREMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPAREMATCH[4] register.               */

/* EVENTS_COMPAREMATCH @Bit 0 : This event is generated when the compare matches for the compare channel [n]. */
  #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Pos (0UL) /*!< Position of EVENTS_COMPAREMATCH field.                    */
  #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Msk (0x1UL << PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Pos) /*!< Bit
                                                                            mask of EVENTS_COMPAREMATCH field.*/
  #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPAREMATCH field.      */
  #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPAREMATCH field.      */
  #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_NotGenerated (0x0UL) /*!< Event not generated                            */
  #define PWM_EVENTS_COMPAREMATCH_EVENTS_COMPAREMATCH_Generated (0x1UL) /*!< Event generated                                   */


/* PWM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define PWM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define PWM_PUBLISH_STOPPED_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define PWM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
  #define PWM_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* PWM_PUBLISH_SEQSTARTED: Publish configuration for event SEQSTARTED[n] */
  #define PWM_PUBLISH_SEQSTARTED_MaxCount (2UL)      /*!< Max size of PUBLISH_SEQSTARTED[2] array.                             */
  #define PWM_PUBLISH_SEQSTARTED_MaxIndex (1UL)      /*!< Max index of PUBLISH_SEQSTARTED[2] array.                            */
  #define PWM_PUBLISH_SEQSTARTED_MinIndex (0UL)      /*!< Min index of PUBLISH_SEQSTARTED[2] array.                            */
  #define PWM_PUBLISH_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQSTARTED[2] register.                 */

/* CHIDX @Bits 0..7 : DPPI channel that event SEQSTARTED[n] will publish to */
  #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define PWM_PUBLISH_SEQSTARTED_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define PWM_PUBLISH_SEQSTARTED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field.                    */
  #define PWM_PUBLISH_SEQSTARTED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_SEQSTARTED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* PWM_PUBLISH_SEQEND: Publish configuration for event SEQEND[n] */
  #define PWM_PUBLISH_SEQEND_MaxCount (2UL)          /*!< Max size of PUBLISH_SEQEND[2] array.                                 */
  #define PWM_PUBLISH_SEQEND_MaxIndex (1UL)          /*!< Max index of PUBLISH_SEQEND[2] array.                                */
  #define PWM_PUBLISH_SEQEND_MinIndex (0UL)          /*!< Min index of PUBLISH_SEQEND[2] array.                                */
  #define PWM_PUBLISH_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQEND[2] register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event SEQEND[n] will publish to */
  #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define PWM_PUBLISH_SEQEND_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define PWM_PUBLISH_SEQEND_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_SEQEND_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field.                            */
  #define PWM_PUBLISH_SEQEND_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_SEQEND_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* PWM_PUBLISH_PWMPERIODEND: Publish configuration for event PWMPERIODEND */
  #define PWM_PUBLISH_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PWMPERIODEND register.                */

/* CHIDX @Bits 0..7 : DPPI channel that event PWMPERIODEND will publish to */
  #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field.                */
  #define PWM_PUBLISH_PWMPERIODEND_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_PWMPERIODEND_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* PWM_PUBLISH_LOOPSDONE: Publish configuration for event LOOPSDONE */
  #define PWM_PUBLISH_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LOOPSDONE register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that event LOOPSDONE will publish to */
  #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define PWM_PUBLISH_LOOPSDONE_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define PWM_PUBLISH_LOOPSDONE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field.                      */
  #define PWM_PUBLISH_LOOPSDONE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_LOOPSDONE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* PWM_PUBLISH_RAMUNDERFLOW: Publish configuration for event RAMUNDERFLOW */
  #define PWM_PUBLISH_RAMUNDERFLOW_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RAMUNDERFLOW register.                */

/* CHIDX @Bits 0..7 : DPPI channel that event RAMUNDERFLOW will publish to */
  #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Msk (0xFFUL << PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define PWM_PUBLISH_RAMUNDERFLOW_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_RAMUNDERFLOW_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_RAMUNDERFLOW_EN_Msk (0x1UL << PWM_PUBLISH_RAMUNDERFLOW_EN_Pos) /*!< Bit mask of EN field.                */
  #define PWM_PUBLISH_RAMUNDERFLOW_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_RAMUNDERFLOW_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_RAMUNDERFLOW_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define PWM_PUBLISH_RAMUNDERFLOW_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* PWM_PUBLISH_COMPAREMATCH: Publish configuration for event COMPAREMATCH[n] */
  #define PWM_PUBLISH_COMPAREMATCH_MaxCount (4UL)    /*!< Max size of PUBLISH_COMPAREMATCH[4] array.                           */
  #define PWM_PUBLISH_COMPAREMATCH_MaxIndex (3UL)    /*!< Max index of PUBLISH_COMPAREMATCH[4] array.                          */
  #define PWM_PUBLISH_COMPAREMATCH_MinIndex (0UL)    /*!< Min index of PUBLISH_COMPAREMATCH[4] array.                          */
  #define PWM_PUBLISH_COMPAREMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPAREMATCH[4] register.             */

/* CHIDX @Bits 0..7 : DPPI channel that event COMPAREMATCH[n] will publish to */
  #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Msk (0xFFUL << PWM_PUBLISH_COMPAREMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define PWM_PUBLISH_COMPAREMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define PWM_PUBLISH_COMPAREMATCH_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define PWM_PUBLISH_COMPAREMATCH_EN_Msk (0x1UL << PWM_PUBLISH_COMPAREMATCH_EN_Pos) /*!< Bit mask of EN field.                */
  #define PWM_PUBLISH_COMPAREMATCH_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define PWM_PUBLISH_COMPAREMATCH_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define PWM_PUBLISH_COMPAREMATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define PWM_PUBLISH_COMPAREMATCH_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* PWM_SHORTS: Shortcuts between local events and tasks */
  #define PWM_SHORTS_ResetValue (0x00000000UL)       /*!< Reset value of SHORTS register.                                      */

/* SEQEND0_STOP @Bit 0 : Shortcut between event SEQEND[n] and task STOP */
  #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL)          /*!< Position of SEQEND0_STOP field.                                      */
  #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field.              */
  #define PWM_SHORTS_SEQEND0_STOP_Min (0x0UL)        /*!< Min enumerator value of SEQEND0_STOP field.                          */
  #define PWM_SHORTS_SEQEND0_STOP_Max (0x1UL)        /*!< Max enumerator value of SEQEND0_STOP field.                          */
  #define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
  #define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */

/* SEQEND1_STOP @Bit 1 : Shortcut between event SEQEND[n] and task STOP */
  #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL)          /*!< Position of SEQEND1_STOP field.                                      */
  #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field.              */
  #define PWM_SHORTS_SEQEND1_STOP_Min (0x0UL)        /*!< Min enumerator value of SEQEND1_STOP field.                          */
  #define PWM_SHORTS_SEQEND1_STOP_Max (0x1UL)        /*!< Max enumerator value of SEQEND1_STOP field.                          */
  #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
  #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */

/* LOOPSDONE_DMA_SEQ0_START @Bit 2 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos (2UL) /*!< Position of LOOPSDONE_DMA_SEQ0_START field.                       */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Pos) /*!< Bit mask of
                                                                            LOOPSDONE_DMA_SEQ0_START field.*/
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ0_START field.         */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ0_START field.         */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Disabled (0x0UL) /*!< Disable shortcut                                           */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Enabled (0x1UL) /*!< Enable shortcut                                             */

/* LOOPSDONE_DMA_SEQ1_START @Bit 3 : Shortcut between event LOOPSDONE and task DMA.SEQ[n].START */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos (3UL) /*!< Position of LOOPSDONE_DMA_SEQ1_START field.                       */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Pos) /*!< Bit mask of
                                                                            LOOPSDONE_DMA_SEQ1_START field.*/
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_DMA_SEQ1_START field.         */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_DMA_SEQ1_START field.         */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Disabled (0x0UL) /*!< Disable shortcut                                           */
  #define PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Enabled (0x1UL) /*!< Enable shortcut                                             */

/* LOOPSDONE_STOP @Bit 4 : Shortcut between event LOOPSDONE and task STOP */
  #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL)        /*!< Position of LOOPSDONE_STOP field.                                    */
  #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field.        */
  #define PWM_SHORTS_LOOPSDONE_STOP_Min (0x0UL)      /*!< Min enumerator value of LOOPSDONE_STOP field.                        */
  #define PWM_SHORTS_LOOPSDONE_STOP_Max (0x1UL)      /*!< Max enumerator value of LOOPSDONE_STOP field.                        */
  #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                     */
  #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL)  /*!< Enable shortcut                                                      */

/* RAMUNDERFLOW_STOP @Bit 5 : Shortcut between event RAMUNDERFLOW and task STOP */
  #define PWM_SHORTS_RAMUNDERFLOW_STOP_Pos (5UL)     /*!< Position of RAMUNDERFLOW_STOP field.                                 */
  #define PWM_SHORTS_RAMUNDERFLOW_STOP_Msk (0x1UL << PWM_SHORTS_RAMUNDERFLOW_STOP_Pos) /*!< Bit mask of RAMUNDERFLOW_STOP
                                                                            field.*/
  #define PWM_SHORTS_RAMUNDERFLOW_STOP_Min (0x0UL)   /*!< Min enumerator value of RAMUNDERFLOW_STOP field.                     */
  #define PWM_SHORTS_RAMUNDERFLOW_STOP_Max (0x1UL)   /*!< Max enumerator value of RAMUNDERFLOW_STOP field.                     */
  #define PWM_SHORTS_RAMUNDERFLOW_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                  */
  #define PWM_SHORTS_RAMUNDERFLOW_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                    */

/* DMA_SEQ0_BUSERROR_STOP @Bit 6 : Shortcut between event DMA.SEQ[n].BUSERROR and task STOP */
  #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Pos (6UL) /*!< Position of DMA_SEQ0_BUSERROR_STOP field.                           */
  #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Msk (0x1UL << PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Pos) /*!< Bit mask of
                                                                            DMA_SEQ0_BUSERROR_STOP field.*/
  #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_SEQ0_BUSERROR_STOP field.             */
  #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_SEQ0_BUSERROR_STOP field.             */
  #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Disabled (0x0UL) /*!< Disable shortcut                                             */
  #define PWM_SHORTS_DMA_SEQ0_BUSERROR_STOP_Enabled (0x1UL) /*!< Enable shortcut                                               */

/* DMA_SEQ1_BUSERROR_STOP @Bit 7 : Shortcut between event DMA.SEQ[n].BUSERROR and task STOP */
  #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Pos (7UL) /*!< Position of DMA_SEQ1_BUSERROR_STOP field.                           */
  #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Msk (0x1UL << PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Pos) /*!< Bit mask of
                                                                            DMA_SEQ1_BUSERROR_STOP field.*/
  #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_SEQ1_BUSERROR_STOP field.             */
  #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_SEQ1_BUSERROR_STOP field.             */
  #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Disabled (0x0UL) /*!< Disable shortcut                                             */
  #define PWM_SHORTS_DMA_SEQ1_BUSERROR_STOP_Enabled (0x1UL) /*!< Enable shortcut                                               */


/* PWM_INTEN: Enable or disable interrupt */
  #define PWM_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */

/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
  #define PWM_INTEN_STOPPED_Pos (1UL)                /*!< Position of STOPPED field.                                           */
  #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                               */
  #define PWM_INTEN_STOPPED_Min (0x0UL)              /*!< Min enumerator value of STOPPED field.                               */
  #define PWM_INTEN_STOPPED_Max (0x1UL)              /*!< Max enumerator value of STOPPED field.                               */
  #define PWM_INTEN_STOPPED_Disabled (0x0UL)         /*!< Disable                                                              */
  #define PWM_INTEN_STOPPED_Enabled (0x1UL)          /*!< Enable                                                               */

/* SEQSTARTED0 @Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
  #define PWM_INTEN_SEQSTARTED0_Pos (2UL)            /*!< Position of SEQSTARTED0 field.                                       */
  #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field.                   */
  #define PWM_INTEN_SEQSTARTED0_Min (0x0UL)          /*!< Min enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTEN_SEQSTARTED0_Max (0x1UL)          /*!< Max enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL)     /*!< Disable                                                              */
  #define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL)      /*!< Enable                                                               */

/* SEQSTARTED1 @Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
  #define PWM_INTEN_SEQSTARTED1_Pos (3UL)            /*!< Position of SEQSTARTED1 field.                                       */
  #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field.                   */
  #define PWM_INTEN_SEQSTARTED1_Min (0x0UL)          /*!< Min enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTEN_SEQSTARTED1_Max (0x1UL)          /*!< Max enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL)     /*!< Disable                                                              */
  #define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL)      /*!< Enable                                                               */

/* SEQEND0 @Bit 4 : Enable or disable interrupt for event SEQEND[0] */
  #define PWM_INTEN_SEQEND0_Pos (4UL)                /*!< Position of SEQEND0 field.                                           */
  #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field.                               */
  #define PWM_INTEN_SEQEND0_Min (0x0UL)              /*!< Min enumerator value of SEQEND0 field.                               */
  #define PWM_INTEN_SEQEND0_Max (0x1UL)              /*!< Max enumerator value of SEQEND0 field.                               */
  #define PWM_INTEN_SEQEND0_Disabled (0x0UL)         /*!< Disable                                                              */
  #define PWM_INTEN_SEQEND0_Enabled (0x1UL)          /*!< Enable                                                               */

/* SEQEND1 @Bit 5 : Enable or disable interrupt for event SEQEND[1] */
  #define PWM_INTEN_SEQEND1_Pos (5UL)                /*!< Position of SEQEND1 field.                                           */
  #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field.                               */
  #define PWM_INTEN_SEQEND1_Min (0x0UL)              /*!< Min enumerator value of SEQEND1 field.                               */
  #define PWM_INTEN_SEQEND1_Max (0x1UL)              /*!< Max enumerator value of SEQEND1 field.                               */
  #define PWM_INTEN_SEQEND1_Disabled (0x0UL)         /*!< Disable                                                              */
  #define PWM_INTEN_SEQEND1_Enabled (0x1UL)          /*!< Enable                                                               */

/* PWMPERIODEND @Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
  #define PWM_INTEN_PWMPERIODEND_Pos (6UL)           /*!< Position of PWMPERIODEND field.                                      */
  #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.                */
  #define PWM_INTEN_PWMPERIODEND_Min (0x0UL)         /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTEN_PWMPERIODEND_Max (0x1UL)         /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL)    /*!< Disable                                                              */
  #define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL)     /*!< Enable                                                               */

/* LOOPSDONE @Bit 7 : Enable or disable interrupt for event LOOPSDONE */
  #define PWM_INTEN_LOOPSDONE_Pos (7UL)              /*!< Position of LOOPSDONE field.                                         */
  #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field.                         */
  #define PWM_INTEN_LOOPSDONE_Min (0x0UL)            /*!< Min enumerator value of LOOPSDONE field.                             */
  #define PWM_INTEN_LOOPSDONE_Max (0x1UL)            /*!< Max enumerator value of LOOPSDONE field.                             */
  #define PWM_INTEN_LOOPSDONE_Disabled (0x0UL)       /*!< Disable                                                              */
  #define PWM_INTEN_LOOPSDONE_Enabled (0x1UL)        /*!< Enable                                                               */

/* RAMUNDERFLOW @Bit 8 : Enable or disable interrupt for event RAMUNDERFLOW */
  #define PWM_INTEN_RAMUNDERFLOW_Pos (8UL)           /*!< Position of RAMUNDERFLOW field.                                      */
  #define PWM_INTEN_RAMUNDERFLOW_Msk (0x1UL << PWM_INTEN_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field.                */
  #define PWM_INTEN_RAMUNDERFLOW_Min (0x0UL)         /*!< Min enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTEN_RAMUNDERFLOW_Max (0x1UL)         /*!< Max enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTEN_RAMUNDERFLOW_Disabled (0x0UL)    /*!< Disable                                                              */
  #define PWM_INTEN_RAMUNDERFLOW_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMASEQ0END @Bit 9 : Enable or disable interrupt for event DMASEQ0END */
  #define PWM_INTEN_DMASEQ0END_Pos (9UL)             /*!< Position of DMASEQ0END field.                                        */
  #define PWM_INTEN_DMASEQ0END_Msk (0x1UL << PWM_INTEN_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field.                      */
  #define PWM_INTEN_DMASEQ0END_Min (0x0UL)           /*!< Min enumerator value of DMASEQ0END field.                            */
  #define PWM_INTEN_DMASEQ0END_Max (0x1UL)           /*!< Max enumerator value of DMASEQ0END field.                            */
  #define PWM_INTEN_DMASEQ0END_Disabled (0x0UL)      /*!< Disable                                                              */
  #define PWM_INTEN_DMASEQ0END_Enabled (0x1UL)       /*!< Enable                                                               */

/* DMASEQ0READY @Bit 10 : Enable or disable interrupt for event DMASEQ0READY */
  #define PWM_INTEN_DMASEQ0READY_Pos (10UL)          /*!< Position of DMASEQ0READY field.                                      */
  #define PWM_INTEN_DMASEQ0READY_Msk (0x1UL << PWM_INTEN_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field.                */
  #define PWM_INTEN_DMASEQ0READY_Min (0x0UL)         /*!< Min enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTEN_DMASEQ0READY_Max (0x1UL)         /*!< Max enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTEN_DMASEQ0READY_Disabled (0x0UL)    /*!< Disable                                                              */
  #define PWM_INTEN_DMASEQ0READY_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMASEQ0BUSERROR @Bit 11 : Enable or disable interrupt for event DMASEQ0BUSERROR */
  #define PWM_INTEN_DMASEQ0BUSERROR_Pos (11UL)       /*!< Position of DMASEQ0BUSERROR field.                                   */
  #define PWM_INTEN_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTEN_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field.       */
  #define PWM_INTEN_DMASEQ0BUSERROR_Min (0x0UL)      /*!< Min enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTEN_DMASEQ0BUSERROR_Max (0x1UL)      /*!< Max enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTEN_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Disable                                                              */
  #define PWM_INTEN_DMASEQ0BUSERROR_Enabled (0x1UL)  /*!< Enable                                                               */

/* DMASEQ1END @Bit 12 : Enable or disable interrupt for event DMASEQ1END */
  #define PWM_INTEN_DMASEQ1END_Pos (12UL)            /*!< Position of DMASEQ1END field.                                        */
  #define PWM_INTEN_DMASEQ1END_Msk (0x1UL << PWM_INTEN_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field.                      */
  #define PWM_INTEN_DMASEQ1END_Min (0x0UL)           /*!< Min enumerator value of DMASEQ1END field.                            */
  #define PWM_INTEN_DMASEQ1END_Max (0x1UL)           /*!< Max enumerator value of DMASEQ1END field.                            */
  #define PWM_INTEN_DMASEQ1END_Disabled (0x0UL)      /*!< Disable                                                              */
  #define PWM_INTEN_DMASEQ1END_Enabled (0x1UL)       /*!< Enable                                                               */

/* DMASEQ1READY @Bit 13 : Enable or disable interrupt for event DMASEQ1READY */
  #define PWM_INTEN_DMASEQ1READY_Pos (13UL)          /*!< Position of DMASEQ1READY field.                                      */
  #define PWM_INTEN_DMASEQ1READY_Msk (0x1UL << PWM_INTEN_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field.                */
  #define PWM_INTEN_DMASEQ1READY_Min (0x0UL)         /*!< Min enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTEN_DMASEQ1READY_Max (0x1UL)         /*!< Max enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTEN_DMASEQ1READY_Disabled (0x0UL)    /*!< Disable                                                              */
  #define PWM_INTEN_DMASEQ1READY_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMASEQ1BUSERROR @Bit 14 : Enable or disable interrupt for event DMASEQ1BUSERROR */
  #define PWM_INTEN_DMASEQ1BUSERROR_Pos (14UL)       /*!< Position of DMASEQ1BUSERROR field.                                   */
  #define PWM_INTEN_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTEN_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field.       */
  #define PWM_INTEN_DMASEQ1BUSERROR_Min (0x0UL)      /*!< Min enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTEN_DMASEQ1BUSERROR_Max (0x1UL)      /*!< Max enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTEN_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Disable                                                              */
  #define PWM_INTEN_DMASEQ1BUSERROR_Enabled (0x1UL)  /*!< Enable                                                               */

/* COMPAREMATCH0 @Bit 15 : Enable or disable interrupt for event COMPAREMATCH[0] */
  #define PWM_INTEN_COMPAREMATCH0_Pos (15UL)         /*!< Position of COMPAREMATCH0 field.                                     */
  #define PWM_INTEN_COMPAREMATCH0_Msk (0x1UL << PWM_INTEN_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field.             */
  #define PWM_INTEN_COMPAREMATCH0_Min (0x0UL)        /*!< Min enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTEN_COMPAREMATCH0_Max (0x1UL)        /*!< Max enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTEN_COMPAREMATCH0_Disabled (0x0UL)   /*!< Disable                                                              */
  #define PWM_INTEN_COMPAREMATCH0_Enabled (0x1UL)    /*!< Enable                                                               */

/* COMPAREMATCH1 @Bit 16 : Enable or disable interrupt for event COMPAREMATCH[1] */
  #define PWM_INTEN_COMPAREMATCH1_Pos (16UL)         /*!< Position of COMPAREMATCH1 field.                                     */
  #define PWM_INTEN_COMPAREMATCH1_Msk (0x1UL << PWM_INTEN_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field.             */
  #define PWM_INTEN_COMPAREMATCH1_Min (0x0UL)        /*!< Min enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTEN_COMPAREMATCH1_Max (0x1UL)        /*!< Max enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTEN_COMPAREMATCH1_Disabled (0x0UL)   /*!< Disable                                                              */
  #define PWM_INTEN_COMPAREMATCH1_Enabled (0x1UL)    /*!< Enable                                                               */

/* COMPAREMATCH2 @Bit 17 : Enable or disable interrupt for event COMPAREMATCH[2] */
  #define PWM_INTEN_COMPAREMATCH2_Pos (17UL)         /*!< Position of COMPAREMATCH2 field.                                     */
  #define PWM_INTEN_COMPAREMATCH2_Msk (0x1UL << PWM_INTEN_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field.             */
  #define PWM_INTEN_COMPAREMATCH2_Min (0x0UL)        /*!< Min enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTEN_COMPAREMATCH2_Max (0x1UL)        /*!< Max enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTEN_COMPAREMATCH2_Disabled (0x0UL)   /*!< Disable                                                              */
  #define PWM_INTEN_COMPAREMATCH2_Enabled (0x1UL)    /*!< Enable                                                               */

/* COMPAREMATCH3 @Bit 18 : Enable or disable interrupt for event COMPAREMATCH[3] */
  #define PWM_INTEN_COMPAREMATCH3_Pos (18UL)         /*!< Position of COMPAREMATCH3 field.                                     */
  #define PWM_INTEN_COMPAREMATCH3_Msk (0x1UL << PWM_INTEN_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field.             */
  #define PWM_INTEN_COMPAREMATCH3_Min (0x0UL)        /*!< Min enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTEN_COMPAREMATCH3_Max (0x1UL)        /*!< Max enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTEN_COMPAREMATCH3_Disabled (0x0UL)   /*!< Disable                                                              */
  #define PWM_INTEN_COMPAREMATCH3_Enabled (0x1UL)    /*!< Enable                                                               */


/* PWM_INTENSET: Enable interrupt */
  #define PWM_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
  #define PWM_INTENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define PWM_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define PWM_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define PWM_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
  #define PWM_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* SEQSTARTED0 @Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
  #define PWM_INTENSET_SEQSTARTED0_Pos (2UL)         /*!< Position of SEQSTARTED0 field.                                       */
  #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field.             */
  #define PWM_INTENSET_SEQSTARTED0_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTENSET_SEQSTARTED0_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTENSET_SEQSTARTED0_Set (0x1UL)       /*!< Enable                                                               */
  #define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* SEQSTARTED1 @Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
  #define PWM_INTENSET_SEQSTARTED1_Pos (3UL)         /*!< Position of SEQSTARTED1 field.                                       */
  #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field.             */
  #define PWM_INTENSET_SEQSTARTED1_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTENSET_SEQSTARTED1_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTENSET_SEQSTARTED1_Set (0x1UL)       /*!< Enable                                                               */
  #define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* SEQEND0 @Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
  #define PWM_INTENSET_SEQEND0_Pos (4UL)             /*!< Position of SEQEND0 field.                                           */
  #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field.                         */
  #define PWM_INTENSET_SEQEND0_Min (0x0UL)           /*!< Min enumerator value of SEQEND0 field.                               */
  #define PWM_INTENSET_SEQEND0_Max (0x1UL)           /*!< Max enumerator value of SEQEND0 field.                               */
  #define PWM_INTENSET_SEQEND0_Set (0x1UL)           /*!< Enable                                                               */
  #define PWM_INTENSET_SEQEND0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_SEQEND0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* SEQEND1 @Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
  #define PWM_INTENSET_SEQEND1_Pos (5UL)             /*!< Position of SEQEND1 field.                                           */
  #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field.                         */
  #define PWM_INTENSET_SEQEND1_Min (0x0UL)           /*!< Min enumerator value of SEQEND1 field.                               */
  #define PWM_INTENSET_SEQEND1_Max (0x1UL)           /*!< Max enumerator value of SEQEND1 field.                               */
  #define PWM_INTENSET_SEQEND1_Set (0x1UL)           /*!< Enable                                                               */
  #define PWM_INTENSET_SEQEND1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_SEQEND1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PWMPERIODEND @Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
  #define PWM_INTENSET_PWMPERIODEND_Pos (6UL)        /*!< Position of PWMPERIODEND field.                                      */
  #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.          */
  #define PWM_INTENSET_PWMPERIODEND_Min (0x0UL)      /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTENSET_PWMPERIODEND_Max (0x1UL)      /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTENSET_PWMPERIODEND_Set (0x1UL)      /*!< Enable                                                               */
  #define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* LOOPSDONE @Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
  #define PWM_INTENSET_LOOPSDONE_Pos (7UL)           /*!< Position of LOOPSDONE field.                                         */
  #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field.                   */
  #define PWM_INTENSET_LOOPSDONE_Min (0x0UL)         /*!< Min enumerator value of LOOPSDONE field.                             */
  #define PWM_INTENSET_LOOPSDONE_Max (0x1UL)         /*!< Max enumerator value of LOOPSDONE field.                             */
  #define PWM_INTENSET_LOOPSDONE_Set (0x1UL)         /*!< Enable                                                               */
  #define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* RAMUNDERFLOW @Bit 8 : Write '1' to enable interrupt for event RAMUNDERFLOW */
  #define PWM_INTENSET_RAMUNDERFLOW_Pos (8UL)        /*!< Position of RAMUNDERFLOW field.                                      */
  #define PWM_INTENSET_RAMUNDERFLOW_Msk (0x1UL << PWM_INTENSET_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field.          */
  #define PWM_INTENSET_RAMUNDERFLOW_Min (0x0UL)      /*!< Min enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTENSET_RAMUNDERFLOW_Max (0x1UL)      /*!< Max enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTENSET_RAMUNDERFLOW_Set (0x1UL)      /*!< Enable                                                               */
  #define PWM_INTENSET_RAMUNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_RAMUNDERFLOW_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMASEQ0END @Bit 9 : Write '1' to enable interrupt for event DMASEQ0END */
  #define PWM_INTENSET_DMASEQ0END_Pos (9UL)          /*!< Position of DMASEQ0END field.                                        */
  #define PWM_INTENSET_DMASEQ0END_Msk (0x1UL << PWM_INTENSET_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field.                */
  #define PWM_INTENSET_DMASEQ0END_Min (0x0UL)        /*!< Min enumerator value of DMASEQ0END field.                            */
  #define PWM_INTENSET_DMASEQ0END_Max (0x1UL)        /*!< Max enumerator value of DMASEQ0END field.                            */
  #define PWM_INTENSET_DMASEQ0END_Set (0x1UL)        /*!< Enable                                                               */
  #define PWM_INTENSET_DMASEQ0END_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_DMASEQ0END_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMASEQ0READY @Bit 10 : Write '1' to enable interrupt for event DMASEQ0READY */
  #define PWM_INTENSET_DMASEQ0READY_Pos (10UL)       /*!< Position of DMASEQ0READY field.                                      */
  #define PWM_INTENSET_DMASEQ0READY_Msk (0x1UL << PWM_INTENSET_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field.          */
  #define PWM_INTENSET_DMASEQ0READY_Min (0x0UL)      /*!< Min enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTENSET_DMASEQ0READY_Max (0x1UL)      /*!< Max enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTENSET_DMASEQ0READY_Set (0x1UL)      /*!< Enable                                                               */
  #define PWM_INTENSET_DMASEQ0READY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_DMASEQ0READY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMASEQ0BUSERROR @Bit 11 : Write '1' to enable interrupt for event DMASEQ0BUSERROR */
  #define PWM_INTENSET_DMASEQ0BUSERROR_Pos (11UL)    /*!< Position of DMASEQ0BUSERROR field.                                   */
  #define PWM_INTENSET_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTENSET_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */
  #define PWM_INTENSET_DMASEQ0BUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTENSET_DMASEQ0BUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTENSET_DMASEQ0BUSERROR_Set (0x1UL)   /*!< Enable                                                               */
  #define PWM_INTENSET_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define PWM_INTENSET_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* DMASEQ1END @Bit 12 : Write '1' to enable interrupt for event DMASEQ1END */
  #define PWM_INTENSET_DMASEQ1END_Pos (12UL)         /*!< Position of DMASEQ1END field.                                        */
  #define PWM_INTENSET_DMASEQ1END_Msk (0x1UL << PWM_INTENSET_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field.                */
  #define PWM_INTENSET_DMASEQ1END_Min (0x0UL)        /*!< Min enumerator value of DMASEQ1END field.                            */
  #define PWM_INTENSET_DMASEQ1END_Max (0x1UL)        /*!< Max enumerator value of DMASEQ1END field.                            */
  #define PWM_INTENSET_DMASEQ1END_Set (0x1UL)        /*!< Enable                                                               */
  #define PWM_INTENSET_DMASEQ1END_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_DMASEQ1END_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMASEQ1READY @Bit 13 : Write '1' to enable interrupt for event DMASEQ1READY */
  #define PWM_INTENSET_DMASEQ1READY_Pos (13UL)       /*!< Position of DMASEQ1READY field.                                      */
  #define PWM_INTENSET_DMASEQ1READY_Msk (0x1UL << PWM_INTENSET_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field.          */
  #define PWM_INTENSET_DMASEQ1READY_Min (0x0UL)      /*!< Min enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTENSET_DMASEQ1READY_Max (0x1UL)      /*!< Max enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTENSET_DMASEQ1READY_Set (0x1UL)      /*!< Enable                                                               */
  #define PWM_INTENSET_DMASEQ1READY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENSET_DMASEQ1READY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMASEQ1BUSERROR @Bit 14 : Write '1' to enable interrupt for event DMASEQ1BUSERROR */
  #define PWM_INTENSET_DMASEQ1BUSERROR_Pos (14UL)    /*!< Position of DMASEQ1BUSERROR field.                                   */
  #define PWM_INTENSET_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTENSET_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */
  #define PWM_INTENSET_DMASEQ1BUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTENSET_DMASEQ1BUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTENSET_DMASEQ1BUSERROR_Set (0x1UL)   /*!< Enable                                                               */
  #define PWM_INTENSET_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define PWM_INTENSET_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* COMPAREMATCH0 @Bit 15 : Write '1' to enable interrupt for event COMPAREMATCH[0] */
  #define PWM_INTENSET_COMPAREMATCH0_Pos (15UL)      /*!< Position of COMPAREMATCH0 field.                                     */
  #define PWM_INTENSET_COMPAREMATCH0_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field.       */
  #define PWM_INTENSET_COMPAREMATCH0_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTENSET_COMPAREMATCH0_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTENSET_COMPAREMATCH0_Set (0x1UL)     /*!< Enable                                                               */
  #define PWM_INTENSET_COMPAREMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENSET_COMPAREMATCH0_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* COMPAREMATCH1 @Bit 16 : Write '1' to enable interrupt for event COMPAREMATCH[1] */
  #define PWM_INTENSET_COMPAREMATCH1_Pos (16UL)      /*!< Position of COMPAREMATCH1 field.                                     */
  #define PWM_INTENSET_COMPAREMATCH1_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field.       */
  #define PWM_INTENSET_COMPAREMATCH1_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTENSET_COMPAREMATCH1_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTENSET_COMPAREMATCH1_Set (0x1UL)     /*!< Enable                                                               */
  #define PWM_INTENSET_COMPAREMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENSET_COMPAREMATCH1_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* COMPAREMATCH2 @Bit 17 : Write '1' to enable interrupt for event COMPAREMATCH[2] */
  #define PWM_INTENSET_COMPAREMATCH2_Pos (17UL)      /*!< Position of COMPAREMATCH2 field.                                     */
  #define PWM_INTENSET_COMPAREMATCH2_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field.       */
  #define PWM_INTENSET_COMPAREMATCH2_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTENSET_COMPAREMATCH2_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTENSET_COMPAREMATCH2_Set (0x1UL)     /*!< Enable                                                               */
  #define PWM_INTENSET_COMPAREMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENSET_COMPAREMATCH2_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* COMPAREMATCH3 @Bit 18 : Write '1' to enable interrupt for event COMPAREMATCH[3] */
  #define PWM_INTENSET_COMPAREMATCH3_Pos (18UL)      /*!< Position of COMPAREMATCH3 field.                                     */
  #define PWM_INTENSET_COMPAREMATCH3_Msk (0x1UL << PWM_INTENSET_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field.       */
  #define PWM_INTENSET_COMPAREMATCH3_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTENSET_COMPAREMATCH3_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTENSET_COMPAREMATCH3_Set (0x1UL)     /*!< Enable                                                               */
  #define PWM_INTENSET_COMPAREMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENSET_COMPAREMATCH3_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* PWM_INTENCLR: Disable interrupt */
  #define PWM_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
  #define PWM_INTENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define PWM_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define PWM_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define PWM_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
  #define PWM_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* SEQSTARTED0 @Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
  #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL)         /*!< Position of SEQSTARTED0 field.                                       */
  #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field.             */
  #define PWM_INTENCLR_SEQSTARTED0_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTENCLR_SEQSTARTED0_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL)     /*!< Disable                                                              */
  #define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* SEQSTARTED1 @Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
  #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL)         /*!< Position of SEQSTARTED1 field.                                       */
  #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field.             */
  #define PWM_INTENCLR_SEQSTARTED1_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTENCLR_SEQSTARTED1_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL)     /*!< Disable                                                              */
  #define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* SEQEND0 @Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
  #define PWM_INTENCLR_SEQEND0_Pos (4UL)             /*!< Position of SEQEND0 field.                                           */
  #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field.                         */
  #define PWM_INTENCLR_SEQEND0_Min (0x0UL)           /*!< Min enumerator value of SEQEND0 field.                               */
  #define PWM_INTENCLR_SEQEND0_Max (0x1UL)           /*!< Max enumerator value of SEQEND0 field.                               */
  #define PWM_INTENCLR_SEQEND0_Clear (0x1UL)         /*!< Disable                                                              */
  #define PWM_INTENCLR_SEQEND0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_SEQEND0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* SEQEND1 @Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
  #define PWM_INTENCLR_SEQEND1_Pos (5UL)             /*!< Position of SEQEND1 field.                                           */
  #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field.                         */
  #define PWM_INTENCLR_SEQEND1_Min (0x0UL)           /*!< Min enumerator value of SEQEND1 field.                               */
  #define PWM_INTENCLR_SEQEND1_Max (0x1UL)           /*!< Max enumerator value of SEQEND1 field.                               */
  #define PWM_INTENCLR_SEQEND1_Clear (0x1UL)         /*!< Disable                                                              */
  #define PWM_INTENCLR_SEQEND1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_SEQEND1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PWMPERIODEND @Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
  #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL)        /*!< Position of PWMPERIODEND field.                                      */
  #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.          */
  #define PWM_INTENCLR_PWMPERIODEND_Min (0x0UL)      /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTENCLR_PWMPERIODEND_Max (0x1UL)      /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL)    /*!< Disable                                                              */
  #define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* LOOPSDONE @Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
  #define PWM_INTENCLR_LOOPSDONE_Pos (7UL)           /*!< Position of LOOPSDONE field.                                         */
  #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field.                   */
  #define PWM_INTENCLR_LOOPSDONE_Min (0x0UL)         /*!< Min enumerator value of LOOPSDONE field.                             */
  #define PWM_INTENCLR_LOOPSDONE_Max (0x1UL)         /*!< Max enumerator value of LOOPSDONE field.                             */
  #define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL)       /*!< Disable                                                              */
  #define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* RAMUNDERFLOW @Bit 8 : Write '1' to disable interrupt for event RAMUNDERFLOW */
  #define PWM_INTENCLR_RAMUNDERFLOW_Pos (8UL)        /*!< Position of RAMUNDERFLOW field.                                      */
  #define PWM_INTENCLR_RAMUNDERFLOW_Msk (0x1UL << PWM_INTENCLR_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field.          */
  #define PWM_INTENCLR_RAMUNDERFLOW_Min (0x0UL)      /*!< Min enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTENCLR_RAMUNDERFLOW_Max (0x1UL)      /*!< Max enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTENCLR_RAMUNDERFLOW_Clear (0x1UL)    /*!< Disable                                                              */
  #define PWM_INTENCLR_RAMUNDERFLOW_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_RAMUNDERFLOW_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMASEQ0END @Bit 9 : Write '1' to disable interrupt for event DMASEQ0END */
  #define PWM_INTENCLR_DMASEQ0END_Pos (9UL)          /*!< Position of DMASEQ0END field.                                        */
  #define PWM_INTENCLR_DMASEQ0END_Msk (0x1UL << PWM_INTENCLR_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field.                */
  #define PWM_INTENCLR_DMASEQ0END_Min (0x0UL)        /*!< Min enumerator value of DMASEQ0END field.                            */
  #define PWM_INTENCLR_DMASEQ0END_Max (0x1UL)        /*!< Max enumerator value of DMASEQ0END field.                            */
  #define PWM_INTENCLR_DMASEQ0END_Clear (0x1UL)      /*!< Disable                                                              */
  #define PWM_INTENCLR_DMASEQ0END_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_DMASEQ0END_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMASEQ0READY @Bit 10 : Write '1' to disable interrupt for event DMASEQ0READY */
  #define PWM_INTENCLR_DMASEQ0READY_Pos (10UL)       /*!< Position of DMASEQ0READY field.                                      */
  #define PWM_INTENCLR_DMASEQ0READY_Msk (0x1UL << PWM_INTENCLR_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field.          */
  #define PWM_INTENCLR_DMASEQ0READY_Min (0x0UL)      /*!< Min enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTENCLR_DMASEQ0READY_Max (0x1UL)      /*!< Max enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTENCLR_DMASEQ0READY_Clear (0x1UL)    /*!< Disable                                                              */
  #define PWM_INTENCLR_DMASEQ0READY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_DMASEQ0READY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMASEQ0BUSERROR @Bit 11 : Write '1' to disable interrupt for event DMASEQ0BUSERROR */
  #define PWM_INTENCLR_DMASEQ0BUSERROR_Pos (11UL)    /*!< Position of DMASEQ0BUSERROR field.                                   */
  #define PWM_INTENCLR_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTENCLR_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field. */
  #define PWM_INTENCLR_DMASEQ0BUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTENCLR_DMASEQ0BUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTENCLR_DMASEQ0BUSERROR_Clear (0x1UL) /*!< Disable                                                              */
  #define PWM_INTENCLR_DMASEQ0BUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define PWM_INTENCLR_DMASEQ0BUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* DMASEQ1END @Bit 12 : Write '1' to disable interrupt for event DMASEQ1END */
  #define PWM_INTENCLR_DMASEQ1END_Pos (12UL)         /*!< Position of DMASEQ1END field.                                        */
  #define PWM_INTENCLR_DMASEQ1END_Msk (0x1UL << PWM_INTENCLR_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field.                */
  #define PWM_INTENCLR_DMASEQ1END_Min (0x0UL)        /*!< Min enumerator value of DMASEQ1END field.                            */
  #define PWM_INTENCLR_DMASEQ1END_Max (0x1UL)        /*!< Max enumerator value of DMASEQ1END field.                            */
  #define PWM_INTENCLR_DMASEQ1END_Clear (0x1UL)      /*!< Disable                                                              */
  #define PWM_INTENCLR_DMASEQ1END_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_DMASEQ1END_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMASEQ1READY @Bit 13 : Write '1' to disable interrupt for event DMASEQ1READY */
  #define PWM_INTENCLR_DMASEQ1READY_Pos (13UL)       /*!< Position of DMASEQ1READY field.                                      */
  #define PWM_INTENCLR_DMASEQ1READY_Msk (0x1UL << PWM_INTENCLR_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field.          */
  #define PWM_INTENCLR_DMASEQ1READY_Min (0x0UL)      /*!< Min enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTENCLR_DMASEQ1READY_Max (0x1UL)      /*!< Max enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTENCLR_DMASEQ1READY_Clear (0x1UL)    /*!< Disable                                                              */
  #define PWM_INTENCLR_DMASEQ1READY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define PWM_INTENCLR_DMASEQ1READY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMASEQ1BUSERROR @Bit 14 : Write '1' to disable interrupt for event DMASEQ1BUSERROR */
  #define PWM_INTENCLR_DMASEQ1BUSERROR_Pos (14UL)    /*!< Position of DMASEQ1BUSERROR field.                                   */
  #define PWM_INTENCLR_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTENCLR_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field. */
  #define PWM_INTENCLR_DMASEQ1BUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTENCLR_DMASEQ1BUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTENCLR_DMASEQ1BUSERROR_Clear (0x1UL) /*!< Disable                                                              */
  #define PWM_INTENCLR_DMASEQ1BUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define PWM_INTENCLR_DMASEQ1BUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* COMPAREMATCH0 @Bit 15 : Write '1' to disable interrupt for event COMPAREMATCH[0] */
  #define PWM_INTENCLR_COMPAREMATCH0_Pos (15UL)      /*!< Position of COMPAREMATCH0 field.                                     */
  #define PWM_INTENCLR_COMPAREMATCH0_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field.       */
  #define PWM_INTENCLR_COMPAREMATCH0_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH0_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH0_Clear (0x1UL)   /*!< Disable                                                              */
  #define PWM_INTENCLR_COMPAREMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENCLR_COMPAREMATCH0_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* COMPAREMATCH1 @Bit 16 : Write '1' to disable interrupt for event COMPAREMATCH[1] */
  #define PWM_INTENCLR_COMPAREMATCH1_Pos (16UL)      /*!< Position of COMPAREMATCH1 field.                                     */
  #define PWM_INTENCLR_COMPAREMATCH1_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field.       */
  #define PWM_INTENCLR_COMPAREMATCH1_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH1_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH1_Clear (0x1UL)   /*!< Disable                                                              */
  #define PWM_INTENCLR_COMPAREMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENCLR_COMPAREMATCH1_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* COMPAREMATCH2 @Bit 17 : Write '1' to disable interrupt for event COMPAREMATCH[2] */
  #define PWM_INTENCLR_COMPAREMATCH2_Pos (17UL)      /*!< Position of COMPAREMATCH2 field.                                     */
  #define PWM_INTENCLR_COMPAREMATCH2_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field.       */
  #define PWM_INTENCLR_COMPAREMATCH2_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH2_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH2_Clear (0x1UL)   /*!< Disable                                                              */
  #define PWM_INTENCLR_COMPAREMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENCLR_COMPAREMATCH2_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* COMPAREMATCH3 @Bit 18 : Write '1' to disable interrupt for event COMPAREMATCH[3] */
  #define PWM_INTENCLR_COMPAREMATCH3_Pos (18UL)      /*!< Position of COMPAREMATCH3 field.                                     */
  #define PWM_INTENCLR_COMPAREMATCH3_Msk (0x1UL << PWM_INTENCLR_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field.       */
  #define PWM_INTENCLR_COMPAREMATCH3_Min (0x0UL)     /*!< Min enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH3_Max (0x1UL)     /*!< Max enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTENCLR_COMPAREMATCH3_Clear (0x1UL)   /*!< Disable                                                              */
  #define PWM_INTENCLR_COMPAREMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define PWM_INTENCLR_COMPAREMATCH3_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* PWM_INTPEND: Pending interrupts */
  #define PWM_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */

/* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */
  #define PWM_INTPEND_STOPPED_Pos (1UL)              /*!< Position of STOPPED field.                                           */
  #define PWM_INTPEND_STOPPED_Msk (0x1UL << PWM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field.                           */
  #define PWM_INTPEND_STOPPED_Min (0x0UL)            /*!< Min enumerator value of STOPPED field.                               */
  #define PWM_INTPEND_STOPPED_Max (0x1UL)            /*!< Max enumerator value of STOPPED field.                               */
  #define PWM_INTPEND_STOPPED_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_STOPPED_Pending (0x1UL)        /*!< Read: Pending                                                        */

/* SEQSTARTED0 @Bit 2 : Read pending status of interrupt for event SEQSTARTED[0] */
  #define PWM_INTPEND_SEQSTARTED0_Pos (2UL)          /*!< Position of SEQSTARTED0 field.                                       */
  #define PWM_INTPEND_SEQSTARTED0_Msk (0x1UL << PWM_INTPEND_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field.               */
  #define PWM_INTPEND_SEQSTARTED0_Min (0x0UL)        /*!< Min enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTPEND_SEQSTARTED0_Max (0x1UL)        /*!< Max enumerator value of SEQSTARTED0 field.                           */
  #define PWM_INTPEND_SEQSTARTED0_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_SEQSTARTED0_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* SEQSTARTED1 @Bit 3 : Read pending status of interrupt for event SEQSTARTED[1] */
  #define PWM_INTPEND_SEQSTARTED1_Pos (3UL)          /*!< Position of SEQSTARTED1 field.                                       */
  #define PWM_INTPEND_SEQSTARTED1_Msk (0x1UL << PWM_INTPEND_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field.               */
  #define PWM_INTPEND_SEQSTARTED1_Min (0x0UL)        /*!< Min enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTPEND_SEQSTARTED1_Max (0x1UL)        /*!< Max enumerator value of SEQSTARTED1 field.                           */
  #define PWM_INTPEND_SEQSTARTED1_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_SEQSTARTED1_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* SEQEND0 @Bit 4 : Read pending status of interrupt for event SEQEND[0] */
  #define PWM_INTPEND_SEQEND0_Pos (4UL)              /*!< Position of SEQEND0 field.                                           */
  #define PWM_INTPEND_SEQEND0_Msk (0x1UL << PWM_INTPEND_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field.                           */
  #define PWM_INTPEND_SEQEND0_Min (0x0UL)            /*!< Min enumerator value of SEQEND0 field.                               */
  #define PWM_INTPEND_SEQEND0_Max (0x1UL)            /*!< Max enumerator value of SEQEND0 field.                               */
  #define PWM_INTPEND_SEQEND0_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_SEQEND0_Pending (0x1UL)        /*!< Read: Pending                                                        */

/* SEQEND1 @Bit 5 : Read pending status of interrupt for event SEQEND[1] */
  #define PWM_INTPEND_SEQEND1_Pos (5UL)              /*!< Position of SEQEND1 field.                                           */
  #define PWM_INTPEND_SEQEND1_Msk (0x1UL << PWM_INTPEND_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field.                           */
  #define PWM_INTPEND_SEQEND1_Min (0x0UL)            /*!< Min enumerator value of SEQEND1 field.                               */
  #define PWM_INTPEND_SEQEND1_Max (0x1UL)            /*!< Max enumerator value of SEQEND1 field.                               */
  #define PWM_INTPEND_SEQEND1_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_SEQEND1_Pending (0x1UL)        /*!< Read: Pending                                                        */

/* PWMPERIODEND @Bit 6 : Read pending status of interrupt for event PWMPERIODEND */
  #define PWM_INTPEND_PWMPERIODEND_Pos (6UL)         /*!< Position of PWMPERIODEND field.                                      */
  #define PWM_INTPEND_PWMPERIODEND_Msk (0x1UL << PWM_INTPEND_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.            */
  #define PWM_INTPEND_PWMPERIODEND_Min (0x0UL)       /*!< Min enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTPEND_PWMPERIODEND_Max (0x1UL)       /*!< Max enumerator value of PWMPERIODEND field.                          */
  #define PWM_INTPEND_PWMPERIODEND_NotPending (0x0UL) /*!< Read: Not pending                                                   */
  #define PWM_INTPEND_PWMPERIODEND_Pending (0x1UL)   /*!< Read: Pending                                                        */

/* LOOPSDONE @Bit 7 : Read pending status of interrupt for event LOOPSDONE */
  #define PWM_INTPEND_LOOPSDONE_Pos (7UL)            /*!< Position of LOOPSDONE field.                                         */
  #define PWM_INTPEND_LOOPSDONE_Msk (0x1UL << PWM_INTPEND_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field.                     */
  #define PWM_INTPEND_LOOPSDONE_Min (0x0UL)          /*!< Min enumerator value of LOOPSDONE field.                             */
  #define PWM_INTPEND_LOOPSDONE_Max (0x1UL)          /*!< Max enumerator value of LOOPSDONE field.                             */
  #define PWM_INTPEND_LOOPSDONE_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_LOOPSDONE_Pending (0x1UL)      /*!< Read: Pending                                                        */

/* RAMUNDERFLOW @Bit 8 : Read pending status of interrupt for event RAMUNDERFLOW */
  #define PWM_INTPEND_RAMUNDERFLOW_Pos (8UL)         /*!< Position of RAMUNDERFLOW field.                                      */
  #define PWM_INTPEND_RAMUNDERFLOW_Msk (0x1UL << PWM_INTPEND_RAMUNDERFLOW_Pos) /*!< Bit mask of RAMUNDERFLOW field.            */
  #define PWM_INTPEND_RAMUNDERFLOW_Min (0x0UL)       /*!< Min enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTPEND_RAMUNDERFLOW_Max (0x1UL)       /*!< Max enumerator value of RAMUNDERFLOW field.                          */
  #define PWM_INTPEND_RAMUNDERFLOW_NotPending (0x0UL) /*!< Read: Not pending                                                   */
  #define PWM_INTPEND_RAMUNDERFLOW_Pending (0x1UL)   /*!< Read: Pending                                                        */

/* DMASEQ0END @Bit 9 : Read pending status of interrupt for event DMASEQ0END */
  #define PWM_INTPEND_DMASEQ0END_Pos (9UL)           /*!< Position of DMASEQ0END field.                                        */
  #define PWM_INTPEND_DMASEQ0END_Msk (0x1UL << PWM_INTPEND_DMASEQ0END_Pos) /*!< Bit mask of DMASEQ0END field.                  */
  #define PWM_INTPEND_DMASEQ0END_Min (0x0UL)         /*!< Min enumerator value of DMASEQ0END field.                            */
  #define PWM_INTPEND_DMASEQ0END_Max (0x1UL)         /*!< Max enumerator value of DMASEQ0END field.                            */
  #define PWM_INTPEND_DMASEQ0END_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_DMASEQ0END_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* DMASEQ0READY @Bit 10 : Read pending status of interrupt for event DMASEQ0READY */
  #define PWM_INTPEND_DMASEQ0READY_Pos (10UL)        /*!< Position of DMASEQ0READY field.                                      */
  #define PWM_INTPEND_DMASEQ0READY_Msk (0x1UL << PWM_INTPEND_DMASEQ0READY_Pos) /*!< Bit mask of DMASEQ0READY field.            */
  #define PWM_INTPEND_DMASEQ0READY_Min (0x0UL)       /*!< Min enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTPEND_DMASEQ0READY_Max (0x1UL)       /*!< Max enumerator value of DMASEQ0READY field.                          */
  #define PWM_INTPEND_DMASEQ0READY_NotPending (0x0UL) /*!< Read: Not pending                                                   */
  #define PWM_INTPEND_DMASEQ0READY_Pending (0x1UL)   /*!< Read: Pending                                                        */

/* DMASEQ0BUSERROR @Bit 11 : Read pending status of interrupt for event DMASEQ0BUSERROR */
  #define PWM_INTPEND_DMASEQ0BUSERROR_Pos (11UL)     /*!< Position of DMASEQ0BUSERROR field.                                   */
  #define PWM_INTPEND_DMASEQ0BUSERROR_Msk (0x1UL << PWM_INTPEND_DMASEQ0BUSERROR_Pos) /*!< Bit mask of DMASEQ0BUSERROR field.   */
  #define PWM_INTPEND_DMASEQ0BUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTPEND_DMASEQ0BUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMASEQ0BUSERROR field.                       */
  #define PWM_INTPEND_DMASEQ0BUSERROR_NotPending (0x0UL) /*!< Read: Not pending                                                */
  #define PWM_INTPEND_DMASEQ0BUSERROR_Pending (0x1UL) /*!< Read: Pending                                                       */

/* DMASEQ1END @Bit 12 : Read pending status of interrupt for event DMASEQ1END */
  #define PWM_INTPEND_DMASEQ1END_Pos (12UL)          /*!< Position of DMASEQ1END field.                                        */
  #define PWM_INTPEND_DMASEQ1END_Msk (0x1UL << PWM_INTPEND_DMASEQ1END_Pos) /*!< Bit mask of DMASEQ1END field.                  */
  #define PWM_INTPEND_DMASEQ1END_Min (0x0UL)         /*!< Min enumerator value of DMASEQ1END field.                            */
  #define PWM_INTPEND_DMASEQ1END_Max (0x1UL)         /*!< Max enumerator value of DMASEQ1END field.                            */
  #define PWM_INTPEND_DMASEQ1END_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
  #define PWM_INTPEND_DMASEQ1END_Pending (0x1UL)     /*!< Read: Pending                                                        */

/* DMASEQ1READY @Bit 13 : Read pending status of interrupt for event DMASEQ1READY */
  #define PWM_INTPEND_DMASEQ1READY_Pos (13UL)        /*!< Position of DMASEQ1READY field.                                      */
  #define PWM_INTPEND_DMASEQ1READY_Msk (0x1UL << PWM_INTPEND_DMASEQ1READY_Pos) /*!< Bit mask of DMASEQ1READY field.            */
  #define PWM_INTPEND_DMASEQ1READY_Min (0x0UL)       /*!< Min enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTPEND_DMASEQ1READY_Max (0x1UL)       /*!< Max enumerator value of DMASEQ1READY field.                          */
  #define PWM_INTPEND_DMASEQ1READY_NotPending (0x0UL) /*!< Read: Not pending                                                   */
  #define PWM_INTPEND_DMASEQ1READY_Pending (0x1UL)   /*!< Read: Pending                                                        */

/* DMASEQ1BUSERROR @Bit 14 : Read pending status of interrupt for event DMASEQ1BUSERROR */
  #define PWM_INTPEND_DMASEQ1BUSERROR_Pos (14UL)     /*!< Position of DMASEQ1BUSERROR field.                                   */
  #define PWM_INTPEND_DMASEQ1BUSERROR_Msk (0x1UL << PWM_INTPEND_DMASEQ1BUSERROR_Pos) /*!< Bit mask of DMASEQ1BUSERROR field.   */
  #define PWM_INTPEND_DMASEQ1BUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTPEND_DMASEQ1BUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMASEQ1BUSERROR field.                       */
  #define PWM_INTPEND_DMASEQ1BUSERROR_NotPending (0x0UL) /*!< Read: Not pending                                                */
  #define PWM_INTPEND_DMASEQ1BUSERROR_Pending (0x1UL) /*!< Read: Pending                                                       */

/* COMPAREMATCH0 @Bit 15 : Read pending status of interrupt for event COMPAREMATCH[0] */
  #define PWM_INTPEND_COMPAREMATCH0_Pos (15UL)       /*!< Position of COMPAREMATCH0 field.                                     */
  #define PWM_INTPEND_COMPAREMATCH0_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH0_Pos) /*!< Bit mask of COMPAREMATCH0 field.         */
  #define PWM_INTPEND_COMPAREMATCH0_Min (0x0UL)      /*!< Min enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTPEND_COMPAREMATCH0_Max (0x1UL)      /*!< Max enumerator value of COMPAREMATCH0 field.                         */
  #define PWM_INTPEND_COMPAREMATCH0_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define PWM_INTPEND_COMPAREMATCH0_Pending (0x1UL)  /*!< Read: Pending                                                        */

/* COMPAREMATCH1 @Bit 16 : Read pending status of interrupt for event COMPAREMATCH[1] */
  #define PWM_INTPEND_COMPAREMATCH1_Pos (16UL)       /*!< Position of COMPAREMATCH1 field.                                     */
  #define PWM_INTPEND_COMPAREMATCH1_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH1_Pos) /*!< Bit mask of COMPAREMATCH1 field.         */
  #define PWM_INTPEND_COMPAREMATCH1_Min (0x0UL)      /*!< Min enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTPEND_COMPAREMATCH1_Max (0x1UL)      /*!< Max enumerator value of COMPAREMATCH1 field.                         */
  #define PWM_INTPEND_COMPAREMATCH1_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define PWM_INTPEND_COMPAREMATCH1_Pending (0x1UL)  /*!< Read: Pending                                                        */

/* COMPAREMATCH2 @Bit 17 : Read pending status of interrupt for event COMPAREMATCH[2] */
  #define PWM_INTPEND_COMPAREMATCH2_Pos (17UL)       /*!< Position of COMPAREMATCH2 field.                                     */
  #define PWM_INTPEND_COMPAREMATCH2_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH2_Pos) /*!< Bit mask of COMPAREMATCH2 field.         */
  #define PWM_INTPEND_COMPAREMATCH2_Min (0x0UL)      /*!< Min enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTPEND_COMPAREMATCH2_Max (0x1UL)      /*!< Max enumerator value of COMPAREMATCH2 field.                         */
  #define PWM_INTPEND_COMPAREMATCH2_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define PWM_INTPEND_COMPAREMATCH2_Pending (0x1UL)  /*!< Read: Pending                                                        */

/* COMPAREMATCH3 @Bit 18 : Read pending status of interrupt for event COMPAREMATCH[3] */
  #define PWM_INTPEND_COMPAREMATCH3_Pos (18UL)       /*!< Position of COMPAREMATCH3 field.                                     */
  #define PWM_INTPEND_COMPAREMATCH3_Msk (0x1UL << PWM_INTPEND_COMPAREMATCH3_Pos) /*!< Bit mask of COMPAREMATCH3 field.         */
  #define PWM_INTPEND_COMPAREMATCH3_Min (0x0UL)      /*!< Min enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTPEND_COMPAREMATCH3_Max (0x1UL)      /*!< Max enumerator value of COMPAREMATCH3 field.                         */
  #define PWM_INTPEND_COMPAREMATCH3_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define PWM_INTPEND_COMPAREMATCH3_Pending (0x1UL)  /*!< Read: Pending                                                        */


/* PWM_ENABLE: PWM module enable register */
  #define PWM_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bit 0 : Enable or disable PWM module */
  #define PWM_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
  #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
  #define PWM_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
  #define PWM_ENABLE_ENABLE_Max (0x1UL)              /*!< Max enumerator value of ENABLE field.                                */
  #define PWM_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disabled                                                             */
  #define PWM_ENABLE_ENABLE_Enabled (0x1UL)          /*!< Enable                                                               */


/* PWM_MODE: Selects operating mode of the wave counter */
  #define PWM_MODE_ResetValue (0x00000000UL)         /*!< Reset value of MODE register.                                        */

/* UPDOWN @Bit 0 : Selects up mode or up-and-down mode for the counter */
  #define PWM_MODE_UPDOWN_Pos (0UL)                  /*!< Position of UPDOWN field.                                            */
  #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field.                                    */
  #define PWM_MODE_UPDOWN_Min (0x0UL)                /*!< Min enumerator value of UPDOWN field.                                */
  #define PWM_MODE_UPDOWN_Max (0x1UL)                /*!< Max enumerator value of UPDOWN field.                                */
  #define PWM_MODE_UPDOWN_Up (0x0UL)                 /*!< Up counter, edge-aligned PWM duty cycle                              */
  #define PWM_MODE_UPDOWN_UpAndDown (0x1UL)          /*!< Up and down counter, center-aligned PWM duty cycle                   */


/* PWM_COUNTERTOP: Value up to which the pulse generator counter counts */
  #define PWM_COUNTERTOP_ResetValue (0x000003FFUL)   /*!< Reset value of COUNTERTOP register.                                  */

/* COUNTERTOP @Bits 0..14 : Value up to which the pulse generator counter counts. This register is ignored when
                            DECODER.MODE=WaveForm and only values from RAM are used. */

  #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL)        /*!< Position of COUNTERTOP field.                                        */
  #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field.         */
  #define PWM_COUNTERTOP_COUNTERTOP_Min (0x0003UL)   /*!< Min value of COUNTERTOP field.                                       */
  #define PWM_COUNTERTOP_COUNTERTOP_Max (0x7FFFUL)   /*!< Max size of COUNTERTOP field.                                        */


/* PWM_PRESCALER: Configuration for PWM_CLK */
  #define PWM_PRESCALER_ResetValue (0x00000000UL)    /*!< Reset value of PRESCALER register.                                   */

/* PRESCALER @Bits 0..2 : Prescaler of PWM_CLK */
  #define PWM_PRESCALER_PRESCALER_Pos (0UL)          /*!< Position of PRESCALER field.                                         */
  #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field.                 */
  #define PWM_PRESCALER_PRESCALER_Min (0x0UL)        /*!< Min enumerator value of PRESCALER field.                             */
  #define PWM_PRESCALER_PRESCALER_Max (0x7UL)        /*!< Max enumerator value of PRESCALER field.                             */
  #define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL)      /*!< Divide by 1 (16 MHz)                                                 */
  #define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL)      /*!< Divide by 2 (8 MHz)                                                  */
  #define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL)      /*!< Divide by 4 (4 MHz)                                                  */
  #define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL)      /*!< Divide by 8 (2 MHz)                                                  */
  #define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL)     /*!< Divide by 16 (1 MHz)                                                 */
  #define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL)     /*!< Divide by 32 (500 kHz)                                               */
  #define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL)     /*!< Divide by 64 (250 kHz)                                               */
  #define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL)    /*!< Divide by 128 (125 kHz)                                              */


/* PWM_DECODER: Configuration of the decoder */
  #define PWM_DECODER_ResetValue (0x00000000UL)      /*!< Reset value of DECODER register.                                     */

/* LOAD @Bits 0..1 : How a sequence is read from RAM and spread to the compare register */
  #define PWM_DECODER_LOAD_Pos (0UL)                 /*!< Position of LOAD field.                                              */
  #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field.                                    */
  #define PWM_DECODER_LOAD_Min (0x0UL)               /*!< Min enumerator value of LOAD field.                                  */
  #define PWM_DECODER_LOAD_Max (0x3UL)               /*!< Max enumerator value of LOAD field.                                  */
  #define PWM_DECODER_LOAD_Common (0x0UL)            /*!< 1st half word (16-bit) used in all PWM channels 0..3                 */
  #define PWM_DECODER_LOAD_Grouped (0x1UL)           /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3*/
  #define PWM_DECODER_LOAD_Individual (0x2UL)        /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3        */
  #define PWM_DECODER_LOAD_WaveForm (0x3UL)          /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP  */

/* MODE @Bit 8 : Selects source for advancing the active sequence */
  #define PWM_DECODER_MODE_Pos (8UL)                 /*!< Position of MODE field.                                              */
  #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field.                                    */
  #define PWM_DECODER_MODE_Min (0x0UL)               /*!< Min enumerator value of MODE field.                                  */
  #define PWM_DECODER_MODE_Max (0x1UL)               /*!< Max enumerator value of MODE field.                                  */
  #define PWM_DECODER_MODE_RefreshCount (0x0UL)      /*!< SEQ[n].REFRESH is used to determine loading internal compare
                                                          registers*/
  #define PWM_DECODER_MODE_NextStep (0x1UL)          /*!< NEXTSTEP task causes a new value to be loaded to internal compare
                                                          registers*/


/* PWM_LOOP: Number of playbacks of a loop */
  #define PWM_LOOP_ResetValue (0x00000000UL)         /*!< Reset value of LOOP register.                                        */

/* CNT @Bits 0..15 : Number of playbacks of pattern cycles */
  #define PWM_LOOP_CNT_Pos (0UL)                     /*!< Position of CNT field.                                               */
  #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field.                                          */
  #define PWM_LOOP_CNT_Min (0x0UL)                   /*!< Min enumerator value of CNT field.                                   */
  #define PWM_LOOP_CNT_Max (0x0UL)                   /*!< Max enumerator value of CNT field.                                   */
  #define PWM_LOOP_CNT_Disabled (0x0000UL)           /*!< Looping disabled (stop at the end of the sequence)                   */


/* PWM_IDLEOUT: Configure the output value on the PWM channel during idle */
  #define PWM_IDLEOUT_ResetValue (0x00000000UL)      /*!< Reset value of IDLEOUT register.                                     */

/* VAL0 @Bit 0 : Idle output value for PWM channel [0] */
  #define PWM_IDLEOUT_VAL0_Pos (0UL)                 /*!< Position of VAL0 field.                                              */
  #define PWM_IDLEOUT_VAL0_Msk (0x1UL << PWM_IDLEOUT_VAL0_Pos) /*!< Bit mask of VAL0 field.                                    */

/* VAL1 @Bit 1 : Idle output value for PWM channel [1] */
  #define PWM_IDLEOUT_VAL1_Pos (1UL)                 /*!< Position of VAL1 field.                                              */
  #define PWM_IDLEOUT_VAL1_Msk (0x1UL << PWM_IDLEOUT_VAL1_Pos) /*!< Bit mask of VAL1 field.                                    */

/* VAL2 @Bit 2 : Idle output value for PWM channel [2] */
  #define PWM_IDLEOUT_VAL2_Pos (2UL)                 /*!< Position of VAL2 field.                                              */
  #define PWM_IDLEOUT_VAL2_Msk (0x1UL << PWM_IDLEOUT_VAL2_Pos) /*!< Bit mask of VAL2 field.                                    */

/* VAL3 @Bit 3 : Idle output value for PWM channel [3] */
  #define PWM_IDLEOUT_VAL3_Pos (3UL)                 /*!< Position of VAL3 field.                                              */
  #define PWM_IDLEOUT_VAL3_Msk (0x1UL << PWM_IDLEOUT_VAL3_Pos) /*!< Bit mask of VAL3 field.                                    */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           QDEC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ==================================================== Struct QDEC_PSEL ===================================================== */
/**
  * @brief PSEL [QDEC_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  LED;                               /*!< (@ 0x00000000) Pin select for LED signal                             */
  __IOM uint32_t  A;                                 /*!< (@ 0x00000004) Pin select for A signal                               */
  __IOM uint32_t  B;                                 /*!< (@ 0x00000008) Pin select for B signal                               */
} NRF_QDEC_PSEL_Type;                                /*!< Size = 12 (0x00C)                                                    */

/* QDEC_PSEL_LED: Pin select for LED signal */
  #define QDEC_PSEL_LED_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of LED register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define QDEC_PSEL_LED_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define QDEC_PSEL_LED_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define QDEC_PSEL_LED_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define QDEC_PSEL_LED_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define QDEC_PSEL_LED_PORT_Msk (0x7UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define QDEC_PSEL_LED_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define QDEC_PSEL_LED_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define QDEC_PSEL_LED_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define QDEC_PSEL_LED_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define QDEC_PSEL_LED_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define QDEC_PSEL_LED_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define QDEC_PSEL_LED_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* QDEC_PSEL_A: Pin select for A signal */
  #define QDEC_PSEL_A_ResetValue (0xFFFFFFFFUL)      /*!< Reset value of A register.                                           */

/* PIN @Bits 0..4 : Pin number */
  #define QDEC_PSEL_A_PIN_Pos (0UL)                  /*!< Position of PIN field.                                               */
  #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field.                                      */
  #define QDEC_PSEL_A_PIN_Min (0x00UL)               /*!< Min value of PIN field.                                              */
  #define QDEC_PSEL_A_PIN_Max (0x1FUL)               /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define QDEC_PSEL_A_PORT_Pos (5UL)                 /*!< Position of PORT field.                                              */
  #define QDEC_PSEL_A_PORT_Msk (0x7UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field.                                    */
  #define QDEC_PSEL_A_PORT_Min (0x0UL)               /*!< Min value of PORT field.                                             */
  #define QDEC_PSEL_A_PORT_Max (0x7UL)               /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define QDEC_PSEL_A_CONNECT_Pos (31UL)             /*!< Position of CONNECT field.                                           */
  #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field.                           */
  #define QDEC_PSEL_A_CONNECT_Min (0x0UL)            /*!< Min enumerator value of CONNECT field.                               */
  #define QDEC_PSEL_A_CONNECT_Max (0x1UL)            /*!< Max enumerator value of CONNECT field.                               */
  #define QDEC_PSEL_A_CONNECT_Disconnected (0x1UL)   /*!< Disconnect                                                           */
  #define QDEC_PSEL_A_CONNECT_Connected (0x0UL)      /*!< Connect                                                              */


/* QDEC_PSEL_B: Pin select for B signal */
  #define QDEC_PSEL_B_ResetValue (0xFFFFFFFFUL)      /*!< Reset value of B register.                                           */

/* PIN @Bits 0..4 : Pin number */
  #define QDEC_PSEL_B_PIN_Pos (0UL)                  /*!< Position of PIN field.                                               */
  #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field.                                      */
  #define QDEC_PSEL_B_PIN_Min (0x00UL)               /*!< Min value of PIN field.                                              */
  #define QDEC_PSEL_B_PIN_Max (0x1FUL)               /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define QDEC_PSEL_B_PORT_Pos (5UL)                 /*!< Position of PORT field.                                              */
  #define QDEC_PSEL_B_PORT_Msk (0x7UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field.                                    */
  #define QDEC_PSEL_B_PORT_Min (0x0UL)               /*!< Min value of PORT field.                                             */
  #define QDEC_PSEL_B_PORT_Max (0x7UL)               /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define QDEC_PSEL_B_CONNECT_Pos (31UL)             /*!< Position of CONNECT field.                                           */
  #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field.                           */
  #define QDEC_PSEL_B_CONNECT_Min (0x0UL)            /*!< Min enumerator value of CONNECT field.                               */
  #define QDEC_PSEL_B_CONNECT_Max (0x1UL)            /*!< Max enumerator value of CONNECT field.                               */
  #define QDEC_PSEL_B_CONNECT_Disconnected (0x1UL)   /*!< Disconnect                                                           */
  #define QDEC_PSEL_B_CONNECT_Connected (0x0UL)      /*!< Connect                                                              */


/* ======================================================= Struct QDEC ======================================================= */
/**
  * @brief Quadrature Decoder
  */
  typedef struct {                                   /*!< QDEC Structure                                                       */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Task starting the quadrature decoder                  */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Task stopping the quadrature decoder                  */
    __OM uint32_t TASKS_READCLRACC;                  /*!< (@ 0x00000008) Read and clear ACC and ACCDBL                         */
    __OM uint32_t TASKS_RDCLRACC;                    /*!< (@ 0x0000000C) Read and clear ACC                                    */
    __OM uint32_t TASKS_RDCLRDBL;                    /*!< (@ 0x00000010) Read and clear ACCDBL                                 */
    __IM uint32_t RESERVED[27];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_READCLRACC;             /*!< (@ 0x00000088) Subscribe configuration for task READCLRACC           */
    __IOM uint32_t SUBSCRIBE_RDCLRACC;               /*!< (@ 0x0000008C) Subscribe configuration for task RDCLRACC             */
    __IOM uint32_t SUBSCRIBE_RDCLRDBL;               /*!< (@ 0x00000090) Subscribe configuration for task RDCLRDBL             */
    __IM uint32_t RESERVED1[27];
    __IOM uint32_t EVENTS_SAMPLERDY;                 /*!< (@ 0x00000100) Event being generated for every new sample value
                                                                         written to the SAMPLE register*/
    __IOM uint32_t EVENTS_REPORTRDY;                 /*!< (@ 0x00000104) Non-null report ready                                 */
    __IOM uint32_t EVENTS_ACCOF;                     /*!< (@ 0x00000108) ACC or ACCDBL register overflow                       */
    __IOM uint32_t EVENTS_DBLRDY;                    /*!< (@ 0x0000010C) Double displacement(s) detected                       */
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000110) QDEC has been stopped                                 */
    __IM uint32_t RESERVED2[27];
    __IOM uint32_t PUBLISH_SAMPLERDY;                /*!< (@ 0x00000180) Publish configuration for event SAMPLERDY             */
    __IOM uint32_t PUBLISH_REPORTRDY;                /*!< (@ 0x00000184) Publish configuration for event REPORTRDY             */
    __IOM uint32_t PUBLISH_ACCOF;                    /*!< (@ 0x00000188) Publish configuration for event ACCOF                 */
    __IOM uint32_t PUBLISH_DBLRDY;                   /*!< (@ 0x0000018C) Publish configuration for event DBLRDY                */
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000190) Publish configuration for event STOPPED               */
    __IM uint32_t RESERVED3[27];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED4[64];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED5[125];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable the quadrature decoder                         */
    __IOM uint32_t LEDPOL;                           /*!< (@ 0x00000504) LED output pin polarity                               */
    __IOM uint32_t SAMPLEPER;                        /*!< (@ 0x00000508) Sample period                                         */
    __IM int32_t  SAMPLE;                            /*!< (@ 0x0000050C) Motion sample value                                   */
    __IOM uint32_t REPORTPER;                        /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY and
                                                                         DBLRDY events can be generated*/
    __IM int32_t  ACC;                               /*!< (@ 0x00000514) Register accumulating the valid transitions           */
    __IM int32_t  ACCREAD;                           /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the READCLRACC
                                                                         or RDCLRACC task*/
    __IOM NRF_QDEC_PSEL_Type PSEL;                   /*!< (@ 0x0000051C) (unspecified)                                         */
    __IOM uint32_t DBFEN;                            /*!< (@ 0x00000528) Enable input debounce filters                         */
    __IM uint32_t RESERVED6[5];
    __IOM uint32_t LEDPRE;                           /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling  */
    __IM uint32_t ACCDBL;                            /*!< (@ 0x00000544) Register accumulating the number of detected double
                                                                         transitions*/
    __IM uint32_t ACCDBLREAD;                        /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC or
                                                                         RDCLRDBL task*/
  } NRF_QDEC_Type;                                   /*!< Size = 1356 (0x54C)                                                  */

/* QDEC_TASKS_START: Task starting the quadrature decoder */
  #define QDEC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Task starting the quadrature decoder */
  #define QDEC_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
  #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
  #define QDEC_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
  #define QDEC_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
  #define QDEC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */


/* QDEC_TASKS_STOP: Task stopping the quadrature decoder */
  #define QDEC_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Task stopping the quadrature decoder */
  #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
  #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
  #define QDEC_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
  #define QDEC_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
  #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */


/* QDEC_TASKS_READCLRACC: Read and clear ACC and ACCDBL */
  #define QDEC_TASKS_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_READCLRACC register.                       */

/* TASKS_READCLRACC @Bit 0 : Read and clear ACC and ACCDBL */
  #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field.                            */
  #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of
                                                                            TASKS_READCLRACC field.*/
  #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_READCLRACC field.              */
  #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_READCLRACC field.              */
  #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (0x1UL) /*!< Trigger task                                             */


/* QDEC_TASKS_RDCLRACC: Read and clear ACC */
  #define QDEC_TASKS_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRACC register.                           */

/* TASKS_RDCLRACC @Bit 0 : Read and clear ACC */
  #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field.                                  */
  #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of
                                                                            TASKS_RDCLRACC field.*/
  #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRACC field.                    */
  #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRACC field.                    */
  #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (0x1UL) /*!< Trigger task                                                 */


/* QDEC_TASKS_RDCLRDBL: Read and clear ACCDBL */
  #define QDEC_TASKS_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRDBL register.                           */

/* TASKS_RDCLRDBL @Bit 0 : Read and clear ACCDBL */
  #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field.                                  */
  #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of
                                                                            TASKS_RDCLRDBL field.*/
  #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRDBL field.                    */
  #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRDBL field.                    */
  #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (0x1UL) /*!< Trigger task                                                 */


/* QDEC_SUBSCRIBE_START: Subscribe configuration for task START */
  #define QDEC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define QDEC_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define QDEC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define QDEC_SUBSCRIBE_START_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define QDEC_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define QDEC_SUBSCRIBE_START_EN_Msk (0x1UL << QDEC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
  #define QDEC_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define QDEC_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* QDEC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define QDEC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define QDEC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define QDEC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define QDEC_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define QDEC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define QDEC_SUBSCRIBE_STOP_EN_Msk (0x1UL << QDEC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
  #define QDEC_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define QDEC_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* QDEC_SUBSCRIBE_READCLRACC: Subscribe configuration for task READCLRACC */
  #define QDEC_SUBSCRIBE_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_READCLRACC register.               */

/* CHIDX @Bits 0..7 : DPPI channel that task READCLRACC will subscribe to */
  #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_SUBSCRIBE_READCLRACC_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define QDEC_SUBSCRIBE_READCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_READCLRACC_EN_Pos) /*!< Bit mask of EN field.              */
  #define QDEC_SUBSCRIBE_READCLRACC_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_READCLRACC_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_READCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription                                              */
  #define QDEC_SUBSCRIBE_READCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription                                                */


/* QDEC_SUBSCRIBE_RDCLRACC: Subscribe configuration for task RDCLRACC */
  #define QDEC_SUBSCRIBE_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRACC register.                   */

/* CHIDX @Bits 0..7 : DPPI channel that task RDCLRACC will subscribe to */
  #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_SUBSCRIBE_RDCLRACC_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define QDEC_SUBSCRIBE_RDCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRACC_EN_Pos) /*!< Bit mask of EN field.                  */
  #define QDEC_SUBSCRIBE_RDCLRACC_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_RDCLRACC_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_RDCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define QDEC_SUBSCRIBE_RDCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* QDEC_SUBSCRIBE_RDCLRDBL: Subscribe configuration for task RDCLRDBL */
  #define QDEC_SUBSCRIBE_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRDBL register.                   */

/* CHIDX @Bits 0..7 : DPPI channel that task RDCLRDBL will subscribe to */
  #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos) /*!< Bit mask of EN field.                  */
  #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* QDEC_EVENTS_SAMPLERDY: Event being generated for every new sample value written to the SAMPLE register */
  #define QDEC_EVENTS_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SAMPLERDY register.                       */

/* EVENTS_SAMPLERDY @Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
  #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field.                            */
  #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of
                                                                            EVENTS_SAMPLERDY field.*/
  #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_SAMPLERDY field.              */
  #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_SAMPLERDY field.              */
  #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0x0UL) /*!< Event not generated                                 */
  #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (0x1UL) /*!< Event generated                                        */


/* QDEC_EVENTS_REPORTRDY: Non-null report ready */
  #define QDEC_EVENTS_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_REPORTRDY register.                       */

/* EVENTS_REPORTRDY @Bit 0 : Non-null report ready */
  #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field.                            */
  #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of
                                                                            EVENTS_REPORTRDY field.*/
  #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_REPORTRDY field.              */
  #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_REPORTRDY field.              */
  #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0x0UL) /*!< Event not generated                                 */
  #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (0x1UL) /*!< Event generated                                        */


/* QDEC_EVENTS_ACCOF: ACC or ACCDBL register overflow */
  #define QDEC_EVENTS_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACCOF register.                               */

/* EVENTS_ACCOF @Bit 0 : ACC or ACCDBL register overflow */
  #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL)   /*!< Position of EVENTS_ACCOF field.                                      */
  #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field.*/
  #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACCOF field.                          */
  #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACCOF field.                          */
  #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (0x1UL) /*!< Event generated                                                */


/* QDEC_EVENTS_DBLRDY: Double displacement(s) detected */
  #define QDEC_EVENTS_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DBLRDY register.                             */

/* EVENTS_DBLRDY @Bit 0 : Double displacement(s) detected */
  #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field.                                     */
  #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY
                                                                            field.*/
  #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DBLRDY field.                       */
  #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DBLRDY field.                       */
  #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (0x1UL) /*!< Event generated                                              */


/* QDEC_EVENTS_STOPPED: QDEC has been stopped */
  #define QDEC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */

/* EVENTS_STOPPED @Bit 0 : QDEC has been stopped */
  #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
  #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
                                                                            EVENTS_STOPPED field.*/
  #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
  #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
  #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */


/* QDEC_PUBLISH_SAMPLERDY: Publish configuration for event SAMPLERDY */
  #define QDEC_PUBLISH_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SAMPLERDY register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event SAMPLERDY will publish to */
  #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_PUBLISH_SAMPLERDY_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define QDEC_PUBLISH_SAMPLERDY_EN_Msk (0x1UL << QDEC_PUBLISH_SAMPLERDY_EN_Pos) /*!< Bit mask of EN field.                    */
  #define QDEC_PUBLISH_SAMPLERDY_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_SAMPLERDY_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_SAMPLERDY_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define QDEC_PUBLISH_SAMPLERDY_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* QDEC_PUBLISH_REPORTRDY: Publish configuration for event REPORTRDY */
  #define QDEC_PUBLISH_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_REPORTRDY register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event REPORTRDY will publish to */
  #define QDEC_PUBLISH_REPORTRDY_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define QDEC_PUBLISH_REPORTRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_REPORTRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define QDEC_PUBLISH_REPORTRDY_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define QDEC_PUBLISH_REPORTRDY_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_PUBLISH_REPORTRDY_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define QDEC_PUBLISH_REPORTRDY_EN_Msk (0x1UL << QDEC_PUBLISH_REPORTRDY_EN_Pos) /*!< Bit mask of EN field.                    */
  #define QDEC_PUBLISH_REPORTRDY_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_REPORTRDY_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_REPORTRDY_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define QDEC_PUBLISH_REPORTRDY_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* QDEC_PUBLISH_ACCOF: Publish configuration for event ACCOF */
  #define QDEC_PUBLISH_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACCOF register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event ACCOF will publish to */
  #define QDEC_PUBLISH_ACCOF_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define QDEC_PUBLISH_ACCOF_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_ACCOF_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define QDEC_PUBLISH_ACCOF_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define QDEC_PUBLISH_ACCOF_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_PUBLISH_ACCOF_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define QDEC_PUBLISH_ACCOF_EN_Msk (0x1UL << QDEC_PUBLISH_ACCOF_EN_Pos) /*!< Bit mask of EN field.                            */
  #define QDEC_PUBLISH_ACCOF_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_ACCOF_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_ACCOF_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define QDEC_PUBLISH_ACCOF_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* QDEC_PUBLISH_DBLRDY: Publish configuration for event DBLRDY */
  #define QDEC_PUBLISH_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DBLRDY register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event DBLRDY will publish to */
  #define QDEC_PUBLISH_DBLRDY_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define QDEC_PUBLISH_DBLRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_DBLRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define QDEC_PUBLISH_DBLRDY_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define QDEC_PUBLISH_DBLRDY_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_PUBLISH_DBLRDY_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define QDEC_PUBLISH_DBLRDY_EN_Msk (0x1UL << QDEC_PUBLISH_DBLRDY_EN_Pos) /*!< Bit mask of EN field.                          */
  #define QDEC_PUBLISH_DBLRDY_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_DBLRDY_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_DBLRDY_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define QDEC_PUBLISH_DBLRDY_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* QDEC_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define QDEC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define QDEC_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define QDEC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define QDEC_PUBLISH_STOPPED_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define QDEC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define QDEC_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define QDEC_PUBLISH_STOPPED_EN_Msk (0x1UL << QDEC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
  #define QDEC_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define QDEC_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define QDEC_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* QDEC_SHORTS: Shortcuts between local events and tasks */
  #define QDEC_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* REPORTRDY_READCLRACC @Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
  #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field.                              */
  #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of
                                                                            REPORTRDY_READCLRACC field.*/
  #define QDEC_SHORTS_REPORTRDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_READCLRACC field.                */
  #define QDEC_SHORTS_REPORTRDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_READCLRACC field.                */
  #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut                                              */
  #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut                                                */

/* SAMPLERDY_STOP @Bit 1 : Shortcut between event SAMPLERDY and task STOP */
  #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL)       /*!< Position of SAMPLERDY_STOP field.                                    */
  #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field.      */
  #define QDEC_SHORTS_SAMPLERDY_STOP_Min (0x0UL)     /*!< Min enumerator value of SAMPLERDY_STOP field.                        */
  #define QDEC_SHORTS_SAMPLERDY_STOP_Max (0x1UL)     /*!< Max enumerator value of SAMPLERDY_STOP field.                        */
  #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* REPORTRDY_RDCLRACC @Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
  #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL)   /*!< Position of REPORTRDY_RDCLRACC field.                                */
  #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC
                                                                            field.*/
  #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_RDCLRACC field.                    */
  #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_RDCLRACC field.                    */
  #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0x0UL) /*!< Disable shortcut                                                */
  #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (0x1UL) /*!< Enable shortcut                                                  */

/* REPORTRDY_STOP @Bit 3 : Shortcut between event REPORTRDY and task STOP */
  #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL)       /*!< Position of REPORTRDY_STOP field.                                    */
  #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field.      */
  #define QDEC_SHORTS_REPORTRDY_STOP_Min (0x0UL)     /*!< Min enumerator value of REPORTRDY_STOP field.                        */
  #define QDEC_SHORTS_REPORTRDY_STOP_Max (0x1UL)     /*!< Max enumerator value of REPORTRDY_STOP field.                        */
  #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* DBLRDY_RDCLRDBL @Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
  #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL)      /*!< Position of DBLRDY_RDCLRDBL field.                                   */
  #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field.   */
  #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Min (0x0UL)    /*!< Min enumerator value of DBLRDY_RDCLRDBL field.                       */
  #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Max (0x1UL)    /*!< Max enumerator value of DBLRDY_RDCLRDBL field.                       */
  #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* DBLRDY_STOP @Bit 5 : Shortcut between event DBLRDY and task STOP */
  #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL)          /*!< Position of DBLRDY_STOP field.                                       */
  #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field.               */
  #define QDEC_SHORTS_DBLRDY_STOP_Min (0x0UL)        /*!< Min enumerator value of DBLRDY_STOP field.                           */
  #define QDEC_SHORTS_DBLRDY_STOP_Max (0x1UL)        /*!< Max enumerator value of DBLRDY_STOP field.                           */
  #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
  #define QDEC_SHORTS_DBLRDY_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */

/* SAMPLERDY_READCLRACC @Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
  #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field.                              */
  #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of
                                                                            SAMPLERDY_READCLRACC field.*/
  #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY_READCLRACC field.                */
  #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY_READCLRACC field.                */
  #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut                                              */
  #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut                                                */


/* QDEC_INTENSET: Enable interrupt */
  #define QDEC_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* SAMPLERDY @Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
  #define QDEC_INTENSET_SAMPLERDY_Pos (0UL)          /*!< Position of SAMPLERDY field.                                         */
  #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field.                 */
  #define QDEC_INTENSET_SAMPLERDY_Min (0x0UL)        /*!< Min enumerator value of SAMPLERDY field.                             */
  #define QDEC_INTENSET_SAMPLERDY_Max (0x1UL)        /*!< Max enumerator value of SAMPLERDY field.                             */
  #define QDEC_INTENSET_SAMPLERDY_Set (0x1UL)        /*!< Enable                                                               */
  #define QDEC_INTENSET_SAMPLERDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define QDEC_INTENSET_SAMPLERDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* REPORTRDY @Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
  #define QDEC_INTENSET_REPORTRDY_Pos (1UL)          /*!< Position of REPORTRDY field.                                         */
  #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field.                 */
  #define QDEC_INTENSET_REPORTRDY_Min (0x0UL)        /*!< Min enumerator value of REPORTRDY field.                             */
  #define QDEC_INTENSET_REPORTRDY_Max (0x1UL)        /*!< Max enumerator value of REPORTRDY field.                             */
  #define QDEC_INTENSET_REPORTRDY_Set (0x1UL)        /*!< Enable                                                               */
  #define QDEC_INTENSET_REPORTRDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define QDEC_INTENSET_REPORTRDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* ACCOF @Bit 2 : Write '1' to enable interrupt for event ACCOF */
  #define QDEC_INTENSET_ACCOF_Pos (2UL)              /*!< Position of ACCOF field.                                             */
  #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field.                             */
  #define QDEC_INTENSET_ACCOF_Min (0x0UL)            /*!< Min enumerator value of ACCOF field.                                 */
  #define QDEC_INTENSET_ACCOF_Max (0x1UL)            /*!< Max enumerator value of ACCOF field.                                 */
  #define QDEC_INTENSET_ACCOF_Set (0x1UL)            /*!< Enable                                                               */
  #define QDEC_INTENSET_ACCOF_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define QDEC_INTENSET_ACCOF_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* DBLRDY @Bit 3 : Write '1' to enable interrupt for event DBLRDY */
  #define QDEC_INTENSET_DBLRDY_Pos (3UL)             /*!< Position of DBLRDY field.                                            */
  #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field.                          */
  #define QDEC_INTENSET_DBLRDY_Min (0x0UL)           /*!< Min enumerator value of DBLRDY field.                                */
  #define QDEC_INTENSET_DBLRDY_Max (0x1UL)           /*!< Max enumerator value of DBLRDY field.                                */
  #define QDEC_INTENSET_DBLRDY_Set (0x1UL)           /*!< Enable                                                               */
  #define QDEC_INTENSET_DBLRDY_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define QDEC_INTENSET_DBLRDY_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 4 : Write '1' to enable interrupt for event STOPPED */
  #define QDEC_INTENSET_STOPPED_Pos (4UL)            /*!< Position of STOPPED field.                                           */
  #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define QDEC_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define QDEC_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define QDEC_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
  #define QDEC_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define QDEC_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* QDEC_INTENCLR: Disable interrupt */
  #define QDEC_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* SAMPLERDY @Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
  #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL)          /*!< Position of SAMPLERDY field.                                         */
  #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field.                 */
  #define QDEC_INTENCLR_SAMPLERDY_Min (0x0UL)        /*!< Min enumerator value of SAMPLERDY field.                             */
  #define QDEC_INTENCLR_SAMPLERDY_Max (0x1UL)        /*!< Max enumerator value of SAMPLERDY field.                             */
  #define QDEC_INTENCLR_SAMPLERDY_Clear (0x1UL)      /*!< Disable                                                              */
  #define QDEC_INTENCLR_SAMPLERDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define QDEC_INTENCLR_SAMPLERDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* REPORTRDY @Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
  #define QDEC_INTENCLR_REPORTRDY_Pos (1UL)          /*!< Position of REPORTRDY field.                                         */
  #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field.                 */
  #define QDEC_INTENCLR_REPORTRDY_Min (0x0UL)        /*!< Min enumerator value of REPORTRDY field.                             */
  #define QDEC_INTENCLR_REPORTRDY_Max (0x1UL)        /*!< Max enumerator value of REPORTRDY field.                             */
  #define QDEC_INTENCLR_REPORTRDY_Clear (0x1UL)      /*!< Disable                                                              */
  #define QDEC_INTENCLR_REPORTRDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define QDEC_INTENCLR_REPORTRDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* ACCOF @Bit 2 : Write '1' to disable interrupt for event ACCOF */
  #define QDEC_INTENCLR_ACCOF_Pos (2UL)              /*!< Position of ACCOF field.                                             */
  #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field.                             */
  #define QDEC_INTENCLR_ACCOF_Min (0x0UL)            /*!< Min enumerator value of ACCOF field.                                 */
  #define QDEC_INTENCLR_ACCOF_Max (0x1UL)            /*!< Max enumerator value of ACCOF field.                                 */
  #define QDEC_INTENCLR_ACCOF_Clear (0x1UL)          /*!< Disable                                                              */
  #define QDEC_INTENCLR_ACCOF_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define QDEC_INTENCLR_ACCOF_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* DBLRDY @Bit 3 : Write '1' to disable interrupt for event DBLRDY */
  #define QDEC_INTENCLR_DBLRDY_Pos (3UL)             /*!< Position of DBLRDY field.                                            */
  #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field.                          */
  #define QDEC_INTENCLR_DBLRDY_Min (0x0UL)           /*!< Min enumerator value of DBLRDY field.                                */
  #define QDEC_INTENCLR_DBLRDY_Max (0x1UL)           /*!< Max enumerator value of DBLRDY field.                                */
  #define QDEC_INTENCLR_DBLRDY_Clear (0x1UL)         /*!< Disable                                                              */
  #define QDEC_INTENCLR_DBLRDY_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define QDEC_INTENCLR_DBLRDY_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 4 : Write '1' to disable interrupt for event STOPPED */
  #define QDEC_INTENCLR_STOPPED_Pos (4UL)            /*!< Position of STOPPED field.                                           */
  #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define QDEC_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define QDEC_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define QDEC_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
  #define QDEC_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define QDEC_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* QDEC_ENABLE: Enable the quadrature decoder */
  #define QDEC_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bit 0 : Enable or disable the quadrature decoder */
  #define QDEC_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
  #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
  #define QDEC_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
  #define QDEC_ENABLE_ENABLE_Max (0x1UL)             /*!< Max enumerator value of ENABLE field.                                */
  #define QDEC_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable                                                              */
  #define QDEC_ENABLE_ENABLE_Enabled (0x1UL)         /*!< Enable                                                               */


/* QDEC_LEDPOL: LED output pin polarity */
  #define QDEC_LEDPOL_ResetValue (0x00000000UL)      /*!< Reset value of LEDPOL register.                                      */

/* LEDPOL @Bit 0 : LED output pin polarity */
  #define QDEC_LEDPOL_LEDPOL_Pos (0UL)               /*!< Position of LEDPOL field.                                            */
  #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field.                              */
  #define QDEC_LEDPOL_LEDPOL_Min (0x0UL)             /*!< Min enumerator value of LEDPOL field.                                */
  #define QDEC_LEDPOL_LEDPOL_Max (0x1UL)             /*!< Max enumerator value of LEDPOL field.                                */
  #define QDEC_LEDPOL_LEDPOL_ActiveLow (0x0UL)       /*!< Led active on output pin low                                         */
  #define QDEC_LEDPOL_LEDPOL_ActiveHigh (0x1UL)      /*!< Led active on output pin high                                        */


/* QDEC_SAMPLEPER: Sample period */
  #define QDEC_SAMPLEPER_ResetValue (0x00000000UL)   /*!< Reset value of SAMPLEPER register.                                   */

/* SAMPLEPER @Bits 0..3 : Sample period. The SAMPLE register will be updated for every new sample */
  #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL)         /*!< Position of SAMPLEPER field.                                         */
  #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field.               */
  #define QDEC_SAMPLEPER_SAMPLEPER_Min (0x0UL)       /*!< Min enumerator value of SAMPLEPER field.                             */
  #define QDEC_SAMPLEPER_SAMPLEPER_Max (0xAUL)       /*!< Max enumerator value of SAMPLEPER field.                             */
  #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x0UL)     /*!< 128 us                                                               */
  #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x1UL)     /*!< 256 us                                                               */
  #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x2UL)     /*!< 512 us                                                               */
  #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x3UL)    /*!< 1024 us                                                              */
  #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x4UL)    /*!< 2048 us                                                              */
  #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x5UL)    /*!< 4096 us                                                              */
  #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x6UL)    /*!< 8192 us                                                              */
  #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x7UL)   /*!< 16384 us                                                             */
  #define QDEC_SAMPLEPER_SAMPLEPER_32ms (0x8UL)      /*!< 32768 us                                                             */
  #define QDEC_SAMPLEPER_SAMPLEPER_65ms (0x9UL)      /*!< 65536 us                                                             */
  #define QDEC_SAMPLEPER_SAMPLEPER_131ms (0xAUL)     /*!< 131072 us                                                            */


/* QDEC_SAMPLE: Motion sample value */
  #define QDEC_SAMPLE_ResetValue (0x00000000UL)      /*!< Reset value of SAMPLE register.                                      */

/* SAMPLE @Bits 0..31 : Last motion sample */
  #define QDEC_SAMPLE_SAMPLE_Pos (0UL)               /*!< Position of SAMPLE field.                                            */
  #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field.                       */
  #define QDEC_SAMPLE_SAMPLE_Min (0xFFFFFFFFUL)      /*!< Min value of SAMPLE field.                                           */
  #define QDEC_SAMPLE_SAMPLE_Max (0x00000002UL)      /*!< Max size of SAMPLE field.                                            */


/* QDEC_REPORTPER: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
  #define QDEC_REPORTPER_ResetValue (0x00000000UL)   /*!< Reset value of REPORTPER register.                                   */

/* REPORTPER @Bits 0..3 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY
                          events can be generated. */

  #define QDEC_REPORTPER_REPORTPER_Pos (0UL)         /*!< Position of REPORTPER field.                                         */
  #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field.               */
  #define QDEC_REPORTPER_REPORTPER_Min (0x0UL)       /*!< Min enumerator value of REPORTPER field.                             */
  #define QDEC_REPORTPER_REPORTPER_Max (0x8UL)       /*!< Max enumerator value of REPORTPER field.                             */
  #define QDEC_REPORTPER_REPORTPER_10Smpl (0x0UL)    /*!< 10 samples/report                                                    */
  #define QDEC_REPORTPER_REPORTPER_40Smpl (0x1UL)    /*!< 40 samples/report                                                    */
  #define QDEC_REPORTPER_REPORTPER_80Smpl (0x2UL)    /*!< 80 samples/report                                                    */
  #define QDEC_REPORTPER_REPORTPER_120Smpl (0x3UL)   /*!< 120 samples/report                                                   */
  #define QDEC_REPORTPER_REPORTPER_160Smpl (0x4UL)   /*!< 160 samples/report                                                   */
  #define QDEC_REPORTPER_REPORTPER_200Smpl (0x5UL)   /*!< 200 samples/report                                                   */
  #define QDEC_REPORTPER_REPORTPER_240Smpl (0x6UL)   /*!< 240 samples/report                                                   */
  #define QDEC_REPORTPER_REPORTPER_280Smpl (0x7UL)   /*!< 280 samples/report                                                   */
  #define QDEC_REPORTPER_REPORTPER_1Smpl (0x8UL)     /*!< 1 sample/report                                                      */


/* QDEC_ACC: Register accumulating the valid transitions */
  #define QDEC_ACC_ResetValue (0x00000000UL)         /*!< Reset value of ACC register.                                         */

/* ACC @Bits 0..31 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
  #define QDEC_ACC_ACC_Pos (0UL)                     /*!< Position of ACC field.                                               */
  #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field.                                      */
  #define QDEC_ACC_ACC_Min (0xFFFFFC00UL)            /*!< Min value of ACC field.                                              */
  #define QDEC_ACC_ACC_Max (0x000003FFUL)            /*!< Max size of ACC field.                                               */


/* QDEC_ACCREAD: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
  #define QDEC_ACCREAD_ResetValue (0x00000000UL)     /*!< Reset value of ACCREAD register.                                     */

/* ACCREAD @Bits 0..31 : Snapshot of the ACC register. */
  #define QDEC_ACCREAD_ACCREAD_Pos (0UL)             /*!< Position of ACCREAD field.                                           */
  #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field.                  */
  #define QDEC_ACCREAD_ACCREAD_Min (0xFFFFFC00UL)    /*!< Min value of ACCREAD field.                                          */
  #define QDEC_ACCREAD_ACCREAD_Max (0x000003FFUL)    /*!< Max size of ACCREAD field.                                           */


/* QDEC_DBFEN: Enable input debounce filters */
  #define QDEC_DBFEN_ResetValue (0x00000000UL)       /*!< Reset value of DBFEN register.                                       */

/* DBFEN @Bit 0 : Enable input debounce filters */
  #define QDEC_DBFEN_DBFEN_Pos (0UL)                 /*!< Position of DBFEN field.                                             */
  #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field.                                   */
  #define QDEC_DBFEN_DBFEN_Min (0x0UL)               /*!< Min enumerator value of DBFEN field.                                 */
  #define QDEC_DBFEN_DBFEN_Max (0x1UL)               /*!< Max enumerator value of DBFEN field.                                 */
  #define QDEC_DBFEN_DBFEN_Disabled (0x0UL)          /*!< Debounce input filters disabled                                      */
  #define QDEC_DBFEN_DBFEN_Enabled (0x1UL)           /*!< Debounce input filters enabled                                       */


/* QDEC_LEDPRE: Time period the LED is switched ON prior to sampling */
  #define QDEC_LEDPRE_ResetValue (0x00000010UL)      /*!< Reset value of LEDPRE register.                                      */

/* LEDPRE @Bits 0..8 : Period in us the LED is switched on prior to sampling */
  #define QDEC_LEDPRE_LEDPRE_Pos (0UL)               /*!< Position of LEDPRE field.                                            */
  #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field.                            */
  #define QDEC_LEDPRE_LEDPRE_Min (0x001UL)           /*!< Min value of LEDPRE field.                                           */
  #define QDEC_LEDPRE_LEDPRE_Max (0x1FFUL)           /*!< Max size of LEDPRE field.                                            */


/* QDEC_ACCDBL: Register accumulating the number of detected double transitions */
  #define QDEC_ACCDBL_ResetValue (0x00000000UL)      /*!< Reset value of ACCDBL register.                                      */

/* ACCDBL @Bits 0..3 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
  #define QDEC_ACCDBL_ACCDBL_Pos (0UL)               /*!< Position of ACCDBL field.                                            */
  #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field.                              */
  #define QDEC_ACCDBL_ACCDBL_Min (0x0UL)             /*!< Min value of ACCDBL field.                                           */
  #define QDEC_ACCDBL_ACCDBL_Max (0xFUL)             /*!< Max size of ACCDBL field.                                            */


/* QDEC_ACCDBLREAD: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
  #define QDEC_ACCDBLREAD_ResetValue (0x00000000UL)  /*!< Reset value of ACCDBLREAD register.                                  */

/* ACCDBLREAD @Bits 0..3 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is
                           triggered. */

  #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL)       /*!< Position of ACCDBLREAD field.                                        */
  #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field.          */
  #define QDEC_ACCDBLREAD_ACCDBLREAD_Min (0x0UL)     /*!< Min value of ACCDBLREAD field.                                       */
  #define QDEC_ACCDBLREAD_ACCDBLREAD_Max (0xFUL)     /*!< Max size of ACCDBLREAD field.                                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           RADIO                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ==================================================== Struct RADIO_PSEL ==================================================== */
/**
  * @brief PSEL [RADIO_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  DFEGPIO[8];                        /*!< (@ 0x00000000) Pin select for DFE pin n                              */
} NRF_RADIO_PSEL_Type;                               /*!< Size = 32 (0x020)                                                    */

/* RADIO_PSEL_DFEGPIO: Pin select for DFE pin n */
  #define RADIO_PSEL_DFEGPIO_MaxCount (8UL)          /*!< Max size of DFEGPIO[8] array.                                        */
  #define RADIO_PSEL_DFEGPIO_MaxIndex (7UL)          /*!< Max index of DFEGPIO[8] array.                                       */
  #define RADIO_PSEL_DFEGPIO_MinIndex (0UL)          /*!< Min index of DFEGPIO[8] array.                                       */
  #define RADIO_PSEL_DFEGPIO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DFEGPIO[8] register.                                */

/* PIN @Bits 0..4 : Pin number */
  #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL)           /*!< Position of PIN field.                                               */
  #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field.                        */
  #define RADIO_PSEL_DFEGPIO_PIN_Min (0x00UL)        /*!< Min value of PIN field.                                              */
  #define RADIO_PSEL_DFEGPIO_PIN_Max (0x1FUL)        /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..8 : Port number */
  #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL)          /*!< Position of PORT field.                                              */
  #define RADIO_PSEL_DFEGPIO_PORT_Msk (0xFUL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field.                      */
  #define RADIO_PSEL_DFEGPIO_PORT_Min (0x0UL)        /*!< Min value of PORT field.                                             */
  #define RADIO_PSEL_DFEGPIO_PORT_Max (0x1UL)        /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL)      /*!< Position of CONNECT field.                                           */
  #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field.             */
  #define RADIO_PSEL_DFEGPIO_CONNECT_Min (0x0UL)     /*!< Min enumerator value of CONNECT field.                               */
  #define RADIO_PSEL_DFEGPIO_CONNECT_Max (0x1UL)     /*!< Max enumerator value of CONNECT field.                               */
  #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                      */
  #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0x0UL) /*!< Connect                                                            */



/* ================================================= Struct RADIO_DFEPACKET ================================================== */
/**
  * @brief DFEPACKET [RADIO_DFEPACKET] DFE packet EasyDMA channel
  */
typedef struct {
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes to transfer                   */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
  __IM  uint32_t  CURRENTAMOUNT;                     /*!< (@ 0x0000000C) Number of bytes transferred in the current transaction*/
} NRF_RADIO_DFEPACKET_Type;                          /*!< Size = 16 (0x010)                                                    */

/* RADIO_DFEPACKET_PTR: Data pointer */
  #define RADIO_DFEPACKET_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register.                                      */

/* PTR @Bits 0..31 : Data pointer */
  #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL)          /*!< Position of PTR field.                                               */
  #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field.                */


/* RADIO_DFEPACKET_MAXCNT: Maximum number of bytes to transfer */
  #define RADIO_DFEPACKET_MAXCNT_ResetValue (0x00004000UL) /*!< Reset value of MAXCNT register.                                */

/* MAXCNT @Bits 0..15 : Maximum number of bytes to transfer */
  #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL)    /*!< Position of MAXCNT field.                                            */
  #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0xFFFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.     */


/* RADIO_DFEPACKET_AMOUNT: Number of bytes transferred in the last transaction */
  #define RADIO_DFEPACKET_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction */
  #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL)    /*!< Position of AMOUNT field.                                            */
  #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.     */


/* RADIO_DFEPACKET_CURRENTAMOUNT: Number of bytes transferred in the current transaction */
  #define RADIO_DFEPACKET_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register.                  */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the current transaction. Continuously updated. */
  #define RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field.                                        */
  #define RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of
                                                                            AMOUNT field.*/



/* ================================================== Struct RADIO_CSTONES =================================================== */
/**
  * @brief CSTONES [RADIO_CSTONES] (unspecified)
  */
typedef struct {
  __IOM uint32_t  MODE;                              /*!< (@ 0x00000000) Selects the mode(s) that are activated on the start
                                                                         signal*/
  __IOM uint32_t  NUMSAMPLES;                        /*!< (@ 0x00000004) Number of input samples at 2MHz sample rate           */
  __IOM uint32_t  NEXTFREQUENCY;                     /*!< (@ 0x00000008) The value of FREQUENCY that will be used in the next
                                                                         step*/
  __IOM uint32_t  FFOIN;                             /*!< (@ 0x0000000C) Override value of FFO (Fractional Frequency Offset) if
                                                                         not to be based on the frequency estimate derived from
                                                                         CnAcc (autocorrelation of the scaled input signal)
                                                                         value*/
  __IOM uint32_t  FFOSOURCE;                         /*!< (@ 0x00000010) Source of FFO                                         */
  __IOM uint32_t  FAEPEER;                           /*!< (@ 0x00000014) FAEPEER (Frequency Actuation Error) of peer if known.
                                                                         Used during Mode 0 steps.*/
  __IOM uint32_t  PHASESHIFT;                        /*!< (@ 0x00000018) Parameter used in TPM, provided by software           */
  __IOM uint32_t  NUMSAMPLESCOEFF;                   /*!< (@ 0x0000001C) Parameter used in TPM, provided by software           */
  __IM  uint32_t  PCT16;                             /*!< (@ 0x00000020) Mean magnitude and mean phase converted to IQ         */
  __IM  uint32_t  MAGPHASEMEAN;                      /*!< (@ 0x00000024) Mean magnitude and phase of the signal before it is
                                                                         converted to PCT16*/
  __IM  uint32_t  IQRAWMEAN;                         /*!< (@ 0x00000028) Mean of IQ values                                     */
  __IM  uint32_t  MAGSTD;                            /*!< (@ 0x0000002C) Magnitude standard deviation approximation            */
  __IM  uint32_t  CNACC;                             /*!< (@ 0x00000030) Output of the autocorrelation of the accumulated IQ
                                                                         signal*/
  __IM  uint32_t  FFOEST;                            /*!< (@ 0x00000034) FFO estimate                                          */
  __IOM uint32_t  DOWNSAMPLE;                        /*!< (@ 0x00000038) Turn on/off down sample of input IQ-signals           */
  __IM  uint32_t  FINETUNENEXT;                      /*!< (@ 0x0000003C) Number of full ADPLL finetune steps                   */
  __IM  uint32_t  CFOPHASE;                          /*!< (@ 0x00000040) Cordic output of CnAcc                                */
  __IM  uint32_t  FREQOFFSET;                        /*!< (@ 0x00000044) Frequency offset estimate                             */
  __IM  uint32_t  PCT11;                             /*!< (@ 0x00000048) Mean magnitude and mean phase converted to IQ. IQ
                                                                         values limited to [-1024,1023].*/
  __IM  uint32_t  LFAENEXT;                          /*!< (@ 0x0000004C) Quantization error between ADPLL frequency and the
                                                                         desired value of FFO * RF Frequency. Values limited to
                                                                         [-64,63] with units 7.6294 Hz.*/
} NRF_RADIO_CSTONES_Type;                            /*!< Size = 80 (0x050)                                                    */

/* RADIO_CSTONES_MODE: Selects the mode(s) that are activated on the start signal */
  #define RADIO_CSTONES_MODE_ResetValue (0x00000003UL) /*!< Reset value of MODE register.                                      */

/* TPM @Bit 0 : Enable or disable TPM */
  #define RADIO_CSTONES_MODE_TPM_Pos (0UL)           /*!< Position of TPM field.                                               */
  #define RADIO_CSTONES_MODE_TPM_Msk (0x1UL << RADIO_CSTONES_MODE_TPM_Pos) /*!< Bit mask of TPM field.                         */
  #define RADIO_CSTONES_MODE_TPM_Min (0x0UL)         /*!< Min enumerator value of TPM field.                                   */
  #define RADIO_CSTONES_MODE_TPM_Max (0x1UL)         /*!< Max enumerator value of TPM field.                                   */
  #define RADIO_CSTONES_MODE_TPM_Disabled (0x0UL)    /*!< TPM is disabled                                                      */
  #define RADIO_CSTONES_MODE_TPM_Enabled (0x1UL)     /*!< TPM is enabled                                                       */

/* TFM @Bit 1 : Enable or disable TFM */
  #define RADIO_CSTONES_MODE_TFM_Pos (1UL)           /*!< Position of TFM field.                                               */
  #define RADIO_CSTONES_MODE_TFM_Msk (0x1UL << RADIO_CSTONES_MODE_TFM_Pos) /*!< Bit mask of TFM field.                         */
  #define RADIO_CSTONES_MODE_TFM_Min (0x0UL)         /*!< Min enumerator value of TFM field.                                   */
  #define RADIO_CSTONES_MODE_TFM_Max (0x1UL)         /*!< Max enumerator value of TFM field.                                   */
  #define RADIO_CSTONES_MODE_TFM_Disabled (0x0UL)    /*!< TFM is disabled                                                      */
  #define RADIO_CSTONES_MODE_TFM_Enabled (0x1UL)     /*!< TFM is enabled                                                       */


/* RADIO_CSTONES_NUMSAMPLES: Number of input samples at 2MHz sample rate */
  #define RADIO_CSTONES_NUMSAMPLES_ResetValue (0x000000A0UL) /*!< Reset value of NUMSAMPLES register.                          */

/* NUMSAMPLES @Bits 0..7 : Maximum value supported is 160 */
  #define RADIO_CSTONES_NUMSAMPLES_NUMSAMPLES_Pos (0UL) /*!< Position of NUMSAMPLES field.                                     */
  #define RADIO_CSTONES_NUMSAMPLES_NUMSAMPLES_Msk (0xFFUL << RADIO_CSTONES_NUMSAMPLES_NUMSAMPLES_Pos) /*!< Bit mask of
                                                                            NUMSAMPLES field.*/


/* RADIO_CSTONES_NEXTFREQUENCY: The value of FREQUENCY that will be used in the next step */
  #define RADIO_CSTONES_NEXTFREQUENCY_ResetValue (0x00000000UL) /*!< Reset value of NEXTFREQUENCY register.                    */

/* NEXTFREQUENCY @Bits 0..6 : Frequency = 2400 + FREQUENCY (MHz) */
  #define RADIO_CSTONES_NEXTFREQUENCY_NEXTFREQUENCY_Pos (0UL) /*!< Position of NEXTFREQUENCY field.                            */
  #define RADIO_CSTONES_NEXTFREQUENCY_NEXTFREQUENCY_Msk (0x7FUL << RADIO_CSTONES_NEXTFREQUENCY_NEXTFREQUENCY_Pos) /*!< Bit mask
                                                                            of NEXTFREQUENCY field.*/


/* RADIO_CSTONES_FFOIN: Override value of FFO (Fractional Frequency Offset) if not to be based on the frequency estimate derived
                         from CnAcc (autocorrelation of the scaled input signal) value */

  #define RADIO_CSTONES_FFOIN_ResetValue (0x00000000UL) /*!< Reset value of FFOIN register.                                    */

/* FFFIN @Bits 0..11 : Units 62.5 ppb. Max range +/-100 ppm plus margin. */
  #define RADIO_CSTONES_FFOIN_FFFIN_Pos (0UL)        /*!< Position of FFFIN field.                                             */
  #define RADIO_CSTONES_FFOIN_FFFIN_Msk (0xFFFUL << RADIO_CSTONES_FFOIN_FFFIN_Pos) /*!< Bit mask of FFFIN field.               */


/* RADIO_CSTONES_FFOSOURCE: Source of FFO */
  #define RADIO_CSTONES_FFOSOURCE_ResetValue (0x00000001UL) /*!< Reset value of FFOSOURCE register.                            */

/* FFOSOURCE @Bit 0 : Use external or internal FFOSOURCE */
  #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Pos (0UL) /*!< Position of FFOSOURCE field.                                        */
  #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Msk (0x1UL << RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Pos) /*!< Bit mask of FFOSOURCE
                                                                            field.*/
  #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Min (0x0UL) /*!< Min enumerator value of FFOSOURCE field.                          */
  #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Max (0x1UL) /*!< Max enumerator value of FFOSOURCE field.                          */
  #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_External (0x0UL) /*!< Use FFOIN                                                    */
  #define RADIO_CSTONES_FFOSOURCE_FFOSOURCE_Internal (0x1UL) /*!< Calc FFO from CnAcc                                          */


/* RADIO_CSTONES_FAEPEER: FAEPEER (Frequency Actuation Error) of peer if known. Used during Mode 0 steps. */
  #define RADIO_CSTONES_FAEPEER_ResetValue (0x00000000UL) /*!< Reset value of FAEPEER register.                                */

/* FAEPEER @Bits 0..7 : Units 31.25 ppb. */
  #define RADIO_CSTONES_FAEPEER_FAEPEER_Pos (0UL)    /*!< Position of FAEPEER field.                                           */
  #define RADIO_CSTONES_FAEPEER_FAEPEER_Msk (0xFFUL << RADIO_CSTONES_FAEPEER_FAEPEER_Pos) /*!< Bit mask of FAEPEER field.      */


/* RADIO_CSTONES_PHASESHIFT: Parameter used in TPM, provided by software */
  #define RADIO_CSTONES_PHASESHIFT_ResetValue (0x00000000UL) /*!< Reset value of PHASESHIFT register.                          */

/* PHASESHIFT @Bits 0..15 : Phase shift used in TPM calculation */
  #define RADIO_CSTONES_PHASESHIFT_PHASESHIFT_Pos (0UL) /*!< Position of PHASESHIFT field.                                     */
  #define RADIO_CSTONES_PHASESHIFT_PHASESHIFT_Msk (0xFFFFUL << RADIO_CSTONES_PHASESHIFT_PHASESHIFT_Pos) /*!< Bit mask of
                                                                            PHASESHIFT field.*/


/* RADIO_CSTONES_NUMSAMPLESCOEFF: Parameter used in TPM, provided by software */
  #define RADIO_CSTONES_NUMSAMPLESCOEFF_ResetValue (0x0000199AUL) /*!< Reset value of NUMSAMPLESCOEFF register.                */

/* NUMSAMPLESCOEFF @Bits 0..15 : Coefficient 2**16/(numSamples/16) in Q1.15 format (Default numsamples value is 160) */
  #define RADIO_CSTONES_NUMSAMPLESCOEFF_NUMSAMPLESCOEFF_Pos (0UL) /*!< Position of NUMSAMPLESCOEFF field.                      */
  #define RADIO_CSTONES_NUMSAMPLESCOEFF_NUMSAMPLESCOEFF_Msk (0xFFFFUL << RADIO_CSTONES_NUMSAMPLESCOEFF_NUMSAMPLESCOEFF_Pos) /*!<
                                                                            Bit mask of NUMSAMPLESCOEFF field.*/


/* RADIO_CSTONES_PCT16: Mean magnitude and mean phase converted to IQ */
  #define RADIO_CSTONES_PCT16_ResetValue (0x00000000UL) /*!< Reset value of PCT16 register.                                    */

/* PCT16I @Bits 0..15 : Inphase */
  #define RADIO_CSTONES_PCT16_PCT16I_Pos (0UL)       /*!< Position of PCT16I field.                                            */
  #define RADIO_CSTONES_PCT16_PCT16I_Msk (0xFFFFUL << RADIO_CSTONES_PCT16_PCT16I_Pos) /*!< Bit mask of PCT16I field.           */

/* PCT16Q @Bits 16..31 : Quadrature */
  #define RADIO_CSTONES_PCT16_PCT16Q_Pos (16UL)      /*!< Position of PCT16Q field.                                            */
  #define RADIO_CSTONES_PCT16_PCT16Q_Msk (0xFFFFUL << RADIO_CSTONES_PCT16_PCT16Q_Pos) /*!< Bit mask of PCT16Q field.           */


/* RADIO_CSTONES_MAGPHASEMEAN: Mean magnitude and phase of the signal before it is converted to PCT16 */
  #define RADIO_CSTONES_MAGPHASEMEAN_ResetValue (0x00000000UL) /*!< Reset value of MAGPHASEMEAN register.                      */

/* PHASE @Bits 0..15 : Mean phase */
  #define RADIO_CSTONES_MAGPHASEMEAN_PHASE_Pos (0UL) /*!< Position of PHASE field.                                             */
  #define RADIO_CSTONES_MAGPHASEMEAN_PHASE_Msk (0xFFFFUL << RADIO_CSTONES_MAGPHASEMEAN_PHASE_Pos) /*!< Bit mask of PHASE field.*/

/* MAG @Bits 16..31 : Mean magnitude */
  #define RADIO_CSTONES_MAGPHASEMEAN_MAG_Pos (16UL)  /*!< Position of MAG field.                                               */
  #define RADIO_CSTONES_MAGPHASEMEAN_MAG_Msk (0xFFFFUL << RADIO_CSTONES_MAGPHASEMEAN_MAG_Pos) /*!< Bit mask of MAG field.      */


/* RADIO_CSTONES_IQRAWMEAN: Mean of IQ values */
  #define RADIO_CSTONES_IQRAWMEAN_ResetValue (0x00000000UL) /*!< Reset value of IQRAWMEAN register.                            */

/* IQRAWMEANI @Bits 0..15 : Inphase */
  #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANI_Pos (0UL) /*!< Position of IQRAWMEANI field.                                      */
  #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANI_Msk (0xFFFFUL << RADIO_CSTONES_IQRAWMEAN_IQRAWMEANI_Pos) /*!< Bit mask of
                                                                            IQRAWMEANI field.*/

/* IQRAWMEANQ @Bits 16..31 : Quadrature */
  #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANQ_Pos (16UL) /*!< Position of IQRAWMEANQ field.                                     */
  #define RADIO_CSTONES_IQRAWMEAN_IQRAWMEANQ_Msk (0xFFFFUL << RADIO_CSTONES_IQRAWMEAN_IQRAWMEANQ_Pos) /*!< Bit mask of
                                                                            IQRAWMEANQ field.*/


/* RADIO_CSTONES_MAGSTD: Magnitude standard deviation approximation */
  #define RADIO_CSTONES_MAGSTD_ResetValue (0x00000000UL) /*!< Reset value of MAGSTD register.                                  */

/* MAGSTD @Bits 0..15 : Magnitude standard deviation approximation */
  #define RADIO_CSTONES_MAGSTD_MAGSTD_Pos (0UL)      /*!< Position of MAGSTD field.                                            */
  #define RADIO_CSTONES_MAGSTD_MAGSTD_Msk (0xFFFFUL << RADIO_CSTONES_MAGSTD_MAGSTD_Pos) /*!< Bit mask of MAGSTD field.         */


/* RADIO_CSTONES_CNACC: Output of the autocorrelation of the accumulated IQ signal */
  #define RADIO_CSTONES_CNACC_ResetValue (0x00000000UL) /*!< Reset value of CNACC register.                                    */

/* CNACCI @Bits 0..15 : (unspecified) */
  #define RADIO_CSTONES_CNACC_CNACCI_Pos (0UL)       /*!< Position of CNACCI field.                                            */
  #define RADIO_CSTONES_CNACC_CNACCI_Msk (0xFFFFUL << RADIO_CSTONES_CNACC_CNACCI_Pos) /*!< Bit mask of CNACCI field.           */

/* CNACCQ @Bits 16..31 : (unspecified) */
  #define RADIO_CSTONES_CNACC_CNACCQ_Pos (16UL)      /*!< Position of CNACCQ field.                                            */
  #define RADIO_CSTONES_CNACC_CNACCQ_Msk (0xFFFFUL << RADIO_CSTONES_CNACC_CNACCQ_Pos) /*!< Bit mask of CNACCQ field.           */


/* RADIO_CSTONES_FFOEST: FFO estimate */
  #define RADIO_CSTONES_FFOEST_ResetValue (0x00000000UL) /*!< Reset value of FFOEST register.                                  */

/* FFOEST @Bits 0..11 : Units 62.5 ppb. Max range +/-100 ppm plus margin. */
  #define RADIO_CSTONES_FFOEST_FFOEST_Pos (0UL)      /*!< Position of FFOEST field.                                            */
  #define RADIO_CSTONES_FFOEST_FFOEST_Msk (0xFFFUL << RADIO_CSTONES_FFOEST_FFOEST_Pos) /*!< Bit mask of FFOEST field.          */


/* RADIO_CSTONES_DOWNSAMPLE: Turn on/off down sample of input IQ-signals */
  #define RADIO_CSTONES_DOWNSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of DOWNSAMPLE register.                          */

/* ENABLEFILTER @Bit 0 : Turn on/off down sample of input IQ-signals */
  #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Pos (0UL) /*!< Position of ENABLEFILTER field.                                 */
  #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Msk (0x1UL << RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Pos) /*!< Bit mask of
                                                                            ENABLEFILTER field.*/
  #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Min (0x0UL) /*!< Min enumerator value of ENABLEFILTER field.                   */
  #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_Max (0x1UL) /*!< Max enumerator value of ENABLEFILTER field.                   */
  #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_OFF (0x0UL) /*!< Disable filter                                                */
  #define RADIO_CSTONES_DOWNSAMPLE_ENABLEFILTER_ON (0x1UL) /*!< Enable filter                                                  */

/* RATE @Bit 1 : Indicating if BLE1M or BLE2M is used */
  #define RADIO_CSTONES_DOWNSAMPLE_RATE_Pos (1UL)    /*!< Position of RATE field.                                              */
  #define RADIO_CSTONES_DOWNSAMPLE_RATE_Msk (0x1UL << RADIO_CSTONES_DOWNSAMPLE_RATE_Pos) /*!< Bit mask of RATE field.          */
  #define RADIO_CSTONES_DOWNSAMPLE_RATE_Min (0x0UL)  /*!< Min enumerator value of RATE field.                                  */
  #define RADIO_CSTONES_DOWNSAMPLE_RATE_Max (0x1UL)  /*!< Max enumerator value of RATE field.                                  */
  #define RADIO_CSTONES_DOWNSAMPLE_RATE_BLE1M (0x0UL) /*!< Radio mode BLE1M is used                                            */
  #define RADIO_CSTONES_DOWNSAMPLE_RATE_BLE2m (0x1UL) /*!< Radio mode BLE2M is used                                            */


/* RADIO_CSTONES_FINETUNENEXT: Number of full ADPLL finetune steps */
  #define RADIO_CSTONES_FINETUNENEXT_ResetValue (0x00000000UL) /*!< Reset value of FINETUNENEXT register.                      */

/* FINETUNENEXT @Bits 0..12 : Units of 488.28125 Hz */
  #define RADIO_CSTONES_FINETUNENEXT_FINETUNENEXT_Pos (0UL) /*!< Position of FINETUNENEXT field.                               */
  #define RADIO_CSTONES_FINETUNENEXT_FINETUNENEXT_Msk (0x1FFFUL << RADIO_CSTONES_FINETUNENEXT_FINETUNENEXT_Pos) /*!< Bit mask of
                                                                            FINETUNENEXT field.*/


/* RADIO_CSTONES_CFOPHASE: Cordic output of CnAcc */
  #define RADIO_CSTONES_CFOPHASE_ResetValue (0x00000000UL) /*!< Reset value of CFOPHASE register.                              */

/* CFOPHASE @Bits 0..15 : (unspecified) */
  #define RADIO_CSTONES_CFOPHASE_CFOPHASE_Pos (0UL)  /*!< Position of CFOPHASE field.                                          */
  #define RADIO_CSTONES_CFOPHASE_CFOPHASE_Msk (0xFFFFUL << RADIO_CSTONES_CFOPHASE_CFOPHASE_Pos) /*!< Bit mask of CFOPHASE
                                                                            field.*/


/* RADIO_CSTONES_FREQOFFSET: Frequency offset estimate */
  #define RADIO_CSTONES_FREQOFFSET_ResetValue (0x00000000UL) /*!< Reset value of FREQOFFSET register.                          */

/* FREQOFFSET @Bits 0..13 : (unspecified) */
  #define RADIO_CSTONES_FREQOFFSET_FREQOFFSET_Pos (0UL) /*!< Position of FREQOFFSET field.                                     */
  #define RADIO_CSTONES_FREQOFFSET_FREQOFFSET_Msk (0x3FFFUL << RADIO_CSTONES_FREQOFFSET_FREQOFFSET_Pos) /*!< Bit mask of
                                                                            FREQOFFSET field.*/


/* RADIO_CSTONES_PCT11: Mean magnitude and mean phase converted to IQ. IQ values limited to [-1024,1023]. */
  #define RADIO_CSTONES_PCT11_ResetValue (0x00000000UL) /*!< Reset value of PCT11 register.                                    */

/* PCT11I @Bits 0..10 : Inphase */
  #define RADIO_CSTONES_PCT11_PCT11I_Pos (0UL)       /*!< Position of PCT11I field.                                            */
  #define RADIO_CSTONES_PCT11_PCT11I_Msk (0x7FFUL << RADIO_CSTONES_PCT11_PCT11I_Pos) /*!< Bit mask of PCT11I field.            */

/* PCT11Q @Bits 11..21 : Quadrature */
  #define RADIO_CSTONES_PCT11_PCT11Q_Pos (11UL)      /*!< Position of PCT11Q field.                                            */
  #define RADIO_CSTONES_PCT11_PCT11Q_Msk (0x7FFUL << RADIO_CSTONES_PCT11_PCT11Q_Pos) /*!< Bit mask of PCT11Q field.            */


/* RADIO_CSTONES_LFAENEXT: Quantization error between ADPLL frequency and the desired value of FFO * RF Frequency. Values
                            limited to [-64,63] with units 7.6294 Hz. */

  #define RADIO_CSTONES_LFAENEXT_ResetValue (0x00000000UL) /*!< Reset value of LFAENEXT register.                              */

/* LFAENEXT @Bits 0..6 : Inphase */
  #define RADIO_CSTONES_LFAENEXT_LFAENEXT_Pos (0UL)  /*!< Position of LFAENEXT field.                                          */
  #define RADIO_CSTONES_LFAENEXT_LFAENEXT_Msk (0x7FUL << RADIO_CSTONES_LFAENEXT_LFAENEXT_Pos) /*!< Bit mask of LFAENEXT field. */



/* ==================================================== Struct RADIO_RTT ===================================================== */
/**
  * @brief RTT [RADIO_RTT] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) RTT Config.                                           */
  __IOM uint32_t  SEGMENT01;                         /*!< (@ 0x00000004) RTT segments 0 and 1                                  */
  __IOM uint32_t  SEGMENT23;                         /*!< (@ 0x00000008) RTT segments 2 and 3                                  */
  __IOM uint32_t  SEGMENT45;                         /*!< (@ 0x0000000C) RTT segments 4 and 5                                  */
  __IOM uint32_t  SEGMENT67;                         /*!< (@ 0x00000010) RTT segments 6 and 7                                  */
} NRF_RADIO_RTT_Type;                                /*!< Size = 20 (0x014)                                                    */

/* RADIO_RTT_CONFIG: RTT Config. */
  #define RADIO_RTT_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                                      */

/* EN @Bit 0 : Enable RTT Functionality. Only valid for BLE 1MBPS and 2MBPS mode */
  #define RADIO_RTT_CONFIG_EN_Pos (0UL)              /*!< Position of EN field.                                                */
  #define RADIO_RTT_CONFIG_EN_Msk (0x1UL << RADIO_RTT_CONFIG_EN_Pos) /*!< Bit mask of EN field.                                */
  #define RADIO_RTT_CONFIG_EN_Min (0x0UL)            /*!< Min enumerator value of EN field.                                    */
  #define RADIO_RTT_CONFIG_EN_Max (0x1UL)            /*!< Max enumerator value of EN field.                                    */
  #define RADIO_RTT_CONFIG_EN_Disabled (0x0UL)       /*!< Disable RTT Block                                                    */
  #define RADIO_RTT_CONFIG_EN_Enabled (0x1UL)        /*!< Enable RTT Block                                                     */

/* ENFULLAA @Bit 1 : Enabling/Disable ping over the entire access address. */
  #define RADIO_RTT_CONFIG_ENFULLAA_Pos (1UL)        /*!< Position of ENFULLAA field.                                          */
  #define RADIO_RTT_CONFIG_ENFULLAA_Msk (0x1UL << RADIO_RTT_CONFIG_ENFULLAA_Pos) /*!< Bit mask of ENFULLAA field.              */
  #define RADIO_RTT_CONFIG_ENFULLAA_Min (0x0UL)      /*!< Min enumerator value of ENFULLAA field.                              */
  #define RADIO_RTT_CONFIG_ENFULLAA_Max (0x1UL)      /*!< Max enumerator value of ENFULLAA field.                              */
  #define RADIO_RTT_CONFIG_ENFULLAA_Disabled (0x0UL) /*!< Disable ping over the entire access address, i.e., enable only over
                                                          the first 16-bit access address*/
  #define RADIO_RTT_CONFIG_ENFULLAA_Enabled (0x1UL)  /*!< Enable ping over the entire access address                           */

/* ROLE @Bit 2 : Role as a Initiator or Reflector. */
  #define RADIO_RTT_CONFIG_ROLE_Pos (2UL)            /*!< Position of ROLE field.                                              */
  #define RADIO_RTT_CONFIG_ROLE_Msk (0x1UL << RADIO_RTT_CONFIG_ROLE_Pos) /*!< Bit mask of ROLE field.                          */
  #define RADIO_RTT_CONFIG_ROLE_Min (0x0UL)          /*!< Min enumerator value of ROLE field.                                  */
  #define RADIO_RTT_CONFIG_ROLE_Max (0x1UL)          /*!< Max enumerator value of ROLE field.                                  */
  #define RADIO_RTT_CONFIG_ROLE_Initiator (0x0UL)    /*!< Initiator                                                            */
  #define RADIO_RTT_CONFIG_ROLE_Reflector (0x1UL)    /*!< Reflector                                                            */

/* NUMSEGMENTS @Bits 3..6 : Number of 16bit payload segments available for ToA detection. Allowed values are 0, 2, 4, 6 and 8. */
  #define RADIO_RTT_CONFIG_NUMSEGMENTS_Pos (3UL)     /*!< Position of NUMSEGMENTS field.                                       */
  #define RADIO_RTT_CONFIG_NUMSEGMENTS_Msk (0xFUL << RADIO_RTT_CONFIG_NUMSEGMENTS_Pos) /*!< Bit mask of NUMSEGMENTS field.     */

/* EFSDELAY @Bits 8..16 : Early Frame Sync Delay, i.e., number of cycles to wait for access address to anchor correctly. For
                          2MBPSBLE mode, the EFSDELAY value is 64 (2us) and for 1MBPSBLE mode, it can be 256 (8us). */

  #define RADIO_RTT_CONFIG_EFSDELAY_Pos (8UL)        /*!< Position of EFSDELAY field.                                          */
  #define RADIO_RTT_CONFIG_EFSDELAY_Msk (0x1FFUL << RADIO_RTT_CONFIG_EFSDELAY_Pos) /*!< Bit mask of EFSDELAY field.            */


/* RADIO_RTT_SEGMENT01: RTT segments 0 and 1 */
  #define RADIO_RTT_SEGMENT01_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT01 register.                                */

/* DATA @Bits 0..31 : Data Bits 31 - 0 */
  #define RADIO_RTT_SEGMENT01_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define RADIO_RTT_SEGMENT01_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT01_DATA_Pos) /*!< Bit mask of DATA field.             */


/* RADIO_RTT_SEGMENT23: RTT segments 2 and 3 */
  #define RADIO_RTT_SEGMENT23_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT23 register.                                */

/* DATA @Bits 0..31 : Data Bits 63 - 32 */
  #define RADIO_RTT_SEGMENT23_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define RADIO_RTT_SEGMENT23_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT23_DATA_Pos) /*!< Bit mask of DATA field.             */


/* RADIO_RTT_SEGMENT45: RTT segments 4 and 5 */
  #define RADIO_RTT_SEGMENT45_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT45 register.                                */

/* DATA @Bits 0..31 : Data Bits 95 - 64 */
  #define RADIO_RTT_SEGMENT45_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define RADIO_RTT_SEGMENT45_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT45_DATA_Pos) /*!< Bit mask of DATA field.             */


/* RADIO_RTT_SEGMENT67: RTT segments 6 and 7 */
  #define RADIO_RTT_SEGMENT67_ResetValue (0x00000000UL) /*!< Reset value of SEGMENT67 register.                                */

/* DATA @Bits 0..31 : Data Bits 127 - 96 */
  #define RADIO_RTT_SEGMENT67_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define RADIO_RTT_SEGMENT67_DATA_Msk (0xFFFFFFFFUL << RADIO_RTT_SEGMENT67_DATA_Pos) /*!< Bit mask of DATA field.             */


/* ====================================================== Struct RADIO ======================================================= */
/**
  * @brief 2.4 GHz radio
  */
  typedef struct {                                   /*!< RADIO Structure                                                      */
    __OM uint32_t TASKS_TXEN;                        /*!< (@ 0x00000000) Enable RADIO in TX mode                               */
    __OM uint32_t TASKS_RXEN;                        /*!< (@ 0x00000004) Enable RADIO in RX mode                               */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000008) Start RADIO                                           */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x0000000C) Stop RADIO                                            */
    __OM uint32_t TASKS_DISABLE;                     /*!< (@ 0x00000010) Disable RADIO                                         */
    __OM uint32_t TASKS_RSSISTART;                   /*!< (@ 0x00000014) Start the RSSI and take one single sample of the
                                                                         receive signal strength*/
    __OM uint32_t TASKS_BCSTART;                     /*!< (@ 0x00000018) Start the bit counter                                 */
    __OM uint32_t TASKS_BCSTOP;                      /*!< (@ 0x0000001C) Stop the bit counter                                  */
    __OM uint32_t TASKS_EDSTART;                     /*!< (@ 0x00000020) Start the energy detect measurement used in IEEE
                                                                         802.15.4 mode*/
    __OM uint32_t TASKS_EDSTOP;                      /*!< (@ 0x00000024) Stop the energy detect measurement                    */
    __OM uint32_t TASKS_CCASTART;                    /*!< (@ 0x00000028) Start the clear channel assessment used in IEEE
                                                                         802.15.4 mode*/
    __OM uint32_t TASKS_CCASTOP;                     /*!< (@ 0x0000002C) Stop the clear channel assessment                     */
    __IM uint32_t RESERVED[29];
    __OM uint32_t TASKS_SOFTRESET;                   /*!< (@ 0x000000A4) Reset all public registers, but with these exceptions:
                                                                         DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH
                                                                         registers. Only to be used in DISABLED state.*/
    __IM uint32_t RESERVED1[22];
    __IOM uint32_t SUBSCRIBE_TXEN;                   /*!< (@ 0x00000100) Subscribe configuration for task TXEN                 */
    __IOM uint32_t SUBSCRIBE_RXEN;                   /*!< (@ 0x00000104) Subscribe configuration for task RXEN                 */
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000108) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x0000010C) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_DISABLE;                /*!< (@ 0x00000110) Subscribe configuration for task DISABLE              */
    __IOM uint32_t SUBSCRIBE_RSSISTART;              /*!< (@ 0x00000114) Subscribe configuration for task RSSISTART            */
    __IOM uint32_t SUBSCRIBE_BCSTART;                /*!< (@ 0x00000118) Subscribe configuration for task BCSTART              */
    __IOM uint32_t SUBSCRIBE_BCSTOP;                 /*!< (@ 0x0000011C) Subscribe configuration for task BCSTOP               */
    __IOM uint32_t SUBSCRIBE_EDSTART;                /*!< (@ 0x00000120) Subscribe configuration for task EDSTART              */
    __IOM uint32_t SUBSCRIBE_EDSTOP;                 /*!< (@ 0x00000124) Subscribe configuration for task EDSTOP               */
    __IOM uint32_t SUBSCRIBE_CCASTART;               /*!< (@ 0x00000128) Subscribe configuration for task CCASTART             */
    __IOM uint32_t SUBSCRIBE_CCASTOP;                /*!< (@ 0x0000012C) Subscribe configuration for task CCASTOP              */
    __IM uint32_t RESERVED2[29];
    __IOM uint32_t SUBSCRIBE_SOFTRESET;              /*!< (@ 0x000001A4) Subscribe configuration for task SOFTRESET            */
    __IM uint32_t RESERVED3[22];
    __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000200) RADIO has ramped up and is ready to be started        */
    __IOM uint32_t EVENTS_TXREADY;                   /*!< (@ 0x00000204) RADIO has ramped up and is ready to be started TX path*/
    __IOM uint32_t EVENTS_RXREADY;                   /*!< (@ 0x00000208) RADIO has ramped up and is ready to be started RX path*/
    __IOM uint32_t EVENTS_ADDRESS;                   /*!< (@ 0x0000020C) Address sent or received                              */
    __IOM uint32_t EVENTS_FRAMESTART;                /*!< (@ 0x00000210) IEEE 802.15.4 length field received                   */
    __IOM uint32_t EVENTS_PAYLOAD;                   /*!< (@ 0x00000214) Packet payload sent or received                       */
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000218) Memory access for packet data has been completed      */
    __IOM uint32_t EVENTS_PHYEND;                    /*!< (@ 0x0000021C) The last bit is sent on air or last bit is received   */
    __IOM uint32_t EVENTS_DISABLED;                  /*!< (@ 0x00000220) RADIO has been disabled                               */
    __IOM uint32_t EVENTS_DEVMATCH;                  /*!< (@ 0x00000224) A device address match occurred on the last received
                                                                         packet*/
    __IOM uint32_t EVENTS_DEVMISS;                   /*!< (@ 0x00000228) No device address match occurred on the last received
                                                                         packet*/
    __IOM uint32_t EVENTS_CRCOK;                     /*!< (@ 0x0000022C) Packet received with CRC ok                           */
    __IOM uint32_t EVENTS_CRCERROR;                  /*!< (@ 0x00000230) Packet received with CRC error                        */
    __IM uint32_t RESERVED4;
    __IOM uint32_t EVENTS_BCMATCH;                   /*!< (@ 0x00000238) Bit counter reached bit count value                   */
    __IOM uint32_t EVENTS_EDEND;                     /*!< (@ 0x0000023C) Sampling of energy detection complete (a new ED sample
                                                                         is ready for readout from the RADIO.EDSAMPLE register)*/
    __IOM uint32_t EVENTS_EDSTOPPED;                 /*!< (@ 0x00000240) The sampling of energy detection has stopped          */
    __IOM uint32_t EVENTS_CCAIDLE;                   /*!< (@ 0x00000244) Wireless medium in idle - clear to send               */
    __IOM uint32_t EVENTS_CCABUSY;                   /*!< (@ 0x00000248) Wireless medium busy - do not send                    */
    __IOM uint32_t EVENTS_CCASTOPPED;                /*!< (@ 0x0000024C) The CCA has stopped                                   */
    __IOM uint32_t EVENTS_RATEBOOST;                 /*!< (@ 0x00000250) Ble_LR CI field received, receive mode is changed from
                                                                         Ble_LR125Kbit to Ble_LR500Kbit*/
    __IOM uint32_t EVENTS_MHRMATCH;                  /*!< (@ 0x00000254) MAC header match found                                */
    __IOM uint32_t EVENTS_SYNC;                      /*!< (@ 0x00000258) Initial sync detected                                 */
    __IOM uint32_t EVENTS_CTEPRESENT;                /*!< (@ 0x0000025C) CTEInfo byte is received                              */
    __IM uint32_t RESERVED5[40];
    __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000300) Publish configuration for event READY                 */
    __IOM uint32_t PUBLISH_TXREADY;                  /*!< (@ 0x00000304) Publish configuration for event TXREADY               */
    __IOM uint32_t PUBLISH_RXREADY;                  /*!< (@ 0x00000308) Publish configuration for event RXREADY               */
    __IOM uint32_t PUBLISH_ADDRESS;                  /*!< (@ 0x0000030C) Publish configuration for event ADDRESS               */
    __IOM uint32_t PUBLISH_FRAMESTART;               /*!< (@ 0x00000310) Publish configuration for event FRAMESTART            */
    __IOM uint32_t PUBLISH_PAYLOAD;                  /*!< (@ 0x00000314) Publish configuration for event PAYLOAD               */
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000318) Publish configuration for event END                   */
    __IOM uint32_t PUBLISH_PHYEND;                   /*!< (@ 0x0000031C) Publish configuration for event PHYEND                */
    __IOM uint32_t PUBLISH_DISABLED;                 /*!< (@ 0x00000320) Publish configuration for event DISABLED              */
    __IOM uint32_t PUBLISH_DEVMATCH;                 /*!< (@ 0x00000324) Publish configuration for event DEVMATCH              */
    __IOM uint32_t PUBLISH_DEVMISS;                  /*!< (@ 0x00000328) Publish configuration for event DEVMISS               */
    __IOM uint32_t PUBLISH_CRCOK;                    /*!< (@ 0x0000032C) Publish configuration for event CRCOK                 */
    __IOM uint32_t PUBLISH_CRCERROR;                 /*!< (@ 0x00000330) Publish configuration for event CRCERROR              */
    __IM uint32_t RESERVED6;
    __IOM uint32_t PUBLISH_BCMATCH;                  /*!< (@ 0x00000338) Publish configuration for event BCMATCH               */
    __IOM uint32_t PUBLISH_EDEND;                    /*!< (@ 0x0000033C) Publish configuration for event EDEND                 */
    __IOM uint32_t PUBLISH_EDSTOPPED;                /*!< (@ 0x00000340) Publish configuration for event EDSTOPPED             */
    __IOM uint32_t PUBLISH_CCAIDLE;                  /*!< (@ 0x00000344) Publish configuration for event CCAIDLE               */
    __IOM uint32_t PUBLISH_CCABUSY;                  /*!< (@ 0x00000348) Publish configuration for event CCABUSY               */
    __IOM uint32_t PUBLISH_CCASTOPPED;               /*!< (@ 0x0000034C) Publish configuration for event CCASTOPPED            */
    __IOM uint32_t PUBLISH_RATEBOOST;                /*!< (@ 0x00000350) Publish configuration for event RATEBOOST             */
    __IOM uint32_t PUBLISH_MHRMATCH;                 /*!< (@ 0x00000354) Publish configuration for event MHRMATCH              */
    __IOM uint32_t PUBLISH_SYNC;                     /*!< (@ 0x00000358) Publish configuration for event SYNC                  */
    __IOM uint32_t PUBLISH_CTEPRESENT;               /*!< (@ 0x0000035C) Publish configuration for event CTEPRESENT            */
    __IM uint32_t RESERVED7[40];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000400) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED8[33];
    __IOM uint32_t INTENSET00;                       /*!< (@ 0x00000488) Enable interrupt                                      */
    __IM uint32_t RESERVED9;
    __IOM uint32_t INTENCLR00;                       /*!< (@ 0x00000490) Disable interrupt                                     */
    __IM uint32_t RESERVED10[5];
    __IOM uint32_t INTENSET10;                       /*!< (@ 0x000004A8) Enable interrupt                                      */
    __IM uint32_t RESERVED11;
    __IOM uint32_t INTENCLR10;                       /*!< (@ 0x000004B0) Disable interrupt                                     */
    __IM uint32_t RESERVED12[19];
    __IOM uint32_t MODE;                             /*!< (@ 0x00000500) Data rate and modulation                              */
    __IM uint32_t RESERVED13[7];
    __IM uint32_t STATE;                             /*!< (@ 0x00000520) Current radio state                                   */
    __IM uint32_t RESERVED14[3];
    __IOM uint32_t EDCTRL;                           /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control                   */
    __IM uint32_t EDSAMPLE;                          /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level                     */
    __IOM uint32_t CCACTRL;                          /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control        */
    __IM uint32_t RESERVED15;
    __IOM uint32_t DATAWHITE;                        /*!< (@ 0x00000540) Data whitening configuration                          */
    __IM uint32_t RESERVED16[112];
    __IOM uint32_t TIMING;                           /*!< (@ 0x00000704) Timing                                                */
    __IOM uint32_t FREQUENCY;                        /*!< (@ 0x00000708) Frequency                                             */
    __IM uint32_t RESERVED17;
    __IOM uint32_t TXPOWER;                          /*!< (@ 0x00000710) Output power                                          */
    __IOM uint32_t TIFS;                             /*!< (@ 0x00000714) Interframe spacing in us                              */
    __IM uint32_t RSSISAMPLE;                        /*!< (@ 0x00000718) RSSI sample                                           */
    __IM uint32_t RESERVED18[123];
    __IOM uint32_t FECONFIG;                         /*!< (@ 0x00000908) Config register                                       */
    __IM uint32_t RESERVED19[253];
    __IOM uint32_t DFEMODE;                          /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or
                                                                         Angle-of-Departure (AOD)*/
    __IM uint32_t DFESTATUS;                         /*!< (@ 0x00000D04) DFE status information                                */
    __IM uint32_t RESERVED20[2];
    __IOM uint32_t DFECTRL1;                         /*!< (@ 0x00000D10) Various configuration for Direction finding           */
    __IOM uint32_t DFECTRL2;                         /*!< (@ 0x00000D14) Start offset for Direction finding                    */
    __IM uint32_t RESERVED21[4];
    __IOM uint32_t SWITCHPATTERN;                    /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna             */
    __OM uint32_t CLEARPATTERN;                      /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control      */
    __IOM NRF_RADIO_PSEL_Type PSEL;                  /*!< (@ 0x00000D30) (unspecified)                                         */
    __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET;        /*!< (@ 0x00000D50) DFE packet EasyDMA channel                            */
    __IM uint32_t RESERVED22[43];
    __IM uint32_t CRCSTATUS;                         /*!< (@ 0x00000E0C) CRC status                                            */
    __IM uint32_t RXMATCH;                           /*!< (@ 0x00000E10) Received address                                      */
    __IM uint32_t RXCRC;                             /*!< (@ 0x00000E14) CRC field of previously received packet               */
    __IM uint32_t DAI;                               /*!< (@ 0x00000E18) Device address match index                            */
    __IM uint32_t PDUSTAT;                           /*!< (@ 0x00000E1C) Payload status                                        */
    __IOM uint32_t PCNF0;                            /*!< (@ 0x00000E20) Packet configuration register 0                       */
    __IM uint32_t RESERVED23;
    __IOM uint32_t PCNF1;                            /*!< (@ 0x00000E28) Packet configuration register 1                       */
    __IOM uint32_t BASE0;                            /*!< (@ 0x00000E2C) Base address 0                                        */
    __IOM uint32_t BASE1;                            /*!< (@ 0x00000E30) Base address 1                                        */
    __IOM uint32_t PREFIX0;                          /*!< (@ 0x00000E34) Prefixes bytes for logical addresses 0-3              */
    __IOM uint32_t PREFIX1;                          /*!< (@ 0x00000E38) Prefixes bytes for logical addresses 4-7              */
    __IOM uint32_t TXADDRESS;                        /*!< (@ 0x00000E3C) Transmit address select                               */
    __IOM uint32_t RXADDRESSES;                      /*!< (@ 0x00000E40) Receive address select                                */
    __IOM uint32_t CRCCNF;                           /*!< (@ 0x00000E44) CRC configuration                                     */
    __IOM uint32_t CRCPOLY;                          /*!< (@ 0x00000E48) CRC polynomial                                        */
    __IOM uint32_t CRCINIT;                          /*!< (@ 0x00000E4C) CRC initial value                                     */
    __IOM uint32_t DAB[8];                           /*!< (@ 0x00000E50) Device address base segment n                         */
    __IOM uint32_t DAP[8];                           /*!< (@ 0x00000E70) Device address prefix n                               */
    __IOM uint32_t DACNF;                            /*!< (@ 0x00000E90) Device address match configuration                    */
    __IOM uint32_t BCC;                              /*!< (@ 0x00000E94) Bit counter compare                                   */
    __IM uint32_t RESERVED24[3];
    __IM uint32_t CTESTATUS;                         /*!< (@ 0x00000EA4) CTEInfo parsed from received packet                   */
    __IM uint32_t RESERVED25[3];
    __IOM uint32_t MHRMATCHCONF;                     /*!< (@ 0x00000EB4) Search pattern configuration                          */
    __IOM uint32_t MHRMATCHMASK;                     /*!< (@ 0x00000EB8) Pattern mask                                          */
    __IOM uint32_t SFD;                              /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter                */
    __IOM uint32_t CTEINLINECONF;                    /*!< (@ 0x00000EC0) Configuration for CTE inline mode                     */
    __IM uint32_t RESERVED26[3];
    __IOM uint32_t PACKETPTR;                        /*!< (@ 0x00000ED0) Packet pointer                                        */
    __IM uint32_t RESERVED27[75];
    __IOM NRF_RADIO_CSTONES_Type CSTONES;            /*!< (@ 0x00001000) (unspecified)                                         */
    __IOM NRF_RADIO_RTT_Type RTT;                    /*!< (@ 0x00001050) (unspecified)                                         */
  } NRF_RADIO_Type;                                  /*!< Size = 4196 (0x1064)                                                 */

/* RADIO_TASKS_TXEN: Enable RADIO in TX mode */
  #define RADIO_TASKS_TXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TXEN register.                                  */

/* TASKS_TXEN @Bit 0 : Enable RADIO in TX mode */
  #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL)      /*!< Position of TASKS_TXEN field.                                        */
  #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field.        */
  #define RADIO_TASKS_TXEN_TASKS_TXEN_Min (0x1UL)    /*!< Min enumerator value of TASKS_TXEN field.                            */
  #define RADIO_TASKS_TXEN_TASKS_TXEN_Max (0x1UL)    /*!< Max enumerator value of TASKS_TXEN field.                            */
  #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (0x1UL) /*!< Trigger task                                                        */


/* RADIO_TASKS_RXEN: Enable RADIO in RX mode */
  #define RADIO_TASKS_RXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RXEN register.                                  */

/* TASKS_RXEN @Bit 0 : Enable RADIO in RX mode */
  #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL)      /*!< Position of TASKS_RXEN field.                                        */
  #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field.        */
  #define RADIO_TASKS_RXEN_TASKS_RXEN_Min (0x1UL)    /*!< Min enumerator value of TASKS_RXEN field.                            */
  #define RADIO_TASKS_RXEN_TASKS_RXEN_Max (0x1UL)    /*!< Max enumerator value of TASKS_RXEN field.                            */
  #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (0x1UL) /*!< Trigger task                                                        */


/* RADIO_TASKS_START: Start RADIO */
  #define RADIO_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */

/* TASKS_START @Bit 0 : Start RADIO */
  #define RADIO_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
  #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
  #define RADIO_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
  #define RADIO_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
  #define RADIO_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */


/* RADIO_TASKS_STOP: Stop RADIO */
  #define RADIO_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop RADIO */
  #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
  #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
  #define RADIO_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
  #define RADIO_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
  #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */


/* RADIO_TASKS_DISABLE: Disable RADIO */
  #define RADIO_TASKS_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_DISABLE register.                            */

/* TASKS_DISABLE @Bit 0 : Disable RADIO */
  #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field.                                    */
  #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE
                                                                            field.*/
  #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Min (0x1UL) /*!< Min enumerator value of TASKS_DISABLE field.                      */
  #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Max (0x1UL) /*!< Max enumerator value of TASKS_DISABLE field.                      */
  #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task                                                  */


/* RADIO_TASKS_RSSISTART: Start the RSSI and take one single sample of the receive signal strength */
  #define RADIO_TASKS_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RSSISTART register.                        */

/* TASKS_RSSISTART @Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
  #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field.                              */
  #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of
                                                                            TASKS_RSSISTART field.*/
  #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Min (0x1UL) /*!< Min enumerator value of TASKS_RSSISTART field.                */
  #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of TASKS_RSSISTART field.                */
  #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (0x1UL) /*!< Trigger task                                              */


/* RADIO_TASKS_BCSTART: Start the bit counter */
  #define RADIO_TASKS_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTART register.                            */

/* TASKS_BCSTART @Bit 0 : Start the bit counter */
  #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field.                                    */
  #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART
                                                                            field.*/
  #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTART field.                      */
  #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTART field.                      */
  #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (0x1UL) /*!< Trigger task                                                  */


/* RADIO_TASKS_BCSTOP: Stop the bit counter */
  #define RADIO_TASKS_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTOP register.                              */

/* TASKS_BCSTOP @Bit 0 : Stop the bit counter */
  #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL)  /*!< Position of TASKS_BCSTOP field.                                      */
  #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP
                                                                            field.*/
  #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTOP field.                         */
  #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTOP field.                         */
  #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (0x1UL) /*!< Trigger task                                                    */


/* RADIO_TASKS_EDSTART: Start the energy detect measurement used in IEEE 802.15.4 mode */
  #define RADIO_TASKS_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTART register.                            */

/* TASKS_EDSTART @Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
  #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field.                                    */
  #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART
                                                                            field.*/
  #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTART field.                      */
  #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTART field.                      */
  #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (0x1UL) /*!< Trigger task                                                  */


/* RADIO_TASKS_EDSTOP: Stop the energy detect measurement */
  #define RADIO_TASKS_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTOP register.                              */

/* TASKS_EDSTOP @Bit 0 : Stop the energy detect measurement */
  #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL)  /*!< Position of TASKS_EDSTOP field.                                      */
  #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP
                                                                            field.*/
  #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTOP field.                         */
  #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTOP field.                         */
  #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (0x1UL) /*!< Trigger task                                                    */


/* RADIO_TASKS_CCASTART: Start the clear channel assessment used in IEEE 802.15.4 mode */
  #define RADIO_TASKS_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTART register.                          */

/* TASKS_CCASTART @Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
  #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field.                                 */
  #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of
                                                                            TASKS_CCASTART field.*/
  #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTART field.                   */
  #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTART field.                   */
  #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (0x1UL) /*!< Trigger task                                                */


/* RADIO_TASKS_CCASTOP: Stop the clear channel assessment */
  #define RADIO_TASKS_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTOP register.                            */

/* TASKS_CCASTOP @Bit 0 : Stop the clear channel assessment */
  #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field.                                    */
  #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP
                                                                            field.*/
  #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTOP field.                      */
  #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTOP field.                      */
  #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (0x1UL) /*!< Trigger task                                                  */


/* RADIO_TASKS_SOFTRESET: Reset all public registers, but with these exceptions: DMA registers and EVENT/INTEN/SUBSCRIBE/PUBLISH
                           registers. Only to be used in DISABLED state. */

  #define RADIO_TASKS_SOFTRESET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SOFTRESET register.                        */

/* TASKS_SOFTRESET @Bit 0 : Reset all public registers, but with these exceptions: DMA registers and
                            EVENT/INTEN/SUBSCRIBE/PUBLISH registers. Only to be used in DISABLED state. */

  #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Pos (0UL) /*!< Position of TASKS_SOFTRESET field.                              */
  #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Msk (0x1UL << RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Pos) /*!< Bit mask of
                                                                            TASKS_SOFTRESET field.*/
  #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Min (0x1UL) /*!< Min enumerator value of TASKS_SOFTRESET field.                */
  #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Max (0x1UL) /*!< Max enumerator value of TASKS_SOFTRESET field.                */
  #define RADIO_TASKS_SOFTRESET_TASKS_SOFTRESET_Trigger (0x1UL) /*!< Trigger task                                              */


/* RADIO_SUBSCRIBE_TXEN: Subscribe configuration for task TXEN */
  #define RADIO_SUBSCRIBE_TXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TXEN register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task TXEN will subscribe to */
  #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define RADIO_SUBSCRIBE_TXEN_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_TXEN_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field.                        */
  #define RADIO_SUBSCRIBE_TXEN_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_TXEN_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_RXEN: Subscribe configuration for task RXEN */
  #define RADIO_SUBSCRIBE_RXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RXEN register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task RXEN will subscribe to */
  #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define RADIO_SUBSCRIBE_RXEN_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_RXEN_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field.                        */
  #define RADIO_SUBSCRIBE_RXEN_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_RXEN_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_START: Subscribe configuration for task START */
  #define RADIO_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_SUBSCRIBE_START_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_START_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_START_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_SUBSCRIBE_START_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_START_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_START_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define RADIO_SUBSCRIBE_START_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define RADIO_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define RADIO_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                        */
  #define RADIO_SUBSCRIBE_STOP_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_STOP_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define RADIO_SUBSCRIBE_STOP_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_DISABLE: Subscribe configuration for task DISABLE */
  #define RADIO_SUBSCRIBE_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_DISABLE register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task DISABLE will subscribe to */
  #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field.                  */
  #define RADIO_SUBSCRIBE_DISABLE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_DISABLE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_RSSISTART: Subscribe configuration for task RSSISTART */
  #define RADIO_SUBSCRIBE_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RSSISTART register.                */

/* CHIDX @Bits 0..7 : DPPI channel that task RSSISTART will subscribe to */
  #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field.              */
  #define RADIO_SUBSCRIBE_RSSISTART_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_RSSISTART_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0x0UL) /*!< Disable subscription                                              */
  #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                */


/* RADIO_SUBSCRIBE_BCSTART: Subscribe configuration for task BCSTART */
  #define RADIO_SUBSCRIBE_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTART register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task BCSTART will subscribe to */
  #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field.                  */
  #define RADIO_SUBSCRIBE_BCSTART_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_BCSTART_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_BCSTOP: Subscribe configuration for task BCSTOP */
  #define RADIO_SUBSCRIBE_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTOP register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that task BCSTOP will subscribe to */
  #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RADIO_SUBSCRIBE_BCSTOP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_BCSTOP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_EDSTART: Subscribe configuration for task EDSTART */
  #define RADIO_SUBSCRIBE_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTART register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task EDSTART will subscribe to */
  #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field.                  */
  #define RADIO_SUBSCRIBE_EDSTART_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_EDSTART_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_EDSTOP: Subscribe configuration for task EDSTOP */
  #define RADIO_SUBSCRIBE_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTOP register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that task EDSTOP will subscribe to */
  #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RADIO_SUBSCRIBE_EDSTOP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_EDSTOP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_CCASTART: Subscribe configuration for task CCASTART */
  #define RADIO_SUBSCRIBE_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTART register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that task CCASTART will subscribe to */
  #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field.                */
  #define RADIO_SUBSCRIBE_CCASTART_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_CCASTART_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
  #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */


/* RADIO_SUBSCRIBE_CCASTOP: Subscribe configuration for task CCASTOP */
  #define RADIO_SUBSCRIBE_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTOP register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task CCASTOP will subscribe to */
  #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field.                  */
  #define RADIO_SUBSCRIBE_CCASTOP_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_CCASTOP_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* RADIO_SUBSCRIBE_SOFTRESET: Subscribe configuration for task SOFTRESET */
  #define RADIO_SUBSCRIBE_SOFTRESET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SOFTRESET register.                */

/* CHIDX @Bits 0..7 : DPPI channel that task SOFTRESET will subscribe to */
  #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define RADIO_SUBSCRIBE_SOFTRESET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_SUBSCRIBE_SOFTRESET_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define RADIO_SUBSCRIBE_SOFTRESET_EN_Msk (0x1UL << RADIO_SUBSCRIBE_SOFTRESET_EN_Pos) /*!< Bit mask of EN field.              */
  #define RADIO_SUBSCRIBE_SOFTRESET_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_SOFTRESET_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define RADIO_SUBSCRIBE_SOFTRESET_EN_Disabled (0x0UL) /*!< Disable subscription                                              */
  #define RADIO_SUBSCRIBE_SOFTRESET_EN_Enabled (0x1UL) /*!< Enable subscription                                                */


/* RADIO_EVENTS_READY: RADIO has ramped up and is ready to be started */
  #define RADIO_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                              */

/* EVENTS_READY @Bit 0 : RADIO has ramped up and is ready to be started */
  #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL)  /*!< Position of EVENTS_READY field.                                      */
  #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY
                                                                            field.*/
  #define RADIO_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                         */
  #define RADIO_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                         */
  #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define RADIO_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                               */


/* RADIO_EVENTS_TXREADY: RADIO has ramped up and is ready to be started TX path */
  #define RADIO_EVENTS_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXREADY register.                          */

/* EVENTS_TXREADY @Bit 0 : RADIO has ramped up and is ready to be started TX path */
  #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field.                                 */
  #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of
                                                                            EVENTS_TXREADY field.*/
  #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXREADY field.                   */
  #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXREADY field.                   */
  #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_RXREADY: RADIO has ramped up and is ready to be started RX path */
  #define RADIO_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register.                          */

/* EVENTS_RXREADY @Bit 0 : RADIO has ramped up and is ready to be started RX path */
  #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field.                                 */
  #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of
                                                                            EVENTS_RXREADY field.*/
  #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field.                   */
  #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field.                   */
  #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_ADDRESS: Address sent or received */
  #define RADIO_EVENTS_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ADDRESS register.                          */

/* EVENTS_ADDRESS @Bit 0 : Address sent or received */
  #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field.                                 */
  #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of
                                                                            EVENTS_ADDRESS field.*/
  #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Min (0x0UL) /*!< Min enumerator value of EVENTS_ADDRESS field.                   */
  #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Max (0x1UL) /*!< Max enumerator value of EVENTS_ADDRESS field.                   */
  #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_FRAMESTART: IEEE 802.15.4 length field received */
  #define RADIO_EVENTS_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMESTART register.                    */

/* EVENTS_FRAMESTART @Bit 0 : IEEE 802.15.4 length field received */
  #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field.                        */
  #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask
                                                                            of EVENTS_FRAMESTART field.*/
  #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMESTART field.          */
  #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMESTART field.          */
  #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated                                     */


/* RADIO_EVENTS_PAYLOAD: Packet payload sent or received */
  #define RADIO_EVENTS_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PAYLOAD register.                          */

/* EVENTS_PAYLOAD @Bit 0 : Packet payload sent or received */
  #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field.                                 */
  #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of
                                                                            EVENTS_PAYLOAD field.*/
  #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of EVENTS_PAYLOAD field.                   */
  #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of EVENTS_PAYLOAD field.                   */
  #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_END: Memory access for packet data has been completed */
  #define RADIO_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : Memory access for packet data has been completed */
  #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL)      /*!< Position of EVENTS_END field.                                        */
  #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.        */
  #define RADIO_EVENTS_END_EVENTS_END_Min (0x0UL)    /*!< Min enumerator value of EVENTS_END field.                            */
  #define RADIO_EVENTS_END_EVENTS_END_Max (0x1UL)    /*!< Max enumerator value of EVENTS_END field.                            */
  #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                            */
  #define RADIO_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                   */


/* RADIO_EVENTS_PHYEND: The last bit is sent on air or last bit is received */
  #define RADIO_EVENTS_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PHYEND register.                            */

/* EVENTS_PHYEND @Bit 0 : The last bit is sent on air or last bit is received */
  #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field.                                    */
  #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND
                                                                            field.*/
  #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PHYEND field.                      */
  #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PHYEND field.                      */
  #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (0x1UL) /*!< Event generated                                             */


/* RADIO_EVENTS_DISABLED: RADIO has been disabled */
  #define RADIO_EVENTS_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DISABLED register.                        */

/* EVENTS_DISABLED @Bit 0 : RADIO has been disabled */
  #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field.                              */
  #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of
                                                                            EVENTS_DISABLED field.*/
  #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Min (0x0UL) /*!< Min enumerator value of EVENTS_DISABLED field.                */
  #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Max (0x1UL) /*!< Max enumerator value of EVENTS_DISABLED field.                */
  #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (0x1UL) /*!< Event generated                                         */


/* RADIO_EVENTS_DEVMATCH: A device address match occurred on the last received packet */
  #define RADIO_EVENTS_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMATCH register.                        */

/* EVENTS_DEVMATCH @Bit 0 : A device address match occurred on the last received packet */
  #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field.                              */
  #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of
                                                                            EVENTS_DEVMATCH field.*/
  #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMATCH field.                */
  #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMATCH field.                */
  #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (0x1UL) /*!< Event generated                                         */


/* RADIO_EVENTS_DEVMISS: No device address match occurred on the last received packet */
  #define RADIO_EVENTS_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMISS register.                          */

/* EVENTS_DEVMISS @Bit 0 : No device address match occurred on the last received packet */
  #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field.                                 */
  #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of
                                                                            EVENTS_DEVMISS field.*/
  #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMISS field.                   */
  #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMISS field.                   */
  #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_CRCOK: Packet received with CRC ok */
  #define RADIO_EVENTS_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCOK register.                              */

/* EVENTS_CRCOK @Bit 0 : Packet received with CRC ok */
  #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL)  /*!< Position of EVENTS_CRCOK field.                                      */
  #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK
                                                                            field.*/
  #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCOK field.                         */
  #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCOK field.                         */
  #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (0x1UL) /*!< Event generated                                               */


/* RADIO_EVENTS_CRCERROR: Packet received with CRC error */
  #define RADIO_EVENTS_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCERROR register.                        */

/* EVENTS_CRCERROR @Bit 0 : Packet received with CRC error */
  #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field.                              */
  #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of
                                                                            EVENTS_CRCERROR field.*/
  #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCERROR field.                */
  #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCERROR field.                */
  #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (0x1UL) /*!< Event generated                                         */


/* RADIO_EVENTS_BCMATCH: Bit counter reached bit count value */
  #define RADIO_EVENTS_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_BCMATCH register.                          */

/* EVENTS_BCMATCH @Bit 0 : Bit counter reached bit count value */
  #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field.                                 */
  #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of
                                                                            EVENTS_BCMATCH field.*/
  #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_BCMATCH field.                   */
  #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_BCMATCH field.                   */
  #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_EDEND: Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE
                        register) */

  #define RADIO_EVENTS_EDEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDEND register.                              */

/* EVENTS_EDEND @Bit 0 : Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE
                         register) */

  #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL)  /*!< Position of EVENTS_EDEND field.                                      */
  #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND
                                                                            field.*/
  #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDEND field.                         */
  #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDEND field.                         */
  #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (0x1UL) /*!< Event generated                                               */


/* RADIO_EVENTS_EDSTOPPED: The sampling of energy detection has stopped */
  #define RADIO_EVENTS_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDSTOPPED register.                      */

/* EVENTS_EDSTOPPED @Bit 0 : The sampling of energy detection has stopped */
  #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field.                           */
  #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of
                                                                            EVENTS_EDSTOPPED field.*/
  #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDSTOPPED field.             */
  #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDSTOPPED field.             */
  #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (0x1UL) /*!< Event generated                                       */


/* RADIO_EVENTS_CCAIDLE: Wireless medium in idle - clear to send */
  #define RADIO_EVENTS_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCAIDLE register.                          */

/* EVENTS_CCAIDLE @Bit 0 : Wireless medium in idle - clear to send */
  #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field.                                 */
  #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of
                                                                            EVENTS_CCAIDLE field.*/
  #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCAIDLE field.                   */
  #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCAIDLE field.                   */
  #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_CCABUSY: Wireless medium busy - do not send */
  #define RADIO_EVENTS_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCABUSY register.                          */

/* EVENTS_CCABUSY @Bit 0 : Wireless medium busy - do not send */
  #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field.                                 */
  #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of
                                                                            EVENTS_CCABUSY field.*/
  #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCABUSY field.                   */
  #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCABUSY field.                   */
  #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (0x1UL) /*!< Event generated                                           */


/* RADIO_EVENTS_CCASTOPPED: The CCA has stopped */
  #define RADIO_EVENTS_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCASTOPPED register.                    */

/* EVENTS_CCASTOPPED @Bit 0 : The CCA has stopped */
  #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field.                        */
  #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask
                                                                            of EVENTS_CCASTOPPED field.*/
  #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCASTOPPED field.          */
  #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCASTOPPED field.          */
  #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (0x1UL) /*!< Event generated                                     */


/* RADIO_EVENTS_RATEBOOST: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */
  #define RADIO_EVENTS_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RATEBOOST register.                      */

/* EVENTS_RATEBOOST @Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */
  #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field.                           */
  #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of
                                                                            EVENTS_RATEBOOST field.*/
  #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of EVENTS_RATEBOOST field.             */
  #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of EVENTS_RATEBOOST field.             */
  #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (0x1UL) /*!< Event generated                                       */


/* RADIO_EVENTS_MHRMATCH: MAC header match found */
  #define RADIO_EVENTS_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MHRMATCH register.                        */

/* EVENTS_MHRMATCH @Bit 0 : MAC header match found */
  #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field.                              */
  #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of
                                                                            EVENTS_MHRMATCH field.*/
  #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_MHRMATCH field.                */
  #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_MHRMATCH field.                */
  #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (0x1UL) /*!< Event generated                                         */


/* RADIO_EVENTS_SYNC: Initial sync detected */
  #define RADIO_EVENTS_SYNC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SYNC register.                                */

/* EVENTS_SYNC @Bit 0 : Initial sync detected */
  #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL)    /*!< Position of EVENTS_SYNC field.                                       */
  #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field.   */
  #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Min (0x0UL)  /*!< Min enumerator value of EVENTS_SYNC field.                           */
  #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Max (0x1UL)  /*!< Max enumerator value of EVENTS_SYNC field.                           */
  #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (0x1UL) /*!< Event generated                                                 */


/* RADIO_EVENTS_CTEPRESENT: CTEInfo byte is received */
  #define RADIO_EVENTS_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTEPRESENT register.                    */

/* EVENTS_CTEPRESENT @Bit 0 : CTEInfo byte is received */
  #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field.                        */
  #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask
                                                                            of EVENTS_CTEPRESENT field.*/
  #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of EVENTS_CTEPRESENT field.          */
  #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of EVENTS_CTEPRESENT field.          */
  #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (0x1UL) /*!< Event generated                                     */


/* RADIO_PUBLISH_READY: Publish configuration for event READY */
  #define RADIO_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define RADIO_PUBLISH_READY_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_READY_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_READY_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                          */
  #define RADIO_PUBLISH_READY_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_READY_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_READY_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_READY_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_TXREADY: Publish configuration for event TXREADY */
  #define RADIO_PUBLISH_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXREADY register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event TXREADY will publish to */
  #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_TXREADY_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_TXREADY_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_TXREADY_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_TXREADY_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_TXREADY_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_TXREADY_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_RXREADY: Publish configuration for event RXREADY */
  #define RADIO_PUBLISH_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXREADY register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event RXREADY will publish to */
  #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_RXREADY_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_RXREADY_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_RXREADY_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_RXREADY_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_RXREADY_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_RXREADY_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_ADDRESS: Publish configuration for event ADDRESS */
  #define RADIO_PUBLISH_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ADDRESS register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event ADDRESS will publish to */
  #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_ADDRESS_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_ADDRESS_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_ADDRESS_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_ADDRESS_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_ADDRESS_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_FRAMESTART: Publish configuration for event FRAMESTART */
  #define RADIO_PUBLISH_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMESTART register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that event FRAMESTART will publish to */
  #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define RADIO_PUBLISH_FRAMESTART_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define RADIO_PUBLISH_FRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field.                */
  #define RADIO_PUBLISH_FRAMESTART_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_FRAMESTART_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* RADIO_PUBLISH_PAYLOAD: Publish configuration for event PAYLOAD */
  #define RADIO_PUBLISH_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PAYLOAD register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event PAYLOAD will publish to */
  #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_PAYLOAD_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_PAYLOAD_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_PAYLOAD_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_PAYLOAD_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_END: Publish configuration for event END */
  #define RADIO_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define RADIO_PUBLISH_END_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define RADIO_PUBLISH_END_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_END_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_END_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                              */
  #define RADIO_PUBLISH_END_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_END_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_END_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_END_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_PHYEND: Publish configuration for event PHYEND */
  #define RADIO_PUBLISH_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PHYEND register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event PHYEND will publish to */
  #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define RADIO_PUBLISH_PHYEND_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_PHYEND_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field.                        */
  #define RADIO_PUBLISH_PHYEND_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_PHYEND_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_PHYEND_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_PHYEND_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_DISABLED: Publish configuration for event DISABLED */
  #define RADIO_PUBLISH_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DISABLED register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that event DISABLED will publish to */
  #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define RADIO_PUBLISH_DISABLED_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_DISABLED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RADIO_PUBLISH_DISABLED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_DISABLED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_DISABLED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_DISABLED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_DEVMATCH: Publish configuration for event DEVMATCH */
  #define RADIO_PUBLISH_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMATCH register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that event DEVMATCH will publish to */
  #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define RADIO_PUBLISH_DEVMATCH_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_DEVMATCH_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RADIO_PUBLISH_DEVMATCH_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_DEVMATCH_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_DEVMISS: Publish configuration for event DEVMISS */
  #define RADIO_PUBLISH_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMISS register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event DEVMISS will publish to */
  #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_DEVMISS_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_DEVMISS_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_DEVMISS_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_DEVMISS_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_DEVMISS_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_CRCOK: Publish configuration for event CRCOK */
  #define RADIO_PUBLISH_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCOK register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that event CRCOK will publish to */
  #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define RADIO_PUBLISH_CRCOK_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_CRCOK_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field.                          */
  #define RADIO_PUBLISH_CRCOK_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CRCOK_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CRCOK_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_CRCOK_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_CRCERROR: Publish configuration for event CRCERROR */
  #define RADIO_PUBLISH_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCERROR register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that event CRCERROR will publish to */
  #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define RADIO_PUBLISH_CRCERROR_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_CRCERROR_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RADIO_PUBLISH_CRCERROR_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CRCERROR_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_CRCERROR_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_BCMATCH: Publish configuration for event BCMATCH */
  #define RADIO_PUBLISH_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_BCMATCH register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BCMATCH will publish to */
  #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_BCMATCH_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_BCMATCH_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_BCMATCH_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_BCMATCH_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_BCMATCH_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_EDEND: Publish configuration for event EDEND */
  #define RADIO_PUBLISH_EDEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDEND register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that event EDEND will publish to */
  #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define RADIO_PUBLISH_EDEND_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_EDEND_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_EDEND_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field.                          */
  #define RADIO_PUBLISH_EDEND_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_EDEND_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_EDEND_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_EDEND_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_EDSTOPPED: Publish configuration for event EDSTOPPED */
  #define RADIO_PUBLISH_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDSTOPPED register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that event EDSTOPPED will publish to */
  #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field.                  */
  #define RADIO_PUBLISH_EDSTOPPED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_EDSTOPPED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_CCAIDLE: Publish configuration for event CCAIDLE */
  #define RADIO_PUBLISH_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCAIDLE register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event CCAIDLE will publish to */
  #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_CCAIDLE_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_CCAIDLE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_CCAIDLE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CCAIDLE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_CCABUSY: Publish configuration for event CCABUSY */
  #define RADIO_PUBLISH_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCABUSY register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event CCABUSY will publish to */
  #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RADIO_PUBLISH_CCABUSY_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_CCABUSY_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RADIO_PUBLISH_CCABUSY_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CCABUSY_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_CCABUSY_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_CCASTOPPED: Publish configuration for event CCASTOPPED */
  #define RADIO_PUBLISH_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCASTOPPED register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that event CCASTOPPED will publish to */
  #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field.                */
  #define RADIO_PUBLISH_CCASTOPPED_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CCASTOPPED_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* RADIO_PUBLISH_RATEBOOST: Publish configuration for event RATEBOOST */
  #define RADIO_PUBLISH_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RATEBOOST register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that event RATEBOOST will publish to */
  #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define RADIO_PUBLISH_RATEBOOST_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_RATEBOOST_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field.                  */
  #define RADIO_PUBLISH_RATEBOOST_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_RATEBOOST_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_MHRMATCH: Publish configuration for event MHRMATCH */
  #define RADIO_PUBLISH_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_MHRMATCH register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that event MHRMATCH will publish to */
  #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define RADIO_PUBLISH_MHRMATCH_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_MHRMATCH_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RADIO_PUBLISH_MHRMATCH_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_MHRMATCH_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_SYNC: Publish configuration for event SYNC */
  #define RADIO_PUBLISH_SYNC_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SYNC register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event SYNC will publish to */
  #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define RADIO_PUBLISH_SYNC_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define RADIO_PUBLISH_SYNC_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_SYNC_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field.                            */
  #define RADIO_PUBLISH_SYNC_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_SYNC_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_SYNC_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define RADIO_PUBLISH_SYNC_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* RADIO_PUBLISH_CTEPRESENT: Publish configuration for event CTEPRESENT */
  #define RADIO_PUBLISH_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTEPRESENT register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that event CTEPRESENT will publish to */
  #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field.                */
  #define RADIO_PUBLISH_CTEPRESENT_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CTEPRESENT_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* RADIO_SHORTS: Shortcuts between local events and tasks */
  #define RADIO_SHORTS_ResetValue (0x00000000UL)     /*!< Reset value of SHORTS register.                                      */

/* READY_START @Bit 0 : Shortcut between event READY and task START */
  #define RADIO_SHORTS_READY_START_Pos (0UL)         /*!< Position of READY_START field.                                       */
  #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field.             */
  #define RADIO_SHORTS_READY_START_Min (0x0UL)       /*!< Min enumerator value of READY_START field.                           */
  #define RADIO_SHORTS_READY_START_Max (0x1UL)       /*!< Max enumerator value of READY_START field.                           */
  #define RADIO_SHORTS_READY_START_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
  #define RADIO_SHORTS_READY_START_Enabled (0x1UL)   /*!< Enable shortcut                                                      */

/* DISABLED_TXEN @Bit 2 : Shortcut between event DISABLED and task TXEN */
  #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL)       /*!< Position of DISABLED_TXEN field.                                     */
  #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field.       */
  #define RADIO_SHORTS_DISABLED_TXEN_Min (0x0UL)     /*!< Min enumerator value of DISABLED_TXEN field.                         */
  #define RADIO_SHORTS_DISABLED_TXEN_Max (0x1UL)     /*!< Max enumerator value of DISABLED_TXEN field.                         */
  #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define RADIO_SHORTS_DISABLED_TXEN_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* DISABLED_RXEN @Bit 3 : Shortcut between event DISABLED and task RXEN */
  #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL)       /*!< Position of DISABLED_RXEN field.                                     */
  #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field.       */
  #define RADIO_SHORTS_DISABLED_RXEN_Min (0x0UL)     /*!< Min enumerator value of DISABLED_RXEN field.                         */
  #define RADIO_SHORTS_DISABLED_RXEN_Max (0x1UL)     /*!< Max enumerator value of DISABLED_RXEN field.                         */
  #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define RADIO_SHORTS_DISABLED_RXEN_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* ADDRESS_RSSISTART @Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
  #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL)   /*!< Position of ADDRESS_RSSISTART field.                                 */
  #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART
                                                                            field.*/
  #define RADIO_SHORTS_ADDRESS_RSSISTART_Min (0x0UL) /*!< Min enumerator value of ADDRESS_RSSISTART field.                     */
  #define RADIO_SHORTS_ADDRESS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of ADDRESS_RSSISTART field.                     */
  #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0x0UL) /*!< Disable shortcut                                                */
  #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (0x1UL) /*!< Enable shortcut                                                  */

/* END_START @Bit 5 : Shortcut between event END and task START */
  #define RADIO_SHORTS_END_START_Pos (5UL)           /*!< Position of END_START field.                                         */
  #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field.                   */
  #define RADIO_SHORTS_END_START_Min (0x0UL)         /*!< Min enumerator value of END_START field.                             */
  #define RADIO_SHORTS_END_START_Max (0x1UL)         /*!< Max enumerator value of END_START field.                             */
  #define RADIO_SHORTS_END_START_Disabled (0x0UL)    /*!< Disable shortcut                                                     */
  #define RADIO_SHORTS_END_START_Enabled (0x1UL)     /*!< Enable shortcut                                                      */

/* ADDRESS_BCSTART @Bit 6 : Shortcut between event ADDRESS and task BCSTART */
  #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL)     /*!< Position of ADDRESS_BCSTART field.                                   */
  #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
  #define RADIO_SHORTS_ADDRESS_BCSTART_Min (0x0UL)   /*!< Min enumerator value of ADDRESS_BCSTART field.                       */
  #define RADIO_SHORTS_ADDRESS_BCSTART_Max (0x1UL)   /*!< Max enumerator value of ADDRESS_BCSTART field.                       */
  #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut                                                  */
  #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut                                                    */

/* RXREADY_CCASTART @Bit 10 : Shortcut between event RXREADY and task CCASTART */
  #define RADIO_SHORTS_RXREADY_CCASTART_Pos (10UL)   /*!< Position of RXREADY_CCASTART field.                                  */
  #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART
                                                                            field.*/
  #define RADIO_SHORTS_RXREADY_CCASTART_Min (0x0UL)  /*!< Min enumerator value of RXREADY_CCASTART field.                      */
  #define RADIO_SHORTS_RXREADY_CCASTART_Max (0x1UL)  /*!< Max enumerator value of RXREADY_CCASTART field.                      */
  #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0x0UL) /*!< Disable shortcut                                                 */
  #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (0x1UL) /*!< Enable shortcut                                                   */

/* CCAIDLE_TXEN @Bit 11 : Shortcut between event CCAIDLE and task TXEN */
  #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (11UL)       /*!< Position of CCAIDLE_TXEN field.                                      */
  #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field.          */
  #define RADIO_SHORTS_CCAIDLE_TXEN_Min (0x0UL)      /*!< Min enumerator value of CCAIDLE_TXEN field.                          */
  #define RADIO_SHORTS_CCAIDLE_TXEN_Max (0x1UL)      /*!< Max enumerator value of CCAIDLE_TXEN field.                          */
  #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0x0UL) /*!< Disable shortcut                                                     */
  #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (0x1UL)  /*!< Enable shortcut                                                      */

/* CCABUSY_DISABLE @Bit 12 : Shortcut between event CCABUSY and task DISABLE */
  #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (12UL)    /*!< Position of CCABUSY_DISABLE field.                                   */
  #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
  #define RADIO_SHORTS_CCABUSY_DISABLE_Min (0x0UL)   /*!< Min enumerator value of CCABUSY_DISABLE field.                       */
  #define RADIO_SHORTS_CCABUSY_DISABLE_Max (0x1UL)   /*!< Max enumerator value of CCABUSY_DISABLE field.                       */
  #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0x0UL) /*!< Disable shortcut                                                  */
  #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (0x1UL) /*!< Enable shortcut                                                    */

/* FRAMESTART_BCSTART @Bit 13 : Shortcut between event FRAMESTART and task BCSTART */
  #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (13UL) /*!< Position of FRAMESTART_BCSTART field.                                */
  #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART
                                                                            field.*/
  #define RADIO_SHORTS_FRAMESTART_BCSTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART_BCSTART field.                   */
  #define RADIO_SHORTS_FRAMESTART_BCSTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART_BCSTART field.                   */
  #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0x0UL) /*!< Disable shortcut                                               */
  #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (0x1UL) /*!< Enable shortcut                                                 */

/* READY_EDSTART @Bit 14 : Shortcut between event READY and task EDSTART */
  #define RADIO_SHORTS_READY_EDSTART_Pos (14UL)      /*!< Position of READY_EDSTART field.                                     */
  #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field.       */
  #define RADIO_SHORTS_READY_EDSTART_Min (0x0UL)     /*!< Min enumerator value of READY_EDSTART field.                         */
  #define RADIO_SHORTS_READY_EDSTART_Max (0x1UL)     /*!< Max enumerator value of READY_EDSTART field.                         */
  #define RADIO_SHORTS_READY_EDSTART_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define RADIO_SHORTS_READY_EDSTART_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* EDEND_DISABLE @Bit 15 : Shortcut between event EDEND and task DISABLE */
  #define RADIO_SHORTS_EDEND_DISABLE_Pos (15UL)      /*!< Position of EDEND_DISABLE field.                                     */
  #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field.       */
  #define RADIO_SHORTS_EDEND_DISABLE_Min (0x0UL)     /*!< Min enumerator value of EDEND_DISABLE field.                         */
  #define RADIO_SHORTS_EDEND_DISABLE_Max (0x1UL)     /*!< Max enumerator value of EDEND_DISABLE field.                         */
  #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define RADIO_SHORTS_EDEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* CCAIDLE_STOP @Bit 16 : Shortcut between event CCAIDLE and task STOP */
  #define RADIO_SHORTS_CCAIDLE_STOP_Pos (16UL)       /*!< Position of CCAIDLE_STOP field.                                      */
  #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field.          */
  #define RADIO_SHORTS_CCAIDLE_STOP_Min (0x0UL)      /*!< Min enumerator value of CCAIDLE_STOP field.                          */
  #define RADIO_SHORTS_CCAIDLE_STOP_Max (0x1UL)      /*!< Max enumerator value of CCAIDLE_STOP field.                          */
  #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                     */
  #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (0x1UL)  /*!< Enable shortcut                                                      */

/* TXREADY_START @Bit 17 : Shortcut between event TXREADY and task START */
  #define RADIO_SHORTS_TXREADY_START_Pos (17UL)      /*!< Position of TXREADY_START field.                                     */
  #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field.       */
  #define RADIO_SHORTS_TXREADY_START_Min (0x0UL)     /*!< Min enumerator value of TXREADY_START field.                         */
  #define RADIO_SHORTS_TXREADY_START_Max (0x1UL)     /*!< Max enumerator value of TXREADY_START field.                         */
  #define RADIO_SHORTS_TXREADY_START_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define RADIO_SHORTS_TXREADY_START_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* RXREADY_START @Bit 18 : Shortcut between event RXREADY and task START */
  #define RADIO_SHORTS_RXREADY_START_Pos (18UL)      /*!< Position of RXREADY_START field.                                     */
  #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field.       */
  #define RADIO_SHORTS_RXREADY_START_Min (0x0UL)     /*!< Min enumerator value of RXREADY_START field.                         */
  #define RADIO_SHORTS_RXREADY_START_Max (0x1UL)     /*!< Max enumerator value of RXREADY_START field.                         */
  #define RADIO_SHORTS_RXREADY_START_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define RADIO_SHORTS_RXREADY_START_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* PHYEND_DISABLE @Bit 19 : Shortcut between event PHYEND and task DISABLE */
  #define RADIO_SHORTS_PHYEND_DISABLE_Pos (19UL)     /*!< Position of PHYEND_DISABLE field.                                    */
  #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field.    */
  #define RADIO_SHORTS_PHYEND_DISABLE_Min (0x0UL)    /*!< Min enumerator value of PHYEND_DISABLE field.                        */
  #define RADIO_SHORTS_PHYEND_DISABLE_Max (0x1UL)    /*!< Max enumerator value of PHYEND_DISABLE field.                        */
  #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* PHYEND_START @Bit 20 : Shortcut between event PHYEND and task START */
  #define RADIO_SHORTS_PHYEND_START_Pos (20UL)       /*!< Position of PHYEND_START field.                                      */
  #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field.          */
  #define RADIO_SHORTS_PHYEND_START_Min (0x0UL)      /*!< Min enumerator value of PHYEND_START field.                          */
  #define RADIO_SHORTS_PHYEND_START_Max (0x1UL)      /*!< Max enumerator value of PHYEND_START field.                          */
  #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut                                                     */
  #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL)  /*!< Enable shortcut                                                      */


/* RADIO_INTENSET00: Enable interrupt */
  #define RADIO_INTENSET00_ResetValue (0x00000000UL) /*!< Reset value of INTENSET00 register.                                  */

/* READY @Bit 0 : Write '1' to enable interrupt for event READY */
  #define RADIO_INTENSET00_READY_Pos (0UL)           /*!< Position of READY field.                                             */
  #define RADIO_INTENSET00_READY_Msk (0x1UL << RADIO_INTENSET00_READY_Pos) /*!< Bit mask of READY field.                       */
  #define RADIO_INTENSET00_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
  #define RADIO_INTENSET00_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
  #define RADIO_INTENSET00_READY_Set (0x1UL)         /*!< Enable                                                               */
  #define RADIO_INTENSET00_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */
  #define RADIO_INTENSET00_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
  #define RADIO_INTENSET00_TXREADY_Msk (0x1UL << RADIO_INTENSET00_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
  #define RADIO_INTENSET00_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
  #define RADIO_INTENSET00_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
  #define RADIO_INTENSET00_TXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */
  #define RADIO_INTENSET00_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
  #define RADIO_INTENSET00_RXREADY_Msk (0x1UL << RADIO_INTENSET00_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
  #define RADIO_INTENSET00_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
  #define RADIO_INTENSET00_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
  #define RADIO_INTENSET00_RXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */
  #define RADIO_INTENSET00_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
  #define RADIO_INTENSET00_ADDRESS_Msk (0x1UL << RADIO_INTENSET00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
  #define RADIO_INTENSET00_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
  #define RADIO_INTENSET00_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
  #define RADIO_INTENSET00_ADDRESS_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */
  #define RADIO_INTENSET00_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
  #define RADIO_INTENSET00_FRAMESTART_Msk (0x1UL << RADIO_INTENSET00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
  #define RADIO_INTENSET00_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENSET00_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENSET00_FRAMESTART_Set (0x1UL)    /*!< Enable                                                               */
  #define RADIO_INTENSET00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENSET00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */
  #define RADIO_INTENSET00_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
  #define RADIO_INTENSET00_PAYLOAD_Msk (0x1UL << RADIO_INTENSET00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
  #define RADIO_INTENSET00_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENSET00_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENSET00_PAYLOAD_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* END @Bit 6 : Write '1' to enable interrupt for event END */
  #define RADIO_INTENSET00_END_Pos (6UL)             /*!< Position of END field.                                               */
  #define RADIO_INTENSET00_END_Msk (0x1UL << RADIO_INTENSET00_END_Pos) /*!< Bit mask of END field.                             */
  #define RADIO_INTENSET00_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
  #define RADIO_INTENSET00_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
  #define RADIO_INTENSET00_END_Set (0x1UL)           /*!< Enable                                                               */
  #define RADIO_INTENSET00_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */
  #define RADIO_INTENSET00_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
  #define RADIO_INTENSET00_PHYEND_Msk (0x1UL << RADIO_INTENSET00_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
  #define RADIO_INTENSET00_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
  #define RADIO_INTENSET00_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
  #define RADIO_INTENSET00_PHYEND_Set (0x1UL)        /*!< Enable                                                               */
  #define RADIO_INTENSET00_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */
  #define RADIO_INTENSET00_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
  #define RADIO_INTENSET00_DISABLED_Msk (0x1UL << RADIO_INTENSET00_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
  #define RADIO_INTENSET00_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
  #define RADIO_INTENSET00_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
  #define RADIO_INTENSET00_DISABLED_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */
  #define RADIO_INTENSET00_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
  #define RADIO_INTENSET00_DEVMATCH_Msk (0x1UL << RADIO_INTENSET00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
  #define RADIO_INTENSET00_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENSET00_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENSET00_DEVMATCH_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */
  #define RADIO_INTENSET00_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
  #define RADIO_INTENSET00_DEVMISS_Msk (0x1UL << RADIO_INTENSET00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
  #define RADIO_INTENSET00_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
  #define RADIO_INTENSET00_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
  #define RADIO_INTENSET00_DEVMISS_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */
  #define RADIO_INTENSET00_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
  #define RADIO_INTENSET00_CRCOK_Msk (0x1UL << RADIO_INTENSET00_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
  #define RADIO_INTENSET00_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
  #define RADIO_INTENSET00_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
  #define RADIO_INTENSET00_CRCOK_Set (0x1UL)         /*!< Enable                                                               */
  #define RADIO_INTENSET00_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */
  #define RADIO_INTENSET00_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
  #define RADIO_INTENSET00_CRCERROR_Msk (0x1UL << RADIO_INTENSET00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
  #define RADIO_INTENSET00_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
  #define RADIO_INTENSET00_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
  #define RADIO_INTENSET00_CRCERROR_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */
  #define RADIO_INTENSET00_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
  #define RADIO_INTENSET00_BCMATCH_Msk (0x1UL << RADIO_INTENSET00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
  #define RADIO_INTENSET00_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
  #define RADIO_INTENSET00_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
  #define RADIO_INTENSET00_BCMATCH_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */
  #define RADIO_INTENSET00_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
  #define RADIO_INTENSET00_EDEND_Msk (0x1UL << RADIO_INTENSET00_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
  #define RADIO_INTENSET00_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
  #define RADIO_INTENSET00_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
  #define RADIO_INTENSET00_EDEND_Set (0x1UL)         /*!< Enable                                                               */
  #define RADIO_INTENSET00_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
  #define RADIO_INTENSET00_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
  #define RADIO_INTENSET00_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
  #define RADIO_INTENSET00_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENSET00_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENSET00_EDSTOPPED_Set (0x1UL)     /*!< Enable                                                               */
  #define RADIO_INTENSET00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENSET00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
  #define RADIO_INTENSET00_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
  #define RADIO_INTENSET00_CCAIDLE_Msk (0x1UL << RADIO_INTENSET00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
  #define RADIO_INTENSET00_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENSET00_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENSET00_CCAIDLE_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */
  #define RADIO_INTENSET00_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
  #define RADIO_INTENSET00_CCABUSY_Msk (0x1UL << RADIO_INTENSET00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
  #define RADIO_INTENSET00_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
  #define RADIO_INTENSET00_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
  #define RADIO_INTENSET00_CCABUSY_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET00_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
  #define RADIO_INTENSET00_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
  #define RADIO_INTENSET00_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
  #define RADIO_INTENSET00_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENSET00_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENSET00_CCASTOPPED_Set (0x1UL)    /*!< Enable                                                               */
  #define RADIO_INTENSET00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENSET00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
  #define RADIO_INTENSET00_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
  #define RADIO_INTENSET00_RATEBOOST_Msk (0x1UL << RADIO_INTENSET00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
  #define RADIO_INTENSET00_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENSET00_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENSET00_RATEBOOST_Set (0x1UL)     /*!< Enable                                                               */
  #define RADIO_INTENSET00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENSET00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */
  #define RADIO_INTENSET00_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
  #define RADIO_INTENSET00_MHRMATCH_Msk (0x1UL << RADIO_INTENSET00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
  #define RADIO_INTENSET00_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENSET00_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENSET00_MHRMATCH_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */
  #define RADIO_INTENSET00_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
  #define RADIO_INTENSET00_SYNC_Msk (0x1UL << RADIO_INTENSET00_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
  #define RADIO_INTENSET00_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
  #define RADIO_INTENSET00_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
  #define RADIO_INTENSET00_SYNC_Set (0x1UL)          /*!< Enable                                                               */
  #define RADIO_INTENSET00_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET00_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */
  #define RADIO_INTENSET00_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
  #define RADIO_INTENSET00_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
  #define RADIO_INTENSET00_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENSET00_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENSET00_CTEPRESENT_Set (0x1UL)    /*!< Enable                                                               */
  #define RADIO_INTENSET00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENSET00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* RADIO_INTENCLR00: Disable interrupt */
  #define RADIO_INTENCLR00_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR00 register.                                  */

/* READY @Bit 0 : Write '1' to disable interrupt for event READY */
  #define RADIO_INTENCLR00_READY_Pos (0UL)           /*!< Position of READY field.                                             */
  #define RADIO_INTENCLR00_READY_Msk (0x1UL << RADIO_INTENCLR00_READY_Pos) /*!< Bit mask of READY field.                       */
  #define RADIO_INTENCLR00_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
  #define RADIO_INTENCLR00_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
  #define RADIO_INTENCLR00_READY_Clear (0x1UL)       /*!< Disable                                                              */
  #define RADIO_INTENCLR00_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */
  #define RADIO_INTENCLR00_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
  #define RADIO_INTENCLR00_TXREADY_Msk (0x1UL << RADIO_INTENCLR00_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
  #define RADIO_INTENCLR00_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
  #define RADIO_INTENCLR00_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
  #define RADIO_INTENCLR00_TXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */
  #define RADIO_INTENCLR00_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
  #define RADIO_INTENCLR00_RXREADY_Msk (0x1UL << RADIO_INTENCLR00_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
  #define RADIO_INTENCLR00_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
  #define RADIO_INTENCLR00_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
  #define RADIO_INTENCLR00_RXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */
  #define RADIO_INTENCLR00_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
  #define RADIO_INTENCLR00_ADDRESS_Msk (0x1UL << RADIO_INTENCLR00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
  #define RADIO_INTENCLR00_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
  #define RADIO_INTENCLR00_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
  #define RADIO_INTENCLR00_ADDRESS_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */
  #define RADIO_INTENCLR00_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
  #define RADIO_INTENCLR00_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
  #define RADIO_INTENCLR00_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENCLR00_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENCLR00_FRAMESTART_Clear (0x1UL)  /*!< Disable                                                              */
  #define RADIO_INTENCLR00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENCLR00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */
  #define RADIO_INTENCLR00_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
  #define RADIO_INTENCLR00_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
  #define RADIO_INTENCLR00_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENCLR00_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENCLR00_PAYLOAD_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* END @Bit 6 : Write '1' to disable interrupt for event END */
  #define RADIO_INTENCLR00_END_Pos (6UL)             /*!< Position of END field.                                               */
  #define RADIO_INTENCLR00_END_Msk (0x1UL << RADIO_INTENCLR00_END_Pos) /*!< Bit mask of END field.                             */
  #define RADIO_INTENCLR00_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
  #define RADIO_INTENCLR00_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
  #define RADIO_INTENCLR00_END_Clear (0x1UL)         /*!< Disable                                                              */
  #define RADIO_INTENCLR00_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */
  #define RADIO_INTENCLR00_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
  #define RADIO_INTENCLR00_PHYEND_Msk (0x1UL << RADIO_INTENCLR00_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
  #define RADIO_INTENCLR00_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
  #define RADIO_INTENCLR00_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
  #define RADIO_INTENCLR00_PHYEND_Clear (0x1UL)      /*!< Disable                                                              */
  #define RADIO_INTENCLR00_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */
  #define RADIO_INTENCLR00_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
  #define RADIO_INTENCLR00_DISABLED_Msk (0x1UL << RADIO_INTENCLR00_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
  #define RADIO_INTENCLR00_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
  #define RADIO_INTENCLR00_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
  #define RADIO_INTENCLR00_DISABLED_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */
  #define RADIO_INTENCLR00_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
  #define RADIO_INTENCLR00_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
  #define RADIO_INTENCLR00_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENCLR00_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENCLR00_DEVMATCH_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */
  #define RADIO_INTENCLR00_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
  #define RADIO_INTENCLR00_DEVMISS_Msk (0x1UL << RADIO_INTENCLR00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
  #define RADIO_INTENCLR00_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
  #define RADIO_INTENCLR00_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
  #define RADIO_INTENCLR00_DEVMISS_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */
  #define RADIO_INTENCLR00_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
  #define RADIO_INTENCLR00_CRCOK_Msk (0x1UL << RADIO_INTENCLR00_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
  #define RADIO_INTENCLR00_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
  #define RADIO_INTENCLR00_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
  #define RADIO_INTENCLR00_CRCOK_Clear (0x1UL)       /*!< Disable                                                              */
  #define RADIO_INTENCLR00_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */
  #define RADIO_INTENCLR00_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
  #define RADIO_INTENCLR00_CRCERROR_Msk (0x1UL << RADIO_INTENCLR00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
  #define RADIO_INTENCLR00_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
  #define RADIO_INTENCLR00_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
  #define RADIO_INTENCLR00_CRCERROR_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */
  #define RADIO_INTENCLR00_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
  #define RADIO_INTENCLR00_BCMATCH_Msk (0x1UL << RADIO_INTENCLR00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
  #define RADIO_INTENCLR00_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
  #define RADIO_INTENCLR00_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
  #define RADIO_INTENCLR00_BCMATCH_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */
  #define RADIO_INTENCLR00_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
  #define RADIO_INTENCLR00_EDEND_Msk (0x1UL << RADIO_INTENCLR00_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
  #define RADIO_INTENCLR00_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
  #define RADIO_INTENCLR00_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
  #define RADIO_INTENCLR00_EDEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define RADIO_INTENCLR00_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
  #define RADIO_INTENCLR00_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
  #define RADIO_INTENCLR00_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
  #define RADIO_INTENCLR00_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENCLR00_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENCLR00_EDSTOPPED_Clear (0x1UL)   /*!< Disable                                                              */
  #define RADIO_INTENCLR00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENCLR00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
  #define RADIO_INTENCLR00_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
  #define RADIO_INTENCLR00_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
  #define RADIO_INTENCLR00_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENCLR00_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENCLR00_CCAIDLE_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */
  #define RADIO_INTENCLR00_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
  #define RADIO_INTENCLR00_CCABUSY_Msk (0x1UL << RADIO_INTENCLR00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
  #define RADIO_INTENCLR00_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
  #define RADIO_INTENCLR00_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
  #define RADIO_INTENCLR00_CCABUSY_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR00_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
  #define RADIO_INTENCLR00_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
  #define RADIO_INTENCLR00_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
  #define RADIO_INTENCLR00_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENCLR00_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENCLR00_CCASTOPPED_Clear (0x1UL)  /*!< Disable                                                              */
  #define RADIO_INTENCLR00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENCLR00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
  #define RADIO_INTENCLR00_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
  #define RADIO_INTENCLR00_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
  #define RADIO_INTENCLR00_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENCLR00_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENCLR00_RATEBOOST_Clear (0x1UL)   /*!< Disable                                                              */
  #define RADIO_INTENCLR00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENCLR00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */
  #define RADIO_INTENCLR00_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
  #define RADIO_INTENCLR00_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
  #define RADIO_INTENCLR00_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENCLR00_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENCLR00_MHRMATCH_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */
  #define RADIO_INTENCLR00_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
  #define RADIO_INTENCLR00_SYNC_Msk (0x1UL << RADIO_INTENCLR00_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
  #define RADIO_INTENCLR00_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
  #define RADIO_INTENCLR00_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
  #define RADIO_INTENCLR00_SYNC_Clear (0x1UL)        /*!< Disable                                                              */
  #define RADIO_INTENCLR00_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR00_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */
  #define RADIO_INTENCLR00_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
  #define RADIO_INTENCLR00_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
  #define RADIO_INTENCLR00_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENCLR00_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENCLR00_CTEPRESENT_Clear (0x1UL)  /*!< Disable                                                              */
  #define RADIO_INTENCLR00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENCLR00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* RADIO_INTENSET10: Enable interrupt */
  #define RADIO_INTENSET10_ResetValue (0x00000000UL) /*!< Reset value of INTENSET10 register.                                  */

/* READY @Bit 0 : Write '1' to enable interrupt for event READY */
  #define RADIO_INTENSET10_READY_Pos (0UL)           /*!< Position of READY field.                                             */
  #define RADIO_INTENSET10_READY_Msk (0x1UL << RADIO_INTENSET10_READY_Pos) /*!< Bit mask of READY field.                       */
  #define RADIO_INTENSET10_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
  #define RADIO_INTENSET10_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
  #define RADIO_INTENSET10_READY_Set (0x1UL)         /*!< Enable                                                               */
  #define RADIO_INTENSET10_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */
  #define RADIO_INTENSET10_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
  #define RADIO_INTENSET10_TXREADY_Msk (0x1UL << RADIO_INTENSET10_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
  #define RADIO_INTENSET10_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
  #define RADIO_INTENSET10_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
  #define RADIO_INTENSET10_TXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */
  #define RADIO_INTENSET10_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
  #define RADIO_INTENSET10_RXREADY_Msk (0x1UL << RADIO_INTENSET10_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
  #define RADIO_INTENSET10_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
  #define RADIO_INTENSET10_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
  #define RADIO_INTENSET10_RXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */
  #define RADIO_INTENSET10_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
  #define RADIO_INTENSET10_ADDRESS_Msk (0x1UL << RADIO_INTENSET10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
  #define RADIO_INTENSET10_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
  #define RADIO_INTENSET10_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
  #define RADIO_INTENSET10_ADDRESS_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */
  #define RADIO_INTENSET10_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
  #define RADIO_INTENSET10_FRAMESTART_Msk (0x1UL << RADIO_INTENSET10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
  #define RADIO_INTENSET10_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENSET10_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENSET10_FRAMESTART_Set (0x1UL)    /*!< Enable                                                               */
  #define RADIO_INTENSET10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENSET10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */
  #define RADIO_INTENSET10_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
  #define RADIO_INTENSET10_PAYLOAD_Msk (0x1UL << RADIO_INTENSET10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
  #define RADIO_INTENSET10_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENSET10_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENSET10_PAYLOAD_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* END @Bit 6 : Write '1' to enable interrupt for event END */
  #define RADIO_INTENSET10_END_Pos (6UL)             /*!< Position of END field.                                               */
  #define RADIO_INTENSET10_END_Msk (0x1UL << RADIO_INTENSET10_END_Pos) /*!< Bit mask of END field.                             */
  #define RADIO_INTENSET10_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
  #define RADIO_INTENSET10_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
  #define RADIO_INTENSET10_END_Set (0x1UL)           /*!< Enable                                                               */
  #define RADIO_INTENSET10_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */
  #define RADIO_INTENSET10_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
  #define RADIO_INTENSET10_PHYEND_Msk (0x1UL << RADIO_INTENSET10_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
  #define RADIO_INTENSET10_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
  #define RADIO_INTENSET10_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
  #define RADIO_INTENSET10_PHYEND_Set (0x1UL)        /*!< Enable                                                               */
  #define RADIO_INTENSET10_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */
  #define RADIO_INTENSET10_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
  #define RADIO_INTENSET10_DISABLED_Msk (0x1UL << RADIO_INTENSET10_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
  #define RADIO_INTENSET10_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
  #define RADIO_INTENSET10_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
  #define RADIO_INTENSET10_DISABLED_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */
  #define RADIO_INTENSET10_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
  #define RADIO_INTENSET10_DEVMATCH_Msk (0x1UL << RADIO_INTENSET10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
  #define RADIO_INTENSET10_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENSET10_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENSET10_DEVMATCH_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */
  #define RADIO_INTENSET10_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
  #define RADIO_INTENSET10_DEVMISS_Msk (0x1UL << RADIO_INTENSET10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
  #define RADIO_INTENSET10_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
  #define RADIO_INTENSET10_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
  #define RADIO_INTENSET10_DEVMISS_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */
  #define RADIO_INTENSET10_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
  #define RADIO_INTENSET10_CRCOK_Msk (0x1UL << RADIO_INTENSET10_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
  #define RADIO_INTENSET10_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
  #define RADIO_INTENSET10_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
  #define RADIO_INTENSET10_CRCOK_Set (0x1UL)         /*!< Enable                                                               */
  #define RADIO_INTENSET10_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */
  #define RADIO_INTENSET10_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
  #define RADIO_INTENSET10_CRCERROR_Msk (0x1UL << RADIO_INTENSET10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
  #define RADIO_INTENSET10_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
  #define RADIO_INTENSET10_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
  #define RADIO_INTENSET10_CRCERROR_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */
  #define RADIO_INTENSET10_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
  #define RADIO_INTENSET10_BCMATCH_Msk (0x1UL << RADIO_INTENSET10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
  #define RADIO_INTENSET10_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
  #define RADIO_INTENSET10_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
  #define RADIO_INTENSET10_BCMATCH_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */
  #define RADIO_INTENSET10_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
  #define RADIO_INTENSET10_EDEND_Msk (0x1UL << RADIO_INTENSET10_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
  #define RADIO_INTENSET10_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
  #define RADIO_INTENSET10_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
  #define RADIO_INTENSET10_EDEND_Set (0x1UL)         /*!< Enable                                                               */
  #define RADIO_INTENSET10_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
  #define RADIO_INTENSET10_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
  #define RADIO_INTENSET10_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
  #define RADIO_INTENSET10_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENSET10_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENSET10_EDSTOPPED_Set (0x1UL)     /*!< Enable                                                               */
  #define RADIO_INTENSET10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENSET10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
  #define RADIO_INTENSET10_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
  #define RADIO_INTENSET10_CCAIDLE_Msk (0x1UL << RADIO_INTENSET10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
  #define RADIO_INTENSET10_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENSET10_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENSET10_CCAIDLE_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */
  #define RADIO_INTENSET10_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
  #define RADIO_INTENSET10_CCABUSY_Msk (0x1UL << RADIO_INTENSET10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
  #define RADIO_INTENSET10_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
  #define RADIO_INTENSET10_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
  #define RADIO_INTENSET10_CCABUSY_Set (0x1UL)       /*!< Enable                                                               */
  #define RADIO_INTENSET10_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
  #define RADIO_INTENSET10_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
  #define RADIO_INTENSET10_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
  #define RADIO_INTENSET10_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENSET10_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENSET10_CCASTOPPED_Set (0x1UL)    /*!< Enable                                                               */
  #define RADIO_INTENSET10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENSET10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
  #define RADIO_INTENSET10_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
  #define RADIO_INTENSET10_RATEBOOST_Msk (0x1UL << RADIO_INTENSET10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
  #define RADIO_INTENSET10_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENSET10_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENSET10_RATEBOOST_Set (0x1UL)     /*!< Enable                                                               */
  #define RADIO_INTENSET10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENSET10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */
  #define RADIO_INTENSET10_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
  #define RADIO_INTENSET10_MHRMATCH_Msk (0x1UL << RADIO_INTENSET10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
  #define RADIO_INTENSET10_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENSET10_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENSET10_MHRMATCH_Set (0x1UL)      /*!< Enable                                                               */
  #define RADIO_INTENSET10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */
  #define RADIO_INTENSET10_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
  #define RADIO_INTENSET10_SYNC_Msk (0x1UL << RADIO_INTENSET10_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
  #define RADIO_INTENSET10_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
  #define RADIO_INTENSET10_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
  #define RADIO_INTENSET10_SYNC_Set (0x1UL)          /*!< Enable                                                               */
  #define RADIO_INTENSET10_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define RADIO_INTENSET10_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */
  #define RADIO_INTENSET10_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
  #define RADIO_INTENSET10_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
  #define RADIO_INTENSET10_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENSET10_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENSET10_CTEPRESENT_Set (0x1UL)    /*!< Enable                                                               */
  #define RADIO_INTENSET10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENSET10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* RADIO_INTENCLR10: Disable interrupt */
  #define RADIO_INTENCLR10_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR10 register.                                  */

/* READY @Bit 0 : Write '1' to disable interrupt for event READY */
  #define RADIO_INTENCLR10_READY_Pos (0UL)           /*!< Position of READY field.                                             */
  #define RADIO_INTENCLR10_READY_Msk (0x1UL << RADIO_INTENCLR10_READY_Pos) /*!< Bit mask of READY field.                       */
  #define RADIO_INTENCLR10_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
  #define RADIO_INTENCLR10_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
  #define RADIO_INTENCLR10_READY_Clear (0x1UL)       /*!< Disable                                                              */
  #define RADIO_INTENCLR10_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */
  #define RADIO_INTENCLR10_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
  #define RADIO_INTENCLR10_TXREADY_Msk (0x1UL << RADIO_INTENCLR10_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
  #define RADIO_INTENCLR10_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
  #define RADIO_INTENCLR10_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
  #define RADIO_INTENCLR10_TXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */
  #define RADIO_INTENCLR10_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
  #define RADIO_INTENCLR10_RXREADY_Msk (0x1UL << RADIO_INTENCLR10_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
  #define RADIO_INTENCLR10_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
  #define RADIO_INTENCLR10_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
  #define RADIO_INTENCLR10_RXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */
  #define RADIO_INTENCLR10_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
  #define RADIO_INTENCLR10_ADDRESS_Msk (0x1UL << RADIO_INTENCLR10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
  #define RADIO_INTENCLR10_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
  #define RADIO_INTENCLR10_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
  #define RADIO_INTENCLR10_ADDRESS_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */
  #define RADIO_INTENCLR10_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
  #define RADIO_INTENCLR10_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
  #define RADIO_INTENCLR10_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENCLR10_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
  #define RADIO_INTENCLR10_FRAMESTART_Clear (0x1UL)  /*!< Disable                                                              */
  #define RADIO_INTENCLR10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENCLR10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */
  #define RADIO_INTENCLR10_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
  #define RADIO_INTENCLR10_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
  #define RADIO_INTENCLR10_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENCLR10_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
  #define RADIO_INTENCLR10_PAYLOAD_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* END @Bit 6 : Write '1' to disable interrupt for event END */
  #define RADIO_INTENCLR10_END_Pos (6UL)             /*!< Position of END field.                                               */
  #define RADIO_INTENCLR10_END_Msk (0x1UL << RADIO_INTENCLR10_END_Pos) /*!< Bit mask of END field.                             */
  #define RADIO_INTENCLR10_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
  #define RADIO_INTENCLR10_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
  #define RADIO_INTENCLR10_END_Clear (0x1UL)         /*!< Disable                                                              */
  #define RADIO_INTENCLR10_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */
  #define RADIO_INTENCLR10_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
  #define RADIO_INTENCLR10_PHYEND_Msk (0x1UL << RADIO_INTENCLR10_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
  #define RADIO_INTENCLR10_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
  #define RADIO_INTENCLR10_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
  #define RADIO_INTENCLR10_PHYEND_Clear (0x1UL)      /*!< Disable                                                              */
  #define RADIO_INTENCLR10_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */
  #define RADIO_INTENCLR10_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
  #define RADIO_INTENCLR10_DISABLED_Msk (0x1UL << RADIO_INTENCLR10_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
  #define RADIO_INTENCLR10_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
  #define RADIO_INTENCLR10_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
  #define RADIO_INTENCLR10_DISABLED_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */
  #define RADIO_INTENCLR10_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
  #define RADIO_INTENCLR10_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
  #define RADIO_INTENCLR10_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENCLR10_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
  #define RADIO_INTENCLR10_DEVMATCH_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */
  #define RADIO_INTENCLR10_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
  #define RADIO_INTENCLR10_DEVMISS_Msk (0x1UL << RADIO_INTENCLR10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
  #define RADIO_INTENCLR10_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
  #define RADIO_INTENCLR10_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
  #define RADIO_INTENCLR10_DEVMISS_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */
  #define RADIO_INTENCLR10_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
  #define RADIO_INTENCLR10_CRCOK_Msk (0x1UL << RADIO_INTENCLR10_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
  #define RADIO_INTENCLR10_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
  #define RADIO_INTENCLR10_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
  #define RADIO_INTENCLR10_CRCOK_Clear (0x1UL)       /*!< Disable                                                              */
  #define RADIO_INTENCLR10_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */
  #define RADIO_INTENCLR10_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
  #define RADIO_INTENCLR10_CRCERROR_Msk (0x1UL << RADIO_INTENCLR10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
  #define RADIO_INTENCLR10_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
  #define RADIO_INTENCLR10_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
  #define RADIO_INTENCLR10_CRCERROR_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */
  #define RADIO_INTENCLR10_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
  #define RADIO_INTENCLR10_BCMATCH_Msk (0x1UL << RADIO_INTENCLR10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
  #define RADIO_INTENCLR10_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
  #define RADIO_INTENCLR10_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
  #define RADIO_INTENCLR10_BCMATCH_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */
  #define RADIO_INTENCLR10_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
  #define RADIO_INTENCLR10_EDEND_Msk (0x1UL << RADIO_INTENCLR10_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
  #define RADIO_INTENCLR10_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
  #define RADIO_INTENCLR10_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
  #define RADIO_INTENCLR10_EDEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define RADIO_INTENCLR10_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
  #define RADIO_INTENCLR10_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
  #define RADIO_INTENCLR10_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
  #define RADIO_INTENCLR10_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENCLR10_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
  #define RADIO_INTENCLR10_EDSTOPPED_Clear (0x1UL)   /*!< Disable                                                              */
  #define RADIO_INTENCLR10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENCLR10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
  #define RADIO_INTENCLR10_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
  #define RADIO_INTENCLR10_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
  #define RADIO_INTENCLR10_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENCLR10_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
  #define RADIO_INTENCLR10_CCAIDLE_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */
  #define RADIO_INTENCLR10_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
  #define RADIO_INTENCLR10_CCABUSY_Msk (0x1UL << RADIO_INTENCLR10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
  #define RADIO_INTENCLR10_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
  #define RADIO_INTENCLR10_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
  #define RADIO_INTENCLR10_CCABUSY_Clear (0x1UL)     /*!< Disable                                                              */
  #define RADIO_INTENCLR10_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
  #define RADIO_INTENCLR10_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
  #define RADIO_INTENCLR10_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
  #define RADIO_INTENCLR10_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENCLR10_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
  #define RADIO_INTENCLR10_CCASTOPPED_Clear (0x1UL)  /*!< Disable                                                              */
  #define RADIO_INTENCLR10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENCLR10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
  #define RADIO_INTENCLR10_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
  #define RADIO_INTENCLR10_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
  #define RADIO_INTENCLR10_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENCLR10_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
  #define RADIO_INTENCLR10_RATEBOOST_Clear (0x1UL)   /*!< Disable                                                              */
  #define RADIO_INTENCLR10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RADIO_INTENCLR10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */
  #define RADIO_INTENCLR10_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
  #define RADIO_INTENCLR10_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
  #define RADIO_INTENCLR10_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENCLR10_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
  #define RADIO_INTENCLR10_MHRMATCH_Clear (0x1UL)    /*!< Disable                                                              */
  #define RADIO_INTENCLR10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */
  #define RADIO_INTENCLR10_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
  #define RADIO_INTENCLR10_SYNC_Msk (0x1UL << RADIO_INTENCLR10_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
  #define RADIO_INTENCLR10_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
  #define RADIO_INTENCLR10_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
  #define RADIO_INTENCLR10_SYNC_Clear (0x1UL)        /*!< Disable                                                              */
  #define RADIO_INTENCLR10_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define RADIO_INTENCLR10_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */
  #define RADIO_INTENCLR10_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
  #define RADIO_INTENCLR10_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
  #define RADIO_INTENCLR10_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENCLR10_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
  #define RADIO_INTENCLR10_CTEPRESENT_Clear (0x1UL)  /*!< Disable                                                              */
  #define RADIO_INTENCLR10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define RADIO_INTENCLR10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* RADIO_MODE: Data rate and modulation */
  #define RADIO_MODE_ResetValue (0x00000000UL)       /*!< Reset value of MODE register.                                        */

/* MODE @Bits 0..3 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
  #define RADIO_MODE_MODE_Pos (0UL)                  /*!< Position of MODE field.                                              */
  #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                      */
  #define RADIO_MODE_MODE_Min (0x0UL)                /*!< Min enumerator value of MODE field.                                  */
  #define RADIO_MODE_MODE_Max (0xFUL)                /*!< Max enumerator value of MODE field.                                  */
  #define RADIO_MODE_MODE_Nrf_1Mbit (0x0UL)          /*!< 1 Mbps Nordic proprietary radio mode                                 */
  #define RADIO_MODE_MODE_Nrf_2Mbit (0x1UL)          /*!< 2 Mbps Nordic proprietary radio mode                                 */
  #define RADIO_MODE_MODE_Ble_1Mbit (0x3UL)          /*!< 1 Mbps BLE                                                           */
  #define RADIO_MODE_MODE_Ble_2Mbit (0x4UL)          /*!< 2 Mbps BLE                                                           */
  #define RADIO_MODE_MODE_Ble_LR125Kbit (0x5UL)      /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX                     */
  #define RADIO_MODE_MODE_Ble_LR500Kbit (0x6UL)      /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX                     */
  #define RADIO_MODE_MODE_Nrf_4Mbit_0BT6 (0x9UL)     /*!< 4 Mbps Nordic proprietary radio mode (BT=0.6/h=0.5)                  */
  #define RADIO_MODE_MODE_Nrf_4Mbit_0BT4 (0xAUL)     /*!< 4 Mbps Nordic proprietary radio mode (BT=0.4/h=0.5)                  */
  #define RADIO_MODE_MODE_Ieee802154_250Kbit (0xFUL) /*!< IEEE 802.15.4-2006 250 kbps                                          */


/* RADIO_STATE: Current radio state */
  #define RADIO_STATE_ResetValue (0x00000000UL)      /*!< Reset value of STATE register.                                       */

/* STATE @Bits 0..3 : Current radio state */
  #define RADIO_STATE_STATE_Pos (0UL)                /*!< Position of STATE field.                                             */
  #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field.                                 */
  #define RADIO_STATE_STATE_Min (0x0UL)              /*!< Min enumerator value of STATE field.                                 */
  #define RADIO_STATE_STATE_Max (0xCUL)              /*!< Max enumerator value of STATE field.                                 */
  #define RADIO_STATE_STATE_Disabled (0x0UL)         /*!< RADIO is in the DISABLED state                                       */
  #define RADIO_STATE_STATE_RxRu (0x1UL)             /*!< RADIO is in the RXRU state                                           */
  #define RADIO_STATE_STATE_RxIdle (0x2UL)           /*!< RADIO is in the RXIDLE state                                         */
  #define RADIO_STATE_STATE_Rx (0x3UL)               /*!< RADIO is in the RX state                                             */
  #define RADIO_STATE_STATE_RxDisable (0x4UL)        /*!< RADIO is in the RXDISABLE state                                      */
  #define RADIO_STATE_STATE_TxRu (0x9UL)             /*!< RADIO is in the TXRU state                                           */
  #define RADIO_STATE_STATE_TxIdle (0xAUL)           /*!< RADIO is in the TXIDLE state                                         */
  #define RADIO_STATE_STATE_Tx (0xBUL)               /*!< RADIO is in the TX state                                             */
  #define RADIO_STATE_STATE_TxDisable (0xCUL)        /*!< RADIO is in the TXDISABLE state                                      */


/* RADIO_EDCTRL: IEEE 802.15.4 energy detect control */
  #define RADIO_EDCTRL_ResetValue (0x20000000UL)     /*!< Reset value of EDCTRL register.                                      */

/* EDCNT @Bits 0..20 : IEEE 802.15.4 energy detect loop count */
  #define RADIO_EDCTRL_EDCNT_Pos (0UL)               /*!< Position of EDCNT field.                                             */
  #define RADIO_EDCTRL_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCTRL_EDCNT_Pos) /*!< Bit mask of EDCNT field.                          */

/* EDPERIOD @Bits 24..29 : IEEE 802.15.4 energy detect period, 4us resolution, no averaging except the IEEE 802.15.4 ED range
                           128us (32) */

  #define RADIO_EDCTRL_EDPERIOD_Pos (24UL)           /*!< Position of EDPERIOD field.                                          */
  #define RADIO_EDCTRL_EDPERIOD_Msk (0x3FUL << RADIO_EDCTRL_EDPERIOD_Pos) /*!< Bit mask of EDPERIOD field.                     */
  #define RADIO_EDCTRL_EDPERIOD_Min (0x20UL)         /*!< Min enumerator value of EDPERIOD field.                              */
  #define RADIO_EDCTRL_EDPERIOD_Max (0x20UL)         /*!< Max enumerator value of EDPERIOD field.                              */
  #define RADIO_EDCTRL_EDPERIOD_Default (0x20UL)     /*!< (unspecified)                                                        */


/* RADIO_EDSAMPLE: IEEE 802.15.4 energy detect level */
  #define RADIO_EDSAMPLE_ResetValue (0x00000000UL)   /*!< Reset value of EDSAMPLE register.                                    */

/* EDLVL @Bits 0..7 : IEEE 802.15.4 energy detect level */
  #define RADIO_EDSAMPLE_EDLVL_Pos (0UL)             /*!< Position of EDLVL field.                                             */
  #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field.                          */
  #define RADIO_EDSAMPLE_EDLVL_Min (0x00UL)          /*!< Min value of EDLVL field.                                            */
  #define RADIO_EDSAMPLE_EDLVL_Max (0x7FUL)          /*!< Max size of EDLVL field.                                             */


/* RADIO_CCACTRL: IEEE 802.15.4 clear channel assessment control */
  #define RADIO_CCACTRL_ResetValue (0x052D0000UL)    /*!< Reset value of CCACTRL register.                                     */

/* CCAMODE @Bits 0..2 : CCA mode of operation */
  #define RADIO_CCACTRL_CCAMODE_Pos (0UL)            /*!< Position of CCAMODE field.                                           */
  #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field.                       */
  #define RADIO_CCACTRL_CCAMODE_Min (0x0UL)          /*!< Min enumerator value of CCAMODE field.                               */
  #define RADIO_CCACTRL_CCAMODE_Max (0x4UL)          /*!< Max enumerator value of CCAMODE field.                               */
  #define RADIO_CCACTRL_CCAMODE_EdMode (0x0UL)       /*!< Energy above threshold                                               */
  #define RADIO_CCACTRL_CCAMODE_CarrierMode (0x1UL)  /*!< Carrier seen                                                         */
  #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (0x2UL) /*!< Energy above threshold AND carrier seen                          */
  #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (0x3UL) /*!< Energy above threshold OR carrier seen                            */
  #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (0x4UL)  /*!< Energy above threshold test mode that will abort when first ED
                                                          measurement over threshold is seen. No averaging.*/

/* CCAEDTHRES @Bits 8..15 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
  #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL)         /*!< Position of CCAEDTHRES field.                                        */
  #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field.             */

/* CCACORRTHRES @Bits 16..23 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and
                               CarrierOrEdMode. */

  #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL)      /*!< Position of CCACORRTHRES field.                                      */
  #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field.       */

/* CCACORRCNT @Bits 24..31 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect
                             is enabled. */

  #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL)        /*!< Position of CCACORRCNT field.                                        */
  #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field.             */


/* RADIO_DATAWHITE: Data whitening configuration */
  #define RADIO_DATAWHITE_ResetValue (0x00890040UL)  /*!< Reset value of DATAWHITE register.                                   */

/* IV @Bits 0..8 : Whitening initial value */
  #define RADIO_DATAWHITE_IV_Pos (0UL)               /*!< Position of IV field.                                                */
  #define RADIO_DATAWHITE_IV_Msk (0x1FFUL << RADIO_DATAWHITE_IV_Pos) /*!< Bit mask of IV field.                                */

/* POLY @Bits 16..25 : Whitening polynomial */
  #define RADIO_DATAWHITE_POLY_Pos (16UL)            /*!< Position of POLY field.                                              */
  #define RADIO_DATAWHITE_POLY_Msk (0x3FFUL << RADIO_DATAWHITE_POLY_Pos) /*!< Bit mask of POLY field.                          */


/* RADIO_TIMING: Timing */
  #define RADIO_TIMING_ResetValue (0x00000001UL)     /*!< Reset value of TIMING register.                                      */

/* RU @Bit 0 : Ramp-up time */
  #define RADIO_TIMING_RU_Pos (0UL)                  /*!< Position of RU field.                                                */
  #define RADIO_TIMING_RU_Msk (0x1UL << RADIO_TIMING_RU_Pos) /*!< Bit mask of RU field.                                        */
  #define RADIO_TIMING_RU_Min (0x0UL)                /*!< Min enumerator value of RU field.                                    */
  #define RADIO_TIMING_RU_Max (0x1UL)                /*!< Max enumerator value of RU field.                                    */
  #define RADIO_TIMING_RU_Legacy (0x0UL)             /*!< Legacy ramp-up time                                                  */
  #define RADIO_TIMING_RU_Fast (0x1UL)               /*!< Fast ramp-up (default)                                               */


/* RADIO_FREQUENCY: Frequency */
  #define RADIO_FREQUENCY_ResetValue (0x00000002UL)  /*!< Reset value of FREQUENCY register.                                   */

/* FREQUENCY @Bits 0..6 : Radio channel frequency. Frequency = 2400 + FREQUENCY (MHz). */
  #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL)        /*!< Position of FREQUENCY field.                                         */
  #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field.            */

/* MAP @Bit 8 : Channel map selection. 0: Channel map between 2400 MHZ to 2500 MHz, Frequency = 2400 + FREQUENCY (MHz). 1:
                Channel map between 2360 MHZ to 2460 MHz, Frequency = 2360 + FREQUENCY (MHz). */

  #define RADIO_FREQUENCY_MAP_Pos (8UL)              /*!< Position of MAP field.                                               */
  #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field.                               */


/* RADIO_TXPOWER: Output power */
  #define RADIO_TXPOWER_ResetValue (0x00000013UL)    /*!< Reset value of TXPOWER register.                                     */

/* TXPOWER @Bits 0..10 : RADIO output power */
  #define RADIO_TXPOWER_TXPOWER_Pos (0UL)            /*!< Position of TXPOWER field.                                           */
  #define RADIO_TXPOWER_TXPOWER_Msk (0x7FFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field.                     */
  #define RADIO_TXPOWER_TXPOWER_Min (0x1UL)          /*!< Min enumerator value of TXPOWER field.                               */
  #define RADIO_TXPOWER_TXPOWER_Max (0x130UL)        /*!< Max enumerator value of TXPOWER field.                               */
  #define RADIO_TXPOWER_TXPOWER_MaxdBm (0x03FUL)     /*!< +8 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x03FUL)    /*!< +8 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x039UL)    /*!< +7 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x033UL)    /*!< +6 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x02DUL)    /*!< +5 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x028UL)    /*!< +4 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x023UL)    /*!< +3 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x01FUL)    /*!< +2 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Pos1dBm (0x01BUL)    /*!< +1 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_0dBm (0x018UL)       /*!< 0 dBm                                                                */
  #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0x015UL)    /*!< -1 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0x013UL)    /*!< -2 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg3dBm (0x011UL)    /*!< -3 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0x00FUL)    /*!< -4 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg5dBm (0x00DUL)    /*!< -5 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg6dBm (0x00BUL)    /*!< -6 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg7dBm (0x00AUL)    /*!< -7 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0x009UL)    /*!< -8 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg9dBm (0x008UL)    /*!< -9 dBm                                                               */
  #define RADIO_TXPOWER_TXPOWER_Neg10dBm (0x007UL)   /*!< -10 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0x006UL)   /*!< -12 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg14dBm (0x005UL)   /*!< -14 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0x004UL)   /*!< -16 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg18dBm (0x003UL)   /*!< -18 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0x002UL)   /*!< -20 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg22dBm (0x002UL)   /*!< -22 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg28dBm (0x001UL)   /*!< -28 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0x130UL)   /*!< -40 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_Neg46dBm (0x110UL)   /*!< -46 dBm                                                              */
  #define RADIO_TXPOWER_TXPOWER_MindBm (0x110UL)     /*!< -46 dBm                                                              */


/* RADIO_TIFS: Interframe spacing in us */
  #define RADIO_TIFS_ResetValue (0x00000000UL)       /*!< Reset value of TIFS register.                                        */

/* TIFS @Bits 0..9 : Interframe spacing in us. Interframe space is the time interval between two consecutive packets. It is
                     defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of
                     the first bit of the subsequent packet. */

  #define RADIO_TIFS_TIFS_Pos (0UL)                  /*!< Position of TIFS field.                                              */
  #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field.                                    */


/* RADIO_RSSISAMPLE: RSSI sample */
  #define RADIO_RSSISAMPLE_ResetValue (0x0000007FUL) /*!< Reset value of RSSISAMPLE register.                                  */

/* RSSISAMPLE @Bits 0..6 : RSSI sample result. The value of this register is read as a positive value while the actual received
                           signal strength is a negative value. Actual received signal strength is therefore as follows:
                           received signal strength = -A dBm. */

  #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL)      /*!< Position of RSSISAMPLE field.                                        */
  #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field.       */


/* RADIO_FECONFIG: Config register */
  #define RADIO_FECONFIG_ResetValue (0x10800005UL)   /*!< Reset value of FECONFIG register.                                    */

/* SCALERMODE @Bit 20 : Mode for narrow scaling output. */
  #define RADIO_FECONFIG_SCALERMODE_Pos (20UL)       /*!< Position of SCALERMODE field.                                        */
  #define RADIO_FECONFIG_SCALERMODE_Msk (0x1UL << RADIO_FECONFIG_SCALERMODE_Pos) /*!< Bit mask of SCALERMODE field.            */
  #define RADIO_FECONFIG_SCALERMODE_Min (0x0UL)      /*!< Min enumerator value of SCALERMODE field.                            */
  #define RADIO_FECONFIG_SCALERMODE_Max (0x1UL)      /*!< Max enumerator value of SCALERMODE field.                            */
  #define RADIO_FECONFIG_SCALERMODE_Disabled (0x0UL) /*!< Classic log based scaling mode.                                      */
  #define RADIO_FECONFIG_SCALERMODE_Enabled (0x1UL)  /*!< LUT based scaling mode.                                              */


/* RADIO_DFEMODE: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
  #define RADIO_DFEMODE_ResetValue (0x00000000UL)    /*!< Reset value of DFEMODE register.                                     */

/* DFEOPMODE @Bits 0..1 : Direction finding operation mode */
  #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL)          /*!< Position of DFEOPMODE field.                                         */
  #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field.                 */
  #define RADIO_DFEMODE_DFEOPMODE_Min (0x0UL)        /*!< Min enumerator value of DFEOPMODE field.                             */
  #define RADIO_DFEMODE_DFEOPMODE_Max (0x3UL)        /*!< Max enumerator value of DFEOPMODE field.                             */
  #define RADIO_DFEMODE_DFEOPMODE_Disabled (0x0UL)   /*!< Direction finding mode disabled                                      */
  #define RADIO_DFEMODE_DFEOPMODE_AoD (0x2UL)        /*!< Direction finding mode set to AoD                                    */
  #define RADIO_DFEMODE_DFEOPMODE_AoA (0x3UL)        /*!< Direction finding mode set to AoA                                    */


/* RADIO_DFESTATUS: DFE status information */
  #define RADIO_DFESTATUS_ResetValue (0x00000000UL)  /*!< Reset value of DFESTATUS register.                                   */

/* SWITCHINGSTATE @Bits 0..2 : Internal state of switching state machine */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL)   /*!< Position of SWITCHINGSTATE field.                                    */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE
                                                                            field.*/
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Min (0x0UL) /*!< Min enumerator value of SWITCHINGSTATE field.                        */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Max (0x5UL) /*!< Max enumerator value of SWITCHINGSTATE field.                        */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0x0UL) /*!< Switching state Idle                                                */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (0x1UL) /*!< Switching state Offset                                            */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (0x2UL) /*!< Switching state Guard                                              */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (0x3UL) /*!< Switching state Ref                                                  */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (0x4UL) /*!< Switching state Switching                                      */
  #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (0x5UL) /*!< Switching state Ending                                            */

/* SAMPLINGSTATE @Bit 4 : Internal state of sampling state machine */
  #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL)    /*!< Position of SAMPLINGSTATE field.                                     */
  #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
  #define RADIO_DFESTATUS_SAMPLINGSTATE_Min (0x0UL)  /*!< Min enumerator value of SAMPLINGSTATE field.                         */
  #define RADIO_DFESTATUS_SAMPLINGSTATE_Max (0x1UL)  /*!< Max enumerator value of SAMPLINGSTATE field.                         */
  #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0x0UL) /*!< Sampling state Idle                                                  */
  #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (0x1UL) /*!< Sampling state Sampling                                          */


/* RADIO_DFECTRL1: Various configuration for Direction finding */
  #define RADIO_DFECTRL1_ResetValue (0x00023282UL)   /*!< Reset value of DFECTRL1 register.                                    */

/* NUMBEROF8US @Bits 0..5 : Length of the AoA/AoD procedure in number of 8 us units */
  #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL)       /*!< Position of NUMBEROF8US field.                                       */
  #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field.        */

/* DFEINEXTENSION @Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
  #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL)    /*!< Position of DFEINEXTENSION field.                                    */
  #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field.*/
  #define RADIO_DFECTRL1_DFEINEXTENSION_Min (0x0UL)  /*!< Min enumerator value of DFEINEXTENSION field.                        */
  #define RADIO_DFECTRL1_DFEINEXTENSION_Max (0x1UL)  /*!< Max enumerator value of DFEINEXTENSION field.                        */
  #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (0x1UL)  /*!< AoA/AoD procedure triggered at end of CRC                            */
  #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0x0UL) /*!< Antenna switching/sampling is done in the packet payload          */

/* TSWITCHSPACING @Bits 8..10 : Interval between every time the antenna is changed in the SWITCHING state */
  #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL)    /*!< Position of TSWITCHSPACING field.                                    */
  #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field.*/
  #define RADIO_DFECTRL1_TSWITCHSPACING_Min (0x1UL)  /*!< Min enumerator value of TSWITCHSPACING field.                        */
  #define RADIO_DFECTRL1_TSWITCHSPACING_Max (0x3UL)  /*!< Max enumerator value of TSWITCHSPACING field.                        */
  #define RADIO_DFECTRL1_TSWITCHSPACING_4us (0x1UL)  /*!< 4us                                                                  */
  #define RADIO_DFECTRL1_TSWITCHSPACING_2us (0x2UL)  /*!< 2us                                                                  */
  #define RADIO_DFECTRL1_TSWITCHSPACING_1us (0x3UL)  /*!< 1us                                                                  */

/* TSAMPLESPACINGREF @Bits 12..14 : Interval between samples in the REFERENCE period */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field.                                */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of
                                                                            TSAMPLESPACINGREF field.*/
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Min (0x1UL) /*!< Min enumerator value of TSAMPLESPACINGREF field.                   */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Max (0x6UL) /*!< Max enumerator value of TSAMPLESPACINGREF field.                   */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (0x1UL) /*!< 4us                                                                */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (0x2UL) /*!< 2us                                                                */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (0x3UL) /*!< 1us                                                                */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (0x4UL) /*!< 0.5us                                                            */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (0x5UL) /*!< 0.25us                                                           */
  #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (0x6UL) /*!< 0.125us                                                          */

/* SAMPLETYPE @Bit 15 : Whether to sample I/Q or magnitude/phase */
  #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL)       /*!< Position of SAMPLETYPE field.                                        */
  #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field.            */
  #define RADIO_DFECTRL1_SAMPLETYPE_Min (0x0UL)      /*!< Min enumerator value of SAMPLETYPE field.                            */
  #define RADIO_DFECTRL1_SAMPLETYPE_Max (0x1UL)      /*!< Max enumerator value of SAMPLETYPE field.                            */
  #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0x0UL)       /*!< Complex samples in I and Q                                           */
  #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (0x1UL) /*!< Complex samples as magnitude and phase                               */

/* TSAMPLESPACING @Bits 16..18 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
  #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL)   /*!< Position of TSAMPLESPACING field.                                    */
  #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field.*/
  #define RADIO_DFECTRL1_TSAMPLESPACING_Min (0x1UL)  /*!< Min enumerator value of TSAMPLESPACING field.                        */
  #define RADIO_DFECTRL1_TSAMPLESPACING_Max (0x6UL)  /*!< Max enumerator value of TSAMPLESPACING field.                        */
  #define RADIO_DFECTRL1_TSAMPLESPACING_4us (0x1UL)  /*!< 4us                                                                  */
  #define RADIO_DFECTRL1_TSAMPLESPACING_2us (0x2UL)  /*!< 2us                                                                  */
  #define RADIO_DFECTRL1_TSAMPLESPACING_1us (0x3UL)  /*!< 1us                                                                  */
  #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (0x4UL) /*!< 0.5us                                                               */
  #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (0x5UL) /*!< 0.25us                                                              */
  #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (0x6UL) /*!< 0.125us                                                             */

/* REPEATPATTERN @Bits 20..23 : Repeat every antenna pattern N times. */
  #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL)    /*!< Position of REPEATPATTERN field.                                     */
  #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field.   */
  #define RADIO_DFECTRL1_REPEATPATTERN_Min (0x0UL)   /*!< Min enumerator value of REPEATPATTERN field.                         */
  #define RADIO_DFECTRL1_REPEATPATTERN_Max (0x0UL)   /*!< Max enumerator value of REPEATPATTERN field.                         */
  #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0x0UL) /*!< Do not repeat (1 time in total)                                   */

/* AGCBACKOFFGAIN @Bits 24..27 : Gain will be lowered by the specified number of gain steps at the start of CTE */
  #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL)   /*!< Position of AGCBACKOFFGAIN field.                                    */
  #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field.*/


/* RADIO_DFECTRL2: Start offset for Direction finding */
  #define RADIO_DFECTRL2_ResetValue (0x00000000UL)   /*!< Reset value of DFECTRL2 register.                                    */

/* TSWITCHOFFSET @Bits 0..12 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */
  #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL)     /*!< Position of TSWITCHOFFSET field.                                     */
  #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field.*/

/* TSAMPLEOFFSET @Bits 16..27 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning
                                of the REFERENCE state - 12 us after switching start */

  #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL)    /*!< Position of TSAMPLEOFFSET field.                                     */
  #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */


/* RADIO_SWITCHPATTERN: GPIO patterns to be used for each antenna */
  #define RADIO_SWITCHPATTERN_ResetValue (0x00000000UL) /*!< Reset value of SWITCHPATTERN register.                            */

/* SWITCHPATTERN @Bits 0..7 : Fill array of GPIO patterns for antenna control */
  #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field.                                    */
  #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN
                                                                            field.*/


/* RADIO_CLEARPATTERN: Clear the GPIO pattern array for antenna control */
  #define RADIO_CLEARPATTERN_ResetValue (0x00000000UL) /*!< Reset value of CLEARPATTERN register.                              */

/* CLEARPATTERN @Bit 0 : Clear the GPIO pattern array for antenna control Behaves as a task register, but does not have PPI nor
                         IRQ */

  #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL)  /*!< Position of CLEARPATTERN field.                                      */
  #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN
                                                                            field.*/


/* RADIO_CRCSTATUS: CRC status */
  #define RADIO_CRCSTATUS_ResetValue (0x00000000UL)  /*!< Reset value of CRCSTATUS register.                                   */

/* CRCSTATUS @Bit 0 : CRC status of packet received */
  #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL)        /*!< Position of CRCSTATUS field.                                         */
  #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field.             */
  #define RADIO_CRCSTATUS_CRCSTATUS_Min (0x0UL)      /*!< Min enumerator value of CRCSTATUS field.                             */
  #define RADIO_CRCSTATUS_CRCSTATUS_Max (0x1UL)      /*!< Max enumerator value of CRCSTATUS field.                             */
  #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0x0UL) /*!< Packet received with CRC error                                       */
  #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (0x1UL)    /*!< Packet received with CRC ok                                          */


/* RADIO_RXMATCH: Received address */
  #define RADIO_RXMATCH_ResetValue (0x00000000UL)    /*!< Reset value of RXMATCH register.                                     */

/* RXMATCH @Bits 0..2 : Received address */
  #define RADIO_RXMATCH_RXMATCH_Pos (0UL)            /*!< Position of RXMATCH field.                                           */
  #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field.                       */


/* RADIO_RXCRC: CRC field of previously received packet */
  #define RADIO_RXCRC_ResetValue (0x00000000UL)      /*!< Reset value of RXCRC register.                                       */

/* RXCRC @Bits 0..23 : CRC field of previously received packet */
  #define RADIO_RXCRC_RXCRC_Pos (0UL)                /*!< Position of RXCRC field.                                             */
  #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field.                            */


/* RADIO_DAI: Device address match index */
  #define RADIO_DAI_ResetValue (0x00000000UL)        /*!< Reset value of DAI register.                                         */

/* DAI @Bits 0..2 : Device address match index */
  #define RADIO_DAI_DAI_Pos (0UL)                    /*!< Position of DAI field.                                               */
  #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field.                                           */


/* RADIO_PDUSTAT: Payload status */
  #define RADIO_PDUSTAT_ResetValue (0x00000000UL)    /*!< Reset value of PDUSTAT register.                                     */

/* PDUSTAT @Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
  #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL)            /*!< Position of PDUSTAT field.                                           */
  #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field.                       */
  #define RADIO_PDUSTAT_PDUSTAT_Min (0x0UL)          /*!< Min enumerator value of PDUSTAT field.                               */
  #define RADIO_PDUSTAT_PDUSTAT_Max (0x1UL)          /*!< Max enumerator value of PDUSTAT field.                               */
  #define RADIO_PDUSTAT_PDUSTAT_LessThan (0x0UL)     /*!< Payload less than PCNF1.MAXLEN                                       */
  #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (0x1UL)  /*!< Payload greater than PCNF1.MAXLEN                                    */

/* CISTAT @Bits 1..2 : Status on what rate packet is received with in Long Range */
  #define RADIO_PDUSTAT_CISTAT_Pos (1UL)             /*!< Position of CISTAT field.                                            */
  #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field.                          */
  #define RADIO_PDUSTAT_CISTAT_Min (0x0UL)           /*!< Min enumerator value of CISTAT field.                                */
  #define RADIO_PDUSTAT_CISTAT_Max (0x1UL)           /*!< Max enumerator value of CISTAT field.                                */
  #define RADIO_PDUSTAT_CISTAT_LR125kbit (0x0UL)     /*!< Frame is received at 125 kbps                                        */
  #define RADIO_PDUSTAT_CISTAT_LR500kbit (0x1UL)     /*!< Frame is received at 500 kbps                                        */


/* RADIO_PCNF0: Packet configuration register 0 */
  #define RADIO_PCNF0_ResetValue (0x00000000UL)      /*!< Reset value of PCNF0 register.                                       */

/* LFLEN @Bits 0..3 : Length on air of LENGTH field in number of bits. */
  #define RADIO_PCNF0_LFLEN_Pos (0UL)                /*!< Position of LFLEN field.                                             */
  #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field.                                 */

/* S0LEN @Bit 8 : Length on air of S0 field in number of bytes. */
  #define RADIO_PCNF0_S0LEN_Pos (8UL)                /*!< Position of S0LEN field.                                             */
  #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field.                                 */

/* S1LEN @Bits 16..19 : Length on air of S1 field in number of bits. */
  #define RADIO_PCNF0_S1LEN_Pos (16UL)               /*!< Position of S1LEN field.                                             */
  #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field.                                 */

/* S1INCL @Bits 20..21 : Include or exclude S1 field in RAM */
  #define RADIO_PCNF0_S1INCL_Pos (20UL)              /*!< Position of S1INCL field.                                            */
  #define RADIO_PCNF0_S1INCL_Msk (0x3UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field.                              */
  #define RADIO_PCNF0_S1INCL_Min (0x0UL)             /*!< Min enumerator value of S1INCL field.                                */
  #define RADIO_PCNF0_S1INCL_Max (0x1UL)             /*!< Max enumerator value of S1INCL field.                                */
  #define RADIO_PCNF0_S1INCL_Automatic (0x0UL)       /*!< Include S1 field in RAM only if S1LEN > 0                            */
  #define RADIO_PCNF0_S1INCL_Include (0x1UL)         /*!< Always include S1 field in RAM independent of S1LEN                  */

/* CILEN @Bits 22..23 : Length of code indicator - long range */
  #define RADIO_PCNF0_CILEN_Pos (22UL)               /*!< Position of CILEN field.                                             */
  #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field.                                 */

/* PLEN @Bits 24..25 : Length of preamble on air. Decision point: TASKS_START task */
  #define RADIO_PCNF0_PLEN_Pos (24UL)                /*!< Position of PLEN field.                                              */
  #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field.                                    */
  #define RADIO_PCNF0_PLEN_Min (0x0UL)               /*!< Min enumerator value of PLEN field.                                  */
  #define RADIO_PCNF0_PLEN_Max (0x3UL)               /*!< Max enumerator value of PLEN field.                                  */
  #define RADIO_PCNF0_PLEN_8bit (0x0UL)              /*!< 8-bit preamble                                                       */
  #define RADIO_PCNF0_PLEN_16bit (0x1UL)             /*!< 16-bit preamble                                                      */
  #define RADIO_PCNF0_PLEN_32bitZero (0x2UL)         /*!< 32-bit zero preamble - used for IEEE 802.15.4                        */
  #define RADIO_PCNF0_PLEN_LongRange (0x3UL)         /*!< Preamble - used for BLE long range                                   */

/* CRCINC @Bit 26 : Indicates if LENGTH field contains CRC or not */
  #define RADIO_PCNF0_CRCINC_Pos (26UL)              /*!< Position of CRCINC field.                                            */
  #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field.                              */
  #define RADIO_PCNF0_CRCINC_Min (0x0UL)             /*!< Min enumerator value of CRCINC field.                                */
  #define RADIO_PCNF0_CRCINC_Max (0x1UL)             /*!< Max enumerator value of CRCINC field.                                */
  #define RADIO_PCNF0_CRCINC_Exclude (0x0UL)         /*!< LENGTH does not contain CRC                                          */
  #define RADIO_PCNF0_CRCINC_Include (0x1UL)         /*!< LENGTH includes CRC                                                  */

/* TERMLEN @Bits 29..30 : Length of TERM field in Long Range operation */
  #define RADIO_PCNF0_TERMLEN_Pos (29UL)             /*!< Position of TERMLEN field.                                           */
  #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field.                           */


/* RADIO_PCNF1: Packet configuration register 1 */
  #define RADIO_PCNF1_ResetValue (0x00000000UL)      /*!< Reset value of PCNF1 register.                                       */

/* MAXLEN @Bits 0..7 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate
                       the payload to MAXLEN. */

  #define RADIO_PCNF1_MAXLEN_Pos (0UL)               /*!< Position of MAXLEN field.                                            */
  #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field.                             */
  #define RADIO_PCNF1_MAXLEN_Min (0x00UL)            /*!< Min value of MAXLEN field.                                           */
  #define RADIO_PCNF1_MAXLEN_Max (0xFFUL)            /*!< Max size of MAXLEN field.                                            */

/* STATLEN @Bits 8..15 : Static length in number of bytes */
  #define RADIO_PCNF1_STATLEN_Pos (8UL)              /*!< Position of STATLEN field.                                           */
  #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field.                          */
  #define RADIO_PCNF1_STATLEN_Min (0x00UL)           /*!< Min value of STATLEN field.                                          */
  #define RADIO_PCNF1_STATLEN_Max (0xFFUL)           /*!< Max size of STATLEN field.                                           */

/* BALEN @Bits 16..18 : Base address length in number of bytes */
  #define RADIO_PCNF1_BALEN_Pos (16UL)               /*!< Position of BALEN field.                                             */
  #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field.                                 */
  #define RADIO_PCNF1_BALEN_Min (0x1UL)              /*!< Min value of BALEN field.                                            */
  #define RADIO_PCNF1_BALEN_Max (0x1UL)              /*!< Max size of BALEN field.                                             */

/* ENDIAN @Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
  #define RADIO_PCNF1_ENDIAN_Pos (24UL)              /*!< Position of ENDIAN field.                                            */
  #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field.                              */
  #define RADIO_PCNF1_ENDIAN_Min (0x0UL)             /*!< Min enumerator value of ENDIAN field.                                */
  #define RADIO_PCNF1_ENDIAN_Max (0x1UL)             /*!< Max enumerator value of ENDIAN field.                                */
  #define RADIO_PCNF1_ENDIAN_Little (0x0UL)          /*!< Least significant bit on air first                                   */
  #define RADIO_PCNF1_ENDIAN_Big (0x1UL)             /*!< Most significant bit on air first                                    */

/* WHITEEN @Bit 25 : Enable or disable packet whitening */
  #define RADIO_PCNF1_WHITEEN_Pos (25UL)             /*!< Position of WHITEEN field.                                           */
  #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field.                           */
  #define RADIO_PCNF1_WHITEEN_Min (0x0UL)            /*!< Min enumerator value of WHITEEN field.                               */
  #define RADIO_PCNF1_WHITEEN_Max (0x1UL)            /*!< Max enumerator value of WHITEEN field.                               */
  #define RADIO_PCNF1_WHITEEN_Disabled (0x0UL)       /*!< Disable                                                              */
  #define RADIO_PCNF1_WHITEEN_Enabled (0x1UL)        /*!< Enable                                                               */

/* WHITEOFFSET @Bit 26 : If whitening is enabled S0 can be configured to be excluded from whitening */
  #define RADIO_PCNF1_WHITEOFFSET_Pos (26UL)         /*!< Position of WHITEOFFSET field.                                       */
  #define RADIO_PCNF1_WHITEOFFSET_Msk (0x1UL << RADIO_PCNF1_WHITEOFFSET_Pos) /*!< Bit mask of WHITEOFFSET field.               */
  #define RADIO_PCNF1_WHITEOFFSET_Min (0x0UL)        /*!< Min enumerator value of WHITEOFFSET field.                           */
  #define RADIO_PCNF1_WHITEOFFSET_Max (0x1UL)        /*!< Max enumerator value of WHITEOFFSET field.                           */
  #define RADIO_PCNF1_WHITEOFFSET_Include (0x0UL)    /*!< S0 included in whitening                                             */
  #define RADIO_PCNF1_WHITEOFFSET_Exclude (0x1UL)    /*!< S0 excluded from whitening                                           */


/* RADIO_BASE0: Base address 0 */
  #define RADIO_BASE0_ResetValue (0x00000000UL)      /*!< Reset value of BASE0 register.                                       */

/* BASE0 @Bits 0..31 : Base address 0 */
  #define RADIO_BASE0_BASE0_Pos (0UL)                /*!< Position of BASE0 field.                                             */
  #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field.                          */


/* RADIO_BASE1: Base address 1 */
  #define RADIO_BASE1_ResetValue (0x00000000UL)      /*!< Reset value of BASE1 register.                                       */

/* BASE1 @Bits 0..31 : Base address 1 */
  #define RADIO_BASE1_BASE1_Pos (0UL)                /*!< Position of BASE1 field.                                             */
  #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field.                          */


/* RADIO_PREFIX0: Prefixes bytes for logical addresses 0-3 */
  #define RADIO_PREFIX0_ResetValue (0x00000000UL)    /*!< Reset value of PREFIX0 register.                                     */

/* AP0 @Bits 0..7 : Address prefix 0 */
  #define RADIO_PREFIX0_AP0_Pos (0UL)                /*!< Position of AP0 field.                                               */
  #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field.                                  */

/* AP1 @Bits 8..15 : Address prefix 1 */
  #define RADIO_PREFIX0_AP1_Pos (8UL)                /*!< Position of AP1 field.                                               */
  #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field.                                  */

/* AP2 @Bits 16..23 : Address prefix 2 */
  #define RADIO_PREFIX0_AP2_Pos (16UL)               /*!< Position of AP2 field.                                               */
  #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field.                                  */

/* AP3 @Bits 24..31 : Address prefix 3 */
  #define RADIO_PREFIX0_AP3_Pos (24UL)               /*!< Position of AP3 field.                                               */
  #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field.                                  */


/* RADIO_PREFIX1: Prefixes bytes for logical addresses 4-7 */
  #define RADIO_PREFIX1_ResetValue (0x00000000UL)    /*!< Reset value of PREFIX1 register.                                     */

/* AP4 @Bits 0..7 : Address prefix 4 */
  #define RADIO_PREFIX1_AP4_Pos (0UL)                /*!< Position of AP4 field.                                               */
  #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field.                                  */

/* AP5 @Bits 8..15 : Address prefix 5 */
  #define RADIO_PREFIX1_AP5_Pos (8UL)                /*!< Position of AP5 field.                                               */
  #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field.                                  */

/* AP6 @Bits 16..23 : Address prefix 6 */
  #define RADIO_PREFIX1_AP6_Pos (16UL)               /*!< Position of AP6 field.                                               */
  #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field.                                  */

/* AP7 @Bits 24..31 : Address prefix 7 */
  #define RADIO_PREFIX1_AP7_Pos (24UL)               /*!< Position of AP7 field.                                               */
  #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field.                                  */


/* RADIO_TXADDRESS: Transmit address select */
  #define RADIO_TXADDRESS_ResetValue (0x00000000UL)  /*!< Reset value of TXADDRESS register.                                   */

/* TXADDRESS @Bits 0..2 : Transmit address select */
  #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL)        /*!< Position of TXADDRESS field.                                         */
  #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field.             */


/* RADIO_RXADDRESSES: Receive address select */
  #define RADIO_RXADDRESSES_ResetValue (0x00000000UL) /*!< Reset value of RXADDRESSES register.                                */

/* ADDR0 @Bit 0 : Enable or disable reception on logical address 0 */
  #define RADIO_RXADDRESSES_ADDR0_Pos (0UL)          /*!< Position of ADDR0 field.                                             */
  #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field.                     */
  #define RADIO_RXADDRESSES_ADDR0_Min (0x0UL)        /*!< Min enumerator value of ADDR0 field.                                 */
  #define RADIO_RXADDRESSES_ADDR0_Max (0x1UL)        /*!< Max enumerator value of ADDR0 field.                                 */
  #define RADIO_RXADDRESSES_ADDR0_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR0_Enabled (0x1UL)    /*!< Enable                                                               */

/* ADDR1 @Bit 1 : Enable or disable reception on logical address 1 */
  #define RADIO_RXADDRESSES_ADDR1_Pos (1UL)          /*!< Position of ADDR1 field.                                             */
  #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field.                     */
  #define RADIO_RXADDRESSES_ADDR1_Min (0x0UL)        /*!< Min enumerator value of ADDR1 field.                                 */
  #define RADIO_RXADDRESSES_ADDR1_Max (0x1UL)        /*!< Max enumerator value of ADDR1 field.                                 */
  #define RADIO_RXADDRESSES_ADDR1_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR1_Enabled (0x1UL)    /*!< Enable                                                               */

/* ADDR2 @Bit 2 : Enable or disable reception on logical address 2 */
  #define RADIO_RXADDRESSES_ADDR2_Pos (2UL)          /*!< Position of ADDR2 field.                                             */
  #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field.                     */
  #define RADIO_RXADDRESSES_ADDR2_Min (0x0UL)        /*!< Min enumerator value of ADDR2 field.                                 */
  #define RADIO_RXADDRESSES_ADDR2_Max (0x1UL)        /*!< Max enumerator value of ADDR2 field.                                 */
  #define RADIO_RXADDRESSES_ADDR2_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR2_Enabled (0x1UL)    /*!< Enable                                                               */

/* ADDR3 @Bit 3 : Enable or disable reception on logical address 3 */
  #define RADIO_RXADDRESSES_ADDR3_Pos (3UL)          /*!< Position of ADDR3 field.                                             */
  #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field.                     */
  #define RADIO_RXADDRESSES_ADDR3_Min (0x0UL)        /*!< Min enumerator value of ADDR3 field.                                 */
  #define RADIO_RXADDRESSES_ADDR3_Max (0x1UL)        /*!< Max enumerator value of ADDR3 field.                                 */
  #define RADIO_RXADDRESSES_ADDR3_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR3_Enabled (0x1UL)    /*!< Enable                                                               */

/* ADDR4 @Bit 4 : Enable or disable reception on logical address 4 */
  #define RADIO_RXADDRESSES_ADDR4_Pos (4UL)          /*!< Position of ADDR4 field.                                             */
  #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field.                     */
  #define RADIO_RXADDRESSES_ADDR4_Min (0x0UL)        /*!< Min enumerator value of ADDR4 field.                                 */
  #define RADIO_RXADDRESSES_ADDR4_Max (0x1UL)        /*!< Max enumerator value of ADDR4 field.                                 */
  #define RADIO_RXADDRESSES_ADDR4_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR4_Enabled (0x1UL)    /*!< Enable                                                               */

/* ADDR5 @Bit 5 : Enable or disable reception on logical address 5 */
  #define RADIO_RXADDRESSES_ADDR5_Pos (5UL)          /*!< Position of ADDR5 field.                                             */
  #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field.                     */
  #define RADIO_RXADDRESSES_ADDR5_Min (0x0UL)        /*!< Min enumerator value of ADDR5 field.                                 */
  #define RADIO_RXADDRESSES_ADDR5_Max (0x1UL)        /*!< Max enumerator value of ADDR5 field.                                 */
  #define RADIO_RXADDRESSES_ADDR5_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR5_Enabled (0x1UL)    /*!< Enable                                                               */

/* ADDR6 @Bit 6 : Enable or disable reception on logical address 6 */
  #define RADIO_RXADDRESSES_ADDR6_Pos (6UL)          /*!< Position of ADDR6 field.                                             */
  #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field.                     */
  #define RADIO_RXADDRESSES_ADDR6_Min (0x0UL)        /*!< Min enumerator value of ADDR6 field.                                 */
  #define RADIO_RXADDRESSES_ADDR6_Max (0x1UL)        /*!< Max enumerator value of ADDR6 field.                                 */
  #define RADIO_RXADDRESSES_ADDR6_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR6_Enabled (0x1UL)    /*!< Enable                                                               */

/* ADDR7 @Bit 7 : Enable or disable reception on logical address 7 */
  #define RADIO_RXADDRESSES_ADDR7_Pos (7UL)          /*!< Position of ADDR7 field.                                             */
  #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field.                     */
  #define RADIO_RXADDRESSES_ADDR7_Min (0x0UL)        /*!< Min enumerator value of ADDR7 field.                                 */
  #define RADIO_RXADDRESSES_ADDR7_Max (0x1UL)        /*!< Max enumerator value of ADDR7 field.                                 */
  #define RADIO_RXADDRESSES_ADDR7_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RADIO_RXADDRESSES_ADDR7_Enabled (0x1UL)    /*!< Enable                                                               */


/* RADIO_CRCCNF: CRC configuration */
  #define RADIO_CRCCNF_ResetValue (0x00000000UL)     /*!< Reset value of CRCCNF register.                                      */

/* LEN @Bits 0..1 : CRC length in number of bytes. */
  #define RADIO_CRCCNF_LEN_Pos (0UL)                 /*!< Position of LEN field.                                               */
  #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field.                                     */
  #define RADIO_CRCCNF_LEN_Min (0x0UL)               /*!< Min enumerator value of LEN field.                                   */
  #define RADIO_CRCCNF_LEN_Max (0x3UL)               /*!< Max enumerator value of LEN field.                                   */
  #define RADIO_CRCCNF_LEN_Disabled (0x0UL)          /*!< CRC length is zero and CRC calculation is disabled                   */
  #define RADIO_CRCCNF_LEN_One (0x1UL)               /*!< CRC length is one byte and CRC calculation is enabled                */
  #define RADIO_CRCCNF_LEN_Two (0x2UL)               /*!< CRC length is two bytes and CRC calculation is enabled               */
  #define RADIO_CRCCNF_LEN_Three (0x3UL)             /*!< CRC length is three bytes and CRC calculation is enabled             */

/* SKIPADDR @Bits 8..10 : Control whether CRC calculation skips the address field. Other fields can also be skipped. */
  #define RADIO_CRCCNF_SKIPADDR_Pos (8UL)            /*!< Position of SKIPADDR field.                                          */
  #define RADIO_CRCCNF_SKIPADDR_Msk (0x7UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field.                      */
  #define RADIO_CRCCNF_SKIPADDR_Min (0x0UL)          /*!< Min enumerator value of SKIPADDR field.                              */
  #define RADIO_CRCCNF_SKIPADDR_Max (0x4UL)          /*!< Max enumerator value of SKIPADDR field.                              */
  #define RADIO_CRCCNF_SKIPADDR_Include (0x0UL)      /*!< CRC calculation includes address field                               */
  #define RADIO_CRCCNF_SKIPADDR_Skip (0x1UL)         /*!< CRC calculation starting at first byte after address field.          */
  #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (0x2UL)   /*!< CRC calculation starting at first byte after length field (as per
                                                          802.15.4 standard).*/
  #define RADIO_CRCCNF_SKIPADDR_SkipS0 (0x3UL)       /*!< CRC calculation starting at first byte after S0 field.               */
  #define RADIO_CRCCNF_SKIPADDR_SkipS1 (0x4UL)       /*!< CRC calculation starting at first byte after S1 field.               */


/* RADIO_CRCPOLY: CRC polynomial */
  #define RADIO_CRCPOLY_ResetValue (0x00000000UL)    /*!< Reset value of CRCPOLY register.                                     */

/* CRCPOLY @Bits 0..23 : CRC polynomial */
  #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL)            /*!< Position of CRCPOLY field.                                           */
  #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field.                  */


/* RADIO_CRCINIT: CRC initial value */
  #define RADIO_CRCINIT_ResetValue (0x00000000UL)    /*!< Reset value of CRCINIT register.                                     */

/* CRCINIT @Bits 0..23 : CRC initial value */
  #define RADIO_CRCINIT_CRCINIT_Pos (0UL)            /*!< Position of CRCINIT field.                                           */
  #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field.                  */


/* RADIO_DAB: Device address base segment n */
  #define RADIO_DAB_MaxCount (8UL)                   /*!< Max size of DAB[8] array.                                            */
  #define RADIO_DAB_MaxIndex (7UL)                   /*!< Max index of DAB[8] array.                                           */
  #define RADIO_DAB_MinIndex (0UL)                   /*!< Min index of DAB[8] array.                                           */
  #define RADIO_DAB_ResetValue (0x00000000UL)        /*!< Reset value of DAB[8] register.                                      */

/* DAB @Bits 0..31 : Device address base segment n */
  #define RADIO_DAB_DAB_Pos (0UL)                    /*!< Position of DAB field.                                               */
  #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field.                                    */


/* RADIO_DAP: Device address prefix n */
  #define RADIO_DAP_MaxCount (8UL)                   /*!< Max size of DAP[8] array.                                            */
  #define RADIO_DAP_MaxIndex (7UL)                   /*!< Max index of DAP[8] array.                                           */
  #define RADIO_DAP_MinIndex (0UL)                   /*!< Min index of DAP[8] array.                                           */
  #define RADIO_DAP_ResetValue (0x00000000UL)        /*!< Reset value of DAP[8] register.                                      */

/* DAP @Bits 0..15 : Device address prefix n */
  #define RADIO_DAP_DAP_Pos (0UL)                    /*!< Position of DAP field.                                               */
  #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field.                                        */


/* RADIO_DACNF: Device address match configuration */
  #define RADIO_DACNF_ResetValue (0x00000000UL)      /*!< Reset value of DACNF register.                                       */

/* ENA0 @Bit 0 : Enable or disable device address matching using device address 0 */
  #define RADIO_DACNF_ENA0_Pos (0UL)                 /*!< Position of ENA0 field.                                              */
  #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field.                                    */
  #define RADIO_DACNF_ENA0_Min (0x0UL)               /*!< Min enumerator value of ENA0 field.                                  */
  #define RADIO_DACNF_ENA0_Max (0x1UL)               /*!< Max enumerator value of ENA0 field.                                  */
  #define RADIO_DACNF_ENA0_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA0_Enabled (0x1UL)           /*!< Enabled                                                              */

/* ENA1 @Bit 1 : Enable or disable device address matching using device address 1 */
  #define RADIO_DACNF_ENA1_Pos (1UL)                 /*!< Position of ENA1 field.                                              */
  #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field.                                    */
  #define RADIO_DACNF_ENA1_Min (0x0UL)               /*!< Min enumerator value of ENA1 field.                                  */
  #define RADIO_DACNF_ENA1_Max (0x1UL)               /*!< Max enumerator value of ENA1 field.                                  */
  #define RADIO_DACNF_ENA1_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA1_Enabled (0x1UL)           /*!< Enabled                                                              */

/* ENA2 @Bit 2 : Enable or disable device address matching using device address 2 */
  #define RADIO_DACNF_ENA2_Pos (2UL)                 /*!< Position of ENA2 field.                                              */
  #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field.                                    */
  #define RADIO_DACNF_ENA2_Min (0x0UL)               /*!< Min enumerator value of ENA2 field.                                  */
  #define RADIO_DACNF_ENA2_Max (0x1UL)               /*!< Max enumerator value of ENA2 field.                                  */
  #define RADIO_DACNF_ENA2_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA2_Enabled (0x1UL)           /*!< Enabled                                                              */

/* ENA3 @Bit 3 : Enable or disable device address matching using device address 3 */
  #define RADIO_DACNF_ENA3_Pos (3UL)                 /*!< Position of ENA3 field.                                              */
  #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field.                                    */
  #define RADIO_DACNF_ENA3_Min (0x0UL)               /*!< Min enumerator value of ENA3 field.                                  */
  #define RADIO_DACNF_ENA3_Max (0x1UL)               /*!< Max enumerator value of ENA3 field.                                  */
  #define RADIO_DACNF_ENA3_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA3_Enabled (0x1UL)           /*!< Enabled                                                              */

/* ENA4 @Bit 4 : Enable or disable device address matching using device address 4 */
  #define RADIO_DACNF_ENA4_Pos (4UL)                 /*!< Position of ENA4 field.                                              */
  #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field.                                    */
  #define RADIO_DACNF_ENA4_Min (0x0UL)               /*!< Min enumerator value of ENA4 field.                                  */
  #define RADIO_DACNF_ENA4_Max (0x1UL)               /*!< Max enumerator value of ENA4 field.                                  */
  #define RADIO_DACNF_ENA4_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA4_Enabled (0x1UL)           /*!< Enabled                                                              */

/* ENA5 @Bit 5 : Enable or disable device address matching using device address 5 */
  #define RADIO_DACNF_ENA5_Pos (5UL)                 /*!< Position of ENA5 field.                                              */
  #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field.                                    */
  #define RADIO_DACNF_ENA5_Min (0x0UL)               /*!< Min enumerator value of ENA5 field.                                  */
  #define RADIO_DACNF_ENA5_Max (0x1UL)               /*!< Max enumerator value of ENA5 field.                                  */
  #define RADIO_DACNF_ENA5_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA5_Enabled (0x1UL)           /*!< Enabled                                                              */

/* ENA6 @Bit 6 : Enable or disable device address matching using device address 6 */
  #define RADIO_DACNF_ENA6_Pos (6UL)                 /*!< Position of ENA6 field.                                              */
  #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field.                                    */
  #define RADIO_DACNF_ENA6_Min (0x0UL)               /*!< Min enumerator value of ENA6 field.                                  */
  #define RADIO_DACNF_ENA6_Max (0x1UL)               /*!< Max enumerator value of ENA6 field.                                  */
  #define RADIO_DACNF_ENA6_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA6_Enabled (0x1UL)           /*!< Enabled                                                              */

/* ENA7 @Bit 7 : Enable or disable device address matching using device address 7 */
  #define RADIO_DACNF_ENA7_Pos (7UL)                 /*!< Position of ENA7 field.                                              */
  #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field.                                    */
  #define RADIO_DACNF_ENA7_Min (0x0UL)               /*!< Min enumerator value of ENA7 field.                                  */
  #define RADIO_DACNF_ENA7_Max (0x1UL)               /*!< Max enumerator value of ENA7 field.                                  */
  #define RADIO_DACNF_ENA7_Disabled (0x0UL)          /*!< Disabled                                                             */
  #define RADIO_DACNF_ENA7_Enabled (0x1UL)           /*!< Enabled                                                              */

/* TXADD0 @Bit 8 : TxAdd for device address 0 */
  #define RADIO_DACNF_TXADD0_Pos (8UL)               /*!< Position of TXADD0 field.                                            */
  #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field.                              */

/* TXADD1 @Bit 9 : TxAdd for device address 1 */
  #define RADIO_DACNF_TXADD1_Pos (9UL)               /*!< Position of TXADD1 field.                                            */
  #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field.                              */

/* TXADD2 @Bit 10 : TxAdd for device address 2 */
  #define RADIO_DACNF_TXADD2_Pos (10UL)              /*!< Position of TXADD2 field.                                            */
  #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field.                              */

/* TXADD3 @Bit 11 : TxAdd for device address 3 */
  #define RADIO_DACNF_TXADD3_Pos (11UL)              /*!< Position of TXADD3 field.                                            */
  #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field.                              */

/* TXADD4 @Bit 12 : TxAdd for device address 4 */
  #define RADIO_DACNF_TXADD4_Pos (12UL)              /*!< Position of TXADD4 field.                                            */
  #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field.                              */

/* TXADD5 @Bit 13 : TxAdd for device address 5 */
  #define RADIO_DACNF_TXADD5_Pos (13UL)              /*!< Position of TXADD5 field.                                            */
  #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field.                              */

/* TXADD6 @Bit 14 : TxAdd for device address 6 */
  #define RADIO_DACNF_TXADD6_Pos (14UL)              /*!< Position of TXADD6 field.                                            */
  #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field.                              */

/* TXADD7 @Bit 15 : TxAdd for device address 7 */
  #define RADIO_DACNF_TXADD7_Pos (15UL)              /*!< Position of TXADD7 field.                                            */
  #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field.                              */


/* RADIO_BCC: Bit counter compare */
  #define RADIO_BCC_ResetValue (0x00000000UL)        /*!< Reset value of BCC register.                                         */

/* BCC @Bits 0..31 : Bit counter compare */
  #define RADIO_BCC_BCC_Pos (0UL)                    /*!< Position of BCC field.                                               */
  #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field.                                    */


/* RADIO_CTESTATUS: CTEInfo parsed from received packet */
  #define RADIO_CTESTATUS_ResetValue (0x00000000UL)  /*!< Reset value of CTESTATUS register.                                   */

/* CTETIME @Bits 0..4 : CTETime parsed from packet */
  #define RADIO_CTESTATUS_CTETIME_Pos (0UL)          /*!< Position of CTETIME field.                                           */
  #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field.                  */

/* RFU @Bit 5 : RFU parsed from packet */
  #define RADIO_CTESTATUS_RFU_Pos (5UL)              /*!< Position of RFU field.                                               */
  #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field.                               */

/* CTETYPE @Bits 6..7 : CTEType parsed from packet */
  #define RADIO_CTESTATUS_CTETYPE_Pos (6UL)          /*!< Position of CTETYPE field.                                           */
  #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field.                   */


/* RADIO_MHRMATCHCONF: Search pattern configuration */
  #define RADIO_MHRMATCHCONF_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHCONF register.                              */

/* MHRMATCHCONF @Bits 0..31 : Search pattern configuration */
  #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL)  /*!< Position of MHRMATCHCONF field.                                      */
  #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of
                                                                            MHRMATCHCONF field.*/


/* RADIO_MHRMATCHMASK: Pattern mask */
  #define RADIO_MHRMATCHMASK_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHMASK register.                              */

/* MHRMATCHMASK @Bits 0..31 : Pattern mask */
  #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos (0UL)  /*!< Position of MHRMATCHMASK field.                                      */
  #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos) /*!< Bit mask of
                                                                            MHRMATCHMASK field.*/


/* RADIO_SFD: IEEE 802.15.4 start of frame delimiter */
  #define RADIO_SFD_ResetValue (0x000000A7UL)        /*!< Reset value of SFD register.                                         */

/* SFD @Bits 0..7 : IEEE 802.15.4 start of frame delimiter. Note: the least significant 4 bits of the SFD cannot all be zeros. */
  #define RADIO_SFD_SFD_Pos (0UL)                    /*!< Position of SFD field.                                               */
  #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field.                                          */


/* RADIO_CTEINLINECONF: Configuration for CTE inline mode */
  #define RADIO_CTEINLINECONF_ResetValue (0x00002800UL) /*!< Reset value of CTEINLINECONF register.                            */

/* CTEINLINECTRLEN @Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
  #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field.                                */
  #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of
                                                                            CTEINLINECTRLEN field.*/
  #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Min (0x0UL) /*!< Min enumerator value of CTEINLINECTRLEN field.                  */
  #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Max (0x1UL) /*!< Max enumerator value of CTEINLINECTRLEN field.                  */
  #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (0x1UL) /*!< Parsing of CTEInfo is enabled                               */
  #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0x0UL) /*!< Parsing of CTEInfo is disabled                             */

/* CTEINFOINS1 @Bit 3 : CTEInfo is S1 byte or not */
  #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL)  /*!< Position of CTEINFOINS1 field.                                       */
  #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1
                                                                            field.*/
  #define RADIO_CTEINLINECONF_CTEINFOINS1_Min (0x0UL) /*!< Min enumerator value of CTEINFOINS1 field.                          */
  #define RADIO_CTEINLINECONF_CTEINFOINS1_Max (0x1UL) /*!< Max enumerator value of CTEINFOINS1 field.                          */
  #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (0x1UL) /*!< CTEInfo is in S1 byte (data PDU)                                   */
  #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0x0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU)                     */

/* CTEERRORHANDLING @Bit 4 : Sampling/switching if CRC is not OK */
  #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field.                              */
  #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of
                                                                            CTEERRORHANDLING field.*/
  #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Min (0x0UL) /*!< Min enumerator value of CTEERRORHANDLING field.                */
  #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Max (0x1UL) /*!< Max enumerator value of CTEERRORHANDLING field.                */
  #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (0x1UL) /*!< Sampling and antenna switching also when CRC is not OK         */
  #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0x0UL) /*!< No sampling and antenna switching when CRC is not OK            */

/* CTETIMEVALIDRANGE @Bits 6..7 : Max range of CTETime */
  #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field.                            */
  #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of
                                                                            CTETIMEVALIDRANGE field.*/
  #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Min (0x0UL) /*!< Min enumerator value of CTETIMEVALIDRANGE field.              */
  #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Max (0x2UL) /*!< Max enumerator value of CTETIMEVALIDRANGE field.              */
  #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0x0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger
                                                                han 20*/
  #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (0x1UL) /*!< 31 in 8us unit                                                 */
  #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (0x2UL) /*!< 63 in 8us unit                                                 */

/* CTEINLINERXMODE1US @Bits 10..12 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field.                         */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of
                                                                            CTEINLINERXMODE1US field.*/
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE1US field.            */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE1US field.            */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (0x1UL) /*!< 4us                                                          */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (0x2UL) /*!< 2us                                                          */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (0x3UL) /*!< 1us                                                          */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (0x4UL) /*!< 0.5us                                                      */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (0x5UL) /*!< 0.25us                                                     */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (0x6UL) /*!< 0.125us                                                    */

/* CTEINLINERXMODE2US @Bits 13..15 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field.                         */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of
                                                                            CTEINLINERXMODE2US field.*/
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE2US field.            */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE2US field.            */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (0x1UL) /*!< 4us                                                          */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (0x2UL) /*!< 2us                                                          */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (0x3UL) /*!< 1us                                                          */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (0x4UL) /*!< 0.5us                                                      */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (0x5UL) /*!< 0.25us                                                     */
  #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (0x6UL) /*!< 0.125us                                                    */

/* S0CONF @Bits 16..23 : S0 bit pattern to match */
  #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL)      /*!< Position of S0CONF field.                                            */
  #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field.             */

/* S0MASK @Bits 24..31 : S0 bit mask to set which bit to match */
  #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL)      /*!< Position of S0MASK field.                                            */
  #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field.             */


/* RADIO_PACKETPTR: Packet pointer */
  #define RADIO_PACKETPTR_ResetValue (0x00000000UL)  /*!< Reset value of PACKETPTR register.                                   */

/* PTR @Bits 0..31 : Data pointer */
  #define RADIO_PACKETPTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define RADIO_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                        REGULATORS                                        ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* =============================================== Struct REGULATORS_VREGMAIN ================================================ */
/**
  * @brief VREGMAIN [REGULATORS_VREGMAIN] Register interface for main voltage regulator.
  */
typedef struct {
  __IOM uint32_t  DCDCEN;                            /*!< (@ 0x00000000) Enable DC/DC converter for better power efficiency    */
  __IM  uint32_t  INDUCTORDET;                       /*!< (@ 0x00000004) VREGMAIN inductor detection                           */
} NRF_REGULATORS_VREGMAIN_Type;                      /*!< Size = 8 (0x008)                                                     */

/* REGULATORS_VREGMAIN_DCDCEN: Enable DC/DC converter for better power efficiency */
  #define REGULATORS_VREGMAIN_DCDCEN_ResetValue (0x00000000UL) /*!< Reset value of DCDCEN register.                            */

/* VAL @Bit 0 : Enable DC/DC buck converter */
  #define REGULATORS_VREGMAIN_DCDCEN_VAL_Pos (0UL)   /*!< Position of VAL field.                                               */
  #define REGULATORS_VREGMAIN_DCDCEN_VAL_Msk (0x1UL << REGULATORS_VREGMAIN_DCDCEN_VAL_Pos) /*!< Bit mask of VAL field.         */
  #define REGULATORS_VREGMAIN_DCDCEN_VAL_Min (0x0UL) /*!< Min enumerator value of VAL field.                                   */
  #define REGULATORS_VREGMAIN_DCDCEN_VAL_Max (0x1UL) /*!< Max enumerator value of VAL field.                                   */
  #define REGULATORS_VREGMAIN_DCDCEN_VAL_Disabled (0x0UL) /*!< Disable DC/DC converter and use LDO                             */
  #define REGULATORS_VREGMAIN_DCDCEN_VAL_Enabled (0x1UL) /*!< Enable DC/DC converter                                           */


/* REGULATORS_VREGMAIN_INDUCTORDET: VREGMAIN inductor detection */
  #define REGULATORS_VREGMAIN_INDUCTORDET_ResetValue (0x00000000UL) /*!< Reset value of INDUCTORDET register.                  */

/* DETECTED @Bit 0 : (unspecified) */
  #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Pos (0UL) /*!< Position of DETECTED field.                                  */
  #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Msk (0x1UL << REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Pos) /*!< Bit mask of
                                                                            DETECTED field.*/
  #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Min (0x0UL) /*!< Min enumerator value of DETECTED field.                    */
  #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_Max (0x1UL) /*!< Max enumerator value of DETECTED field.                    */
  #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_InductorNotDetected (0x0UL) /*!< VREGMAIN inductor not detected             */
  #define REGULATORS_VREGMAIN_INDUCTORDET_DETECTED_InductorDetected (0x1UL) /*!< VREGMAIN inductor detected                    */


/* ==================================================== Struct REGULATORS ==================================================== */
/**
  * @brief Voltage regulators
  */
  typedef struct {                                   /*!< REGULATORS Structure                                                 */
    __IM uint32_t RESERVED[320];
    __OM uint32_t SYSTEMOFF;                         /*!< (@ 0x00000500) System OFF register                                   */
    __IM uint32_t RESERVED1[11];
    __IOM uint32_t POFCON;                           /*!< (@ 0x00000530) Power-fail comparator configuration                   */
    __IM uint32_t POFSTAT;                           /*!< (@ 0x00000534) Power-fail comparator status register                 */
    __IM uint32_t RESERVED2[50];
    __IOM NRF_REGULATORS_VREGMAIN_Type VREGMAIN;     /*!< (@ 0x00000600) Register interface for main voltage regulator.        */
  } NRF_REGULATORS_Type;                             /*!< Size = 1544 (0x608)                                                  */

/* REGULATORS_SYSTEMOFF: System OFF register */
  #define REGULATORS_SYSTEMOFF_ResetValue (0x00000000UL) /*!< Reset value of SYSTEMOFF register.                               */

/* SYSTEMOFF @Bit 0 : Enable System OFF mode */
  #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL)   /*!< Position of SYSTEMOFF field.                                         */
  #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field.   */
  #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Min (0x1UL) /*!< Min enumerator value of SYSTEMOFF field.                             */
  #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Max (0x1UL) /*!< Max enumerator value of SYSTEMOFF field.                             */
  #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enter (0x1UL) /*!< Enable System OFF mode                                             */


/* REGULATORS_POFCON: Power-fail comparator configuration */
  #define REGULATORS_POFCON_ResetValue (0x00000000UL) /*!< Reset value of POFCON register.                                     */

/* POF @Bit 0 : Enable or disable power-fail comparator */
  #define REGULATORS_POFCON_POF_Pos (0UL)            /*!< Position of POF field.                                               */
  #define REGULATORS_POFCON_POF_Msk (0x1UL << REGULATORS_POFCON_POF_Pos) /*!< Bit mask of POF field.                           */
  #define REGULATORS_POFCON_POF_Min (0x0UL)          /*!< Min enumerator value of POF field.                                   */
  #define REGULATORS_POFCON_POF_Max (0x1UL)          /*!< Max enumerator value of POF field.                                   */
  #define REGULATORS_POFCON_POF_Disabled (0x0UL)     /*!< Disable                                                              */
  #define REGULATORS_POFCON_POF_Enabled (0x1UL)      /*!< Enable                                                               */

/* THRESHOLD @Bits 1..4 : Power-fail comparator threshold setting */
  #define REGULATORS_POFCON_THRESHOLD_Pos (1UL)      /*!< Position of THRESHOLD field.                                         */
  #define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field.         */
  #define REGULATORS_POFCON_THRESHOLD_Min (0x0UL)    /*!< Min enumerator value of THRESHOLD field.                             */
  #define REGULATORS_POFCON_THRESHOLD_Max (0xFUL)    /*!< Max enumerator value of THRESHOLD field.                             */
  #define REGULATORS_POFCON_THRESHOLD_V17 (0x0UL)    /*!< Set threshold to 1.7 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V18 (0x1UL)    /*!< Set threshold to 1.8 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V19 (0x2UL)    /*!< Set threshold to 1.9 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V20 (0x3UL)    /*!< Set threshold to 2.0 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V21 (0x4UL)    /*!< Set threshold to 2.1 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V22 (0x5UL)    /*!< Set threshold to 2.2 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V23 (0x6UL)    /*!< Set threshold to 2.3 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V24 (0x7UL)    /*!< Set threshold to 2.4 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V25 (0x8UL)    /*!< Set threshold to 2.5 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V26 (0x9UL)    /*!< Set threshold to 2.6 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V27 (0xAUL)    /*!< Set threshold to 2.7 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V28 (0xBUL)    /*!< Set threshold to 2.8 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V29 (0xCUL)    /*!< Set threshold to 2.9 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V30 (0xDUL)    /*!< Set threshold to 3.0 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V31 (0xEUL)    /*!< Set threshold to 3.1 V for VDD                                       */
  #define REGULATORS_POFCON_THRESHOLD_V32 (0xFUL)    /*!< Set threshold to 3.2 V for VDD                                       */

/* EVENTDISABLE @Bit 7 : Disable the POFWARN power-fail warning event */
  #define REGULATORS_POFCON_EVENTDISABLE_Pos (7UL)   /*!< Position of EVENTDISABLE field.                                      */
  #define REGULATORS_POFCON_EVENTDISABLE_Msk (0x1UL << REGULATORS_POFCON_EVENTDISABLE_Pos) /*!< Bit mask of EVENTDISABLE field.*/
  #define REGULATORS_POFCON_EVENTDISABLE_Min (0x0UL) /*!< Min enumerator value of EVENTDISABLE field.                          */
  #define REGULATORS_POFCON_EVENTDISABLE_Max (0x1UL) /*!< Max enumerator value of EVENTDISABLE field.                          */
  #define REGULATORS_POFCON_EVENTDISABLE_Enabled (0x0UL) /*!< POFWARN event is generated                                       */
  #define REGULATORS_POFCON_EVENTDISABLE_Disabled (0x1UL) /*!< POFWARN event is not generated                                  */


/* REGULATORS_POFSTAT: Power-fail comparator status register */
  #define REGULATORS_POFSTAT_ResetValue (0x00000000UL) /*!< Reset value of POFSTAT register.                                   */

/* COMPARATOR @Bit 0 : Power-fail comparator status */
  #define REGULATORS_POFSTAT_COMPARATOR_Pos (0UL)    /*!< Position of COMPARATOR field.                                        */
  #define REGULATORS_POFSTAT_COMPARATOR_Msk (0x1UL << REGULATORS_POFSTAT_COMPARATOR_Pos) /*!< Bit mask of COMPARATOR field.    */
  #define REGULATORS_POFSTAT_COMPARATOR_Min (0x0UL)  /*!< Min enumerator value of COMPARATOR field.                            */
  #define REGULATORS_POFSTAT_COMPARATOR_Max (0x1UL)  /*!< Max enumerator value of COMPARATOR field.                            */
  #define REGULATORS_POFSTAT_COMPARATOR_Above (0x0UL) /*!< Voltage detected above VPOF threshold                               */
  #define REGULATORS_POFSTAT_COMPARATOR_Below (0x1UL) /*!< Voltage detected below VPOF threshold                               */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           RESET                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ====================================================== Struct RESET ======================================================= */
/**
  * @brief Reset control
  */
  typedef struct {                                   /*!< RESET Structure                                                      */
    __IM uint32_t RESERVED[384];
    __IOM uint32_t RESETREAS;                        /*!< (@ 0x00000600) Reset reason                                          */
  } NRF_RESET_Type;                                  /*!< Size = 1540 (0x604)                                                  */

/* RESET_RESETREAS: Reset reason */
  #define RESET_RESETREAS_ResetValue (0x00000000UL)  /*!< Reset value of RESETREAS register.                                   */

/* RESETPIN @Bit 0 : Reset from pin reset detected */
  #define RESET_RESETREAS_RESETPIN_Pos (0UL)         /*!< Position of RESETPIN field.                                          */
  #define RESET_RESETREAS_RESETPIN_Msk (0x1UL << RESET_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field.                */
  #define RESET_RESETREAS_RESETPIN_Min (0x0UL)       /*!< Min enumerator value of RESETPIN field.                              */
  #define RESET_RESETREAS_RESETPIN_Max (0x1UL)       /*!< Max enumerator value of RESETPIN field.                              */
  #define RESET_RESETREAS_RESETPIN_NotDetected (0x0UL) /*!< Not detected                                                       */
  #define RESET_RESETREAS_RESETPIN_Detected (0x1UL)  /*!< Detected                                                             */

/* DOG0 @Bit 1 : Reset from watchdog timer 0 detected */
  #define RESET_RESETREAS_DOG0_Pos (1UL)             /*!< Position of DOG0 field.                                              */
  #define RESET_RESETREAS_DOG0_Msk (0x1UL << RESET_RESETREAS_DOG0_Pos) /*!< Bit mask of DOG0 field.                            */
  #define RESET_RESETREAS_DOG0_Min (0x0UL)           /*!< Min enumerator value of DOG0 field.                                  */
  #define RESET_RESETREAS_DOG0_Max (0x1UL)           /*!< Max enumerator value of DOG0 field.                                  */
  #define RESET_RESETREAS_DOG0_NotDetected (0x0UL)   /*!< Not detected                                                         */
  #define RESET_RESETREAS_DOG0_Detected (0x1UL)      /*!< Detected                                                             */

/* DOG1 @Bit 2 : Reset from watchdog timer 1 detected */
  #define RESET_RESETREAS_DOG1_Pos (2UL)             /*!< Position of DOG1 field.                                              */
  #define RESET_RESETREAS_DOG1_Msk (0x1UL << RESET_RESETREAS_DOG1_Pos) /*!< Bit mask of DOG1 field.                            */
  #define RESET_RESETREAS_DOG1_Min (0x0UL)           /*!< Min enumerator value of DOG1 field.                                  */
  #define RESET_RESETREAS_DOG1_Max (0x1UL)           /*!< Max enumerator value of DOG1 field.                                  */
  #define RESET_RESETREAS_DOG1_NotDetected (0x0UL)   /*!< Not detected                                                         */
  #define RESET_RESETREAS_DOG1_Detected (0x1UL)      /*!< Detected                                                             */

/* CTRLAPSOFT @Bit 3 : Soft reset from CTRL-AP detected */
  #define RESET_RESETREAS_CTRLAPSOFT_Pos (3UL)       /*!< Position of CTRLAPSOFT field.                                        */
  #define RESET_RESETREAS_CTRLAPSOFT_Msk (0x1UL << RESET_RESETREAS_CTRLAPSOFT_Pos) /*!< Bit mask of CTRLAPSOFT field.          */
  #define RESET_RESETREAS_CTRLAPSOFT_Min (0x0UL)     /*!< Min enumerator value of CTRLAPSOFT field.                            */
  #define RESET_RESETREAS_CTRLAPSOFT_Max (0x1UL)     /*!< Max enumerator value of CTRLAPSOFT field.                            */
  #define RESET_RESETREAS_CTRLAPSOFT_NotDetected (0x0UL) /*!< Not detected                                                     */
  #define RESET_RESETREAS_CTRLAPSOFT_Detected (0x1UL) /*!< Detected                                                            */

/* CTRLAPHARD @Bit 4 : Reset due to CTRL-AP hard reset */
  #define RESET_RESETREAS_CTRLAPHARD_Pos (4UL)       /*!< Position of CTRLAPHARD field.                                        */
  #define RESET_RESETREAS_CTRLAPHARD_Msk (0x1UL << RESET_RESETREAS_CTRLAPHARD_Pos) /*!< Bit mask of CTRLAPHARD field.          */
  #define RESET_RESETREAS_CTRLAPHARD_Min (0x0UL)     /*!< Min enumerator value of CTRLAPHARD field.                            */
  #define RESET_RESETREAS_CTRLAPHARD_Max (0x1UL)     /*!< Max enumerator value of CTRLAPHARD field.                            */
  #define RESET_RESETREAS_CTRLAPHARD_NotDetected (0x0UL) /*!< Not detected                                                     */
  #define RESET_RESETREAS_CTRLAPHARD_Detected (0x1UL) /*!< Detected                                                            */

/* CTRLAPPIN @Bit 5 : Reset due to CTRL-AP pin reset */
  #define RESET_RESETREAS_CTRLAPPIN_Pos (5UL)        /*!< Position of CTRLAPPIN field.                                         */
  #define RESET_RESETREAS_CTRLAPPIN_Msk (0x1UL << RESET_RESETREAS_CTRLAPPIN_Pos) /*!< Bit mask of CTRLAPPIN field.             */
  #define RESET_RESETREAS_CTRLAPPIN_Min (0x0UL)      /*!< Min enumerator value of CTRLAPPIN field.                             */
  #define RESET_RESETREAS_CTRLAPPIN_Max (0x1UL)      /*!< Max enumerator value of CTRLAPPIN field.                             */
  #define RESET_RESETREAS_CTRLAPPIN_NotDetected (0x0UL) /*!< Not detected                                                      */
  #define RESET_RESETREAS_CTRLAPPIN_Detected (0x1UL) /*!< Detected                                                             */

/* SREQ @Bit 6 : Reset from soft reset detected */
  #define RESET_RESETREAS_SREQ_Pos (6UL)             /*!< Position of SREQ field.                                              */
  #define RESET_RESETREAS_SREQ_Msk (0x1UL << RESET_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field.                            */
  #define RESET_RESETREAS_SREQ_Min (0x0UL)           /*!< Min enumerator value of SREQ field.                                  */
  #define RESET_RESETREAS_SREQ_Max (0x1UL)           /*!< Max enumerator value of SREQ field.                                  */
  #define RESET_RESETREAS_SREQ_NotDetected (0x0UL)   /*!< Not detected                                                         */
  #define RESET_RESETREAS_SREQ_Detected (0x1UL)      /*!< Detected                                                             */

/* LOCKUP @Bit 7 : Reset from CPU lockup detected */
  #define RESET_RESETREAS_LOCKUP_Pos (7UL)           /*!< Position of LOCKUP field.                                            */
  #define RESET_RESETREAS_LOCKUP_Msk (0x1UL << RESET_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field.                      */
  #define RESET_RESETREAS_LOCKUP_Min (0x0UL)         /*!< Min enumerator value of LOCKUP field.                                */
  #define RESET_RESETREAS_LOCKUP_Max (0x1UL)         /*!< Max enumerator value of LOCKUP field.                                */
  #define RESET_RESETREAS_LOCKUP_NotDetected (0x0UL) /*!< Not detected                                                         */
  #define RESET_RESETREAS_LOCKUP_Detected (0x1UL)    /*!< Detected                                                             */

/* OFF @Bit 8 : Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO */
  #define RESET_RESETREAS_OFF_Pos (8UL)              /*!< Position of OFF field.                                               */
  #define RESET_RESETREAS_OFF_Msk (0x1UL << RESET_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field.                               */
  #define RESET_RESETREAS_OFF_Min (0x0UL)            /*!< Min enumerator value of OFF field.                                   */
  #define RESET_RESETREAS_OFF_Max (0x1UL)            /*!< Max enumerator value of OFF field.                                   */
  #define RESET_RESETREAS_OFF_NotDetected (0x0UL)    /*!< Not detected                                                         */
  #define RESET_RESETREAS_OFF_Detected (0x1UL)       /*!< Detected                                                             */

/* LPCOMP @Bit 9 : Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP */
  #define RESET_RESETREAS_LPCOMP_Pos (9UL)           /*!< Position of LPCOMP field.                                            */
  #define RESET_RESETREAS_LPCOMP_Msk (0x1UL << RESET_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field.                      */
  #define RESET_RESETREAS_LPCOMP_Min (0x0UL)         /*!< Min enumerator value of LPCOMP field.                                */
  #define RESET_RESETREAS_LPCOMP_Max (0x1UL)         /*!< Max enumerator value of LPCOMP field.                                */
  #define RESET_RESETREAS_LPCOMP_NotDetected (0x0UL) /*!< Not detected                                                         */
  #define RESET_RESETREAS_LPCOMP_Detected (0x1UL)    /*!< Detected                                                             */

/* DIF @Bit 10 : Reset triggered by Debug Interface */
  #define RESET_RESETREAS_DIF_Pos (10UL)             /*!< Position of DIF field.                                               */
  #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field.                               */
  #define RESET_RESETREAS_DIF_Min (0x0UL)            /*!< Min enumerator value of DIF field.                                   */
  #define RESET_RESETREAS_DIF_Max (0x1UL)            /*!< Max enumerator value of DIF field.                                   */
  #define RESET_RESETREAS_DIF_NotDetected (0x0UL)    /*!< Not detected                                                         */
  #define RESET_RESETREAS_DIF_Detected (0x1UL)       /*!< Detected                                                             */

/* GRTC @Bit 11 : Reset due to wakeup from GRTC */
  #define RESET_RESETREAS_GRTC_Pos (11UL)            /*!< Position of GRTC field.                                              */
  #define RESET_RESETREAS_GRTC_Msk (0x1UL << RESET_RESETREAS_GRTC_Pos) /*!< Bit mask of GRTC field.                            */
  #define RESET_RESETREAS_GRTC_Min (0x0UL)           /*!< Min enumerator value of GRTC field.                                  */
  #define RESET_RESETREAS_GRTC_Max (0x1UL)           /*!< Max enumerator value of GRTC field.                                  */
  #define RESET_RESETREAS_GRTC_NotDetected (0x0UL)   /*!< Not detected                                                         */
  #define RESET_RESETREAS_GRTC_Detected (0x1UL)      /*!< Detected                                                             */

/* NFC @Bit 12 : Reset after wakeup from System OFF mode due to NFC field being detected */
  #define RESET_RESETREAS_NFC_Pos (12UL)             /*!< Position of NFC field.                                               */
  #define RESET_RESETREAS_NFC_Msk (0x1UL << RESET_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field.                               */
  #define RESET_RESETREAS_NFC_Min (0x0UL)            /*!< Min enumerator value of NFC field.                                   */
  #define RESET_RESETREAS_NFC_Max (0x1UL)            /*!< Max enumerator value of NFC field.                                   */
  #define RESET_RESETREAS_NFC_NotDetected (0x0UL)    /*!< Not detected                                                         */
  #define RESET_RESETREAS_NFC_Detected (0x1UL)       /*!< Detected                                                             */

/* SECTAMPER @Bit 13 : Reset due to illegal tampering of the device */
  #define RESET_RESETREAS_SECTAMPER_Pos (13UL)       /*!< Position of SECTAMPER field.                                         */
  #define RESET_RESETREAS_SECTAMPER_Msk (0x1UL << RESET_RESETREAS_SECTAMPER_Pos) /*!< Bit mask of SECTAMPER field.             */
  #define RESET_RESETREAS_SECTAMPER_Min (0x0UL)      /*!< Min enumerator value of SECTAMPER field.                             */
  #define RESET_RESETREAS_SECTAMPER_Max (0x1UL)      /*!< Max enumerator value of SECTAMPER field.                             */
  #define RESET_RESETREAS_SECTAMPER_NotDetected (0x0UL) /*!< Not detected                                                      */
  #define RESET_RESETREAS_SECTAMPER_Detected (0x1UL) /*!< Detected                                                             */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           RRAMC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================= Struct RRAMC_BUFSTATUS ================================================== */
/**
  * @brief BUFSTATUS [RRAMC_BUFSTATUS] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __IM  uint32_t  WRITEBUFEMPTY;                     /*!< (@ 0x00000008) Internal write-buffer is empty                        */
} NRF_RRAMC_BUFSTATUS_Type;                          /*!< Size = 12 (0x00C)                                                    */

/* RRAMC_BUFSTATUS_WRITEBUFEMPTY: Internal write-buffer is empty */
  #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_ResetValue (0x00000000UL) /*!< Reset value of WRITEBUFEMPTY register.                  */

/* EMPTY @Bit 0 : (unspecified) */
  #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos (0UL) /*!< Position of EMPTY field.                                          */
  #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Msk (0x1UL << RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Pos) /*!< Bit mask of EMPTY
                                                                            field.*/
  #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Min (0x0UL) /*!< Min enumerator value of EMPTY field.                            */
  #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Max (0x1UL) /*!< Max enumerator value of EMPTY field.                            */
  #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_NotEmpty (0x0UL) /*!< The internal write-buffer has data that needs committing   */
  #define RRAMC_BUFSTATUS_WRITEBUFEMPTY_EMPTY_Empty (0x1UL) /*!< The internal write-buffer is empty and has no content that
                                                                 needs to be committed*/



/* ==================================================== Struct RRAMC_ECC ===================================================== */
/**
  * @brief ECC [RRAMC_ECC] (unspecified)
  */
typedef struct {
  __IM  uint32_t  ERRORADDR;                         /*!< (@ 0x00000000) Address of the first ECC error that could not be
                                                                         corrected*/
} NRF_RRAMC_ECC_Type;                                /*!< Size = 4 (0x004)                                                     */

/* RRAMC_ECC_ERRORADDR: Address of the first ECC error that could not be corrected */
  #define RRAMC_ECC_ERRORADDR_ResetValue (0x00FFFFFFUL) /*!< Reset value of ERRORADDR register.                                */

/* ADDRESS @Bits 0..31 : ECC error address */
  #define RRAMC_ECC_ERRORADDR_ADDRESS_Pos (0UL)      /*!< Position of ADDRESS field.                                           */
  #define RRAMC_ECC_ERRORADDR_ADDRESS_Msk (0xFFFFFFFFUL << RRAMC_ECC_ERRORADDR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.    */



/* =================================================== Struct RRAMC_POWER ==================================================== */
/**
  * @brief POWER [RRAMC_POWER] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Power configuration                                   */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  LOWPOWERCONFIG;                    /*!< (@ 0x00000008) Low power mode configuration                          */
} NRF_RRAMC_POWER_Type;                              /*!< Size = 12 (0x00C)                                                    */

/* RRAMC_POWER_CONFIG: Power configuration */
  #define RRAMC_POWER_CONFIG_ResetValue (0x00000100UL) /*!< Reset value of CONFIG register.                                    */

/* ACCESSTIMEOUT @Bits 0..15 : Access timeout, in 31.25 ns units, used for going into standby power mode or remain active on
                               wake up */

  #define RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos (0UL) /*!< Position of ACCESSTIMEOUT field.                                     */
  #define RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Msk (0xFFFFUL << RRAMC_POWER_CONFIG_ACCESSTIMEOUT_Pos) /*!< Bit mask of ACCESSTIMEOUT
                                                                            field.*/

/* POF @Bit 16 : Power on failure warning handling configuration */
  #define RRAMC_POWER_CONFIG_POF_Pos (16UL)          /*!< Position of POF field.                                               */
  #define RRAMC_POWER_CONFIG_POF_Msk (0x1UL << RRAMC_POWER_CONFIG_POF_Pos) /*!< Bit mask of POF field.                         */
  #define RRAMC_POWER_CONFIG_POF_Min (0x0UL)         /*!< Min enumerator value of POF field.                                   */
  #define RRAMC_POWER_CONFIG_POF_Max (0x1UL)         /*!< Max enumerator value of POF field.                                   */
  #define RRAMC_POWER_CONFIG_POF_Wait (0x0UL)        /*!< Wait until the current RRAM write finishes                           */
  #define RRAMC_POWER_CONFIG_POF_Abort (0x1UL)       /*!< Abort the current RRAM write                                         */


/* RRAMC_POWER_LOWPOWERCONFIG: Low power mode configuration */
  #define RRAMC_POWER_LOWPOWERCONFIG_ResetValue (0x00000000UL) /*!< Reset value of LOWPOWERCONFIG register.                    */

/* MODE @Bits 0..1 : RRAM low power mode */
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Pos (0UL)  /*!< Position of MODE field.                                              */
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Msk (0x3UL << RRAMC_POWER_LOWPOWERCONFIG_MODE_Pos) /*!< Bit mask of MODE field.      */
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field.                                 */
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field.                                 */
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_PowerDown (0x0UL) /*!< The RRAM goes into power down mode                            */
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_Standby (0x1UL) /*!< The RRAM automatically goes into standby mode while the RRAM is
                                                               not being accessed*/
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_NAP (0x2UL) /*!< The RRAM goes into NAP mode                                         */
  #define RRAMC_POWER_LOWPOWERCONFIG_MODE_PowerOff (0x3UL) /*!< The RRAM is powered Off                                        */



/* =================================================== Struct RRAMC_ERASE ==================================================== */
/**
  * @brief ERASE [RRAMC_ERASE] (unspecified)
  */
typedef struct {
  __IOM uint32_t  ERASEALL;                          /*!< (@ 0x00000000) Register for erasing whole RRAM main block, that
                                                                         includes the SICR and the UICR*/
} NRF_RRAMC_ERASE_Type;                              /*!< Size = 4 (0x004)                                                     */

/* RRAMC_ERASE_ERASEALL: Register for erasing whole RRAM main block, that includes the SICR and the UICR */
  #define RRAMC_ERASE_ERASEALL_ResetValue (0x00000000UL) /*!< Reset value of ERASEALL register.                                */

/* ERASE @Bit 0 : Erase whole RRAM main block */
  #define RRAMC_ERASE_ERASEALL_ERASE_Pos (0UL)       /*!< Position of ERASE field.                                             */
  #define RRAMC_ERASE_ERASEALL_ERASE_Msk (0x1UL << RRAMC_ERASE_ERASEALL_ERASE_Pos) /*!< Bit mask of ERASE field.               */
  #define RRAMC_ERASE_ERASEALL_ERASE_Min (0x0UL)     /*!< Min enumerator value of ERASE field.                                 */
  #define RRAMC_ERASE_ERASEALL_ERASE_Max (0x1UL)     /*!< Max enumerator value of ERASE field.                                 */
  #define RRAMC_ERASE_ERASEALL_ERASE_NoOperation (0x0UL) /*!< No operation                                                     */
  #define RRAMC_ERASE_ERASEALL_ERASE_Erase (0x1UL)   /*!< Start erase of chip                                                  */



/* =================================================== Struct RRAMC_REGION =================================================== */
/**
  * @brief REGION [RRAMC_REGION] RRAMC can apply access privileges to regions of the RRAM. Some regions are dedicated for system
            use and are not available for configuration - refer to the instantiation table for details.

  */
typedef struct {
  __IOM uint32_t  ADDRESS;                           /*!< (@ 0x00000000) Region address                                        */
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000004) Region configuration                                  */
} NRF_RRAMC_REGION_Type;                             /*!< Size = 8 (0x008)                                                     */
  #define RRAMC_REGION_MaxCount (5UL)                /*!< Size of REGION[5] array.                                             */
  #define RRAMC_REGION_MaxIndex (4UL)                /*!< Max index of REGION[5] array.                                        */
  #define RRAMC_REGION_MinIndex (0UL)                /*!< Min index of REGION[5] array.                                        */

/* RRAMC_REGION_ADDRESS: Region address */
  #define RRAMC_REGION_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register.                                 */

/* STARTADDR @Bits 0..31 : Start address of the region [n] */
  #define RRAMC_REGION_ADDRESS_STARTADDR_Pos (0UL)   /*!< Position of STARTADDR field.                                         */
  #define RRAMC_REGION_ADDRESS_STARTADDR_Msk (0xFFFFFFFFUL << RRAMC_REGION_ADDRESS_STARTADDR_Pos) /*!< Bit mask of STARTADDR
                                                                            field.*/


/* RRAMC_REGION_CONFIG: Region configuration */
  #define RRAMC_REGION_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                                   */

/* READ @Bit 0 : Read access */
  #define RRAMC_REGION_CONFIG_READ_Pos (0UL)         /*!< Position of READ field.                                              */
  #define RRAMC_REGION_CONFIG_READ_Msk (0x1UL << RRAMC_REGION_CONFIG_READ_Pos) /*!< Bit mask of READ field.                    */
  #define RRAMC_REGION_CONFIG_READ_Min (0x0UL)       /*!< Min enumerator value of READ field.                                  */
  #define RRAMC_REGION_CONFIG_READ_Max (0x1UL)       /*!< Max enumerator value of READ field.                                  */
  #define RRAMC_REGION_CONFIG_READ_NotAllowed (0x0UL) /*!< Read access to override region [n] is not allowed                   */
  #define RRAMC_REGION_CONFIG_READ_Allowed (0x1UL)   /*!< Read access to override region [n] is allowed                        */

/* WRITE @Bit 1 : Write access */
  #define RRAMC_REGION_CONFIG_WRITE_Pos (1UL)        /*!< Position of WRITE field.                                             */
  #define RRAMC_REGION_CONFIG_WRITE_Msk (0x1UL << RRAMC_REGION_CONFIG_WRITE_Pos) /*!< Bit mask of WRITE field.                 */
  #define RRAMC_REGION_CONFIG_WRITE_Min (0x0UL)      /*!< Min enumerator value of WRITE field.                                 */
  #define RRAMC_REGION_CONFIG_WRITE_Max (0x1UL)      /*!< Max enumerator value of WRITE field.                                 */
  #define RRAMC_REGION_CONFIG_WRITE_NotAllowed (0x0UL) /*!< Write access to override region [n] is not allowed                 */
  #define RRAMC_REGION_CONFIG_WRITE_Allowed (0x1UL)  /*!< Write access to override region [n] is allowed                       */

/* EXECUTE @Bit 2 : Execute access */
  #define RRAMC_REGION_CONFIG_EXECUTE_Pos (2UL)      /*!< Position of EXECUTE field.                                           */
  #define RRAMC_REGION_CONFIG_EXECUTE_Msk (0x1UL << RRAMC_REGION_CONFIG_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.           */
  #define RRAMC_REGION_CONFIG_EXECUTE_Min (0x0UL)    /*!< Min enumerator value of EXECUTE field.                               */
  #define RRAMC_REGION_CONFIG_EXECUTE_Max (0x1UL)    /*!< Max enumerator value of EXECUTE field.                               */
  #define RRAMC_REGION_CONFIG_EXECUTE_NotAllowed (0x0UL) /*!< Execute access to override region [n] is not allowed             */
  #define RRAMC_REGION_CONFIG_EXECUTE_Allowed (0x1UL) /*!< Execute access to override region [n] is allowed                    */

/* SECURE @Bit 3 : Secure access */
  #define RRAMC_REGION_CONFIG_SECURE_Pos (3UL)       /*!< Position of SECURE field.                                            */
  #define RRAMC_REGION_CONFIG_SECURE_Msk (0x1UL << RRAMC_REGION_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field.              */
  #define RRAMC_REGION_CONFIG_SECURE_Min (0x0UL)     /*!< Min enumerator value of SECURE field.                                */
  #define RRAMC_REGION_CONFIG_SECURE_Max (0x1UL)     /*!< Max enumerator value of SECURE field.                                */
  #define RRAMC_REGION_CONFIG_SECURE_NonSecure (0x0UL) /*!< Both Secure and non-Secure access to override region [n] is allowed*/
  #define RRAMC_REGION_CONFIG_SECURE_Secure (0x1UL)  /*!< Only secure access to override region [n] is allowed                 */

/* OWNER @Bits 4..7 : Owner ID */
  #define RRAMC_REGION_CONFIG_OWNER_Pos (4UL)        /*!< Position of OWNER field.                                             */
  #define RRAMC_REGION_CONFIG_OWNER_Msk (0xFUL << RRAMC_REGION_CONFIG_OWNER_Pos) /*!< Bit mask of OWNER field.                 */
  #define RRAMC_REGION_CONFIG_OWNER_Min (0x0UL)      /*!< Min enumerator value of OWNER field.                                 */
  #define RRAMC_REGION_CONFIG_OWNER_Max (0x0UL)      /*!< Max enumerator value of OWNER field.                                 */
  #define RRAMC_REGION_CONFIG_OWNER_NotEnforced (0x0UL) /*!< Owner ID protection is not enforced                               */

/* WRITEONCE @Bit 12 : Write-once */
  #define RRAMC_REGION_CONFIG_WRITEONCE_Pos (12UL)   /*!< Position of WRITEONCE field.                                         */
  #define RRAMC_REGION_CONFIG_WRITEONCE_Msk (0x1UL << RRAMC_REGION_CONFIG_WRITEONCE_Pos) /*!< Bit mask of WRITEONCE field.     */
  #define RRAMC_REGION_CONFIG_WRITEONCE_Min (0x0UL)  /*!< Min enumerator value of WRITEONCE field.                             */
  #define RRAMC_REGION_CONFIG_WRITEONCE_Max (0x1UL)  /*!< Max enumerator value of WRITEONCE field.                             */
  #define RRAMC_REGION_CONFIG_WRITEONCE_Disabled (0x0UL) /*!< Write-once disabled                                              */
  #define RRAMC_REGION_CONFIG_WRITEONCE_Enabled (0x1UL) /*!< Write-once enabled                                                */

/* LOCK @Bit 13 : Enable lock */
  #define RRAMC_REGION_CONFIG_LOCK_Pos (13UL)        /*!< Position of LOCK field.                                              */
  #define RRAMC_REGION_CONFIG_LOCK_Msk (0x1UL << RRAMC_REGION_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field.                    */
  #define RRAMC_REGION_CONFIG_LOCK_Min (0x0UL)       /*!< Min enumerator value of LOCK field.                                  */
  #define RRAMC_REGION_CONFIG_LOCK_Max (0x1UL)       /*!< Max enumerator value of LOCK field.                                  */
  #define RRAMC_REGION_CONFIG_LOCK_Disabled (0x0UL)  /*!< Lock disabled for region [n]                                         */
  #define RRAMC_REGION_CONFIG_LOCK_Enabled (0x1UL)   /*!< Lock enabled for region [n]                                          */

/* SIZE @Bits 16..20 : Size in KBytes of region [n] */
  #define RRAMC_REGION_CONFIG_SIZE_Pos (16UL)        /*!< Position of SIZE field.                                              */
  #define RRAMC_REGION_CONFIG_SIZE_Msk (0x1FUL << RRAMC_REGION_CONFIG_SIZE_Pos) /*!< Bit mask of SIZE field.                   */


/* ====================================================== Struct RRAMC ======================================================= */
/**
  * @brief RRAM controller GLITCH detector
  */
  typedef struct {                                   /*!< RRAMC Structure                                                      */
    __OM uint32_t TASKS_WAKEUP;                      /*!< (@ 0x00000000) Wakeup the RRAM from low power mode                   */
    __IM uint32_t RESERVED;
    __OM uint32_t TASKS_COMMITWRITEBUF;              /*!< (@ 0x00000008) Commits the data stored in internal write-buffer to
                                                                         RRAM*/
    __IM uint32_t RESERVED1[29];
    __IOM uint32_t SUBSCRIBE_WAKEUP;                 /*!< (@ 0x00000080) Subscribe configuration for task WAKEUP               */
    __IM uint32_t RESERVED2;
    __IOM uint32_t SUBSCRIBE_COMMITWRITEBUF;         /*!< (@ 0x00000088) Subscribe configuration for task COMMITWRITEBUF       */
    __IM uint32_t RESERVED3[29];
    __IOM uint32_t EVENTS_WOKENUP;                   /*!< (@ 0x00000100) RRAMC is woken up from low power mode                 */
    __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000104) RRAMC is ready                                        */
    __IOM uint32_t EVENTS_READYNEXT;                 /*!< (@ 0x00000108) Ready to accept a new write operation                 */
    __IOM uint32_t EVENTS_ACCESSERROR;               /*!< (@ 0x0000010C) RRAM access error                                     */
    __IM uint32_t RESERVED4[28];
    __IOM uint32_t PUBLISH_WOKENUP;                  /*!< (@ 0x00000180) Publish configuration for event WOKENUP               */
    __IM uint32_t RESERVED5[95];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED6[60];
    __IM uint32_t READY;                             /*!< (@ 0x00000400) RRAMC ready status                                    */
    __IM uint32_t READYNEXT;                         /*!< (@ 0x00000404) Ready next flag                                       */
    __IM uint32_t ACCESSERRORADDR;                   /*!< (@ 0x00000408) Address of the first access error                     */
    __IM uint32_t RESERVED7;
    __IOM NRF_RRAMC_BUFSTATUS_Type BUFSTATUS;        /*!< (@ 0x00000410) (unspecified)                                         */
    __IM uint32_t RESERVED8;
    __IOM NRF_RRAMC_ECC_Type ECC;                    /*!< (@ 0x00000420) (unspecified)                                         */
    __IM uint32_t RESERVED9[55];
    __IOM uint32_t CONFIG;                           /*!< (@ 0x00000500) Configuration register                                */
    __IM uint32_t RESERVED10[2];
    __IOM uint32_t READYNEXTTIMEOUT;                 /*!< (@ 0x0000050C) Configuration for ready next timeout counter, in units
                                                                         of AXI clock frequency*/
    __IOM NRF_RRAMC_POWER_Type POWER;                /*!< (@ 0x00000510) (unspecified)                                         */
    __IM uint32_t RESERVED11[9];
    __IOM NRF_RRAMC_ERASE_Type ERASE;                /*!< (@ 0x00000540) (unspecified)                                         */
    __IM uint32_t RESERVED12[3];
    __IOM NRF_RRAMC_REGION_Type REGION[5];           /*!< (@ 0x00000550) RRAMC can apply access privileges to regions of the
                                                                         RRAM. Some regions are dedicated for system use and are
                                                                         not available for configuration - refer to the
                                                                         instantiation table for details.*/
  } NRF_RRAMC_Type;                                  /*!< Size = 1400 (0x578)                                                  */

/* RRAMC_TASKS_WAKEUP: Wakeup the RRAM from low power mode */
  #define RRAMC_TASKS_WAKEUP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_WAKEUP register.                              */

/* TASKS_WAKEUP @Bit 0 : Wakeup the RRAM from low power mode */
  #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Pos (0UL)  /*!< Position of TASKS_WAKEUP field.                                      */
  #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Msk (0x1UL << RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Pos) /*!< Bit mask of TASKS_WAKEUP
                                                                            field.*/
  #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Min (0x1UL) /*!< Min enumerator value of TASKS_WAKEUP field.                         */
  #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Max (0x1UL) /*!< Max enumerator value of TASKS_WAKEUP field.                         */
  #define RRAMC_TASKS_WAKEUP_TASKS_WAKEUP_Trigger (0x1UL) /*!< Trigger task                                                    */


/* RRAMC_TASKS_COMMITWRITEBUF: Commits the data stored in internal write-buffer to RRAM */
  #define RRAMC_TASKS_COMMITWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of TASKS_COMMITWRITEBUF register.              */

/* TASKS_COMMITWRITEBUF @Bit 0 : Commits the data stored in internal write-buffer to RRAM */
  #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Pos (0UL) /*!< Position of TASKS_COMMITWRITEBUF field.               */
  #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Msk (0x1UL << RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Pos)
                                                                            /*!< Bit mask of TASKS_COMMITWRITEBUF field.*/
  #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Min (0x1UL) /*!< Min enumerator value of TASKS_COMMITWRITEBUF field. */
  #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Max (0x1UL) /*!< Max enumerator value of TASKS_COMMITWRITEBUF field. */
  #define RRAMC_TASKS_COMMITWRITEBUF_TASKS_COMMITWRITEBUF_Trigger (0x1UL) /*!< Trigger task                                    */


/* RRAMC_SUBSCRIBE_WAKEUP: Subscribe configuration for task WAKEUP */
  #define RRAMC_SUBSCRIBE_WAKEUP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_WAKEUP register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that task WAKEUP will subscribe to */
  #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Msk (0xFFUL << RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define RRAMC_SUBSCRIBE_WAKEUP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RRAMC_SUBSCRIBE_WAKEUP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RRAMC_SUBSCRIBE_WAKEUP_EN_Msk (0x1UL << RRAMC_SUBSCRIBE_WAKEUP_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RRAMC_SUBSCRIBE_WAKEUP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RRAMC_SUBSCRIBE_WAKEUP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RRAMC_SUBSCRIBE_WAKEUP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define RRAMC_SUBSCRIBE_WAKEUP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* RRAMC_SUBSCRIBE_COMMITWRITEBUF: Subscribe configuration for task COMMITWRITEBUF */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_COMMITWRITEBUF register.      */

/* CHIDX @Bits 0..7 : DPPI channel that task COMMITWRITEBUF will subscribe to */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                         */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Msk (0xFFUL << RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                     */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                      */

/* EN @Bit 31 : (unspecified) */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Pos (31UL) /*!< Position of EN field.                                              */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Msk (0x1UL << RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Pos) /*!< Bit mask of EN field.    */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                 */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                 */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Disabled (0x0UL) /*!< Disable subscription                                         */
  #define RRAMC_SUBSCRIBE_COMMITWRITEBUF_EN_Enabled (0x1UL) /*!< Enable subscription                                           */


/* RRAMC_EVENTS_WOKENUP: RRAMC is woken up from low power mode */
  #define RRAMC_EVENTS_WOKENUP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WOKENUP register.                          */

/* EVENTS_WOKENUP @Bit 0 : RRAMC is woken up from low power mode */
  #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Pos (0UL) /*!< Position of EVENTS_WOKENUP field.                                 */
  #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Msk (0x1UL << RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Pos) /*!< Bit mask of
                                                                            EVENTS_WOKENUP field.*/
  #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Min (0x0UL) /*!< Min enumerator value of EVENTS_WOKENUP field.                   */
  #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Max (0x1UL) /*!< Max enumerator value of EVENTS_WOKENUP field.                   */
  #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define RRAMC_EVENTS_WOKENUP_EVENTS_WOKENUP_Generated (0x1UL) /*!< Event generated                                           */


/* RRAMC_EVENTS_READY: RRAMC is ready */
  #define RRAMC_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                              */

/* EVENTS_READY @Bit 0 : RRAMC is ready */
  #define RRAMC_EVENTS_READY_EVENTS_READY_Pos (0UL)  /*!< Position of EVENTS_READY field.                                      */
  #define RRAMC_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RRAMC_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY
                                                                            field.*/
  #define RRAMC_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                         */
  #define RRAMC_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                         */
  #define RRAMC_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define RRAMC_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                               */


/* RRAMC_EVENTS_READYNEXT: Ready to accept a new write operation */
  #define RRAMC_EVENTS_READYNEXT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READYNEXT register.                      */

/* EVENTS_READYNEXT @Bit 0 : Ready to accept a new write operation */
  #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Pos (0UL) /*!< Position of EVENTS_READYNEXT field.                           */
  #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Msk (0x1UL << RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Pos) /*!< Bit mask of
                                                                            EVENTS_READYNEXT field.*/
  #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Min (0x0UL) /*!< Min enumerator value of EVENTS_READYNEXT field.             */
  #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Max (0x1UL) /*!< Max enumerator value of EVENTS_READYNEXT field.             */
  #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define RRAMC_EVENTS_READYNEXT_EVENTS_READYNEXT_Generated (0x1UL) /*!< Event generated                                       */


/* RRAMC_EVENTS_ACCESSERROR: RRAM access error */
  #define RRAMC_EVENTS_ACCESSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACCESSERROR register.                  */

/* EVENTS_ACCESSERROR @Bit 0 : RRAM access error */
  #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Pos (0UL) /*!< Position of EVENTS_ACCESSERROR field.                     */
  #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Msk (0x1UL << RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Pos) /*!< Bit
                                                                            mask of EVENTS_ACCESSERROR field.*/
  #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACCESSERROR field.       */
  #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACCESSERROR field.       */
  #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_NotGenerated (0x0UL) /*!< Event not generated                            */
  #define RRAMC_EVENTS_ACCESSERROR_EVENTS_ACCESSERROR_Generated (0x1UL) /*!< Event generated                                   */


/* RRAMC_PUBLISH_WOKENUP: Publish configuration for event WOKENUP */
  #define RRAMC_PUBLISH_WOKENUP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_WOKENUP register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event WOKENUP will publish to */
  #define RRAMC_PUBLISH_WOKENUP_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define RRAMC_PUBLISH_WOKENUP_CHIDX_Msk (0xFFUL << RRAMC_PUBLISH_WOKENUP_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define RRAMC_PUBLISH_WOKENUP_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define RRAMC_PUBLISH_WOKENUP_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define RRAMC_PUBLISH_WOKENUP_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define RRAMC_PUBLISH_WOKENUP_EN_Msk (0x1UL << RRAMC_PUBLISH_WOKENUP_EN_Pos) /*!< Bit mask of EN field.                      */
  #define RRAMC_PUBLISH_WOKENUP_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define RRAMC_PUBLISH_WOKENUP_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define RRAMC_PUBLISH_WOKENUP_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define RRAMC_PUBLISH_WOKENUP_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* RRAMC_INTEN: Enable or disable interrupt */
  #define RRAMC_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */

/* WOKENUP @Bit 0 : Enable or disable interrupt for event WOKENUP */
  #define RRAMC_INTEN_WOKENUP_Pos (0UL)              /*!< Position of WOKENUP field.                                           */
  #define RRAMC_INTEN_WOKENUP_Msk (0x1UL << RRAMC_INTEN_WOKENUP_Pos) /*!< Bit mask of WOKENUP field.                           */
  #define RRAMC_INTEN_WOKENUP_Min (0x0UL)            /*!< Min enumerator value of WOKENUP field.                               */
  #define RRAMC_INTEN_WOKENUP_Max (0x1UL)            /*!< Max enumerator value of WOKENUP field.                               */
  #define RRAMC_INTEN_WOKENUP_Disabled (0x0UL)       /*!< Disable                                                              */
  #define RRAMC_INTEN_WOKENUP_Enabled (0x1UL)        /*!< Enable                                                               */

/* READY @Bit 1 : Enable or disable interrupt for event READY */
  #define RRAMC_INTEN_READY_Pos (1UL)                /*!< Position of READY field.                                             */
  #define RRAMC_INTEN_READY_Msk (0x1UL << RRAMC_INTEN_READY_Pos) /*!< Bit mask of READY field.                                 */
  #define RRAMC_INTEN_READY_Min (0x0UL)              /*!< Min enumerator value of READY field.                                 */
  #define RRAMC_INTEN_READY_Max (0x1UL)              /*!< Max enumerator value of READY field.                                 */
  #define RRAMC_INTEN_READY_Disabled (0x0UL)         /*!< Disable                                                              */
  #define RRAMC_INTEN_READY_Enabled (0x1UL)          /*!< Enable                                                               */

/* READYNEXT @Bit 2 : Enable or disable interrupt for event READYNEXT */
  #define RRAMC_INTEN_READYNEXT_Pos (2UL)            /*!< Position of READYNEXT field.                                         */
  #define RRAMC_INTEN_READYNEXT_Msk (0x1UL << RRAMC_INTEN_READYNEXT_Pos) /*!< Bit mask of READYNEXT field.                     */
  #define RRAMC_INTEN_READYNEXT_Min (0x0UL)          /*!< Min enumerator value of READYNEXT field.                             */
  #define RRAMC_INTEN_READYNEXT_Max (0x1UL)          /*!< Max enumerator value of READYNEXT field.                             */
  #define RRAMC_INTEN_READYNEXT_Disabled (0x0UL)     /*!< Disable                                                              */
  #define RRAMC_INTEN_READYNEXT_Enabled (0x1UL)      /*!< Enable                                                               */

/* ACCESSERROR @Bit 3 : Enable or disable interrupt for event ACCESSERROR */
  #define RRAMC_INTEN_ACCESSERROR_Pos (3UL)          /*!< Position of ACCESSERROR field.                                       */
  #define RRAMC_INTEN_ACCESSERROR_Msk (0x1UL << RRAMC_INTEN_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field.               */
  #define RRAMC_INTEN_ACCESSERROR_Min (0x0UL)        /*!< Min enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTEN_ACCESSERROR_Max (0x1UL)        /*!< Max enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTEN_ACCESSERROR_Disabled (0x0UL)   /*!< Disable                                                              */
  #define RRAMC_INTEN_ACCESSERROR_Enabled (0x1UL)    /*!< Enable                                                               */


/* RRAMC_INTENSET: Enable interrupt */
  #define RRAMC_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */

/* WOKENUP @Bit 0 : Write '1' to enable interrupt for event WOKENUP */
  #define RRAMC_INTENSET_WOKENUP_Pos (0UL)           /*!< Position of WOKENUP field.                                           */
  #define RRAMC_INTENSET_WOKENUP_Msk (0x1UL << RRAMC_INTENSET_WOKENUP_Pos) /*!< Bit mask of WOKENUP field.                     */
  #define RRAMC_INTENSET_WOKENUP_Min (0x0UL)         /*!< Min enumerator value of WOKENUP field.                               */
  #define RRAMC_INTENSET_WOKENUP_Max (0x1UL)         /*!< Max enumerator value of WOKENUP field.                               */
  #define RRAMC_INTENSET_WOKENUP_Set (0x1UL)         /*!< Enable                                                               */
  #define RRAMC_INTENSET_WOKENUP_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RRAMC_INTENSET_WOKENUP_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* READY @Bit 1 : Write '1' to enable interrupt for event READY */
  #define RRAMC_INTENSET_READY_Pos (1UL)             /*!< Position of READY field.                                             */
  #define RRAMC_INTENSET_READY_Msk (0x1UL << RRAMC_INTENSET_READY_Pos) /*!< Bit mask of READY field.                           */
  #define RRAMC_INTENSET_READY_Min (0x0UL)           /*!< Min enumerator value of READY field.                                 */
  #define RRAMC_INTENSET_READY_Max (0x1UL)           /*!< Max enumerator value of READY field.                                 */
  #define RRAMC_INTENSET_READY_Set (0x1UL)           /*!< Enable                                                               */
  #define RRAMC_INTENSET_READY_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define RRAMC_INTENSET_READY_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* READYNEXT @Bit 2 : Write '1' to enable interrupt for event READYNEXT */
  #define RRAMC_INTENSET_READYNEXT_Pos (2UL)         /*!< Position of READYNEXT field.                                         */
  #define RRAMC_INTENSET_READYNEXT_Msk (0x1UL << RRAMC_INTENSET_READYNEXT_Pos) /*!< Bit mask of READYNEXT field.               */
  #define RRAMC_INTENSET_READYNEXT_Min (0x0UL)       /*!< Min enumerator value of READYNEXT field.                             */
  #define RRAMC_INTENSET_READYNEXT_Max (0x1UL)       /*!< Max enumerator value of READYNEXT field.                             */
  #define RRAMC_INTENSET_READYNEXT_Set (0x1UL)       /*!< Enable                                                               */
  #define RRAMC_INTENSET_READYNEXT_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RRAMC_INTENSET_READYNEXT_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ACCESSERROR @Bit 3 : Write '1' to enable interrupt for event ACCESSERROR */
  #define RRAMC_INTENSET_ACCESSERROR_Pos (3UL)       /*!< Position of ACCESSERROR field.                                       */
  #define RRAMC_INTENSET_ACCESSERROR_Msk (0x1UL << RRAMC_INTENSET_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field.         */
  #define RRAMC_INTENSET_ACCESSERROR_Min (0x0UL)     /*!< Min enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTENSET_ACCESSERROR_Max (0x1UL)     /*!< Max enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTENSET_ACCESSERROR_Set (0x1UL)     /*!< Enable                                                               */
  #define RRAMC_INTENSET_ACCESSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RRAMC_INTENSET_ACCESSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* RRAMC_INTENCLR: Disable interrupt */
  #define RRAMC_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */

/* WOKENUP @Bit 0 : Write '1' to disable interrupt for event WOKENUP */
  #define RRAMC_INTENCLR_WOKENUP_Pos (0UL)           /*!< Position of WOKENUP field.                                           */
  #define RRAMC_INTENCLR_WOKENUP_Msk (0x1UL << RRAMC_INTENCLR_WOKENUP_Pos) /*!< Bit mask of WOKENUP field.                     */
  #define RRAMC_INTENCLR_WOKENUP_Min (0x0UL)         /*!< Min enumerator value of WOKENUP field.                               */
  #define RRAMC_INTENCLR_WOKENUP_Max (0x1UL)         /*!< Max enumerator value of WOKENUP field.                               */
  #define RRAMC_INTENCLR_WOKENUP_Clear (0x1UL)       /*!< Disable                                                              */
  #define RRAMC_INTENCLR_WOKENUP_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define RRAMC_INTENCLR_WOKENUP_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* READY @Bit 1 : Write '1' to disable interrupt for event READY */
  #define RRAMC_INTENCLR_READY_Pos (1UL)             /*!< Position of READY field.                                             */
  #define RRAMC_INTENCLR_READY_Msk (0x1UL << RRAMC_INTENCLR_READY_Pos) /*!< Bit mask of READY field.                           */
  #define RRAMC_INTENCLR_READY_Min (0x0UL)           /*!< Min enumerator value of READY field.                                 */
  #define RRAMC_INTENCLR_READY_Max (0x1UL)           /*!< Max enumerator value of READY field.                                 */
  #define RRAMC_INTENCLR_READY_Clear (0x1UL)         /*!< Disable                                                              */
  #define RRAMC_INTENCLR_READY_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define RRAMC_INTENCLR_READY_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* READYNEXT @Bit 2 : Write '1' to disable interrupt for event READYNEXT */
  #define RRAMC_INTENCLR_READYNEXT_Pos (2UL)         /*!< Position of READYNEXT field.                                         */
  #define RRAMC_INTENCLR_READYNEXT_Msk (0x1UL << RRAMC_INTENCLR_READYNEXT_Pos) /*!< Bit mask of READYNEXT field.               */
  #define RRAMC_INTENCLR_READYNEXT_Min (0x0UL)       /*!< Min enumerator value of READYNEXT field.                             */
  #define RRAMC_INTENCLR_READYNEXT_Max (0x1UL)       /*!< Max enumerator value of READYNEXT field.                             */
  #define RRAMC_INTENCLR_READYNEXT_Clear (0x1UL)     /*!< Disable                                                              */
  #define RRAMC_INTENCLR_READYNEXT_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define RRAMC_INTENCLR_READYNEXT_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* ACCESSERROR @Bit 3 : Write '1' to disable interrupt for event ACCESSERROR */
  #define RRAMC_INTENCLR_ACCESSERROR_Pos (3UL)       /*!< Position of ACCESSERROR field.                                       */
  #define RRAMC_INTENCLR_ACCESSERROR_Msk (0x1UL << RRAMC_INTENCLR_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field.         */
  #define RRAMC_INTENCLR_ACCESSERROR_Min (0x0UL)     /*!< Min enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTENCLR_ACCESSERROR_Max (0x1UL)     /*!< Max enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTENCLR_ACCESSERROR_Clear (0x1UL)   /*!< Disable                                                              */
  #define RRAMC_INTENCLR_ACCESSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define RRAMC_INTENCLR_ACCESSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                        */


/* RRAMC_INTPEND: Pending interrupts */
  #define RRAMC_INTPEND_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND register.                                     */

/* WOKENUP @Bit 0 : Read pending status of interrupt for event WOKENUP */
  #define RRAMC_INTPEND_WOKENUP_Pos (0UL)            /*!< Position of WOKENUP field.                                           */
  #define RRAMC_INTPEND_WOKENUP_Msk (0x1UL << RRAMC_INTPEND_WOKENUP_Pos) /*!< Bit mask of WOKENUP field.                       */
  #define RRAMC_INTPEND_WOKENUP_Min (0x0UL)          /*!< Min enumerator value of WOKENUP field.                               */
  #define RRAMC_INTPEND_WOKENUP_Max (0x1UL)          /*!< Max enumerator value of WOKENUP field.                               */
  #define RRAMC_INTPEND_WOKENUP_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
  #define RRAMC_INTPEND_WOKENUP_Pending (0x1UL)      /*!< Read: Pending                                                        */

/* READY @Bit 1 : Read pending status of interrupt for event READY */
  #define RRAMC_INTPEND_READY_Pos (1UL)              /*!< Position of READY field.                                             */
  #define RRAMC_INTPEND_READY_Msk (0x1UL << RRAMC_INTPEND_READY_Pos) /*!< Bit mask of READY field.                             */
  #define RRAMC_INTPEND_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
  #define RRAMC_INTPEND_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
  #define RRAMC_INTPEND_READY_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
  #define RRAMC_INTPEND_READY_Pending (0x1UL)        /*!< Read: Pending                                                        */

/* READYNEXT @Bit 2 : Read pending status of interrupt for event READYNEXT */
  #define RRAMC_INTPEND_READYNEXT_Pos (2UL)          /*!< Position of READYNEXT field.                                         */
  #define RRAMC_INTPEND_READYNEXT_Msk (0x1UL << RRAMC_INTPEND_READYNEXT_Pos) /*!< Bit mask of READYNEXT field.                 */
  #define RRAMC_INTPEND_READYNEXT_Min (0x0UL)        /*!< Min enumerator value of READYNEXT field.                             */
  #define RRAMC_INTPEND_READYNEXT_Max (0x1UL)        /*!< Max enumerator value of READYNEXT field.                             */
  #define RRAMC_INTPEND_READYNEXT_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define RRAMC_INTPEND_READYNEXT_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* ACCESSERROR @Bit 3 : Read pending status of interrupt for event ACCESSERROR */
  #define RRAMC_INTPEND_ACCESSERROR_Pos (3UL)        /*!< Position of ACCESSERROR field.                                       */
  #define RRAMC_INTPEND_ACCESSERROR_Msk (0x1UL << RRAMC_INTPEND_ACCESSERROR_Pos) /*!< Bit mask of ACCESSERROR field.           */
  #define RRAMC_INTPEND_ACCESSERROR_Min (0x0UL)      /*!< Min enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTPEND_ACCESSERROR_Max (0x1UL)      /*!< Max enumerator value of ACCESSERROR field.                           */
  #define RRAMC_INTPEND_ACCESSERROR_NotPending (0x0UL) /*!< Read: Not pending                                                  */
  #define RRAMC_INTPEND_ACCESSERROR_Pending (0x1UL)  /*!< Read: Pending                                                        */


/* RRAMC_READY: RRAMC ready status */
  #define RRAMC_READY_ResetValue (0x00000000UL)      /*!< Reset value of READY register.                                       */

/* READY @Bit 0 : RRAMC is ready or busy */
  #define RRAMC_READY_READY_Pos (0UL)                /*!< Position of READY field.                                             */
  #define RRAMC_READY_READY_Msk (0x1UL << RRAMC_READY_READY_Pos) /*!< Bit mask of READY field.                                 */
  #define RRAMC_READY_READY_Min (0x0UL)              /*!< Min enumerator value of READY field.                                 */
  #define RRAMC_READY_READY_Max (0x1UL)              /*!< Max enumerator value of READY field.                                 */
  #define RRAMC_READY_READY_Busy (0x0UL)             /*!< RRAMC is busy                                                        */
  #define RRAMC_READY_READY_Ready (0x1UL)            /*!< The current RRAMC operation is completed and RRAMC is ready          */


/* RRAMC_READYNEXT: Ready next flag */
  #define RRAMC_READYNEXT_ResetValue (0x00000000UL)  /*!< Reset value of READYNEXT register.                                   */

/* READYNEXT @Bit 0 : RRAMC can accept a new write operation */
  #define RRAMC_READYNEXT_READYNEXT_Pos (0UL)        /*!< Position of READYNEXT field.                                         */
  #define RRAMC_READYNEXT_READYNEXT_Msk (0x1UL << RRAMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field.             */
  #define RRAMC_READYNEXT_READYNEXT_Min (0x0UL)      /*!< Min enumerator value of READYNEXT field.                             */
  #define RRAMC_READYNEXT_READYNEXT_Max (0x1UL)      /*!< Max enumerator value of READYNEXT field.                             */
  #define RRAMC_READYNEXT_READYNEXT_Busy (0x0UL)     /*!< RRAMC cannot accept any write operation now                          */
  #define RRAMC_READYNEXT_READYNEXT_Ready (0x1UL)    /*!< RRAMC is ready to accept a new write operation                       */


/* RRAMC_ACCESSERRORADDR: Address of the first access error */
  #define RRAMC_ACCESSERRORADDR_ResetValue (0x00FFFFFFUL) /*!< Reset value of ACCESSERRORADDR register.                        */

/* ADDRESS @Bits 0..31 : Access error address */
  #define RRAMC_ACCESSERRORADDR_ADDRESS_Pos (0UL)    /*!< Position of ADDRESS field.                                           */
  #define RRAMC_ACCESSERRORADDR_ADDRESS_Msk (0xFFFFFFFFUL << RRAMC_ACCESSERRORADDR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.*/


/* RRAMC_CONFIG: Configuration register */
  #define RRAMC_CONFIG_ResetValue (0x00000000UL)     /*!< Reset value of CONFIG register.                                      */

/* WEN @Bit 0 : Write enable */
  #define RRAMC_CONFIG_WEN_Pos (0UL)                 /*!< Position of WEN field.                                               */
  #define RRAMC_CONFIG_WEN_Msk (0x1UL << RRAMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field.                                     */
  #define RRAMC_CONFIG_WEN_Min (0x0UL)               /*!< Min enumerator value of WEN field.                                   */
  #define RRAMC_CONFIG_WEN_Max (0x1UL)               /*!< Max enumerator value of WEN field.                                   */
  #define RRAMC_CONFIG_WEN_Disabled (0x0UL)          /*!< Write is disabled                                                    */
  #define RRAMC_CONFIG_WEN_Enabled (0x1UL)           /*!< Write is enabled                                                     */

/* WRITEBUFSIZE @Bits 8..13 : write-buffer size in number of 128-bit words */
  #define RRAMC_CONFIG_WRITEBUFSIZE_Pos (8UL)        /*!< Position of WRITEBUFSIZE field.                                      */
  #define RRAMC_CONFIG_WRITEBUFSIZE_Msk (0x3FUL << RRAMC_CONFIG_WRITEBUFSIZE_Pos) /*!< Bit mask of WRITEBUFSIZE field.         */
  #define RRAMC_CONFIG_WRITEBUFSIZE_Min (0x00UL)     /*!< Min value of WRITEBUFSIZE field.                                     */
  #define RRAMC_CONFIG_WRITEBUFSIZE_Max (0x20UL)     /*!< Max size of WRITEBUFSIZE field.                                      */
  #define RRAMC_CONFIG_WRITEBUFSIZE_Unbuffered (0x00UL) /*!< Disable buffering                                                 */


/* RRAMC_READYNEXTTIMEOUT: Configuration for ready next timeout counter, in units of AXI clock frequency */
  #define RRAMC_READYNEXTTIMEOUT_ResetValue (0x00000080UL) /*!< Reset value of READYNEXTTIMEOUT register.                      */

/* VALUE @Bits 0..11 : Preload value for waiting for a next write */
  #define RRAMC_READYNEXTTIMEOUT_VALUE_Pos (0UL)     /*!< Position of VALUE field.                                             */
  #define RRAMC_READYNEXTTIMEOUT_VALUE_Msk (0xFFFUL << RRAMC_READYNEXTTIMEOUT_VALUE_Pos) /*!< Bit mask of VALUE field.         */
  #define RRAMC_READYNEXTTIMEOUT_VALUE_Min (0x000UL) /*!< Min value of VALUE field.                                            */
  #define RRAMC_READYNEXTTIMEOUT_VALUE_Max (0xFFFUL) /*!< Max size of VALUE field.                                             */

/* EN @Bit 31 : Enable ready next timeout */
  #define RRAMC_READYNEXTTIMEOUT_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define RRAMC_READYNEXTTIMEOUT_EN_Msk (0x1UL << RRAMC_READYNEXTTIMEOUT_EN_Pos) /*!< Bit mask of EN field.                    */
  #define RRAMC_READYNEXTTIMEOUT_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define RRAMC_READYNEXTTIMEOUT_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define RRAMC_READYNEXTTIMEOUT_EN_Disable (0x0UL)  /*!< Disable ready next timeout                                           */
  #define RRAMC_READYNEXTTIMEOUT_EN_Enable (0x1UL)   /*!< Enable ready next timeout                                            */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           SAADC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================= Struct SAADC_EVENTS_CH ================================================== */
/**
  * @brief EVENTS_CH [SAADC_EVENTS_CH] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  LIMITH;                            /*!< (@ 0x00000000) Last results is above CH[n].LIMIT.HIGH                */
  __IOM uint32_t  LIMITL;                            /*!< (@ 0x00000004) Last results is below CH[n].LIMIT.LOW                 */
} NRF_SAADC_EVENTS_CH_Type;                          /*!< Size = 8 (0x008)                                                     */
  #define SAADC_EVENTS_CH_MaxCount (8UL)             /*!< Size of EVENTS_CH[8] array.                                          */
  #define SAADC_EVENTS_CH_MaxIndex (7UL)             /*!< Max index of EVENTS_CH[8] array.                                     */
  #define SAADC_EVENTS_CH_MinIndex (0UL)             /*!< Min index of EVENTS_CH[8] array.                                     */

/* SAADC_EVENTS_CH_LIMITH: Last results is above CH[n].LIMIT.HIGH */
  #define SAADC_EVENTS_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register.                                */

/* LIMITH @Bit 0 : Last results is above CH[n].LIMIT.HIGH */
  #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL)    /*!< Position of LIMITH field.                                            */
  #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field.        */
  #define SAADC_EVENTS_CH_LIMITH_LIMITH_Min (0x0UL)  /*!< Min enumerator value of LIMITH field.                                */
  #define SAADC_EVENTS_CH_LIMITH_LIMITH_Max (0x1UL)  /*!< Max enumerator value of LIMITH field.                                */
  #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated                                                 */


/* SAADC_EVENTS_CH_LIMITL: Last results is below CH[n].LIMIT.LOW */
  #define SAADC_EVENTS_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register.                                */

/* LIMITL @Bit 0 : Last results is below CH[n].LIMIT.LOW */
  #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL)    /*!< Position of LIMITL field.                                            */
  #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field.        */
  #define SAADC_EVENTS_CH_LIMITL_LIMITL_Min (0x0UL)  /*!< Min enumerator value of LIMITL field.                                */
  #define SAADC_EVENTS_CH_LIMITL_LIMITL_Max (0x1UL)  /*!< Max enumerator value of LIMITL field.                                */
  #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated                                                 */



/* ================================================= Struct SAADC_PUBLISH_CH ================================================= */
/**
  * @brief PUBLISH_CH [SAADC_PUBLISH_CH] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  LIMITH;                            /*!< (@ 0x00000000) Publish configuration for event CH[n].LIMITH          */
  __IOM uint32_t  LIMITL;                            /*!< (@ 0x00000004) Publish configuration for event CH[n].LIMITL          */
} NRF_SAADC_PUBLISH_CH_Type;                         /*!< Size = 8 (0x008)                                                     */
  #define SAADC_PUBLISH_CH_MaxCount (8UL)            /*!< Size of PUBLISH_CH[8] array.                                         */
  #define SAADC_PUBLISH_CH_MaxIndex (7UL)            /*!< Max index of PUBLISH_CH[8] array.                                    */
  #define SAADC_PUBLISH_CH_MinIndex (0UL)            /*!< Min index of PUBLISH_CH[8] array.                                    */

/* SAADC_PUBLISH_CH_LIMITH: Publish configuration for event CH[n].LIMITH */
  #define SAADC_PUBLISH_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register.                               */

/* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITH will publish to */
  #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field.                  */
  #define SAADC_PUBLISH_CH_LIMITH_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_CH_LIMITH_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* SAADC_PUBLISH_CH_LIMITL: Publish configuration for event CH[n].LIMITL */
  #define SAADC_PUBLISH_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register.                               */

/* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITL will publish to */
  #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field.                  */
  #define SAADC_PUBLISH_CH_LIMITL_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_CH_LIMITL_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */



/* ==================================================== Struct SAADC_TRIM ==================================================== */
/**
  * @brief TRIM [SAADC_TRIM] (unspecified)
  */
typedef struct {
  __IOM uint32_t  LINCALCOEFF[6];                    /*!< (@ 0x00000000) Linearity calibration coefficient                     */
} NRF_SAADC_TRIM_Type;                               /*!< Size = 24 (0x018)                                                    */

/* SAADC_TRIM_LINCALCOEFF: Linearity calibration coefficient */
  #define SAADC_TRIM_LINCALCOEFF_MaxCount (6UL)      /*!< Max size of LINCALCOEFF[6] array.                                    */
  #define SAADC_TRIM_LINCALCOEFF_MaxIndex (5UL)      /*!< Max index of LINCALCOEFF[6] array.                                   */
  #define SAADC_TRIM_LINCALCOEFF_MinIndex (0UL)      /*!< Min index of LINCALCOEFF[6] array.                                   */
  #define SAADC_TRIM_LINCALCOEFF_ResetValue (0x00000000UL) /*!< Reset value of LINCALCOEFF[6] register.                        */

/* VAL @Bits 0..15 : value */
  #define SAADC_TRIM_LINCALCOEFF_VAL_Pos (0UL)       /*!< Position of VAL field.                                               */
  #define SAADC_TRIM_LINCALCOEFF_VAL_Msk (0xFFFFUL << SAADC_TRIM_LINCALCOEFF_VAL_Pos) /*!< Bit mask of VAL field.              */
  #define SAADC_TRIM_LINCALCOEFF_VAL_Min (0x0000UL)  /*!< Min value of VAL field.                                              */
  #define SAADC_TRIM_LINCALCOEFF_VAL_Max (0xFFFFUL)  /*!< Max size of VAL field.                                               */



/* ===================================================== Struct SAADC_CH ===================================================== */
/**
  * @brief CH [SAADC_CH] (unspecified)
  */
typedef struct {
  __IOM uint32_t  PSELP;                             /*!< (@ 0x00000000) Input positive pin selection for CH[n]                */
  __IOM uint32_t  PSELN;                             /*!< (@ 0x00000004) Input negative pin selection for CH[n]                */
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000008) Input configuration for CH[n]                         */
  __IOM uint32_t  LIMIT;                             /*!< (@ 0x0000000C) High/low limits for event monitoring a channel        */
} NRF_SAADC_CH_Type;                                 /*!< Size = 16 (0x010)                                                    */
  #define SAADC_CH_MaxCount (8UL)                    /*!< Size of CH[8] array.                                                 */
  #define SAADC_CH_MaxIndex (7UL)                    /*!< Max index of CH[8] array.                                            */
  #define SAADC_CH_MinIndex (0UL)                    /*!< Min index of CH[8] array.                                            */

/* SAADC_CH_PSELP: Input positive pin selection for CH[n] */
  #define SAADC_CH_PSELP_ResetValue (0x00000000UL)   /*!< Reset value of PSELP register.                                       */

/* PIN @Bits 0..4 : GPIO pin selection. */
  #define SAADC_CH_PSELP_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define SAADC_CH_PSELP_PIN_Msk (0x1FUL << SAADC_CH_PSELP_PIN_Pos) /*!< Bit mask of PIN field.                                */

/* PORT @Bits 8..11 : GPIO port selection */
  #define SAADC_CH_PSELP_PORT_Pos (8UL)              /*!< Position of PORT field.                                              */
  #define SAADC_CH_PSELP_PORT_Msk (0xFUL << SAADC_CH_PSELP_PORT_Pos) /*!< Bit mask of PORT field.                              */

/* INTERNAL @Bits 12..13 : Internal input selection for analog positive input when CH[n].PSELP.CONNECT = Internal */
  #define SAADC_CH_PSELP_INTERNAL_Pos (12UL)         /*!< Position of INTERNAL field.                                          */
  #define SAADC_CH_PSELP_INTERNAL_Msk (0x3UL << SAADC_CH_PSELP_INTERNAL_Pos) /*!< Bit mask of INTERNAL field.                  */
  #define SAADC_CH_PSELP_INTERNAL_Min (0x0UL)        /*!< Min enumerator value of INTERNAL field.                              */
  #define SAADC_CH_PSELP_INTERNAL_Max (0x2UL)        /*!< Max enumerator value of INTERNAL field.                              */
  #define SAADC_CH_PSELP_INTERNAL_Avdd (0x0UL)       /*!< Connected to the internal 0.9V analog supply rail                    */
  #define SAADC_CH_PSELP_INTERNAL_Dvdd (0x1UL)       /*!< Connected to the internal 0.9V digital supply rail                   */
  #define SAADC_CH_PSELP_INTERNAL_Vdd (0x2UL)        /*!< Connected to VDD                                                     */

/* CONNECT @Bits 30..31 : Connection */
  #define SAADC_CH_PSELP_CONNECT_Pos (30UL)          /*!< Position of CONNECT field.                                           */
  #define SAADC_CH_PSELP_CONNECT_Msk (0x3UL << SAADC_CH_PSELP_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define SAADC_CH_PSELP_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define SAADC_CH_PSELP_CONNECT_Max (0x2UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define SAADC_CH_PSELP_CONNECT_NC (0x0UL)          /*!< Not connected                                                        */
  #define SAADC_CH_PSELP_CONNECT_AnalogInput (0x1UL) /*!< Select analog input                                                  */
  #define SAADC_CH_PSELP_CONNECT_Internal (0x2UL)    /*!< Selects internal inputs.                                             */


/* SAADC_CH_PSELN: Input negative pin selection for CH[n] */
  #define SAADC_CH_PSELN_ResetValue (0x00000000UL)   /*!< Reset value of PSELN register.                                       */

/* PIN @Bits 0..4 : GPIO pin selection. */
  #define SAADC_CH_PSELN_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define SAADC_CH_PSELN_PIN_Msk (0x1FUL << SAADC_CH_PSELN_PIN_Pos) /*!< Bit mask of PIN field.                                */

/* PORT @Bits 8..11 : GPIO Port selection */
  #define SAADC_CH_PSELN_PORT_Pos (8UL)              /*!< Position of PORT field.                                              */
  #define SAADC_CH_PSELN_PORT_Msk (0xFUL << SAADC_CH_PSELN_PORT_Pos) /*!< Bit mask of PORT field.                              */

/* CONNECT @Bits 30..31 : Connection */
  #define SAADC_CH_PSELN_CONNECT_Pos (30UL)          /*!< Position of CONNECT field.                                           */
  #define SAADC_CH_PSELN_CONNECT_Msk (0x3UL << SAADC_CH_PSELN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define SAADC_CH_PSELN_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define SAADC_CH_PSELN_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define SAADC_CH_PSELN_CONNECT_NC (0x0UL)          /*!< Not connected                                                        */
  #define SAADC_CH_PSELN_CONNECT_AnalogInput (0x1UL) /*!< Select analog input                                                  */


/* SAADC_CH_CONFIG: Input configuration for CH[n] */
  #define SAADC_CH_CONFIG_ResetValue (0x00020000UL)  /*!< Reset value of CONFIG register.                                      */

/* GAIN @Bits 8..10 : Gain control */
  #define SAADC_CH_CONFIG_GAIN_Pos (8UL)             /*!< Position of GAIN field.                                              */
  #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field.                            */
  #define SAADC_CH_CONFIG_GAIN_Min (0x0UL)           /*!< Min enumerator value of GAIN field.                                  */
  #define SAADC_CH_CONFIG_GAIN_Max (0x7UL)           /*!< Max enumerator value of GAIN field.                                  */
  #define SAADC_CH_CONFIG_GAIN_Gain2 (0x0UL)         /*!< 2                                                                    */
  #define SAADC_CH_CONFIG_GAIN_Gain1 (0x1UL)         /*!< 1                                                                    */
  #define SAADC_CH_CONFIG_GAIN_Gain2_3 (0x2UL)       /*!< 2/3                                                                  */
  #define SAADC_CH_CONFIG_GAIN_Gain2_4 (0x3UL)       /*!< 2/4                                                                  */
  #define SAADC_CH_CONFIG_GAIN_Gain2_5 (0x4UL)       /*!< 2/5                                                                  */
  #define SAADC_CH_CONFIG_GAIN_Gain2_6 (0x5UL)       /*!< 2/6                                                                  */
  #define SAADC_CH_CONFIG_GAIN_Gain2_7 (0x6UL)       /*!< 2/7                                                                  */
  #define SAADC_CH_CONFIG_GAIN_Gain2_8 (0x7UL)       /*!< 2/8                                                                  */

/* BURST @Bit 11 : Enable burst mode */
  #define SAADC_CH_CONFIG_BURST_Pos (11UL)           /*!< Position of BURST field.                                             */
  #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field.                         */
  #define SAADC_CH_CONFIG_BURST_Min (0x0UL)          /*!< Min enumerator value of BURST field.                                 */
  #define SAADC_CH_CONFIG_BURST_Max (0x1UL)          /*!< Max enumerator value of BURST field.                                 */
  #define SAADC_CH_CONFIG_BURST_Disabled (0x0UL)     /*!< Burst mode is disabled (normal operation)                            */
  #define SAADC_CH_CONFIG_BURST_Enabled (0x1UL)      /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as
                                                          fast as it can, and sends the average to Data RAM.*/

/* REFSEL @Bit 12 : Reference control */
  #define SAADC_CH_CONFIG_REFSEL_Pos (12UL)          /*!< Position of REFSEL field.                                            */
  #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field.                      */
  #define SAADC_CH_CONFIG_REFSEL_Min (0x0UL)         /*!< Min enumerator value of REFSEL field.                                */
  #define SAADC_CH_CONFIG_REFSEL_Max (0x1UL)         /*!< Max enumerator value of REFSEL field.                                */
  #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL)    /*!< Internal reference (0.9 V)                                           */
  #define SAADC_CH_CONFIG_REFSEL_External (0x1UL)    /*!< External reference given at PADC_EXT_REF_1V2                         */

/* MODE @Bit 15 : Enable differential mode */
  #define SAADC_CH_CONFIG_MODE_Pos (15UL)            /*!< Position of MODE field.                                              */
  #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field.                            */
  #define SAADC_CH_CONFIG_MODE_Min (0x0UL)           /*!< Min enumerator value of MODE field.                                  */
  #define SAADC_CH_CONFIG_MODE_Max (0x1UL)           /*!< Max enumerator value of MODE field.                                  */
  #define SAADC_CH_CONFIG_MODE_SE (0x0UL)            /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to
                                                          GND*/
  #define SAADC_CH_CONFIG_MODE_Diff (0x1UL)          /*!< Differential                                                         */

/* TACQ @Bits 16..24 : Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is
                       ((TACQ+1) x 125 ns) */

  #define SAADC_CH_CONFIG_TACQ_Pos (16UL)            /*!< Position of TACQ field.                                              */
  #define SAADC_CH_CONFIG_TACQ_Msk (0x1FFUL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field.                          */
  #define SAADC_CH_CONFIG_TACQ_Min (0x001UL)         /*!< Min value of TACQ field.                                             */
  #define SAADC_CH_CONFIG_TACQ_Max (0x13FUL)         /*!< Max size of TACQ field.                                              */

/* TCONV @Bits 28..30 : Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) */
  #define SAADC_CH_CONFIG_TCONV_Pos (28UL)           /*!< Position of TCONV field.                                             */
  #define SAADC_CH_CONFIG_TCONV_Msk (0x7UL << SAADC_CH_CONFIG_TCONV_Pos) /*!< Bit mask of TCONV field.                         */
  #define SAADC_CH_CONFIG_TCONV_Min (0x1UL)          /*!< Min value of TCONV field.                                            */
  #define SAADC_CH_CONFIG_TCONV_Max (0x7UL)          /*!< Max size of TCONV field.                                             */


/* SAADC_CH_LIMIT: High/low limits for event monitoring a channel */
  #define SAADC_CH_LIMIT_ResetValue (0x7FFF8000UL)   /*!< Reset value of LIMIT register.                                       */

/* LOW @Bits 0..15 : Low level limit */
  #define SAADC_CH_LIMIT_LOW_Pos (0UL)               /*!< Position of LOW field.                                               */
  #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field.                              */

/* HIGH @Bits 16..31 : High level limit */
  #define SAADC_CH_LIMIT_HIGH_Pos (16UL)             /*!< Position of HIGH field.                                              */
  #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field.                           */



/* =================================================== Struct SAADC_RESULT =================================================== */
/**
  * @brief RESULT [SAADC_RESULT] RESULT EasyDMA channel
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) Data pointer                                          */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of buffer bytes to transfer. Note that
                                                                         one sample is two bytes.*/
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of buffer bytes transferred since last START,
                                                                         updated after the END or STOPPED events*/
  __IM  uint32_t  CURRENTAMOUNT;                     /*!< (@ 0x00000010) Number of buffer bytes transferred since last START,
                                                                         continuously updated*/
} NRF_SAADC_RESULT_Type;                             /*!< Size = 20 (0x014)                                                    */

/* SAADC_RESULT_PTR: Data pointer */
  #define SAADC_RESULT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : Data pointer */
  #define SAADC_RESULT_PTR_PTR_Pos (0UL)             /*!< Position of PTR field.                                               */
  #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field.                      */


/* SAADC_RESULT_MAXCNT: Maximum number of buffer bytes to transfer. Note that one sample is two bytes. */
  #define SAADC_RESULT_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                   */

/* MAXCNT @Bits 0..14 : Maximum number of buffer bytes to transfer. Note that one sample is two bytes. */
  #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL)       /*!< Position of MAXCNT field.                                            */
  #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.           */


/* SAADC_RESULT_AMOUNT: Number of buffer bytes transferred since last START, updated after the END or STOPPED events */
  #define SAADC_RESULT_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                   */

/* AMOUNT @Bits 0..14 : Number of buffer bytes transferred since last START, updated after the END or STOPPED events. */
  #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL)       /*!< Position of AMOUNT field.                                            */
  #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.           */


/* SAADC_RESULT_CURRENTAMOUNT: Number of buffer bytes transferred since last START, continuously updated */
  #define SAADC_RESULT_CURRENTAMOUNT_ResetValue (0x00000000UL) /*!< Reset value of CURRENTAMOUNT register.                     */

/* AMOUNT @Bits 0..14 : Number of buffer bytes transferred since last START, continuously updated. */
  #define SAADC_RESULT_CURRENTAMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field.                                           */
  #define SAADC_RESULT_CURRENTAMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_CURRENTAMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT
                                                                            field.*/


/* ====================================================== Struct SAADC ======================================================= */
/**
  * @brief Analog to Digital Converter
  */
  typedef struct {                                   /*!< SAADC Structure                                                      */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in RAM    */
    __OM uint32_t TASKS_SAMPLE;                      /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels
                                                                         are sampled. This task requires that SAADC has started,
                                                                         i.e. EVENTS_STARTED was set and EVENTS_STOPPED was
                                                                         not.*/
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion    */
    __OM uint32_t TASKS_CALIBRATEOFFSET;             /*!< (@ 0x0000000C) Starts offset auto-calibration                        */
    __IM uint32_t RESERVED[28];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_SAMPLE;                 /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE               */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000088) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET;        /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET      */
    __IM uint32_t RESERVED1[28];
    __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000100) The ADC DMA has started                               */
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000104) The ADC has filled up the Result buffer               */
    __IOM uint32_t EVENTS_DONE;                      /*!< (@ 0x00000108) A conversion task has been completed. Depending on the
                                                                         mode, multiple conversions might be needed for a result
                                                                         to be transferred to RAM.*/
    __IOM uint32_t EVENTS_RESULTDONE;                /*!< (@ 0x0000010C) A result is ready to get transferred to RAM.          */
    __IOM uint32_t EVENTS_CALIBRATEDONE;             /*!< (@ 0x00000110) Calibration is complete                               */
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000114) The ADC DMA has stopped                               */
    __IOM NRF_SAADC_EVENTS_CH_Type EVENTS_CH[8];     /*!< (@ 0x00000118) Peripheral events.                                    */
    __IM uint32_t RESERVED2[10];
    __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x00000180) Publish configuration for event STARTED               */
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000184) Publish configuration for event END                   */
    __IOM uint32_t PUBLISH_DONE;                     /*!< (@ 0x00000188) Publish configuration for event DONE                  */
    __IOM uint32_t PUBLISH_RESULTDONE;               /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE            */
    __IOM uint32_t PUBLISH_CALIBRATEDONE;            /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE         */
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000194) Publish configuration for event STOPPED               */
    __IOM NRF_SAADC_PUBLISH_CH_Type PUBLISH_CH[8];   /*!< (@ 0x00000198) Publish configuration for events                      */
    __IM uint32_t RESERVED3[10];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED4[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED5[61];
    __IM uint32_t STATUS;                            /*!< (@ 0x00000400) Status                                                */
    __IM uint32_t RESERVED6[15];
    __IOM NRF_SAADC_TRIM_Type TRIM;                  /*!< (@ 0x00000440) (unspecified)                                         */
    __IM uint32_t RESERVED7[42];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable or disable ADC                                 */
    __IM uint32_t RESERVED8[3];
    __IOM NRF_SAADC_CH_Type CH[8];                   /*!< (@ 0x00000510) (unspecified)                                         */
    __IM uint32_t RESERVED9[24];
    __IOM uint32_t RESOLUTION;                       /*!< (@ 0x000005F0) Resolution configuration                              */
    __IOM uint32_t OVERSAMPLE;                       /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should not be
                                                                         combined with SCAN unless burst is enabled. The
                                                                         RESOLUTION is applied before averaging, thus for high
                                                                         OVERSAMPLE a higher RESOLUTION should be used.*/
    __IOM uint32_t SAMPLERATE;                       /*!< (@ 0x000005F8) Configures the sampling rate for either task-triggered
                                                                         or continuous operation using a local timer*/
    __IM uint32_t RESERVED10[11];
    __IOM NRF_SAADC_RESULT_Type RESULT;              /*!< (@ 0x00000628) RESULT EasyDMA channel                                */
    __IM uint32_t RESERVED11[6];
    __IOM uint32_t NOISESHAPE;                       /*!< (@ 0x00000654) SAADC provides two operational noise shaping modes (one
                                                                         that prioritizes higher bandwith, while the other
                                                                         prioritizes higher accuracy) that allow trade-offs
                                                                         between ADC resolution, power consumption, and signal
                                                                         bandwidth.*/
  } NRF_SAADC_Type;                                  /*!< Size = 1624 (0x658)                                                  */

/* SAADC_TASKS_START: Start the ADC and prepare the result buffer in RAM */
  #define SAADC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */

/* TASKS_START @Bit 0 : Start the ADC and prepare the result buffer in RAM */
  #define SAADC_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
  #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
  #define SAADC_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
  #define SAADC_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
  #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */


/* SAADC_TASKS_SAMPLE: Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has
                        started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. */

  #define SAADC_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register.                              */

/* TASKS_SAMPLE @Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled. This task requires that SAADC has
                         started, i.e. EVENTS_STARTED was set and EVENTS_STOPPED was not. */

  #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)  /*!< Position of TASKS_SAMPLE field.                                      */
  #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE
                                                                            field.*/
  #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field.                         */
  #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field.                         */
  #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task                                                    */


/* SAADC_TASKS_STOP: Stop the ADC and terminate any on-going conversion */
  #define SAADC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop the ADC and terminate any on-going conversion */
  #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
  #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
  #define SAADC_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
  #define SAADC_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
  #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */


/* SAADC_TASKS_CALIBRATEOFFSET: Starts offset auto-calibration */
  #define SAADC_TASKS_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CALIBRATEOFFSET register.            */

/* TASKS_CALIBRATEOFFSET @Bit 0 : Starts offset auto-calibration */
  #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field.            */
  #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos)
                                                                            /*!< Bit mask of TASKS_CALIBRATEOFFSET field.*/
  #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Min (0x1UL) /*!< Min enumerator value of TASKS_CALIBRATEOFFSET
                                                                            field.*/
  #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Max (0x1UL) /*!< Max enumerator value of TASKS_CALIBRATEOFFSET
                                                                            field.*/
  #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task                                  */


/* SAADC_SUBSCRIBE_START: Subscribe configuration for task START */
  #define SAADC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define SAADC_SUBSCRIBE_START_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define SAADC_SUBSCRIBE_START_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_SUBSCRIBE_START_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                      */
  #define SAADC_SUBSCRIBE_START_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define SAADC_SUBSCRIBE_START_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* SAADC_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */
  #define SAADC_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register.                      */

/* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */
  #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field.                    */
  #define SAADC_SUBSCRIBE_SAMPLE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define SAADC_SUBSCRIBE_SAMPLE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* SAADC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define SAADC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define SAADC_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define SAADC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                        */
  #define SAADC_SUBSCRIBE_STOP_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define SAADC_SUBSCRIBE_STOP_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* SAADC_SUBSCRIBE_CALIBRATEOFFSET: Subscribe configuration for task CALIBRATEOFFSET */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CALIBRATEOFFSET register.    */

/* CHIDX @Bits 0..7 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                        */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                    */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                     */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field.                                             */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field.  */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription                                        */
  #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription                                          */


/* SAADC_EVENTS_STARTED: The ADC DMA has started */
  #define SAADC_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                          */

/* EVENTS_STARTED @Bit 0 : The ADC DMA has started */
  #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                 */
  #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
                                                                            EVENTS_STARTED field.*/
  #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                   */
  #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                   */
  #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                           */


/* SAADC_EVENTS_END: The ADC has filled up the Result buffer */
  #define SAADC_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : The ADC has filled up the Result buffer */
  #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL)      /*!< Position of EVENTS_END field.                                        */
  #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.        */
  #define SAADC_EVENTS_END_EVENTS_END_Min (0x0UL)    /*!< Min enumerator value of EVENTS_END field.                            */
  #define SAADC_EVENTS_END_EVENTS_END_Max (0x1UL)    /*!< Max enumerator value of EVENTS_END field.                            */
  #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                            */
  #define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                   */


/* SAADC_EVENTS_DONE: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a
                       result to be transferred to RAM. */

  #define SAADC_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register.                                */

/* EVENTS_DONE @Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a
                        result to be transferred to RAM. */

  #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL)    /*!< Position of EVENTS_DONE field.                                       */
  #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field.   */
  #define SAADC_EVENTS_DONE_EVENTS_DONE_Min (0x0UL)  /*!< Min enumerator value of EVENTS_DONE field.                           */
  #define SAADC_EVENTS_DONE_EVENTS_DONE_Max (0x1UL)  /*!< Max enumerator value of EVENTS_DONE field.                           */
  #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated                                                 */


/* SAADC_EVENTS_RESULTDONE: A result is ready to get transferred to RAM. */
  #define SAADC_EVENTS_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESULTDONE register.                    */

/* EVENTS_RESULTDONE @Bit 0 : A result is ready to get transferred to RAM. */
  #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field.                        */
  #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask
                                                                            of EVENTS_RESULTDONE field.*/
  #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESULTDONE field.          */
  #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESULTDONE field.          */
  #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated                                     */


/* SAADC_EVENTS_CALIBRATEDONE: Calibration is complete */
  #define SAADC_EVENTS_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CALIBRATEDONE register.              */

/* EVENTS_CALIBRATEDONE @Bit 0 : Calibration is complete */
  #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field.               */
  #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos)
                                                                            /*!< Bit mask of EVENTS_CALIBRATEDONE field.*/
  #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CALIBRATEDONE field. */
  #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CALIBRATEDONE field. */
  #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated                        */
  #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated                               */


/* SAADC_EVENTS_STOPPED: The ADC DMA has stopped */
  #define SAADC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                          */

/* EVENTS_STOPPED @Bit 0 : The ADC DMA has stopped */
  #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                 */
  #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
                                                                            EVENTS_STOPPED field.*/
  #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                   */
  #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                   */
  #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                           */


/* SAADC_PUBLISH_STARTED: Publish configuration for event STARTED */
  #define SAADC_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
  #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define SAADC_PUBLISH_STARTED_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define SAADC_PUBLISH_STARTED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_STARTED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                      */
  #define SAADC_PUBLISH_STARTED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_STARTED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* SAADC_PUBLISH_END: Publish configuration for event END */
  #define SAADC_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define SAADC_PUBLISH_END_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define SAADC_PUBLISH_END_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define SAADC_PUBLISH_END_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_END_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                              */
  #define SAADC_PUBLISH_END_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_END_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_END_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define SAADC_PUBLISH_END_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* SAADC_PUBLISH_DONE: Publish configuration for event DONE */
  #define SAADC_PUBLISH_DONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DONE register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event DONE will publish to */
  #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define SAADC_PUBLISH_DONE_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define SAADC_PUBLISH_DONE_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_DONE_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field.                            */
  #define SAADC_PUBLISH_DONE_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_DONE_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* SAADC_PUBLISH_RESULTDONE: Publish configuration for event RESULTDONE */
  #define SAADC_PUBLISH_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESULTDONE register.                  */

/* CHIDX @Bits 0..7 : DPPI channel that event RESULTDONE will publish to */
  #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define SAADC_PUBLISH_RESULTDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define SAADC_PUBLISH_RESULTDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field.                */
  #define SAADC_PUBLISH_RESULTDONE_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_RESULTDONE_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* SAADC_PUBLISH_CALIBRATEDONE: Publish configuration for event CALIBRATEDONE */
  #define SAADC_PUBLISH_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CALIBRATEDONE register.            */

/* CHIDX @Bits 0..7 : DPPI channel that event CALIBRATEDONE will publish to */
  #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
  #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
  #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                        */
  #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL)  /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field.          */
  #define SAADC_PUBLISH_CALIBRATEDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_CALIBRATEDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing                                              */
  #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing                                                */


/* SAADC_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define SAADC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define SAADC_PUBLISH_STOPPED_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define SAADC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                      */
  #define SAADC_PUBLISH_STOPPED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_STOPPED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* SAADC_SHORTS: Shortcuts between local events and tasks */
  #define SAADC_SHORTS_ResetValue (0x00000000UL)     /*!< Reset value of SHORTS register.                                      */

/* DONE_SAMPLE @Bit 0 : Shortcut between event DONE and task SAMPLE */
  #define SAADC_SHORTS_DONE_SAMPLE_Pos (0UL)         /*!< Position of DONE_SAMPLE field.                                       */
  #define SAADC_SHORTS_DONE_SAMPLE_Msk (0x1UL << SAADC_SHORTS_DONE_SAMPLE_Pos) /*!< Bit mask of DONE_SAMPLE field.             */
  #define SAADC_SHORTS_DONE_SAMPLE_Min (0x0UL)       /*!< Min enumerator value of DONE_SAMPLE field.                           */
  #define SAADC_SHORTS_DONE_SAMPLE_Max (0x1UL)       /*!< Max enumerator value of DONE_SAMPLE field.                           */
  #define SAADC_SHORTS_DONE_SAMPLE_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
  #define SAADC_SHORTS_DONE_SAMPLE_Enabled (0x1UL)   /*!< Enable shortcut                                                      */

/* END_START @Bit 1 : Shortcut between event END and task START */
  #define SAADC_SHORTS_END_START_Pos (1UL)           /*!< Position of END_START field.                                         */
  #define SAADC_SHORTS_END_START_Msk (0x1UL << SAADC_SHORTS_END_START_Pos) /*!< Bit mask of END_START field.                   */
  #define SAADC_SHORTS_END_START_Min (0x0UL)         /*!< Min enumerator value of END_START field.                             */
  #define SAADC_SHORTS_END_START_Max (0x1UL)         /*!< Max enumerator value of END_START field.                             */
  #define SAADC_SHORTS_END_START_Disabled (0x0UL)    /*!< Disable shortcut                                                     */
  #define SAADC_SHORTS_END_START_Enabled (0x1UL)     /*!< Enable shortcut                                                      */


/* SAADC_INTEN: Enable or disable interrupt */
  #define SAADC_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */

/* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */
  #define SAADC_INTEN_STARTED_Pos (0UL)              /*!< Position of STARTED field.                                           */
  #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field.                           */
  #define SAADC_INTEN_STARTED_Min (0x0UL)            /*!< Min enumerator value of STARTED field.                               */
  #define SAADC_INTEN_STARTED_Max (0x1UL)            /*!< Max enumerator value of STARTED field.                               */
  #define SAADC_INTEN_STARTED_Disabled (0x0UL)       /*!< Disable                                                              */
  #define SAADC_INTEN_STARTED_Enabled (0x1UL)        /*!< Enable                                                               */

/* END @Bit 1 : Enable or disable interrupt for event END */
  #define SAADC_INTEN_END_Pos (1UL)                  /*!< Position of END field.                                               */
  #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field.                                       */
  #define SAADC_INTEN_END_Min (0x0UL)                /*!< Min enumerator value of END field.                                   */
  #define SAADC_INTEN_END_Max (0x1UL)                /*!< Max enumerator value of END field.                                   */
  #define SAADC_INTEN_END_Disabled (0x0UL)           /*!< Disable                                                              */
  #define SAADC_INTEN_END_Enabled (0x1UL)            /*!< Enable                                                               */

/* DONE @Bit 2 : Enable or disable interrupt for event DONE */
  #define SAADC_INTEN_DONE_Pos (2UL)                 /*!< Position of DONE field.                                              */
  #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field.                                    */
  #define SAADC_INTEN_DONE_Min (0x0UL)               /*!< Min enumerator value of DONE field.                                  */
  #define SAADC_INTEN_DONE_Max (0x1UL)               /*!< Max enumerator value of DONE field.                                  */
  #define SAADC_INTEN_DONE_Disabled (0x0UL)          /*!< Disable                                                              */
  #define SAADC_INTEN_DONE_Enabled (0x1UL)           /*!< Enable                                                               */

/* RESULTDONE @Bit 3 : Enable or disable interrupt for event RESULTDONE */
  #define SAADC_INTEN_RESULTDONE_Pos (3UL)           /*!< Position of RESULTDONE field.                                        */
  #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field.                  */
  #define SAADC_INTEN_RESULTDONE_Min (0x0UL)         /*!< Min enumerator value of RESULTDONE field.                            */
  #define SAADC_INTEN_RESULTDONE_Max (0x1UL)         /*!< Max enumerator value of RESULTDONE field.                            */
  #define SAADC_INTEN_RESULTDONE_Disabled (0x0UL)    /*!< Disable                                                              */
  #define SAADC_INTEN_RESULTDONE_Enabled (0x1UL)     /*!< Enable                                                               */

/* CALIBRATEDONE @Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
  #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL)        /*!< Position of CALIBRATEDONE field.                                     */
  #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field.         */
  #define SAADC_INTEN_CALIBRATEDONE_Min (0x0UL)      /*!< Min enumerator value of CALIBRATEDONE field.                         */
  #define SAADC_INTEN_CALIBRATEDONE_Max (0x1UL)      /*!< Max enumerator value of CALIBRATEDONE field.                         */
  #define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable                                                              */
  #define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL)  /*!< Enable                                                               */

/* STOPPED @Bit 5 : Enable or disable interrupt for event STOPPED */
  #define SAADC_INTEN_STOPPED_Pos (5UL)              /*!< Position of STOPPED field.                                           */
  #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                           */
  #define SAADC_INTEN_STOPPED_Min (0x0UL)            /*!< Min enumerator value of STOPPED field.                               */
  #define SAADC_INTEN_STOPPED_Max (0x1UL)            /*!< Max enumerator value of STOPPED field.                               */
  #define SAADC_INTEN_STOPPED_Disabled (0x0UL)       /*!< Disable                                                              */
  #define SAADC_INTEN_STOPPED_Enabled (0x1UL)        /*!< Enable                                                               */

/* CH0LIMITH @Bit 6 : Enable or disable interrupt for event CH0LIMITH */
  #define SAADC_INTEN_CH0LIMITH_Pos (6UL)            /*!< Position of CH0LIMITH field.                                         */
  #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field.                     */
  #define SAADC_INTEN_CH0LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH0LIMITH field.                             */
  #define SAADC_INTEN_CH0LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH0LIMITH field.                             */
  #define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH0LIMITL @Bit 7 : Enable or disable interrupt for event CH0LIMITL */
  #define SAADC_INTEN_CH0LIMITL_Pos (7UL)            /*!< Position of CH0LIMITL field.                                         */
  #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field.                     */
  #define SAADC_INTEN_CH0LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH0LIMITL field.                             */
  #define SAADC_INTEN_CH0LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH0LIMITL field.                             */
  #define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH1LIMITH @Bit 8 : Enable or disable interrupt for event CH1LIMITH */
  #define SAADC_INTEN_CH1LIMITH_Pos (8UL)            /*!< Position of CH1LIMITH field.                                         */
  #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field.                     */
  #define SAADC_INTEN_CH1LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH1LIMITH field.                             */
  #define SAADC_INTEN_CH1LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH1LIMITH field.                             */
  #define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH1LIMITL @Bit 9 : Enable or disable interrupt for event CH1LIMITL */
  #define SAADC_INTEN_CH1LIMITL_Pos (9UL)            /*!< Position of CH1LIMITL field.                                         */
  #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field.                     */
  #define SAADC_INTEN_CH1LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH1LIMITL field.                             */
  #define SAADC_INTEN_CH1LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH1LIMITL field.                             */
  #define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH2LIMITH @Bit 10 : Enable or disable interrupt for event CH2LIMITH */
  #define SAADC_INTEN_CH2LIMITH_Pos (10UL)           /*!< Position of CH2LIMITH field.                                         */
  #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field.                     */
  #define SAADC_INTEN_CH2LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH2LIMITH field.                             */
  #define SAADC_INTEN_CH2LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH2LIMITH field.                             */
  #define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH2LIMITL @Bit 11 : Enable or disable interrupt for event CH2LIMITL */
  #define SAADC_INTEN_CH2LIMITL_Pos (11UL)           /*!< Position of CH2LIMITL field.                                         */
  #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field.                     */
  #define SAADC_INTEN_CH2LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH2LIMITL field.                             */
  #define SAADC_INTEN_CH2LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH2LIMITL field.                             */
  #define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH3LIMITH @Bit 12 : Enable or disable interrupt for event CH3LIMITH */
  #define SAADC_INTEN_CH3LIMITH_Pos (12UL)           /*!< Position of CH3LIMITH field.                                         */
  #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field.                     */
  #define SAADC_INTEN_CH3LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH3LIMITH field.                             */
  #define SAADC_INTEN_CH3LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH3LIMITH field.                             */
  #define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH3LIMITL @Bit 13 : Enable or disable interrupt for event CH3LIMITL */
  #define SAADC_INTEN_CH3LIMITL_Pos (13UL)           /*!< Position of CH3LIMITL field.                                         */
  #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field.                     */
  #define SAADC_INTEN_CH3LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH3LIMITL field.                             */
  #define SAADC_INTEN_CH3LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH3LIMITL field.                             */
  #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH4LIMITH @Bit 14 : Enable or disable interrupt for event CH4LIMITH */
  #define SAADC_INTEN_CH4LIMITH_Pos (14UL)           /*!< Position of CH4LIMITH field.                                         */
  #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field.                     */
  #define SAADC_INTEN_CH4LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH4LIMITH field.                             */
  #define SAADC_INTEN_CH4LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH4LIMITH field.                             */
  #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH4LIMITL @Bit 15 : Enable or disable interrupt for event CH4LIMITL */
  #define SAADC_INTEN_CH4LIMITL_Pos (15UL)           /*!< Position of CH4LIMITL field.                                         */
  #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field.                     */
  #define SAADC_INTEN_CH4LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH4LIMITL field.                             */
  #define SAADC_INTEN_CH4LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH4LIMITL field.                             */
  #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH5LIMITH @Bit 16 : Enable or disable interrupt for event CH5LIMITH */
  #define SAADC_INTEN_CH5LIMITH_Pos (16UL)           /*!< Position of CH5LIMITH field.                                         */
  #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field.                     */
  #define SAADC_INTEN_CH5LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH5LIMITH field.                             */
  #define SAADC_INTEN_CH5LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH5LIMITH field.                             */
  #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH5LIMITL @Bit 17 : Enable or disable interrupt for event CH5LIMITL */
  #define SAADC_INTEN_CH5LIMITL_Pos (17UL)           /*!< Position of CH5LIMITL field.                                         */
  #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field.                     */
  #define SAADC_INTEN_CH5LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH5LIMITL field.                             */
  #define SAADC_INTEN_CH5LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH5LIMITL field.                             */
  #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH6LIMITH @Bit 18 : Enable or disable interrupt for event CH6LIMITH */
  #define SAADC_INTEN_CH6LIMITH_Pos (18UL)           /*!< Position of CH6LIMITH field.                                         */
  #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field.                     */
  #define SAADC_INTEN_CH6LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH6LIMITH field.                             */
  #define SAADC_INTEN_CH6LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH6LIMITH field.                             */
  #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH6LIMITL @Bit 19 : Enable or disable interrupt for event CH6LIMITL */
  #define SAADC_INTEN_CH6LIMITL_Pos (19UL)           /*!< Position of CH6LIMITL field.                                         */
  #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field.                     */
  #define SAADC_INTEN_CH6LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH6LIMITL field.                             */
  #define SAADC_INTEN_CH6LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH6LIMITL field.                             */
  #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH7LIMITH @Bit 20 : Enable or disable interrupt for event CH7LIMITH */
  #define SAADC_INTEN_CH7LIMITH_Pos (20UL)           /*!< Position of CH7LIMITH field.                                         */
  #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field.                     */
  #define SAADC_INTEN_CH7LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH7LIMITH field.                             */
  #define SAADC_INTEN_CH7LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH7LIMITH field.                             */
  #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */

/* CH7LIMITL @Bit 21 : Enable or disable interrupt for event CH7LIMITL */
  #define SAADC_INTEN_CH7LIMITL_Pos (21UL)           /*!< Position of CH7LIMITL field.                                         */
  #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field.                     */
  #define SAADC_INTEN_CH7LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH7LIMITL field.                             */
  #define SAADC_INTEN_CH7LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH7LIMITL field.                             */
  #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
  #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */


/* SAADC_INTENSET: Enable interrupt */
  #define SAADC_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */

/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */
  #define SAADC_INTENSET_STARTED_Pos (0UL)           /*!< Position of STARTED field.                                           */
  #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                     */
  #define SAADC_INTENSET_STARTED_Min (0x0UL)         /*!< Min enumerator value of STARTED field.                               */
  #define SAADC_INTENSET_STARTED_Max (0x1UL)         /*!< Max enumerator value of STARTED field.                               */
  #define SAADC_INTENSET_STARTED_Set (0x1UL)         /*!< Enable                                                               */
  #define SAADC_INTENSET_STARTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_STARTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* END @Bit 1 : Write '1' to enable interrupt for event END */
  #define SAADC_INTENSET_END_Pos (1UL)               /*!< Position of END field.                                               */
  #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field.                                 */
  #define SAADC_INTENSET_END_Min (0x0UL)             /*!< Min enumerator value of END field.                                   */
  #define SAADC_INTENSET_END_Max (0x1UL)             /*!< Max enumerator value of END field.                                   */
  #define SAADC_INTENSET_END_Set (0x1UL)             /*!< Enable                                                               */
  #define SAADC_INTENSET_END_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_END_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* DONE @Bit 2 : Write '1' to enable interrupt for event DONE */
  #define SAADC_INTENSET_DONE_Pos (2UL)              /*!< Position of DONE field.                                              */
  #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field.                              */
  #define SAADC_INTENSET_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
  #define SAADC_INTENSET_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
  #define SAADC_INTENSET_DONE_Set (0x1UL)            /*!< Enable                                                               */
  #define SAADC_INTENSET_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* RESULTDONE @Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
  #define SAADC_INTENSET_RESULTDONE_Pos (3UL)        /*!< Position of RESULTDONE field.                                        */
  #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field.            */
  #define SAADC_INTENSET_RESULTDONE_Min (0x0UL)      /*!< Min enumerator value of RESULTDONE field.                            */
  #define SAADC_INTENSET_RESULTDONE_Max (0x1UL)      /*!< Max enumerator value of RESULTDONE field.                            */
  #define SAADC_INTENSET_RESULTDONE_Set (0x1UL)      /*!< Enable                                                               */
  #define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* CALIBRATEDONE @Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
  #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL)     /*!< Position of CALIBRATEDONE field.                                     */
  #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field.   */
  #define SAADC_INTENSET_CALIBRATEDONE_Min (0x0UL)   /*!< Min enumerator value of CALIBRATEDONE field.                         */
  #define SAADC_INTENSET_CALIBRATEDONE_Max (0x1UL)   /*!< Max enumerator value of CALIBRATEDONE field.                         */
  #define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL)   /*!< Enable                                                               */
  #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* STOPPED @Bit 5 : Write '1' to enable interrupt for event STOPPED */
  #define SAADC_INTENSET_STOPPED_Pos (5UL)           /*!< Position of STOPPED field.                                           */
  #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                     */
  #define SAADC_INTENSET_STOPPED_Min (0x0UL)         /*!< Min enumerator value of STOPPED field.                               */
  #define SAADC_INTENSET_STOPPED_Max (0x1UL)         /*!< Max enumerator value of STOPPED field.                               */
  #define SAADC_INTENSET_STOPPED_Set (0x1UL)         /*!< Enable                                                               */
  #define SAADC_INTENSET_STOPPED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_STOPPED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* CH0LIMITH @Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
  #define SAADC_INTENSET_CH0LIMITH_Pos (6UL)         /*!< Position of CH0LIMITH field.                                         */
  #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field.               */
  #define SAADC_INTENSET_CH0LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITH field.                             */
  #define SAADC_INTENSET_CH0LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITH field.                             */
  #define SAADC_INTENSET_CH0LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH0LIMITL @Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
  #define SAADC_INTENSET_CH0LIMITL_Pos (7UL)         /*!< Position of CH0LIMITL field.                                         */
  #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field.               */
  #define SAADC_INTENSET_CH0LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITL field.                             */
  #define SAADC_INTENSET_CH0LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITL field.                             */
  #define SAADC_INTENSET_CH0LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH1LIMITH @Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
  #define SAADC_INTENSET_CH1LIMITH_Pos (8UL)         /*!< Position of CH1LIMITH field.                                         */
  #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field.               */
  #define SAADC_INTENSET_CH1LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITH field.                             */
  #define SAADC_INTENSET_CH1LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITH field.                             */
  #define SAADC_INTENSET_CH1LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH1LIMITL @Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
  #define SAADC_INTENSET_CH1LIMITL_Pos (9UL)         /*!< Position of CH1LIMITL field.                                         */
  #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field.               */
  #define SAADC_INTENSET_CH1LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITL field.                             */
  #define SAADC_INTENSET_CH1LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITL field.                             */
  #define SAADC_INTENSET_CH1LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH2LIMITH @Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
  #define SAADC_INTENSET_CH2LIMITH_Pos (10UL)        /*!< Position of CH2LIMITH field.                                         */
  #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field.               */
  #define SAADC_INTENSET_CH2LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITH field.                             */
  #define SAADC_INTENSET_CH2LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITH field.                             */
  #define SAADC_INTENSET_CH2LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH2LIMITL @Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
  #define SAADC_INTENSET_CH2LIMITL_Pos (11UL)        /*!< Position of CH2LIMITL field.                                         */
  #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field.               */
  #define SAADC_INTENSET_CH2LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITL field.                             */
  #define SAADC_INTENSET_CH2LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITL field.                             */
  #define SAADC_INTENSET_CH2LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH3LIMITH @Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
  #define SAADC_INTENSET_CH3LIMITH_Pos (12UL)        /*!< Position of CH3LIMITH field.                                         */
  #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field.               */
  #define SAADC_INTENSET_CH3LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITH field.                             */
  #define SAADC_INTENSET_CH3LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITH field.                             */
  #define SAADC_INTENSET_CH3LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH3LIMITL @Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
  #define SAADC_INTENSET_CH3LIMITL_Pos (13UL)        /*!< Position of CH3LIMITL field.                                         */
  #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field.               */
  #define SAADC_INTENSET_CH3LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITL field.                             */
  #define SAADC_INTENSET_CH3LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITL field.                             */
  #define SAADC_INTENSET_CH3LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH4LIMITH @Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
  #define SAADC_INTENSET_CH4LIMITH_Pos (14UL)        /*!< Position of CH4LIMITH field.                                         */
  #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field.               */
  #define SAADC_INTENSET_CH4LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITH field.                             */
  #define SAADC_INTENSET_CH4LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITH field.                             */
  #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH4LIMITL @Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
  #define SAADC_INTENSET_CH4LIMITL_Pos (15UL)        /*!< Position of CH4LIMITL field.                                         */
  #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field.               */
  #define SAADC_INTENSET_CH4LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITL field.                             */
  #define SAADC_INTENSET_CH4LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITL field.                             */
  #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH5LIMITH @Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
  #define SAADC_INTENSET_CH5LIMITH_Pos (16UL)        /*!< Position of CH5LIMITH field.                                         */
  #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field.               */
  #define SAADC_INTENSET_CH5LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITH field.                             */
  #define SAADC_INTENSET_CH5LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITH field.                             */
  #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH5LIMITL @Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
  #define SAADC_INTENSET_CH5LIMITL_Pos (17UL)        /*!< Position of CH5LIMITL field.                                         */
  #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field.               */
  #define SAADC_INTENSET_CH5LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITL field.                             */
  #define SAADC_INTENSET_CH5LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITL field.                             */
  #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH6LIMITH @Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
  #define SAADC_INTENSET_CH6LIMITH_Pos (18UL)        /*!< Position of CH6LIMITH field.                                         */
  #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field.               */
  #define SAADC_INTENSET_CH6LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITH field.                             */
  #define SAADC_INTENSET_CH6LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITH field.                             */
  #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH6LIMITL @Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
  #define SAADC_INTENSET_CH6LIMITL_Pos (19UL)        /*!< Position of CH6LIMITL field.                                         */
  #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field.               */
  #define SAADC_INTENSET_CH6LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITL field.                             */
  #define SAADC_INTENSET_CH6LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITL field.                             */
  #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH7LIMITH @Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
  #define SAADC_INTENSET_CH7LIMITH_Pos (20UL)        /*!< Position of CH7LIMITH field.                                         */
  #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field.               */
  #define SAADC_INTENSET_CH7LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITH field.                             */
  #define SAADC_INTENSET_CH7LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITH field.                             */
  #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH7LIMITL @Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
  #define SAADC_INTENSET_CH7LIMITL_Pos (21UL)        /*!< Position of CH7LIMITL field.                                         */
  #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field.               */
  #define SAADC_INTENSET_CH7LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITL field.                             */
  #define SAADC_INTENSET_CH7LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITL field.                             */
  #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL)       /*!< Enable                                                               */
  #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* SAADC_INTENCLR: Disable interrupt */
  #define SAADC_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */

/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */
  #define SAADC_INTENCLR_STARTED_Pos (0UL)           /*!< Position of STARTED field.                                           */
  #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                     */
  #define SAADC_INTENCLR_STARTED_Min (0x0UL)         /*!< Min enumerator value of STARTED field.                               */
  #define SAADC_INTENCLR_STARTED_Max (0x1UL)         /*!< Max enumerator value of STARTED field.                               */
  #define SAADC_INTENCLR_STARTED_Clear (0x1UL)       /*!< Disable                                                              */
  #define SAADC_INTENCLR_STARTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_STARTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* END @Bit 1 : Write '1' to disable interrupt for event END */
  #define SAADC_INTENCLR_END_Pos (1UL)               /*!< Position of END field.                                               */
  #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field.                                 */
  #define SAADC_INTENCLR_END_Min (0x0UL)             /*!< Min enumerator value of END field.                                   */
  #define SAADC_INTENCLR_END_Max (0x1UL)             /*!< Max enumerator value of END field.                                   */
  #define SAADC_INTENCLR_END_Clear (0x1UL)           /*!< Disable                                                              */
  #define SAADC_INTENCLR_END_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_END_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* DONE @Bit 2 : Write '1' to disable interrupt for event DONE */
  #define SAADC_INTENCLR_DONE_Pos (2UL)              /*!< Position of DONE field.                                              */
  #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field.                              */
  #define SAADC_INTENCLR_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
  #define SAADC_INTENCLR_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
  #define SAADC_INTENCLR_DONE_Clear (0x1UL)          /*!< Disable                                                              */
  #define SAADC_INTENCLR_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* RESULTDONE @Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
  #define SAADC_INTENCLR_RESULTDONE_Pos (3UL)        /*!< Position of RESULTDONE field.                                        */
  #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field.            */
  #define SAADC_INTENCLR_RESULTDONE_Min (0x0UL)      /*!< Min enumerator value of RESULTDONE field.                            */
  #define SAADC_INTENCLR_RESULTDONE_Max (0x1UL)      /*!< Max enumerator value of RESULTDONE field.                            */
  #define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL)    /*!< Disable                                                              */
  #define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* CALIBRATEDONE @Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
  #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL)     /*!< Position of CALIBRATEDONE field.                                     */
  #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field.   */
  #define SAADC_INTENCLR_CALIBRATEDONE_Min (0x0UL)   /*!< Min enumerator value of CALIBRATEDONE field.                         */
  #define SAADC_INTENCLR_CALIBRATEDONE_Max (0x1UL)   /*!< Max enumerator value of CALIBRATEDONE field.                         */
  #define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable                                                              */
  #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* STOPPED @Bit 5 : Write '1' to disable interrupt for event STOPPED */
  #define SAADC_INTENCLR_STOPPED_Pos (5UL)           /*!< Position of STOPPED field.                                           */
  #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                     */
  #define SAADC_INTENCLR_STOPPED_Min (0x0UL)         /*!< Min enumerator value of STOPPED field.                               */
  #define SAADC_INTENCLR_STOPPED_Max (0x1UL)         /*!< Max enumerator value of STOPPED field.                               */
  #define SAADC_INTENCLR_STOPPED_Clear (0x1UL)       /*!< Disable                                                              */
  #define SAADC_INTENCLR_STOPPED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_STOPPED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* CH0LIMITH @Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
  #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL)         /*!< Position of CH0LIMITH field.                                         */
  #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field.               */
  #define SAADC_INTENCLR_CH0LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITH field.                             */
  #define SAADC_INTENCLR_CH0LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITH field.                             */
  #define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH0LIMITL @Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
  #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL)         /*!< Position of CH0LIMITL field.                                         */
  #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field.               */
  #define SAADC_INTENCLR_CH0LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITL field.                             */
  #define SAADC_INTENCLR_CH0LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITL field.                             */
  #define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH1LIMITH @Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
  #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL)         /*!< Position of CH1LIMITH field.                                         */
  #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field.               */
  #define SAADC_INTENCLR_CH1LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITH field.                             */
  #define SAADC_INTENCLR_CH1LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITH field.                             */
  #define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH1LIMITL @Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
  #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL)         /*!< Position of CH1LIMITL field.                                         */
  #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field.               */
  #define SAADC_INTENCLR_CH1LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITL field.                             */
  #define SAADC_INTENCLR_CH1LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITL field.                             */
  #define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH2LIMITH @Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
  #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL)        /*!< Position of CH2LIMITH field.                                         */
  #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field.               */
  #define SAADC_INTENCLR_CH2LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITH field.                             */
  #define SAADC_INTENCLR_CH2LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITH field.                             */
  #define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH2LIMITL @Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
  #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL)        /*!< Position of CH2LIMITL field.                                         */
  #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field.               */
  #define SAADC_INTENCLR_CH2LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITL field.                             */
  #define SAADC_INTENCLR_CH2LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITL field.                             */
  #define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH3LIMITH @Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
  #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL)        /*!< Position of CH3LIMITH field.                                         */
  #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field.               */
  #define SAADC_INTENCLR_CH3LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITH field.                             */
  #define SAADC_INTENCLR_CH3LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITH field.                             */
  #define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH3LIMITL @Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
  #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL)        /*!< Position of CH3LIMITL field.                                         */
  #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field.               */
  #define SAADC_INTENCLR_CH3LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITL field.                             */
  #define SAADC_INTENCLR_CH3LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITL field.                             */
  #define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH4LIMITH @Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
  #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL)        /*!< Position of CH4LIMITH field.                                         */
  #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field.               */
  #define SAADC_INTENCLR_CH4LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITH field.                             */
  #define SAADC_INTENCLR_CH4LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITH field.                             */
  #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH4LIMITL @Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
  #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL)        /*!< Position of CH4LIMITL field.                                         */
  #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field.               */
  #define SAADC_INTENCLR_CH4LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITL field.                             */
  #define SAADC_INTENCLR_CH4LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITL field.                             */
  #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH5LIMITH @Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
  #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL)        /*!< Position of CH5LIMITH field.                                         */
  #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field.               */
  #define SAADC_INTENCLR_CH5LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITH field.                             */
  #define SAADC_INTENCLR_CH5LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITH field.                             */
  #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH5LIMITL @Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
  #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL)        /*!< Position of CH5LIMITL field.                                         */
  #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field.               */
  #define SAADC_INTENCLR_CH5LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITL field.                             */
  #define SAADC_INTENCLR_CH5LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITL field.                             */
  #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH6LIMITH @Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
  #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL)        /*!< Position of CH6LIMITH field.                                         */
  #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field.               */
  #define SAADC_INTENCLR_CH6LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITH field.                             */
  #define SAADC_INTENCLR_CH6LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITH field.                             */
  #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH6LIMITL @Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
  #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL)        /*!< Position of CH6LIMITL field.                                         */
  #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field.               */
  #define SAADC_INTENCLR_CH6LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITL field.                             */
  #define SAADC_INTENCLR_CH6LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITL field.                             */
  #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH7LIMITH @Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
  #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL)        /*!< Position of CH7LIMITH field.                                         */
  #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field.               */
  #define SAADC_INTENCLR_CH7LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITH field.                             */
  #define SAADC_INTENCLR_CH7LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITH field.                             */
  #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* CH7LIMITL @Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
  #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL)        /*!< Position of CH7LIMITL field.                                         */
  #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field.               */
  #define SAADC_INTENCLR_CH7LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITL field.                             */
  #define SAADC_INTENCLR_CH7LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITL field.                             */
  #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
  #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* SAADC_STATUS: Status */
  #define SAADC_STATUS_ResetValue (0x00000000UL)     /*!< Reset value of STATUS register.                                      */

/* STATUS @Bit 0 : Status */
  #define SAADC_STATUS_STATUS_Pos (0UL)              /*!< Position of STATUS field.                                            */
  #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field.                            */
  #define SAADC_STATUS_STATUS_Min (0x0UL)            /*!< Min enumerator value of STATUS field.                                */
  #define SAADC_STATUS_STATUS_Max (0x1UL)            /*!< Max enumerator value of STATUS field.                                */
  #define SAADC_STATUS_STATUS_Ready (0x0UL)          /*!< ADC is ready. No on-going conversion.                                */
  #define SAADC_STATUS_STATUS_Busy (0x1UL)           /*!< ADC is busy. Conversion is in progress.                              */


/* SAADC_ENABLE: Enable or disable ADC */
  #define SAADC_ENABLE_ResetValue (0x00000000UL)     /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bit 0 : Enable or disable ADC */
  #define SAADC_ENABLE_ENABLE_Pos (0UL)              /*!< Position of ENABLE field.                                            */
  #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                            */
  #define SAADC_ENABLE_ENABLE_Min (0x0UL)            /*!< Min enumerator value of ENABLE field.                                */
  #define SAADC_ENABLE_ENABLE_Max (0x1UL)            /*!< Max enumerator value of ENABLE field.                                */
  #define SAADC_ENABLE_ENABLE_Disabled (0x0UL)       /*!< Disable ADC                                                          */
  #define SAADC_ENABLE_ENABLE_Enabled (0x1UL)        /*!< Enable ADC                                                           */


/* SAADC_RESOLUTION: Resolution configuration */
  #define SAADC_RESOLUTION_ResetValue (0x00000001UL) /*!< Reset value of RESOLUTION register.                                  */

/* VAL @Bits 0..2 : Set the resolution */
  #define SAADC_RESOLUTION_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
  #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field.                             */
  #define SAADC_RESOLUTION_VAL_Min (0x0UL)           /*!< Min enumerator value of VAL field.                                   */
  #define SAADC_RESOLUTION_VAL_Max (0x3UL)           /*!< Max enumerator value of VAL field.                                   */
  #define SAADC_RESOLUTION_VAL_8bit (0x0UL)          /*!< 8 bit                                                                */
  #define SAADC_RESOLUTION_VAL_10bit (0x1UL)         /*!< 10 bit                                                               */
  #define SAADC_RESOLUTION_VAL_12bit (0x2UL)         /*!< 12 bit                                                               */
  #define SAADC_RESOLUTION_VAL_14bit (0x3UL)         /*!< 14 bit                                                               */


/* SAADC_OVERSAMPLE: Oversampling configuration. OVERSAMPLE should not be combined with SCAN unless burst is enabled. The
                      RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */

  #define SAADC_OVERSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of OVERSAMPLE register.                                  */

/* OVERSAMPLE @Bits 0..3 : Oversample control */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL)      /*!< Position of OVERSAMPLE field.                                        */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field.        */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Min (0x0UL)    /*!< Min enumerator value of OVERSAMPLE field.                            */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Max (0x8UL)    /*!< Max enumerator value of OVERSAMPLE field.                            */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling                                                  */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x                                                        */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x                                                        */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x                                                        */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x                                                      */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x                                                      */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x                                                      */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x                                                    */
  #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x                                                    */


/* SAADC_SAMPLERATE: Configures the sampling rate for either task-triggered or continuous operation using a local timer */
  #define SAADC_SAMPLERATE_ResetValue (0x00000000UL) /*!< Reset value of SAMPLERATE register.                                  */

/* CC @Bits 0..10 : Capture and compare value. Sample rate is 16 MHz/CC */
  #define SAADC_SAMPLERATE_CC_Pos (0UL)              /*!< Position of CC field.                                                */
  #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field.                              */
  #define SAADC_SAMPLERATE_CC_Min (0x008UL)          /*!< Min value of CC field.                                               */
  #define SAADC_SAMPLERATE_CC_Max (0x7FFUL)          /*!< Max size of CC field.                                                */

/* MODE @Bit 12 : Select mode for sample rate control */
  #define SAADC_SAMPLERATE_MODE_Pos (12UL)           /*!< Position of MODE field.                                              */
  #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field.                          */
  #define SAADC_SAMPLERATE_MODE_Min (0x0UL)          /*!< Min enumerator value of MODE field.                                  */
  #define SAADC_SAMPLERATE_MODE_Max (0x1UL)          /*!< Max enumerator value of MODE field.                                  */
  #define SAADC_SAMPLERATE_MODE_Task (0x0UL)         /*!< Rate is controlled from SAMPLE task                                  */
  #define SAADC_SAMPLERATE_MODE_Timers (0x1UL)       /*!< Rate is controlled from local timer (use CC to control the rate)     */


/* SAADC_NOISESHAPE: SAADC provides two operational noise shaping modes (one that prioritizes higher bandwith, while the other
                      prioritizes higher accuracy) that allow trade-offs between ADC resolution, power consumption, and signal
                      bandwidth. */

  #define SAADC_NOISESHAPE_ResetValue (0x00000000UL) /*!< Reset value of NOISESHAPE register.                                  */

/* NOISESHAPE @Bits 0..1 : Noise shaping configuration */
  #define SAADC_NOISESHAPE_NOISESHAPE_Pos (0UL)      /*!< Position of NOISESHAPE field.                                        */
  #define SAADC_NOISESHAPE_NOISESHAPE_Msk (0x3UL << SAADC_NOISESHAPE_NOISESHAPE_Pos) /*!< Bit mask of NOISESHAPE field.        */
  #define SAADC_NOISESHAPE_NOISESHAPE_Min (0x0UL)    /*!< Min enumerator value of NOISESHAPE field.                            */
  #define SAADC_NOISESHAPE_NOISESHAPE_Max (0x2UL)    /*!< Max enumerator value of NOISESHAPE field.                            */
  #define SAADC_NOISESHAPE_NOISESHAPE_Disable (0x0UL) /*!< Disable noiseshaping. Configurable oversampling.                    */
  #define SAADC_NOISESHAPE_NOISESHAPE_NS1 (0x1UL)    /*!< Noiseshaping and decimating. Larger passband. Decimation ratio 8, 125
                                                          kS/s, with resulting bandwidth around 45 kHz. Takes precedence over
                                                          the OVERSAMPLING register.*/
  #define SAADC_NOISESHAPE_NOISESHAPE_NS2 (0x2UL)    /*!< Noiseshaping and decimating. Smaller passband. Decimation ratio 32,
                                                          31.25 kS/s, with resulting bandwidth around 7 kHz. Takes precedence
                                                          over the OVERSAMPLING register.*/
  #define SAADC_NOISESHAPE_NOISESHAPE_Audio (0x1UL)  /*!< Use enumerator NS1 for future compatibility.                         */
  #define SAADC_NOISESHAPE_NOISESHAPE_Accuracy (0x2UL) /*!< Use enumerator NS2 for future compatibility.                       */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           SICR                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct SICR ======================================================= */
/**
  * @brief Factory Information Configuration Registers
  */
  typedef struct {                                   /*!< SICR Structure                                                       */
    __IM uint32_t RESERVED;
  } NRF_SICR_Type;                                   /*!< Size = 4 (0x004)                                                     */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           SPIM                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct SPIM_TASKS_DMA_RX ================================================= */
/**
  * @brief RX [SPIM_TASKS_DMA_RX] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit
                                                                         in the CONFIG register.*/
  __OM  uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n]
                                                                         bit in the CONFIG register.*/
} NRF_SPIM_TASKS_DMA_RX_Type;                        /*!< Size = 32 (0x020)                                                    */

/* SPIM_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                                  */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                                 */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                                 */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.                 */

/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field.                              */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask
                                                                            of ENABLEMATCH field.*/
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field.                */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field.                */
  #define SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                          */


/* SPIM_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                                */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                               */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                               */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.               */

/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field.                           */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit
                                                                            mask of DISABLEMATCH field.*/
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field.             */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field.             */
  #define SPIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                        */



/* ================================================== Struct SPIM_TASKS_DMA ================================================== */
/**
  * @brief TASKS_DMA [SPIM_TASKS_DMA] Peripheral tasks.
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __OM  NRF_SPIM_TASKS_DMA_RX_Type RX;               /*!< (@ 0x00000008) Peripheral tasks.                                     */
} NRF_SPIM_TASKS_DMA_Type;                           /*!< Size = 40 (0x028)                                                    */


/* ============================================== Struct SPIM_SUBSCRIBE_DMA_RX =============================================== */
/**
  * @brief RX [SPIM_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n]       */
  __IOM uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n]      */
} NRF_SPIM_SUBSCRIBE_DMA_RX_Type;                    /*!< Size = 32 (0x020)                                                    */

/* SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                              */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                             */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                             */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.             */

/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                      */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                  */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                   */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                           */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                              */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                              */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                      */
  #define SPIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                        */


/* SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                            */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                           */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                           */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.           */

/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                     */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                 */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                  */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                          */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                             */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                             */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                     */
  #define SPIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                       */



/* ================================================ Struct SPIM_SUBSCRIBE_DMA ================================================ */
/**
  * @brief SUBSCRIBE_DMA [SPIM_SUBSCRIBE_DMA] Subscribe configuration for tasks
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __IOM NRF_SPIM_SUBSCRIBE_DMA_RX_Type RX;           /*!< (@ 0x00000008) Subscribe configuration for tasks                     */
} NRF_SPIM_SUBSCRIBE_DMA_Type;                       /*!< Size = 40 (0x028)                                                    */


/* ================================================ Struct SPIM_EVENTS_DMA_RX ================================================ */
/**
  * @brief RX [SPIM_EVENTS_DMA_RX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus.        */
} NRF_SPIM_EVENTS_DMA_RX_Type;                       /*!< Size = 28 (0x01C)                                                    */

/* SPIM_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */
  #define SPIM_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define SPIM_EVENTS_DMA_RX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define SPIM_EVENTS_DMA_RX_END_END_Msk (0x1UL << SPIM_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define SPIM_EVENTS_DMA_RX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define SPIM_EVENTS_DMA_RX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define SPIM_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define SPIM_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* SPIM_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define SPIM_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define SPIM_EVENTS_DMA_RX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define SPIM_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << SPIM_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define SPIM_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define SPIM_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define SPIM_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define SPIM_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* SPIM_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */
  #define SPIM_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define SPIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */


/* SPIM_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */
  #define SPIM_EVENTS_DMA_RX_MATCH_MaxCount (4UL)    /*!< Max size of MATCH[4] array.                                          */
  #define SPIM_EVENTS_DMA_RX_MATCH_MaxIndex (3UL)    /*!< Max index of MATCH[4] array.                                         */
  #define SPIM_EVENTS_DMA_RX_MATCH_MinIndex (0UL)    /*!< Min index of MATCH[4] array.                                         */
  #define SPIM_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                            */

/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */
  #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL)   /*!< Position of MATCH field.                                             */
  #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << SPIM_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field.       */
  #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field.                                 */
  #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field.                                 */
  #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define SPIM_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated                                                */



/* ================================================ Struct SPIM_EVENTS_DMA_TX ================================================ */
/**
  * @brief TX [SPIM_EVENTS_DMA_TX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
} NRF_SPIM_EVENTS_DMA_TX_Type;                       /*!< Size = 12 (0x00C)                                                    */

/* SPIM_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */
  #define SPIM_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define SPIM_EVENTS_DMA_TX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define SPIM_EVENTS_DMA_TX_END_END_Msk (0x1UL << SPIM_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define SPIM_EVENTS_DMA_TX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define SPIM_EVENTS_DMA_TX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define SPIM_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define SPIM_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* SPIM_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define SPIM_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define SPIM_EVENTS_DMA_TX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define SPIM_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << SPIM_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define SPIM_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define SPIM_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define SPIM_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define SPIM_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* SPIM_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */
  #define SPIM_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define SPIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */



/* ================================================= Struct SPIM_EVENTS_DMA ================================================== */
/**
  * @brief EVENTS_DMA [SPIM_EVENTS_DMA] Peripheral events.
  */
typedef struct {
  __IOM NRF_SPIM_EVENTS_DMA_RX_Type RX;              /*!< (@ 0x00000000) Peripheral events.                                    */
  __IOM NRF_SPIM_EVENTS_DMA_TX_Type TX;              /*!< (@ 0x0000001C) Peripheral events.                                    */
} NRF_SPIM_EVENTS_DMA_Type;                          /*!< Size = 40 (0x028)                                                    */


/* =============================================== Struct SPIM_PUBLISH_DMA_RX ================================================ */
/**
  * @brief RX [SPIM_PUBLISH_DMA_RX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Publish configuration for event MATCH[n]              */
} NRF_SPIM_PUBLISH_DMA_RX_Type;                      /*!< Size = 28 (0x01C)                                                    */

/* SPIM_PUBLISH_DMA_RX_END: Publish configuration for event END */
  #define SPIM_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define SPIM_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_DMA_RX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define SPIM_PUBLISH_DMA_RX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_RX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define SPIM_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* SPIM_PUBLISH_DMA_RX_READY: Publish configuration for event READY */
  #define SPIM_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define SPIM_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_DMA_RX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define SPIM_PUBLISH_DMA_RX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_RX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define SPIM_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* SPIM_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define SPIM_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */


/* SPIM_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */
  #define SPIM_PUBLISH_DMA_RX_MATCH_MaxCount (4UL)   /*!< Max size of MATCH[4] array.                                          */
  #define SPIM_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL)   /*!< Max index of MATCH[4] array.                                         */
  #define SPIM_PUBLISH_DMA_RX_MATCH_MinIndex (0UL)   /*!< Min index of MATCH[4] array.                                         */
  #define SPIM_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */
  #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define SPIM_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field.              */
  #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define SPIM_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */



/* =============================================== Struct SPIM_PUBLISH_DMA_TX ================================================ */
/**
  * @brief TX [SPIM_PUBLISH_DMA_TX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
} NRF_SPIM_PUBLISH_DMA_TX_Type;                      /*!< Size = 12 (0x00C)                                                    */

/* SPIM_PUBLISH_DMA_TX_END: Publish configuration for event END */
  #define SPIM_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define SPIM_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_DMA_TX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define SPIM_PUBLISH_DMA_TX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_TX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define SPIM_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* SPIM_PUBLISH_DMA_TX_READY: Publish configuration for event READY */
  #define SPIM_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define SPIM_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_DMA_TX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define SPIM_PUBLISH_DMA_TX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_TX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define SPIM_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* SPIM_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define SPIM_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */



/* ================================================= Struct SPIM_PUBLISH_DMA ================================================= */
/**
  * @brief PUBLISH_DMA [SPIM_PUBLISH_DMA] Publish configuration for events
  */
typedef struct {
  __IOM NRF_SPIM_PUBLISH_DMA_RX_Type RX;             /*!< (@ 0x00000000) Publish configuration for events                      */
  __IOM NRF_SPIM_PUBLISH_DMA_TX_Type TX;             /*!< (@ 0x0000001C) Publish configuration for events                      */
} NRF_SPIM_PUBLISH_DMA_Type;                         /*!< Size = 40 (0x028)                                                    */


/* ================================================== Struct SPIM_IFTIMING =================================================== */
/**
  * @brief IFTIMING [SPIM_IFTIMING] (unspecified)
  */
typedef struct {
  __IOM uint32_t  RXDELAY;                           /*!< (@ 0x00000000) Sample delay for input serial data on SDI             */
  __IOM uint32_t  CSNDUR;                            /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge of SCK.
                                                                         When SHORTS.END_START is used, this is also the minimum
                                                                         duration CSN must stay high between transactions.*/
} NRF_SPIM_IFTIMING_Type;                            /*!< Size = 8 (0x008)                                                     */

/* SPIM_IFTIMING_RXDELAY: Sample delay for input serial data on SDI */
  #define SPIM_IFTIMING_RXDELAY_ResetValue (0x00000002UL) /*!< Reset value of RXDELAY register.                                */

/* RXDELAY @Bits 0..2 : Sample delay for input serial data on SDI. The value specifies the number of SPIM core clock cycles
                        delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA
                        = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the
                        input serial data is sampled on the rising edge of SCK. */

  #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL)    /*!< Position of RXDELAY field.                                           */
  #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field.       */
  #define SPIM_IFTIMING_RXDELAY_RXDELAY_Min (0x0UL)  /*!< Min value of RXDELAY field.                                          */
  #define SPIM_IFTIMING_RXDELAY_RXDELAY_Max (0x7UL)  /*!< Max size of RXDELAY field.                                           */


/* SPIM_IFTIMING_CSNDUR: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the
                          minimum duration CSN must stay high between transactions. */

  #define SPIM_IFTIMING_CSNDUR_ResetValue (0x00000002UL) /*!< Reset value of CSNDUR register.                                  */

/* CSNDUR @Bits 0..7 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum
                       duration CSN must stay high between transactions. The value is specified in number of SPIM core clock
                       cycles. */

  #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL)      /*!< Position of CSNDUR field.                                            */
  #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field.           */
  #define SPIM_IFTIMING_CSNDUR_CSNDUR_Min (0x00UL)   /*!< Min value of CSNDUR field.                                           */
  #define SPIM_IFTIMING_CSNDUR_CSNDUR_Max (0xFFUL)   /*!< Max size of CSNDUR field.                                            */



/* ==================================================== Struct SPIM_PSEL ===================================================== */
/**
  * @brief PSEL [SPIM_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  SCK;                               /*!< (@ 0x00000000) Pin select for SCK                                    */
  __IOM uint32_t  MOSI;                              /*!< (@ 0x00000004) Pin select for SDO signal                             */
  __IOM uint32_t  MISO;                              /*!< (@ 0x00000008) Pin select for SDI signal                             */
  __IOM uint32_t  DCX;                               /*!< (@ 0x0000000C) Pin select for DCX signal                             */
  __IOM uint32_t  CSN;                               /*!< (@ 0x00000010) Pin select for CSN                                    */
} NRF_SPIM_PSEL_Type;                                /*!< Size = 20 (0x014)                                                    */

/* SPIM_PSEL_SCK: Pin select for SCK */
  #define SPIM_PSEL_SCK_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCK register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define SPIM_PSEL_SCK_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define SPIM_PSEL_SCK_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define SPIM_PSEL_SCK_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIM_PSEL_SCK_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define SPIM_PSEL_SCK_PORT_Msk (0x7UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define SPIM_PSEL_SCK_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define SPIM_PSEL_SCK_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIM_PSEL_SCK_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define SPIM_PSEL_SCK_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_SCK_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* SPIM_PSEL_MOSI: Pin select for SDO signal */
  #define SPIM_PSEL_MOSI_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MOSI register.                                        */

/* PIN @Bits 0..4 : Pin number */
  #define SPIM_PSEL_MOSI_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define SPIM_PSEL_MOSI_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define SPIM_PSEL_MOSI_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIM_PSEL_MOSI_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define SPIM_PSEL_MOSI_PORT_Msk (0x7UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define SPIM_PSEL_MOSI_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define SPIM_PSEL_MOSI_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define SPIM_PSEL_MOSI_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_MOSI_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */


/* SPIM_PSEL_MISO: Pin select for SDI signal */
  #define SPIM_PSEL_MISO_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MISO register.                                        */

/* PIN @Bits 0..4 : Pin number */
  #define SPIM_PSEL_MISO_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define SPIM_PSEL_MISO_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define SPIM_PSEL_MISO_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIM_PSEL_MISO_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define SPIM_PSEL_MISO_PORT_Msk (0x7UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define SPIM_PSEL_MISO_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define SPIM_PSEL_MISO_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIM_PSEL_MISO_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define SPIM_PSEL_MISO_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_MISO_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */


/* SPIM_PSEL_DCX: Pin select for DCX signal */
  #define SPIM_PSEL_DCX_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of DCX register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define SPIM_PSEL_DCX_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define SPIM_PSEL_DCX_PIN_Msk (0x1FUL << SPIM_PSEL_DCX_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define SPIM_PSEL_DCX_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define SPIM_PSEL_DCX_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIM_PSEL_DCX_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define SPIM_PSEL_DCX_PORT_Msk (0x7UL << SPIM_PSEL_DCX_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define SPIM_PSEL_DCX_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define SPIM_PSEL_DCX_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIM_PSEL_DCX_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define SPIM_PSEL_DCX_CONNECT_Msk (0x1UL << SPIM_PSEL_DCX_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define SPIM_PSEL_DCX_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_DCX_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_DCX_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define SPIM_PSEL_DCX_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* SPIM_PSEL_CSN: Pin select for CSN */
  #define SPIM_PSEL_CSN_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of CSN register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define SPIM_PSEL_CSN_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define SPIM_PSEL_CSN_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define SPIM_PSEL_CSN_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIM_PSEL_CSN_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define SPIM_PSEL_CSN_PORT_Msk (0x7UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define SPIM_PSEL_CSN_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define SPIM_PSEL_CSN_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIM_PSEL_CSN_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define SPIM_PSEL_CSN_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_CSN_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define SPIM_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define SPIM_PSEL_CSN_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */



/* ================================================ Struct SPIM_DMA_RX_MATCH ================================================= */
/**
  * @brief MATCH [SPIM_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Configure individual match events                     */
  __IOM uint32_t  CANDIDATE[4];                      /*!< (@ 0x00000004) The data to look for - any match will trigger the
                                                                         MATCH[n] event, if enabled.*/
} NRF_SPIM_DMA_RX_MATCH_Type;                        /*!< Size = 20 (0x014)                                                    */

/* SPIM_DMA_RX_MATCH_CONFIG: Configure individual match events */
  #define SPIM_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                              */

/* ENABLE0 @Bit 0 : Enable match filter 0 */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field.                                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE1 @Bit 1 : Enable match filter 1 */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field.                                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE2 @Bit 2 : Enable match filter 2 */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field.                                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE3 @Bit 3 : Enable match filter 3 */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field.                                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                             */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field.                                        */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0
                                                                            field.*/
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field.                                        */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1
                                                                            field.*/
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field.                                        */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2
                                                                            field.*/
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field.                                        */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3
                                                                            field.*/
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field.                           */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */


/* SPIM_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */
  #define SPIM_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array.                                      */
  #define SPIM_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array.                                     */
  #define SPIM_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array.                                     */
  #define SPIM_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register.                     */

/* DATA @Bits 0..31 : Data to look for */
  #define SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field.                                              */
  #define SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA
                                                                            field.*/



/* =================================================== Struct SPIM_DMA_RX ==================================================== */
/**
  * @brief RX [SPIM_DMA_RX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  LIST;                              /*!< (@ 0x00000014) EasyDMA list type                                     */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
  __IOM NRF_SPIM_DMA_RX_MATCH_Type MATCH;            /*!< (@ 0x00000024) Registers to control the behavior of the pattern
                                                                         matcher engine*/
} NRF_SPIM_DMA_RX_Type;                              /*!< Size = 56 (0x038)                                                    */

/* SPIM_DMA_RX_PTR: RAM buffer start address */
  #define SPIM_DMA_RX_PTR_ResetValue (0x20000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define SPIM_DMA_RX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define SPIM_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* SPIM_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */
  #define SPIM_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define SPIM_DMA_RX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define SPIM_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define SPIM_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define SPIM_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* SPIM_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define SPIM_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define SPIM_DMA_RX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define SPIM_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define SPIM_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define SPIM_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* SPIM_DMA_RX_LIST: EasyDMA list type */
  #define SPIM_DMA_RX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register.                                        */

/* TYPE @Bits 0..2 : List type */
  #define SPIM_DMA_RX_LIST_TYPE_Pos (0UL)            /*!< Position of TYPE field.                                              */
  #define SPIM_DMA_RX_LIST_TYPE_Msk (0x7UL << SPIM_DMA_RX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field.                          */
  #define SPIM_DMA_RX_LIST_TYPE_Min (0x0UL)          /*!< Min enumerator value of TYPE field.                                  */
  #define SPIM_DMA_RX_LIST_TYPE_Max (0x1UL)          /*!< Max enumerator value of TYPE field.                                  */
  #define SPIM_DMA_RX_LIST_TYPE_Disabled (0x0UL)     /*!< Disable EasyDMA list                                                 */
  #define SPIM_DMA_RX_LIST_TYPE_ArrayList (0x1UL)    /*!< Use array list                                                       */


/* SPIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define SPIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* SPIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define SPIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* =================================================== Struct SPIM_DMA_TX ==================================================== */
/**
  * @brief TX [SPIM_DMA_TX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  LIST;                              /*!< (@ 0x00000014) EasyDMA list type                                     */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_SPIM_DMA_TX_Type;                              /*!< Size = 36 (0x024)                                                    */

/* SPIM_DMA_TX_PTR: RAM buffer start address */
  #define SPIM_DMA_TX_PTR_ResetValue (0x20000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define SPIM_DMA_TX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define SPIM_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* SPIM_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */
  #define SPIM_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define SPIM_DMA_TX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define SPIM_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define SPIM_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define SPIM_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* SPIM_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define SPIM_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define SPIM_DMA_TX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define SPIM_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define SPIM_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define SPIM_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* SPIM_DMA_TX_LIST: EasyDMA list type */
  #define SPIM_DMA_TX_LIST_ResetValue (0x00000000UL) /*!< Reset value of LIST register.                                        */

/* TYPE @Bits 0..2 : List type */
  #define SPIM_DMA_TX_LIST_TYPE_Pos (0UL)            /*!< Position of TYPE field.                                              */
  #define SPIM_DMA_TX_LIST_TYPE_Msk (0x7UL << SPIM_DMA_TX_LIST_TYPE_Pos) /*!< Bit mask of TYPE field.                          */
  #define SPIM_DMA_TX_LIST_TYPE_Min (0x0UL)          /*!< Min enumerator value of TYPE field.                                  */
  #define SPIM_DMA_TX_LIST_TYPE_Max (0x1UL)          /*!< Max enumerator value of TYPE field.                                  */
  #define SPIM_DMA_TX_LIST_TYPE_Disabled (0x0UL)     /*!< Disable EasyDMA list                                                 */
  #define SPIM_DMA_TX_LIST_TYPE_ArrayList (0x1UL)    /*!< Use array list                                                       */


/* SPIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define SPIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* SPIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define SPIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* ===================================================== Struct SPIM_DMA ===================================================== */
/**
  * @brief DMA [SPIM_DMA] (unspecified)
  */
typedef struct {
  __IOM NRF_SPIM_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
  __IOM NRF_SPIM_DMA_TX_Type TX;                     /*!< (@ 0x00000038) (unspecified)                                         */
} NRF_SPIM_DMA_Type;                                 /*!< Size = 92 (0x05C)                                                    */

/* ======================================================= Struct SPIM ======================================================= */
/**
  * @brief Serial Peripheral Interface Master with EasyDMA
  */
  typedef struct {                                   /*!< SPIM Structure                                                       */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start SPI transaction                                 */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop SPI transaction                                  */
    __IM uint32_t RESERVED;
    __OM uint32_t TASKS_SUSPEND;                     /*!< (@ 0x0000000C) Suspend SPI transaction                               */
    __OM uint32_t TASKS_RESUME;                      /*!< (@ 0x00000010) Resume SPI transaction                                */
    __IM uint32_t RESERVED1[5];
    __OM NRF_SPIM_TASKS_DMA_Type TASKS_DMA;          /*!< (@ 0x00000028) Peripheral tasks.                                     */
    __IM uint32_t RESERVED2[12];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED3;
    __IOM uint32_t SUBSCRIBE_SUSPEND;                /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND              */
    __IOM uint32_t SUBSCRIBE_RESUME;                 /*!< (@ 0x00000090) Subscribe configuration for task RESUME               */
    __IM uint32_t RESERVED4[5];
    __IOM NRF_SPIM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks                     */
    __IM uint32_t RESERVED5[12];
    __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000100) SPI transaction has started                           */
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) SPI transaction has stopped                           */
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000108) End of RXD buffer and TXD buffer reached              */
    __IM uint32_t RESERVED6[16];
    __IOM NRF_SPIM_EVENTS_DMA_Type EVENTS_DMA;       /*!< (@ 0x0000014C) Peripheral events.                                    */
    __IM uint32_t RESERVED7[3];
    __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x00000180) Publish configuration for event STARTED               */
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000188) Publish configuration for event END                   */
    __IM uint32_t RESERVED8[16];
    __IOM NRF_SPIM_PUBLISH_DMA_Type PUBLISH_DMA;     /*!< (@ 0x000001CC) Publish configuration for events                      */
    __IM uint32_t RESERVED9[3];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED10[64];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED11[125];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable SPIM                                           */
    __IM uint32_t RESERVED12[10];
    __IOM uint32_t PRESCALER;                        /*!< (@ 0x0000052C) The prescaler is used to set the SPI frequency.       */
    __IM uint32_t RESERVED13[9];
    __IOM uint32_t CONFIG;                           /*!< (@ 0x00000554) Configuration register                                */
    __IM uint32_t RESERVED14[21];
    __IOM NRF_SPIM_IFTIMING_Type IFTIMING;           /*!< (@ 0x000005AC) (unspecified)                                         */
    __IOM uint32_t DCXCNT;                           /*!< (@ 0x000005B4) DCX configuration                                     */
    __IOM uint32_t CSNPOL;                           /*!< (@ 0x000005B8) Polarity of CSN output                                */
    __IM uint32_t RESERVED15;
    __IOM uint32_t ORC;                              /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have been
                                                                         transmitted in the case when RXD.MAXCNT is greater than
                                                                         TXD.MAXCNT*/
    __IM uint32_t RESERVED16[15];
    __IOM NRF_SPIM_PSEL_Type PSEL;                   /*!< (@ 0x00000600) (unspecified)                                         */
    __IM uint32_t RESERVED17[59];
    __IOM NRF_SPIM_DMA_Type DMA;                     /*!< (@ 0x00000700) (unspecified)                                         */
  } NRF_SPIM_Type;                                   /*!< Size = 1884 (0x75C)                                                  */

/* SPIM_TASKS_START: Start SPI transaction */
  #define SPIM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start SPI transaction */
  #define SPIM_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
  #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
  #define SPIM_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
  #define SPIM_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
  #define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */


/* SPIM_TASKS_STOP: Stop SPI transaction */
  #define SPIM_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop SPI transaction */
  #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
  #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
  #define SPIM_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
  #define SPIM_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
  #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */


/* SPIM_TASKS_SUSPEND: Suspend SPI transaction */
  #define SPIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register.                             */

/* TASKS_SUSPEND @Bit 0 : Suspend SPI transaction */
  #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field.                                     */
  #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND
                                                                            field.*/
  #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field.                       */
  #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field.                       */
  #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task                                                   */


/* SPIM_TASKS_RESUME: Resume SPI transaction */
  #define SPIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register.                               */

/* TASKS_RESUME @Bit 0 : Resume SPI transaction */
  #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)   /*!< Position of TASKS_RESUME field.                                      */
  #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/
  #define SPIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field.                          */
  #define SPIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field.                          */
  #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task                                                     */


/* SPIM_SUBSCRIBE_START: Subscribe configuration for task START */
  #define SPIM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define SPIM_SUBSCRIBE_START_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define SPIM_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
  #define SPIM_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* SPIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define SPIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define SPIM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define SPIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
  #define SPIM_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* SPIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */
  #define SPIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */
  #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field.                    */
  #define SPIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* SPIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */
  #define SPIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */
  #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define SPIM_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define SPIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field.                      */
  #define SPIM_SUBSCRIBE_RESUME_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_RESUME_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* SPIM_EVENTS_STARTED: SPI transaction has started */
  #define SPIM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                           */

/* EVENTS_STARTED @Bit 0 : SPI transaction has started */
  #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                  */
  #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
                                                                            EVENTS_STARTED field.*/
  #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                    */
  #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                    */
  #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                            */


/* SPIM_EVENTS_STOPPED: SPI transaction has stopped */
  #define SPIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */

/* EVENTS_STOPPED @Bit 0 : SPI transaction has stopped */
  #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
  #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
                                                                            EVENTS_STOPPED field.*/
  #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
  #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
  #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */


/* SPIM_EVENTS_END: End of RXD buffer and TXD buffer reached */
  #define SPIM_EVENTS_END_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : End of RXD buffer and TXD buffer reached */
  #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL)       /*!< Position of EVENTS_END field.                                        */
  #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.          */
  #define SPIM_EVENTS_END_EVENTS_END_Min (0x0UL)     /*!< Min enumerator value of EVENTS_END field.                            */
  #define SPIM_EVENTS_END_EVENTS_END_Max (0x1UL)     /*!< Max enumerator value of EVENTS_END field.                            */
  #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                    */


/* SPIM_PUBLISH_STARTED: Publish configuration for event STARTED */
  #define SPIM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
  #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define SPIM_PUBLISH_STARTED_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define SPIM_PUBLISH_STARTED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_STARTED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                        */
  #define SPIM_PUBLISH_STARTED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_STARTED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* SPIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define SPIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define SPIM_PUBLISH_STOPPED_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define SPIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
  #define SPIM_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* SPIM_PUBLISH_END: Publish configuration for event END */
  #define SPIM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define SPIM_PUBLISH_END_CHIDX_Pos (0UL)           /*!< Position of CHIDX field.                                             */
  #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                      */
  #define SPIM_PUBLISH_END_CHIDX_Min (0x00UL)        /*!< Min value of CHIDX field.                                            */
  #define SPIM_PUBLISH_END_CHIDX_Max (0xFFUL)        /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIM_PUBLISH_END_EN_Pos (31UL)             /*!< Position of EN field.                                                */
  #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                */
  #define SPIM_PUBLISH_END_EN_Min (0x0UL)            /*!< Min enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_END_EN_Max (0x1UL)            /*!< Max enumerator value of EN field.                                    */
  #define SPIM_PUBLISH_END_EN_Disabled (0x0UL)       /*!< Disable publishing                                                   */
  #define SPIM_PUBLISH_END_EN_Enabled (0x1UL)        /*!< Enable publishing                                                    */


/* SPIM_SHORTS: Shortcuts between local events and tasks */
  #define SPIM_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* END_START @Bit 17 : Shortcut between event END and task START */
  #define SPIM_SHORTS_END_START_Pos (17UL)           /*!< Position of END_START field.                                         */
  #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field.                     */
  #define SPIM_SHORTS_END_START_Min (0x0UL)          /*!< Min enumerator value of END_START field.                             */
  #define SPIM_SHORTS_END_START_Max (0x1UL)          /*!< Max enumerator value of END_START field.                             */
  #define SPIM_SHORTS_END_START_Disabled (0x0UL)     /*!< Disable shortcut                                                     */
  #define SPIM_SHORTS_END_START_Enabled (0x1UL)      /*!< Enable shortcut                                                      */

/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows
                                               daisy-chaining match events. */

  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.   */
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows
                                               daisy-chaining match events. */

  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.   */
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows
                                               daisy-chaining match events. */

  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.   */
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows
                                               daisy-chaining match events. */

  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.   */
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[0] and task DMA.RX.DISABLEMATCH[0] */
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[1] and task DMA.RX.DISABLEMATCH[1] */
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[2] and task DMA.RX.DISABLEMATCH[2] */
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[3] and task DMA.RX.DISABLEMATCH[3] */
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3
                                                                            field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                  */


/* SPIM_INTENSET: Enable interrupt */
  #define SPIM_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */
  #define SPIM_INTENSET_STARTED_Pos (0UL)            /*!< Position of STARTED field.                                           */
  #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
  #define SPIM_INTENSET_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
  #define SPIM_INTENSET_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
  #define SPIM_INTENSET_STARTED_Set (0x1UL)          /*!< Enable                                                               */
  #define SPIM_INTENSET_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
  #define SPIM_INTENSET_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
  #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define SPIM_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define SPIM_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define SPIM_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
  #define SPIM_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* END @Bit 2 : Write '1' to enable interrupt for event END */
  #define SPIM_INTENSET_END_Pos (2UL)                /*!< Position of END field.                                               */
  #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field.                                   */
  #define SPIM_INTENSET_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
  #define SPIM_INTENSET_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
  #define SPIM_INTENSET_END_Set (0x1UL)              /*!< Enable                                                               */
  #define SPIM_INTENSET_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */
  #define SPIM_INTENSET_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define SPIM_INTENSET_DMARXEND_Msk (0x1UL << SPIM_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define SPIM_INTENSET_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define SPIM_INTENSET_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define SPIM_INTENSET_DMARXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define SPIM_INTENSET_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */
  #define SPIM_INTENSET_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define SPIM_INTENSET_DMARXREADY_Msk (0x1UL << SPIM_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define SPIM_INTENSET_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define SPIM_INTENSET_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define SPIM_INTENSET_DMARXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define SPIM_INTENSET_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */
  #define SPIM_INTENSET_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define SPIM_INTENSET_DMARXBUSERROR_Msk (0x1UL << SPIM_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define SPIM_INTENSET_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define SPIM_INTENSET_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define SPIM_INTENSET_DMARXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define SPIM_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIM_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */
  #define SPIM_INTENSET_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define SPIM_INTENSET_DMARXMATCH0_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define SPIM_INTENSET_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define SPIM_INTENSET_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define SPIM_INTENSET_DMARXMATCH0_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIM_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */
  #define SPIM_INTENSET_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define SPIM_INTENSET_DMARXMATCH1_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define SPIM_INTENSET_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define SPIM_INTENSET_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define SPIM_INTENSET_DMARXMATCH1_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIM_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */
  #define SPIM_INTENSET_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define SPIM_INTENSET_DMARXMATCH2_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define SPIM_INTENSET_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define SPIM_INTENSET_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define SPIM_INTENSET_DMARXMATCH2_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIM_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */
  #define SPIM_INTENSET_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define SPIM_INTENSET_DMARXMATCH3_Msk (0x1UL << SPIM_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define SPIM_INTENSET_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define SPIM_INTENSET_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define SPIM_INTENSET_DMARXMATCH3_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIM_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */
  #define SPIM_INTENSET_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define SPIM_INTENSET_DMATXEND_Msk (0x1UL << SPIM_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define SPIM_INTENSET_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define SPIM_INTENSET_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define SPIM_INTENSET_DMATXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define SPIM_INTENSET_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */
  #define SPIM_INTENSET_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define SPIM_INTENSET_DMATXREADY_Msk (0x1UL << SPIM_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define SPIM_INTENSET_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define SPIM_INTENSET_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define SPIM_INTENSET_DMATXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define SPIM_INTENSET_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIM_INTENSET_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */
  #define SPIM_INTENSET_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define SPIM_INTENSET_DMATXBUSERROR_Msk (0x1UL << SPIM_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define SPIM_INTENSET_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define SPIM_INTENSET_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define SPIM_INTENSET_DMATXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define SPIM_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIM_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* SPIM_INTENCLR: Disable interrupt */
  #define SPIM_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */
  #define SPIM_INTENCLR_STARTED_Pos (0UL)            /*!< Position of STARTED field.                                           */
  #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
  #define SPIM_INTENCLR_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
  #define SPIM_INTENCLR_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
  #define SPIM_INTENCLR_STARTED_Clear (0x1UL)        /*!< Disable                                                              */
  #define SPIM_INTENCLR_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
  #define SPIM_INTENCLR_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
  #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define SPIM_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define SPIM_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define SPIM_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
  #define SPIM_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* END @Bit 2 : Write '1' to disable interrupt for event END */
  #define SPIM_INTENCLR_END_Pos (2UL)                /*!< Position of END field.                                               */
  #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field.                                   */
  #define SPIM_INTENCLR_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
  #define SPIM_INTENCLR_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
  #define SPIM_INTENCLR_END_Clear (0x1UL)            /*!< Disable                                                              */
  #define SPIM_INTENCLR_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */
  #define SPIM_INTENCLR_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define SPIM_INTENCLR_DMARXEND_Msk (0x1UL << SPIM_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define SPIM_INTENCLR_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define SPIM_INTENCLR_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define SPIM_INTENCLR_DMARXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */
  #define SPIM_INTENCLR_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define SPIM_INTENCLR_DMARXREADY_Msk (0x1UL << SPIM_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define SPIM_INTENCLR_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define SPIM_INTENCLR_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define SPIM_INTENCLR_DMARXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */
  #define SPIM_INTENCLR_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define SPIM_INTENCLR_DMARXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define SPIM_INTENCLR_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define SPIM_INTENCLR_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define SPIM_INTENCLR_DMARXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIM_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */
  #define SPIM_INTENCLR_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define SPIM_INTENCLR_DMARXMATCH0_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define SPIM_INTENCLR_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH0_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */
  #define SPIM_INTENCLR_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define SPIM_INTENCLR_DMARXMATCH1_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define SPIM_INTENCLR_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH1_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */
  #define SPIM_INTENCLR_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define SPIM_INTENCLR_DMARXMATCH2_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define SPIM_INTENCLR_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH2_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */
  #define SPIM_INTENCLR_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define SPIM_INTENCLR_DMARXMATCH3_Msk (0x1UL << SPIM_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define SPIM_INTENCLR_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define SPIM_INTENCLR_DMARXMATCH3_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */
  #define SPIM_INTENCLR_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define SPIM_INTENCLR_DMATXEND_Msk (0x1UL << SPIM_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define SPIM_INTENCLR_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define SPIM_INTENCLR_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define SPIM_INTENCLR_DMATXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */
  #define SPIM_INTENCLR_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define SPIM_INTENCLR_DMATXREADY_Msk (0x1UL << SPIM_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define SPIM_INTENCLR_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define SPIM_INTENCLR_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define SPIM_INTENCLR_DMATXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIM_INTENCLR_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */
  #define SPIM_INTENCLR_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define SPIM_INTENCLR_DMATXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define SPIM_INTENCLR_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define SPIM_INTENCLR_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define SPIM_INTENCLR_DMATXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define SPIM_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIM_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* SPIM_ENABLE: Enable SPIM */
  #define SPIM_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..3 : Enable or disable SPIM */
  #define SPIM_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
  #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
  #define SPIM_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
  #define SPIM_ENABLE_ENABLE_Max (0x7UL)             /*!< Max enumerator value of ENABLE field.                                */
  #define SPIM_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable SPIM                                                         */
  #define SPIM_ENABLE_ENABLE_Enabled (0x7UL)         /*!< Enable SPIM                                                          */


/* SPIM_PRESCALER: The prescaler is used to set the SPI frequency. */
  #define SPIM_PRESCALER_ResetValue (0x00000040UL)   /*!< Reset value of PRESCALER register.                                   */

/* DIVISOR @Bits 0..6 : Core clock to SCK divisor */
  #define SPIM_PRESCALER_DIVISOR_Pos (0UL)           /*!< Position of DIVISOR field.                                           */
  #define SPIM_PRESCALER_DIVISOR_Msk (0x7FUL << SPIM_PRESCALER_DIVISOR_Pos) /*!< Bit mask of DIVISOR field.                    */
  #define SPIM_PRESCALER_DIVISOR_Min (0x02UL)        /*!< Min value of DIVISOR field.                                          */
  #define SPIM_PRESCALER_DIVISOR_Max (0x7EUL)        /*!< Max size of DIVISOR field.                                           */


/* SPIM_CONFIG: Configuration register */
  #define SPIM_CONFIG_ResetValue (0x00000000UL)      /*!< Reset value of CONFIG register.                                      */

/* ORDER @Bit 0 : Bit order */
  #define SPIM_CONFIG_ORDER_Pos (0UL)                /*!< Position of ORDER field.                                             */
  #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field.                                 */
  #define SPIM_CONFIG_ORDER_Min (0x0UL)              /*!< Min enumerator value of ORDER field.                                 */
  #define SPIM_CONFIG_ORDER_Max (0x1UL)              /*!< Max enumerator value of ORDER field.                                 */
  #define SPIM_CONFIG_ORDER_MsbFirst (0x0UL)         /*!< Most significant bit shifted out first                               */
  #define SPIM_CONFIG_ORDER_LsbFirst (0x1UL)         /*!< Least significant bit shifted out first                              */

/* CPHA @Bit 1 : Serial clock (SCK) phase */
  #define SPIM_CONFIG_CPHA_Pos (1UL)                 /*!< Position of CPHA field.                                              */
  #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field.                                    */
  #define SPIM_CONFIG_CPHA_Min (0x0UL)               /*!< Min enumerator value of CPHA field.                                  */
  #define SPIM_CONFIG_CPHA_Max (0x1UL)               /*!< Max enumerator value of CPHA field.                                  */
  #define SPIM_CONFIG_CPHA_Leading (0x0UL)           /*!< Sample on leading edge of clock, shift serial data on trailing edge  */
  #define SPIM_CONFIG_CPHA_Trailing (0x1UL)          /*!< Sample on trailing edge of clock, shift serial data on leading edge  */

/* CPOL @Bit 2 : Serial clock (SCK) polarity */
  #define SPIM_CONFIG_CPOL_Pos (2UL)                 /*!< Position of CPOL field.                                              */
  #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field.                                    */
  #define SPIM_CONFIG_CPOL_Min (0x0UL)               /*!< Min enumerator value of CPOL field.                                  */
  #define SPIM_CONFIG_CPOL_Max (0x1UL)               /*!< Max enumerator value of CPOL field.                                  */
  #define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL)        /*!< Active high                                                          */
  #define SPIM_CONFIG_CPOL_ActiveLow (0x1UL)         /*!< Active low                                                           */


/* SPIM_DCXCNT: DCX configuration */
  #define SPIM_DCXCNT_ResetValue (0x00000000UL)      /*!< Reset value of DCXCNT register.                                      */

/* DCXCNT @Bits 0..3 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be
                       low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates
                       that all bytes are command bytes. */

  #define SPIM_DCXCNT_DCXCNT_Pos (0UL)               /*!< Position of DCXCNT field.                                            */
  #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field.                              */
  #define SPIM_DCXCNT_DCXCNT_Min (0x0UL)             /*!< Min value of DCXCNT field.                                           */
  #define SPIM_DCXCNT_DCXCNT_Max (0xFUL)             /*!< Max size of DCXCNT field.                                            */


/* SPIM_CSNPOL: Polarity of CSN output */
  #define SPIM_CSNPOL_ResetValue (0x00000000UL)      /*!< Reset value of CSNPOL register.                                      */

/* CSNPOL0 @Bit 0 : Polarity of CSN output */
  #define SPIM_CSNPOL_CSNPOL0_Pos (0UL)              /*!< Position of CSNPOL0 field.                                           */
  #define SPIM_CSNPOL_CSNPOL0_Msk (0x1UL << SPIM_CSNPOL_CSNPOL0_Pos) /*!< Bit mask of CSNPOL0 field.                           */
  #define SPIM_CSNPOL_CSNPOL0_Min (0x0UL)            /*!< Min enumerator value of CSNPOL0 field.                               */
  #define SPIM_CSNPOL_CSNPOL0_Max (0x1UL)            /*!< Max enumerator value of CSNPOL0 field.                               */
  #define SPIM_CSNPOL_CSNPOL0_LOW (0x0UL)            /*!< Active low (idle state high)                                         */
  #define SPIM_CSNPOL_CSNPOL0_HIGH (0x1UL)           /*!< Active high (idle state low)                                         */


/* SPIM_ORC: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than
              TXD.MAXCNT */

  #define SPIM_ORC_ResetValue (0x00000000UL)         /*!< Reset value of ORC register.                                         */

/* ORC @Bits 0..7 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than
                    TXD.MAXCNT. */

  #define SPIM_ORC_ORC_Pos (0UL)                     /*!< Position of ORC field.                                               */
  #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field.                                            */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           SPIS                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct SPIS_TASKS_DMA_RX ================================================= */
/**
  * @brief RX [SPIS_TASKS_DMA_RX] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit
                                                                         in the CONFIG register.*/
  __OM  uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n]
                                                                         bit in the CONFIG register.*/
} NRF_SPIS_TASKS_DMA_RX_Type;                        /*!< Size = 32 (0x020)                                                    */

/* SPIS_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                                  */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                                 */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                                 */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.                 */

/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field.                              */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask
                                                                            of ENABLEMATCH field.*/
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field.                */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field.                */
  #define SPIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                          */


/* SPIS_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                                */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                               */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                               */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.               */

/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field.                           */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit
                                                                            mask of DISABLEMATCH field.*/
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field.             */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field.             */
  #define SPIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                        */



/* ================================================== Struct SPIS_TASKS_DMA ================================================== */
/**
  * @brief TASKS_DMA [SPIS_TASKS_DMA] Peripheral tasks.
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __OM  NRF_SPIS_TASKS_DMA_RX_Type RX;               /*!< (@ 0x00000008) Peripheral tasks.                                     */
} NRF_SPIS_TASKS_DMA_Type;                           /*!< Size = 40 (0x028)                                                    */


/* ============================================== Struct SPIS_SUBSCRIBE_DMA_RX =============================================== */
/**
  * @brief RX [SPIS_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n]       */
  __IOM uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n]      */
} NRF_SPIS_SUBSCRIBE_DMA_RX_Type;                    /*!< Size = 32 (0x020)                                                    */

/* SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                              */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                             */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                             */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.             */

/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                      */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                  */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                   */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                           */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                              */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                              */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                      */
  #define SPIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                        */


/* SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                            */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                           */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                           */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.           */

/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                     */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                 */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                  */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                          */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                             */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                             */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                     */
  #define SPIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                       */



/* ================================================ Struct SPIS_SUBSCRIBE_DMA ================================================ */
/**
  * @brief SUBSCRIBE_DMA [SPIS_SUBSCRIBE_DMA] Subscribe configuration for tasks
  */
typedef struct {
  __IM  uint32_t  RESERVED[2];
  __IOM NRF_SPIS_SUBSCRIBE_DMA_RX_Type RX;           /*!< (@ 0x00000008) Subscribe configuration for tasks                     */
} NRF_SPIS_SUBSCRIBE_DMA_Type;                       /*!< Size = 40 (0x028)                                                    */


/* ================================================ Struct SPIS_EVENTS_DMA_RX ================================================ */
/**
  * @brief RX [SPIS_EVENTS_DMA_RX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus.        */
} NRF_SPIS_EVENTS_DMA_RX_Type;                       /*!< Size = 28 (0x01C)                                                    */

/* SPIS_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */
  #define SPIS_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define SPIS_EVENTS_DMA_RX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define SPIS_EVENTS_DMA_RX_END_END_Msk (0x1UL << SPIS_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define SPIS_EVENTS_DMA_RX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define SPIS_EVENTS_DMA_RX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define SPIS_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define SPIS_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* SPIS_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define SPIS_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define SPIS_EVENTS_DMA_RX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define SPIS_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << SPIS_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define SPIS_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define SPIS_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define SPIS_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define SPIS_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* SPIS_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */
  #define SPIS_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define SPIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */


/* SPIS_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */
  #define SPIS_EVENTS_DMA_RX_MATCH_MaxCount (4UL)    /*!< Max size of MATCH[4] array.                                          */
  #define SPIS_EVENTS_DMA_RX_MATCH_MaxIndex (3UL)    /*!< Max index of MATCH[4] array.                                         */
  #define SPIS_EVENTS_DMA_RX_MATCH_MinIndex (0UL)    /*!< Min index of MATCH[4] array.                                         */
  #define SPIS_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                            */

/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */
  #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL)   /*!< Position of MATCH field.                                             */
  #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << SPIS_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field.       */
  #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field.                                 */
  #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field.                                 */
  #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define SPIS_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated                                                */



/* ================================================ Struct SPIS_EVENTS_DMA_TX ================================================ */
/**
  * @brief TX [SPIS_EVENTS_DMA_TX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
} NRF_SPIS_EVENTS_DMA_TX_Type;                       /*!< Size = 12 (0x00C)                                                    */

/* SPIS_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */
  #define SPIS_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define SPIS_EVENTS_DMA_TX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define SPIS_EVENTS_DMA_TX_END_END_Msk (0x1UL << SPIS_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define SPIS_EVENTS_DMA_TX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define SPIS_EVENTS_DMA_TX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define SPIS_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define SPIS_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* SPIS_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define SPIS_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define SPIS_EVENTS_DMA_TX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define SPIS_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << SPIS_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define SPIS_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define SPIS_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define SPIS_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define SPIS_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* SPIS_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */
  #define SPIS_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define SPIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */



/* ================================================= Struct SPIS_EVENTS_DMA ================================================== */
/**
  * @brief EVENTS_DMA [SPIS_EVENTS_DMA] Peripheral events.
  */
typedef struct {
  __IOM NRF_SPIS_EVENTS_DMA_RX_Type RX;              /*!< (@ 0x00000000) Peripheral events.                                    */
  __IOM NRF_SPIS_EVENTS_DMA_TX_Type TX;              /*!< (@ 0x0000001C) Peripheral events.                                    */
} NRF_SPIS_EVENTS_DMA_Type;                          /*!< Size = 40 (0x028)                                                    */


/* =============================================== Struct SPIS_PUBLISH_DMA_RX ================================================ */
/**
  * @brief RX [SPIS_PUBLISH_DMA_RX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Publish configuration for event MATCH[n]              */
} NRF_SPIS_PUBLISH_DMA_RX_Type;                      /*!< Size = 28 (0x01C)                                                    */

/* SPIS_PUBLISH_DMA_RX_END: Publish configuration for event END */
  #define SPIS_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define SPIS_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_DMA_RX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define SPIS_PUBLISH_DMA_RX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_RX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define SPIS_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* SPIS_PUBLISH_DMA_RX_READY: Publish configuration for event READY */
  #define SPIS_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define SPIS_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_DMA_RX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define SPIS_PUBLISH_DMA_RX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_RX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define SPIS_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* SPIS_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define SPIS_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */


/* SPIS_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */
  #define SPIS_PUBLISH_DMA_RX_MATCH_MaxCount (4UL)   /*!< Max size of MATCH[4] array.                                          */
  #define SPIS_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL)   /*!< Max index of MATCH[4] array.                                         */
  #define SPIS_PUBLISH_DMA_RX_MATCH_MinIndex (0UL)   /*!< Min index of MATCH[4] array.                                         */
  #define SPIS_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */
  #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define SPIS_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field.              */
  #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define SPIS_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */



/* =============================================== Struct SPIS_PUBLISH_DMA_TX ================================================ */
/**
  * @brief TX [SPIS_PUBLISH_DMA_TX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
} NRF_SPIS_PUBLISH_DMA_TX_Type;                      /*!< Size = 12 (0x00C)                                                    */

/* SPIS_PUBLISH_DMA_TX_END: Publish configuration for event END */
  #define SPIS_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define SPIS_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_DMA_TX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define SPIS_PUBLISH_DMA_TX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_TX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define SPIS_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* SPIS_PUBLISH_DMA_TX_READY: Publish configuration for event READY */
  #define SPIS_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define SPIS_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_DMA_TX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define SPIS_PUBLISH_DMA_TX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_TX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define SPIS_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* SPIS_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define SPIS_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */



/* ================================================= Struct SPIS_PUBLISH_DMA ================================================= */
/**
  * @brief PUBLISH_DMA [SPIS_PUBLISH_DMA] Publish configuration for events
  */
typedef struct {
  __IOM NRF_SPIS_PUBLISH_DMA_RX_Type RX;             /*!< (@ 0x00000000) Publish configuration for events                      */
  __IOM NRF_SPIS_PUBLISH_DMA_TX_Type TX;             /*!< (@ 0x0000001C) Publish configuration for events                      */
} NRF_SPIS_PUBLISH_DMA_Type;                         /*!< Size = 40 (0x028)                                                    */


/* ==================================================== Struct SPIS_PSEL ===================================================== */
/**
  * @brief PSEL [SPIS_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  SCK;                               /*!< (@ 0x00000000) Pin select for SCK                                    */
  __IOM uint32_t  MISO;                              /*!< (@ 0x00000004) Pin select for SDO signal                             */
  __IOM uint32_t  MOSI;                              /*!< (@ 0x00000008) Pin select for SDI signal                             */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  CSN;                               /*!< (@ 0x00000010) Pin select for CSN signal                             */
} NRF_SPIS_PSEL_Type;                                /*!< Size = 20 (0x014)                                                    */

/* SPIS_PSEL_SCK: Pin select for SCK */
  #define SPIS_PSEL_SCK_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCK register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define SPIS_PSEL_SCK_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define SPIS_PSEL_SCK_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define SPIS_PSEL_SCK_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIS_PSEL_SCK_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define SPIS_PSEL_SCK_PORT_Msk (0x7UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define SPIS_PSEL_SCK_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define SPIS_PSEL_SCK_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIS_PSEL_SCK_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define SPIS_PSEL_SCK_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_SCK_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* SPIS_PSEL_MISO: Pin select for SDO signal */
  #define SPIS_PSEL_MISO_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MISO register.                                        */

/* PIN @Bits 0..4 : Pin number */
  #define SPIS_PSEL_MISO_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define SPIS_PSEL_MISO_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define SPIS_PSEL_MISO_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIS_PSEL_MISO_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define SPIS_PSEL_MISO_PORT_Msk (0x7UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define SPIS_PSEL_MISO_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define SPIS_PSEL_MISO_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIS_PSEL_MISO_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define SPIS_PSEL_MISO_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_MISO_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */


/* SPIS_PSEL_MOSI: Pin select for SDI signal */
  #define SPIS_PSEL_MOSI_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MOSI register.                                        */

/* PIN @Bits 0..4 : Pin number */
  #define SPIS_PSEL_MOSI_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define SPIS_PSEL_MOSI_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define SPIS_PSEL_MOSI_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIS_PSEL_MOSI_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define SPIS_PSEL_MOSI_PORT_Msk (0x7UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define SPIS_PSEL_MOSI_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define SPIS_PSEL_MOSI_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define SPIS_PSEL_MOSI_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_MOSI_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */


/* SPIS_PSEL_CSN: Pin select for CSN signal */
  #define SPIS_PSEL_CSN_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of CSN register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define SPIS_PSEL_CSN_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define SPIS_PSEL_CSN_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define SPIS_PSEL_CSN_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define SPIS_PSEL_CSN_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define SPIS_PSEL_CSN_PORT_Msk (0x7UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define SPIS_PSEL_CSN_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define SPIS_PSEL_CSN_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define SPIS_PSEL_CSN_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define SPIS_PSEL_CSN_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_CSN_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */



/* ================================================ Struct SPIS_DMA_RX_MATCH ================================================= */
/**
  * @brief MATCH [SPIS_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Configure individual match events                     */
  __IOM uint32_t  CANDIDATE[4];                      /*!< (@ 0x00000004) The data to look for - any match will trigger the
                                                                         MATCH[n] event, if enabled.*/
} NRF_SPIS_DMA_RX_MATCH_Type;                        /*!< Size = 20 (0x014)                                                    */

/* SPIS_DMA_RX_MATCH_CONFIG: Configure individual match events */
  #define SPIS_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                              */

/* ENABLE0 @Bit 0 : Enable match filter 0 */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field.                                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE1 @Bit 1 : Enable match filter 1 */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field.                                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE2 @Bit 2 : Enable match filter 2 */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field.                                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE3 @Bit 3 : Enable match filter 3 */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field.                                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                             */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define SPIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field.                                        */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0
                                                                            field.*/
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field.                                        */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1
                                                                            field.*/
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field.                                        */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2
                                                                            field.*/
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field.                                        */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3
                                                                            field.*/
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field.                           */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define SPIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */


/* SPIS_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */
  #define SPIS_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array.                                      */
  #define SPIS_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array.                                     */
  #define SPIS_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array.                                     */
  #define SPIS_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register.                     */

/* DATA @Bits 0..31 : Data to look for */
  #define SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field.                                              */
  #define SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA
                                                                            field.*/



/* =================================================== Struct SPIS_DMA_RX ==================================================== */
/**
  * @brief RX [SPIS_DMA_RX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
  __IOM NRF_SPIS_DMA_RX_MATCH_Type MATCH;            /*!< (@ 0x00000024) Registers to control the behavior of the pattern
                                                                         matcher engine*/
} NRF_SPIS_DMA_RX_Type;                              /*!< Size = 56 (0x038)                                                    */

/* SPIS_DMA_RX_PTR: RAM buffer start address */
  #define SPIS_DMA_RX_PTR_ResetValue (0x20000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define SPIS_DMA_RX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define SPIS_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* SPIS_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */
  #define SPIS_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define SPIS_DMA_RX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define SPIS_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define SPIS_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define SPIS_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* SPIS_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define SPIS_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define SPIS_DMA_RX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define SPIS_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define SPIS_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define SPIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* SPIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define SPIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* SPIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define SPIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* =================================================== Struct SPIS_DMA_TX ==================================================== */
/**
  * @brief TX [SPIS_DMA_TX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_SPIS_DMA_TX_Type;                              /*!< Size = 36 (0x024)                                                    */

/* SPIS_DMA_TX_PTR: RAM buffer start address */
  #define SPIS_DMA_TX_PTR_ResetValue (0x20000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define SPIS_DMA_TX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define SPIS_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* SPIS_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */
  #define SPIS_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define SPIS_DMA_TX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define SPIS_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define SPIS_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define SPIS_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* SPIS_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define SPIS_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define SPIS_DMA_TX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define SPIS_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define SPIS_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define SPIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* SPIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define SPIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* SPIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define SPIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* ===================================================== Struct SPIS_DMA ===================================================== */
/**
  * @brief DMA [SPIS_DMA] (unspecified)
  */
typedef struct {
  __IOM NRF_SPIS_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
  __IOM NRF_SPIS_DMA_TX_Type TX;                     /*!< (@ 0x00000038) (unspecified)                                         */
} NRF_SPIS_DMA_Type;                                 /*!< Size = 92 (0x05C)                                                    */

/* ======================================================= Struct SPIS ======================================================= */
/**
  * @brief SPI Slave
  */
  typedef struct {                                   /*!< SPIS Structure                                                       */
    __IM uint32_t RESERVED[5];
    __OM uint32_t TASKS_ACQUIRE;                     /*!< (@ 0x00000014) Acquire SPI semaphore                                 */
    __OM uint32_t TASKS_RELEASE;                     /*!< (@ 0x00000018) Release SPI semaphore, enabling the SPI slave to
                                                                         acquire it*/
    __IM uint32_t RESERVED1[3];
    __OM NRF_SPIS_TASKS_DMA_Type TASKS_DMA;          /*!< (@ 0x00000028) Peripheral tasks.                                     */
    __IM uint32_t RESERVED2[17];
    __IOM uint32_t SUBSCRIBE_ACQUIRE;                /*!< (@ 0x00000094) Subscribe configuration for task ACQUIRE              */
    __IOM uint32_t SUBSCRIBE_RELEASE;                /*!< (@ 0x00000098) Subscribe configuration for task RELEASE              */
    __IM uint32_t RESERVED3[3];
    __IOM NRF_SPIS_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks                     */
    __IM uint32_t RESERVED4[13];
    __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000104) Granted transaction completed                         */
    __IM uint32_t RESERVED5[4];
    __IOM uint32_t EVENTS_ACQUIRED;                  /*!< (@ 0x00000118) Semaphore acquired                                    */
    __IM uint32_t RESERVED6[12];
    __IOM NRF_SPIS_EVENTS_DMA_Type EVENTS_DMA;       /*!< (@ 0x0000014C) Peripheral events.                                    */
    __IM uint32_t RESERVED7[4];
    __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000184) Publish configuration for event END                   */
    __IM uint32_t RESERVED8[4];
    __IOM uint32_t PUBLISH_ACQUIRED;                 /*!< (@ 0x00000198) Publish configuration for event ACQUIRED              */
    __IM uint32_t RESERVED9[12];
    __IOM NRF_SPIS_PUBLISH_DMA_Type PUBLISH_DMA;     /*!< (@ 0x000001CC) Publish configuration for events                      */
    __IM uint32_t RESERVED10[3];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED11[64];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED12[61];
    __IM uint32_t SEMSTAT;                           /*!< (@ 0x00000400) Semaphore status register                             */
    __IM uint32_t RESERVED13[15];
    __IOM uint32_t STATUS;                           /*!< (@ 0x00000440) Status from last transaction                          */
    __IM uint32_t RESERVED14[47];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable SPI slave                                      */
    __IM uint32_t RESERVED15[20];
    __IOM uint32_t CONFIG;                           /*!< (@ 0x00000554) Configuration register                                */
    __IM uint32_t RESERVED16;
    __IOM uint32_t DEF;                              /*!< (@ 0x0000055C) Default character. Character clocked out in case of an
                                                                         ignored transaction.*/
    __IM uint32_t RESERVED17[24];
    __IOM uint32_t ORC;                              /*!< (@ 0x000005C0) Over-read character                                   */
    __IM uint32_t RESERVED18[15];
    __IOM NRF_SPIS_PSEL_Type PSEL;                   /*!< (@ 0x00000600) (unspecified)                                         */
    __IM uint32_t RESERVED19[59];
    __IOM NRF_SPIS_DMA_Type DMA;                     /*!< (@ 0x00000700) (unspecified)                                         */
  } NRF_SPIS_Type;                                   /*!< Size = 1884 (0x75C)                                                  */

/* SPIS_TASKS_ACQUIRE: Acquire SPI semaphore */
  #define SPIS_TASKS_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ACQUIRE register.                             */

/* TASKS_ACQUIRE @Bit 0 : Acquire SPI semaphore */
  #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field.                                     */
  #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE
                                                                            field.*/
  #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Min (0x1UL) /*!< Min enumerator value of TASKS_ACQUIRE field.                       */
  #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Max (0x1UL) /*!< Max enumerator value of TASKS_ACQUIRE field.                       */
  #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task                                                   */


/* SPIS_TASKS_RELEASE: Release SPI semaphore, enabling the SPI slave to acquire it */
  #define SPIS_TASKS_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RELEASE register.                             */

/* TASKS_RELEASE @Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
  #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field.                                     */
  #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE
                                                                            field.*/
  #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Min (0x1UL) /*!< Min enumerator value of TASKS_RELEASE field.                       */
  #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Max (0x1UL) /*!< Max enumerator value of TASKS_RELEASE field.                       */
  #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task                                                   */


/* SPIS_SUBSCRIBE_ACQUIRE: Subscribe configuration for task ACQUIRE */
  #define SPIS_SUBSCRIBE_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACQUIRE register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task ACQUIRE will subscribe to */
  #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field.                    */
  #define SPIS_SUBSCRIBE_ACQUIRE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define SPIS_SUBSCRIBE_ACQUIRE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* SPIS_SUBSCRIBE_RELEASE: Subscribe configuration for task RELEASE */
  #define SPIS_SUBSCRIBE_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RELEASE register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task RELEASE will subscribe to */
  #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field.                    */
  #define SPIS_SUBSCRIBE_RELEASE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define SPIS_SUBSCRIBE_RELEASE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* SPIS_EVENTS_END: Granted transaction completed */
  #define SPIS_EVENTS_END_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_END register.                                  */

/* EVENTS_END @Bit 0 : Granted transaction completed */
  #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL)       /*!< Position of EVENTS_END field.                                        */
  #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.          */
  #define SPIS_EVENTS_END_EVENTS_END_Min (0x0UL)     /*!< Min enumerator value of EVENTS_END field.                            */
  #define SPIS_EVENTS_END_EVENTS_END_Max (0x1UL)     /*!< Max enumerator value of EVENTS_END field.                            */
  #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                    */


/* SPIS_EVENTS_ACQUIRED: Semaphore acquired */
  #define SPIS_EVENTS_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACQUIRED register.                         */

/* EVENTS_ACQUIRED @Bit 0 : Semaphore acquired */
  #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field.                               */
  #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of
                                                                            EVENTS_ACQUIRED field.*/
  #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACQUIRED field.                 */
  #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACQUIRED field.                 */
  #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated                                          */


/* SPIS_PUBLISH_END: Publish configuration for event END */
  #define SPIS_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define SPIS_PUBLISH_END_CHIDX_Pos (0UL)           /*!< Position of CHIDX field.                                             */
  #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                      */
  #define SPIS_PUBLISH_END_CHIDX_Min (0x00UL)        /*!< Min value of CHIDX field.                                            */
  #define SPIS_PUBLISH_END_CHIDX_Max (0xFFUL)        /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_END_EN_Pos (31UL)             /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                */
  #define SPIS_PUBLISH_END_EN_Min (0x0UL)            /*!< Min enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_END_EN_Max (0x1UL)            /*!< Max enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_END_EN_Disabled (0x0UL)       /*!< Disable publishing                                                   */
  #define SPIS_PUBLISH_END_EN_Enabled (0x1UL)        /*!< Enable publishing                                                    */


/* SPIS_PUBLISH_ACQUIRED: Publish configuration for event ACQUIRED */
  #define SPIS_PUBLISH_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACQUIRED register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that event ACQUIRED will publish to */
  #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define SPIS_PUBLISH_ACQUIRED_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define SPIS_PUBLISH_ACQUIRED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field.                      */
  #define SPIS_PUBLISH_ACQUIRED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_ACQUIRED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* SPIS_SHORTS: Shortcuts between local events and tasks */
  #define SPIS_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* END_ACQUIRE @Bit 2 : Shortcut between event END and task ACQUIRE */
  #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL)          /*!< Position of END_ACQUIRE field.                                       */
  #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field.               */
  #define SPIS_SHORTS_END_ACQUIRE_Min (0x0UL)        /*!< Min enumerator value of END_ACQUIRE field.                           */
  #define SPIS_SHORTS_END_ACQUIRE_Max (0x1UL)        /*!< Max enumerator value of END_ACQUIRE field.                           */
  #define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
  #define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL)    /*!< Enable shortcut                                                      */

/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows
                                               daisy-chaining match events. */

  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.   */
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows
                                               daisy-chaining match events. */

  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.   */
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows
                                               daisy-chaining match events. */

  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.   */
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows
                                               daisy-chaining match events. */

  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.   */
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3
                                                                            field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define SPIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                  */


/* SPIS_INTENSET: Enable interrupt */
  #define SPIS_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* END @Bit 1 : Write '1' to enable interrupt for event END */
  #define SPIS_INTENSET_END_Pos (1UL)                /*!< Position of END field.                                               */
  #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field.                                   */
  #define SPIS_INTENSET_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
  #define SPIS_INTENSET_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
  #define SPIS_INTENSET_END_Set (0x1UL)              /*!< Enable                                                               */
  #define SPIS_INTENSET_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */

/* ACQUIRED @Bit 6 : Write '1' to enable interrupt for event ACQUIRED */
  #define SPIS_INTENSET_ACQUIRED_Pos (6UL)           /*!< Position of ACQUIRED field.                                          */
  #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field.                    */
  #define SPIS_INTENSET_ACQUIRED_Min (0x0UL)         /*!< Min enumerator value of ACQUIRED field.                              */
  #define SPIS_INTENSET_ACQUIRED_Max (0x1UL)         /*!< Max enumerator value of ACQUIRED field.                              */
  #define SPIS_INTENSET_ACQUIRED_Set (0x1UL)         /*!< Enable                                                               */
  #define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */
  #define SPIS_INTENSET_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define SPIS_INTENSET_DMARXEND_Msk (0x1UL << SPIS_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define SPIS_INTENSET_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define SPIS_INTENSET_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define SPIS_INTENSET_DMARXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define SPIS_INTENSET_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */
  #define SPIS_INTENSET_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define SPIS_INTENSET_DMARXREADY_Msk (0x1UL << SPIS_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define SPIS_INTENSET_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define SPIS_INTENSET_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define SPIS_INTENSET_DMARXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define SPIS_INTENSET_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */
  #define SPIS_INTENSET_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define SPIS_INTENSET_DMARXBUSERROR_Msk (0x1UL << SPIS_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define SPIS_INTENSET_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define SPIS_INTENSET_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define SPIS_INTENSET_DMARXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define SPIS_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIS_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */
  #define SPIS_INTENSET_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define SPIS_INTENSET_DMARXMATCH0_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define SPIS_INTENSET_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define SPIS_INTENSET_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define SPIS_INTENSET_DMARXMATCH0_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIS_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */
  #define SPIS_INTENSET_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define SPIS_INTENSET_DMARXMATCH1_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define SPIS_INTENSET_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define SPIS_INTENSET_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define SPIS_INTENSET_DMARXMATCH1_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIS_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */
  #define SPIS_INTENSET_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define SPIS_INTENSET_DMARXMATCH2_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define SPIS_INTENSET_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define SPIS_INTENSET_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define SPIS_INTENSET_DMARXMATCH2_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIS_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */
  #define SPIS_INTENSET_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define SPIS_INTENSET_DMARXMATCH3_Msk (0x1UL << SPIS_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define SPIS_INTENSET_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define SPIS_INTENSET_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define SPIS_INTENSET_DMARXMATCH3_Set (0x1UL)      /*!< Enable                                                               */
  #define SPIS_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */
  #define SPIS_INTENSET_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define SPIS_INTENSET_DMATXEND_Msk (0x1UL << SPIS_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define SPIS_INTENSET_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define SPIS_INTENSET_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define SPIS_INTENSET_DMATXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define SPIS_INTENSET_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */
  #define SPIS_INTENSET_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define SPIS_INTENSET_DMATXREADY_Msk (0x1UL << SPIS_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define SPIS_INTENSET_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define SPIS_INTENSET_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define SPIS_INTENSET_DMATXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define SPIS_INTENSET_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIS_INTENSET_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */
  #define SPIS_INTENSET_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define SPIS_INTENSET_DMATXBUSERROR_Msk (0x1UL << SPIS_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define SPIS_INTENSET_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define SPIS_INTENSET_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define SPIS_INTENSET_DMATXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define SPIS_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIS_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* SPIS_INTENCLR: Disable interrupt */
  #define SPIS_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* END @Bit 1 : Write '1' to disable interrupt for event END */
  #define SPIS_INTENCLR_END_Pos (1UL)                /*!< Position of END field.                                               */
  #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field.                                   */
  #define SPIS_INTENCLR_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
  #define SPIS_INTENCLR_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
  #define SPIS_INTENCLR_END_Clear (0x1UL)            /*!< Disable                                                              */
  #define SPIS_INTENCLR_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */

/* ACQUIRED @Bit 6 : Write '1' to disable interrupt for event ACQUIRED */
  #define SPIS_INTENCLR_ACQUIRED_Pos (6UL)           /*!< Position of ACQUIRED field.                                          */
  #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field.                    */
  #define SPIS_INTENCLR_ACQUIRED_Min (0x0UL)         /*!< Min enumerator value of ACQUIRED field.                              */
  #define SPIS_INTENCLR_ACQUIRED_Max (0x1UL)         /*!< Max enumerator value of ACQUIRED field.                              */
  #define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL)       /*!< Disable                                                              */
  #define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */
  #define SPIS_INTENCLR_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define SPIS_INTENCLR_DMARXEND_Msk (0x1UL << SPIS_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define SPIS_INTENCLR_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define SPIS_INTENCLR_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define SPIS_INTENCLR_DMARXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */
  #define SPIS_INTENCLR_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define SPIS_INTENCLR_DMARXREADY_Msk (0x1UL << SPIS_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define SPIS_INTENCLR_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define SPIS_INTENCLR_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define SPIS_INTENCLR_DMARXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */
  #define SPIS_INTENCLR_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define SPIS_INTENCLR_DMARXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define SPIS_INTENCLR_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define SPIS_INTENCLR_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define SPIS_INTENCLR_DMARXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIS_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */
  #define SPIS_INTENCLR_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define SPIS_INTENCLR_DMARXMATCH0_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define SPIS_INTENCLR_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH0_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */
  #define SPIS_INTENCLR_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define SPIS_INTENCLR_DMARXMATCH1_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define SPIS_INTENCLR_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH1_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */
  #define SPIS_INTENCLR_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define SPIS_INTENCLR_DMARXMATCH2_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define SPIS_INTENCLR_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH2_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */
  #define SPIS_INTENCLR_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define SPIS_INTENCLR_DMARXMATCH3_Msk (0x1UL << SPIS_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define SPIS_INTENCLR_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define SPIS_INTENCLR_DMARXMATCH3_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */
  #define SPIS_INTENCLR_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define SPIS_INTENCLR_DMATXEND_Msk (0x1UL << SPIS_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define SPIS_INTENCLR_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define SPIS_INTENCLR_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define SPIS_INTENCLR_DMATXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */
  #define SPIS_INTENCLR_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define SPIS_INTENCLR_DMATXREADY_Msk (0x1UL << SPIS_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define SPIS_INTENCLR_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define SPIS_INTENCLR_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define SPIS_INTENCLR_DMATXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define SPIS_INTENCLR_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */
  #define SPIS_INTENCLR_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define SPIS_INTENCLR_DMATXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define SPIS_INTENCLR_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define SPIS_INTENCLR_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define SPIS_INTENCLR_DMATXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define SPIS_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define SPIS_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* SPIS_SEMSTAT: Semaphore status register */
  #define SPIS_SEMSTAT_ResetValue (0x00000001UL)     /*!< Reset value of SEMSTAT register.                                     */

/* SEMSTAT @Bits 0..1 : Semaphore status */
  #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL)             /*!< Position of SEMSTAT field.                                           */
  #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field.                         */
  #define SPIS_SEMSTAT_SEMSTAT_Min (0x0UL)           /*!< Min enumerator value of SEMSTAT field.                               */
  #define SPIS_SEMSTAT_SEMSTAT_Max (0x3UL)           /*!< Max enumerator value of SEMSTAT field.                               */
  #define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL)          /*!< Semaphore is free                                                    */
  #define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL)           /*!< Semaphore is assigned to CPU                                         */
  #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL)          /*!< Semaphore is assigned to SPI slave                                   */
  #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL)    /*!< Semaphore is assigned to SPI but a handover to the CPU is pending    */


/* SPIS_STATUS: Status from last transaction */
  #define SPIS_STATUS_ResetValue (0x00000000UL)      /*!< Reset value of STATUS register.                                      */

/* OVERREAD @Bit 0 : TX buffer over-read detected, and prevented */
  #define SPIS_STATUS_OVERREAD_Pos (0UL)             /*!< Position of OVERREAD field.                                          */
  #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field.                        */
  #define SPIS_STATUS_OVERREAD_Min (0x0UL)           /*!< Min enumerator value of OVERREAD field.                              */
  #define SPIS_STATUS_OVERREAD_Max (0x1UL)           /*!< Max enumerator value of OVERREAD field.                              */
  #define SPIS_STATUS_OVERREAD_NotPresent (0x0UL)    /*!< Read: error not present                                              */
  #define SPIS_STATUS_OVERREAD_Present (0x1UL)       /*!< Read: error present                                                  */
  #define SPIS_STATUS_OVERREAD_Clear (0x1UL)         /*!< Write: clear error on writing '1'                                    */

/* OVERFLOW @Bit 1 : RX buffer overflow detected, and prevented */
  #define SPIS_STATUS_OVERFLOW_Pos (1UL)             /*!< Position of OVERFLOW field.                                          */
  #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field.                        */
  #define SPIS_STATUS_OVERFLOW_Min (0x0UL)           /*!< Min enumerator value of OVERFLOW field.                              */
  #define SPIS_STATUS_OVERFLOW_Max (0x1UL)           /*!< Max enumerator value of OVERFLOW field.                              */
  #define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL)    /*!< Read: error not present                                              */
  #define SPIS_STATUS_OVERFLOW_Present (0x1UL)       /*!< Read: error present                                                  */
  #define SPIS_STATUS_OVERFLOW_Clear (0x1UL)         /*!< Write: clear error on writing '1'                                    */


/* SPIS_ENABLE: Enable SPI slave */
  #define SPIS_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..3 : Enable or disable SPI slave */
  #define SPIS_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
  #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
  #define SPIS_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
  #define SPIS_ENABLE_ENABLE_Max (0x2UL)             /*!< Max enumerator value of ENABLE field.                                */
  #define SPIS_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable SPI slave                                                    */
  #define SPIS_ENABLE_ENABLE_Enabled (0x2UL)         /*!< Enable SPI slave                                                     */


/* SPIS_CONFIG: Configuration register */
  #define SPIS_CONFIG_ResetValue (0x00000000UL)      /*!< Reset value of CONFIG register.                                      */

/* ORDER @Bit 0 : Bit order */
  #define SPIS_CONFIG_ORDER_Pos (0UL)                /*!< Position of ORDER field.                                             */
  #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field.                                 */
  #define SPIS_CONFIG_ORDER_Min (0x0UL)              /*!< Min enumerator value of ORDER field.                                 */
  #define SPIS_CONFIG_ORDER_Max (0x1UL)              /*!< Max enumerator value of ORDER field.                                 */
  #define SPIS_CONFIG_ORDER_MsbFirst (0x0UL)         /*!< Most significant bit shifted out first                               */
  #define SPIS_CONFIG_ORDER_LsbFirst (0x1UL)         /*!< Least significant bit shifted out first                              */

/* CPHA @Bit 1 : Serial clock (SCK) phase */
  #define SPIS_CONFIG_CPHA_Pos (1UL)                 /*!< Position of CPHA field.                                              */
  #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field.                                    */
  #define SPIS_CONFIG_CPHA_Min (0x0UL)               /*!< Min enumerator value of CPHA field.                                  */
  #define SPIS_CONFIG_CPHA_Max (0x1UL)               /*!< Max enumerator value of CPHA field.                                  */
  #define SPIS_CONFIG_CPHA_Leading (0x0UL)           /*!< Sample on leading edge of clock, shift serial data on trailing edge  */
  #define SPIS_CONFIG_CPHA_Trailing (0x1UL)          /*!< Sample on trailing edge of clock, shift serial data on leading edge  */

/* CPOL @Bit 2 : Serial clock (SCK) polarity */
  #define SPIS_CONFIG_CPOL_Pos (2UL)                 /*!< Position of CPOL field.                                              */
  #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field.                                    */
  #define SPIS_CONFIG_CPOL_Min (0x0UL)               /*!< Min enumerator value of CPOL field.                                  */
  #define SPIS_CONFIG_CPOL_Max (0x1UL)               /*!< Max enumerator value of CPOL field.                                  */
  #define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL)        /*!< Active high                                                          */
  #define SPIS_CONFIG_CPOL_ActiveLow (0x1UL)         /*!< Active low                                                           */


/* SPIS_DEF: Default character. Character clocked out in case of an ignored transaction. */
  #define SPIS_DEF_ResetValue (0x00000000UL)         /*!< Reset value of DEF register.                                         */

/* DEF @Bits 0..7 : Default character. Character clocked out in case of an ignored transaction. */
  #define SPIS_DEF_DEF_Pos (0UL)                     /*!< Position of DEF field.                                               */
  #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field.                                            */


/* SPIS_ORC: Over-read character */
  #define SPIS_ORC_ResetValue (0x00000000UL)         /*!< Reset value of ORC register.                                         */

/* ORC @Bits 0..7 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
  #define SPIS_ORC_ORC_Pos (0UL)                     /*!< Position of ORC field.                                               */
  #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field.                                            */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            SPU                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================= Struct SPU_PERIPHACCERR ================================================= */
/**
  * @brief PERIPHACCERR [SPU_PERIPHACCERR] (unspecified)
  */
typedef struct {
  __IM  uint32_t  ADDRESS;                           /*!< (@ 0x00000000) Address of the transaction that caused first error.   */
} NRF_SPU_PERIPHACCERR_Type;                         /*!< Size = 4 (0x004)                                                     */

/* SPU_PERIPHACCERR_ADDRESS: Address of the transaction that caused first error. */
  #define SPU_PERIPHACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register.                             */

/* ADDRESS @Bits 0..15 : Address */
  #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                           */
  #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk (0xFFFFUL << SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS
                                                                            field.*/



/* ==================================================== Struct SPU_PERIPH ==================================================== */
/**
  * @brief PERIPH [SPU_PERIPH] (unspecified)
  */
typedef struct {
  __IOM uint32_t  PERM;                              /*!< (@ 0x00000000) Get and set the applicable access permissions for the
                                                                         peripheral slave index n*/
} NRF_SPU_PERIPH_Type;                               /*!< Size = 4 (0x004)                                                     */
  #define SPU_PERIPH_MaxCount (64UL)                 /*!< Size of PERIPH[64] array.                                            */
  #define SPU_PERIPH_MaxIndex (63UL)                 /*!< Max index of PERIPH[64] array.                                       */
  #define SPU_PERIPH_MinIndex (0UL)                  /*!< Min index of PERIPH[64] array.                                       */

/* SPU_PERIPH_PERM: Get and set the applicable access permissions for the peripheral slave index n */
  #define SPU_PERIPH_PERM_ResetValue (0x8000002AUL)  /*!< Reset value of PERM register.                                        */

/* SECUREMAPPING @Bits 0..1 : Read capabilities for TrustZone Cortex-M secure attribute */
  #define SPU_PERIPH_PERM_SECUREMAPPING_Pos (0UL)    /*!< Position of SECUREMAPPING field.                                     */
  #define SPU_PERIPH_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPH_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
  #define SPU_PERIPH_PERM_SECUREMAPPING_Min (0x0UL)  /*!< Min enumerator value of SECUREMAPPING field.                         */
  #define SPU_PERIPH_PERM_SECUREMAPPING_Max (0x3UL)  /*!< Max enumerator value of SECUREMAPPING field.                         */
  #define SPU_PERIPH_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
  #define SPU_PERIPH_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral        */
  #define SPU_PERIPH_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is
                                                                    defined by the PERIPH[n].PERM register*/
  #define SPU_PERIPH_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism.            */

/* DMA @Bits 2..3 : Read the peripheral DMA capabilities */
  #define SPU_PERIPH_PERM_DMA_Pos (2UL)              /*!< Position of DMA field.                                               */
  #define SPU_PERIPH_PERM_DMA_Msk (0x3UL << SPU_PERIPH_PERM_DMA_Pos) /*!< Bit mask of DMA field.                               */
  #define SPU_PERIPH_PERM_DMA_Min (0x0UL)            /*!< Min enumerator value of DMA field.                                   */
  #define SPU_PERIPH_PERM_DMA_Max (0x2UL)            /*!< Max enumerator value of DMA field.                                   */
  #define SPU_PERIPH_PERM_DMA_NoDMA (0x0UL)          /*!< Peripheral has no DMA capability                                     */
  #define SPU_PERIPH_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same
                                                               security attribute as assigned to the peripheral*/
  #define SPU_PERIPH_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security
                                                             attribute than the one assigned to the peripheral*/

/* SECATTR @Bit 4 : Peripheral security mapping */
  #define SPU_PERIPH_PERM_SECATTR_Pos (4UL)          /*!< Position of SECATTR field.                                           */
  #define SPU_PERIPH_PERM_SECATTR_Msk (0x1UL << SPU_PERIPH_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field.                   */
  #define SPU_PERIPH_PERM_SECATTR_Min (0x0UL)        /*!< Min enumerator value of SECATTR field.                               */
  #define SPU_PERIPH_PERM_SECATTR_Max (0x1UL)        /*!< Max enumerator value of SECATTR field.                               */
  #define SPU_PERIPH_PERM_SECATTR_Secure (0x1UL)     /*!< Peripheral is mapped in secure peripheral address space              */
  #define SPU_PERIPH_PERM_SECATTR_NonSecure (0x0UL)  /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure
                                                          peripheral address space. If SECUREMAPPING == Split: Peripheral is
                                                          mapped in non-secure and secure peripheral address space.*/

/* DMASEC @Bit 5 : Security attribution for the DMA transfer */
  #define SPU_PERIPH_PERM_DMASEC_Pos (5UL)           /*!< Position of DMASEC field.                                            */
  #define SPU_PERIPH_PERM_DMASEC_Msk (0x1UL << SPU_PERIPH_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field.                      */
  #define SPU_PERIPH_PERM_DMASEC_Min (0x0UL)         /*!< Min enumerator value of DMASEC field.                                */
  #define SPU_PERIPH_PERM_DMASEC_Max (0x1UL)         /*!< Max enumerator value of DMASEC field.                                */
  #define SPU_PERIPH_PERM_DMASEC_Secure (0x1UL)      /*!< DMA transfers initiated by this peripheral have the secure attribute
                                                          set*/
  #define SPU_PERIPH_PERM_DMASEC_NonSecure (0x0UL)   /*!< DMA transfers initiated by this peripheral have the non-secure
                                                          attribute set*/

/* LOCK @Bit 8 : Register lock */
  #define SPU_PERIPH_PERM_LOCK_Pos (8UL)             /*!< Position of LOCK field.                                              */
  #define SPU_PERIPH_PERM_LOCK_Msk (0x1UL << SPU_PERIPH_PERM_LOCK_Pos) /*!< Bit mask of LOCK field.                            */
  #define SPU_PERIPH_PERM_LOCK_Min (0x0UL)           /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_PERIPH_PERM_LOCK_Max (0x1UL)           /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_PERIPH_PERM_LOCK_Unlocked (0x0UL)      /*!< This register can be updated                                         */
  #define SPU_PERIPH_PERM_LOCK_Locked (0x1UL)        /*!< The content of this register can not be changed until the next reset */

/* PRESENT @Bit 31 : Indicates if a peripheral is present with peripheral slave index n */
  #define SPU_PERIPH_PERM_PRESENT_Pos (31UL)         /*!< Position of PRESENT field.                                           */
  #define SPU_PERIPH_PERM_PRESENT_Msk (0x1UL << SPU_PERIPH_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field.                   */
  #define SPU_PERIPH_PERM_PRESENT_Min (0x0UL)        /*!< Min enumerator value of PRESENT field.                               */
  #define SPU_PERIPH_PERM_PRESENT_Max (0x1UL)        /*!< Max enumerator value of PRESENT field.                               */
  #define SPU_PERIPH_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present                                            */
  #define SPU_PERIPH_PERM_PRESENT_IsPresent (0x1UL)  /*!< Peripheral is present                                                */



/* ================================================ Struct SPU_FEATURE_DPPIC ================================================= */
/**
  * @brief DPPIC [SPU_FEATURE_DPPIC] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CH[24];                            /*!< (@ 0x00000000) Security configuration for channel n of DPPIC         */
  __IOM uint32_t  CHG[8];                            /*!< (@ 0x00000060) Security configuration for channel group n of DPPIC   */
} NRF_SPU_FEATURE_DPPIC_Type;                        /*!< Size = 128 (0x080)                                                   */

/* SPU_FEATURE_DPPIC_CH: Security configuration for channel n of DPPIC */
  #define SPU_FEATURE_DPPIC_CH_MaxCount (24UL)       /*!< Max size of CH[24] array.                                            */
  #define SPU_FEATURE_DPPIC_CH_MaxIndex (23UL)       /*!< Max index of CH[24] array.                                           */
  #define SPU_FEATURE_DPPIC_CH_MinIndex (0UL)        /*!< Min index of CH[24] array.                                           */
  #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[24] register.                                  */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_DPPIC_CH_SECATTR_Pos (4UL)     /*!< Position of SECATTR field.                                           */
  #define SPU_FEATURE_DPPIC_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field.         */
  #define SPU_FEATURE_DPPIC_CH_SECATTR_Min (0x0UL)   /*!< Min enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_DPPIC_CH_SECATTR_Max (0x1UL)   /*!< Max enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_DPPIC_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                        */
  #define SPU_FEATURE_DPPIC_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_DPPIC_CH_LOCK_Pos (8UL)        /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_DPPIC_CH_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_LOCK_Pos) /*!< Bit mask of LOCK field.                  */
  #define SPU_FEATURE_DPPIC_CH_LOCK_Min (0x0UL)      /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_DPPIC_CH_LOCK_Max (0x1UL)      /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_DPPIC_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                   */
  #define SPU_FEATURE_DPPIC_CH_LOCK_Locked (0x1UL)   /*!< Feature permissions can not be changed until the next reset          */


/* SPU_FEATURE_DPPIC_CHG: Security configuration for channel group n of DPPIC */
  #define SPU_FEATURE_DPPIC_CHG_MaxCount (8UL)       /*!< Max size of CHG[8] array.                                            */
  #define SPU_FEATURE_DPPIC_CHG_MaxIndex (7UL)       /*!< Max index of CHG[8] array.                                           */
  #define SPU_FEATURE_DPPIC_CHG_MinIndex (0UL)       /*!< Min index of CHG[8] array.                                           */
  #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00100010UL) /*!< Reset value of CHG[8] register.                                 */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_DPPIC_CHG_SECATTR_Pos (4UL)    /*!< Position of SECATTR field.                                           */
  #define SPU_FEATURE_DPPIC_CHG_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_SECATTR_Pos) /*!< Bit mask of SECATTR field.       */
  #define SPU_FEATURE_DPPIC_CHG_SECATTR_Min (0x0UL)  /*!< Min enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_DPPIC_CHG_SECATTR_Max (0x1UL)  /*!< Max enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_DPPIC_CHG_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                       */
  #define SPU_FEATURE_DPPIC_CHG_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                               */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_DPPIC_CHG_LOCK_Pos (8UL)       /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_DPPIC_CHG_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_LOCK_Pos) /*!< Bit mask of LOCK field.                */
  #define SPU_FEATURE_DPPIC_CHG_LOCK_Min (0x0UL)     /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_DPPIC_CHG_LOCK_Max (0x1UL)     /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_DPPIC_CHG_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                  */
  #define SPU_FEATURE_DPPIC_CHG_LOCK_Locked (0x1UL)  /*!< Feature permissions can not be changed until the next reset          */



/* ================================================ Struct SPU_FEATURE_GPIOTE ================================================ */
/**
  * @brief GPIOTE [SPU_FEATURE_GPIOTE] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CH[8];                             /*!< (@ 0x00000000) Security configuration for channel o of GPIOTE[n]     */
  __IOM uint32_t  INTERRUPT[8];                      /*!< (@ 0x00000020) Security configuration for interrupt o of GPIOTE[n]   */
} NRF_SPU_FEATURE_GPIOTE_Type;                       /*!< Size = 64 (0x040)                                                    */
  #define SPU_FEATURE_GPIOTE_MaxCount (2UL)          /*!< Size of GPIOTE[2] array.                                             */
  #define SPU_FEATURE_GPIOTE_MaxIndex (1UL)          /*!< Max index of GPIOTE[2] array.                                        */
  #define SPU_FEATURE_GPIOTE_MinIndex (0UL)          /*!< Min index of GPIOTE[2] array.                                        */

/* SPU_FEATURE_GPIOTE_CH: Security configuration for channel o of GPIOTE[n] */
  #define SPU_FEATURE_GPIOTE_CH_MaxCount (8UL)       /*!< Max size of CH[8] array.                                             */
  #define SPU_FEATURE_GPIOTE_CH_MaxIndex (7UL)       /*!< Max index of CH[8] array.                                            */
  #define SPU_FEATURE_GPIOTE_CH_MinIndex (0UL)       /*!< Min index of CH[8] array.                                            */
  #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00100010UL) /*!< Reset value of CH[8] register.                                  */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GPIOTE_CH_SECATTR_Pos (4UL)    /*!< Position of SECATTR field.                                           */
  #define SPU_FEATURE_GPIOTE_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field.       */
  #define SPU_FEATURE_GPIOTE_CH_SECATTR_Min (0x0UL)  /*!< Min enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GPIOTE_CH_SECATTR_Max (0x1UL)  /*!< Max enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GPIOTE_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                       */
  #define SPU_FEATURE_GPIOTE_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                               */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GPIOTE_CH_LOCK_Pos (8UL)       /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_GPIOTE_CH_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_LOCK_Pos) /*!< Bit mask of LOCK field.                */
  #define SPU_FEATURE_GPIOTE_CH_LOCK_Min (0x0UL)     /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GPIOTE_CH_LOCK_Max (0x1UL)     /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GPIOTE_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                  */
  #define SPU_FEATURE_GPIOTE_CH_LOCK_Locked (0x1UL)  /*!< Feature permissions can not be changed until the next reset          */


/* SPU_FEATURE_GPIOTE_INTERRUPT: Security configuration for interrupt o of GPIOTE[n] */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxCount (8UL) /*!< Max size of INTERRUPT[8] array.                                     */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxIndex (7UL) /*!< Max index of INTERRUPT[8] array.                                    */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[8] array.                                    */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[8] register.                    */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                       */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR
                                                                            field.*/
  #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                         */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                         */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                        */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field.                                             */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field.  */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                               */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                               */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                           */
  #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset    */



/* ================================================= Struct SPU_FEATURE_GPIO ================================================= */
/**
  * @brief GPIO [SPU_FEATURE_GPIO] (unspecified)
  */
typedef struct {
  __IOM uint32_t  PIN[32];                           /*!< (@ 0x00000000) Security configuration for GPIO[n] PIN[o]             */
} NRF_SPU_FEATURE_GPIO_Type;                         /*!< Size = 128 (0x080)                                                   */
  #define SPU_FEATURE_GPIO_MaxCount (3UL)            /*!< Size of GPIO[3] array.                                               */
  #define SPU_FEATURE_GPIO_MaxIndex (2UL)            /*!< Max index of GPIO[3] array.                                          */
  #define SPU_FEATURE_GPIO_MinIndex (0UL)            /*!< Min index of GPIO[3] array.                                          */

/* SPU_FEATURE_GPIO_PIN: Security configuration for GPIO[n] PIN[o] */
  #define SPU_FEATURE_GPIO_PIN_MaxCount (32UL)       /*!< Max size of PIN[32] array.                                           */
  #define SPU_FEATURE_GPIO_PIN_MaxIndex (31UL)       /*!< Max index of PIN[32] array.                                          */
  #define SPU_FEATURE_GPIO_PIN_MinIndex (0UL)        /*!< Min index of PIN[32] array.                                          */
  #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00100010UL) /*!< Reset value of PIN[32] register.                                 */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GPIO_PIN_SECATTR_Pos (4UL)     /*!< Position of SECATTR field.                                           */
  #define SPU_FEATURE_GPIO_PIN_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_SECATTR_Pos) /*!< Bit mask of SECATTR field.         */
  #define SPU_FEATURE_GPIO_PIN_SECATTR_Min (0x0UL)   /*!< Min enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GPIO_PIN_SECATTR_Max (0x1UL)   /*!< Max enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GPIO_PIN_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                        */
  #define SPU_FEATURE_GPIO_PIN_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GPIO_PIN_LOCK_Pos (8UL)        /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_GPIO_PIN_LOCK_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_LOCK_Pos) /*!< Bit mask of LOCK field.                  */
  #define SPU_FEATURE_GPIO_PIN_LOCK_Min (0x0UL)      /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GPIO_PIN_LOCK_Max (0x1UL)      /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GPIO_PIN_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                   */
  #define SPU_FEATURE_GPIO_PIN_LOCK_Locked (0x1UL)   /*!< Feature permissions can not be changed until the next reset          */



/* ================================================ Struct SPU_FEATURE_CRACEN ================================================ */
/**
  * @brief CRACEN [SPU_FEATURE_CRACEN] (unspecified)
  */
typedef struct {
  __IOM uint32_t  SEED;                              /*!< (@ 0x00000000) Configuration for CRACEN SEED                         */
} NRF_SPU_FEATURE_CRACEN_Type;                       /*!< Size = 4 (0x004)                                                     */

/* SPU_FEATURE_CRACEN_SEED: Configuration for CRACEN SEED */
  #define SPU_FEATURE_CRACEN_SEED_ResetValue (0x00020010UL) /*!< Reset value of SEED register.                                 */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_CRACEN_SEED_SECATTR_Pos (4UL)  /*!< Position of SECATTR field.                                           */
  #define SPU_FEATURE_CRACEN_SEED_SECATTR_Msk (0x1UL << SPU_FEATURE_CRACEN_SEED_SECATTR_Pos) /*!< Bit mask of SECATTR field.   */
  #define SPU_FEATURE_CRACEN_SEED_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                              */
  #define SPU_FEATURE_CRACEN_SEED_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                              */
  #define SPU_FEATURE_CRACEN_SEED_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                     */
  #define SPU_FEATURE_CRACEN_SEED_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                             */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_CRACEN_SEED_LOCK_Pos (8UL)     /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_CRACEN_SEED_LOCK_Msk (0x1UL << SPU_FEATURE_CRACEN_SEED_LOCK_Pos) /*!< Bit mask of LOCK field.            */
  #define SPU_FEATURE_CRACEN_SEED_LOCK_Min (0x0UL)   /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_CRACEN_SEED_LOCK_Max (0x1UL)   /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_CRACEN_SEED_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                */
  #define SPU_FEATURE_CRACEN_SEED_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset         */



/* ================================================= Struct SPU_FEATURE_GRTC ================================================= */
/**
  * @brief GRTC [SPU_FEATURE_GRTC] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CC[24];                            /*!< (@ 0x00000000) Security configuration for CC n of GRTC               */
  __IM  uint32_t  RESERVED[5];
  __IOM uint32_t  PWMCONFIG;                         /*!< (@ 0x00000074) Security Configuration for PWMCONFIG of GRTC          */
  __IOM uint32_t  CLK;                               /*!< (@ 0x00000078) Security configuration for CLKOUT/CLKCFG of GRTC      */
  __IOM uint32_t  SYSCOUNTER;                        /*!< (@ 0x0000007C) Security configuration for SYSCOUNTERL/SYSCOUNTERH of
                                                                         GRTC*/
  __IOM uint32_t  INTERRUPT[16];                     /*!< (@ 0x00000080) Security configuration for interrupt n of GRTC        */
} NRF_SPU_FEATURE_GRTC_Type;                         /*!< Size = 192 (0x0C0)                                                   */

/* SPU_FEATURE_GRTC_CC: Security configuration for CC n of GRTC */
  #define SPU_FEATURE_GRTC_CC_MaxCount (24UL)        /*!< Max size of CC[24] array.                                            */
  #define SPU_FEATURE_GRTC_CC_MaxIndex (23UL)        /*!< Max index of CC[24] array.                                           */
  #define SPU_FEATURE_GRTC_CC_MinIndex (0UL)         /*!< Min index of CC[24] array.                                           */
  #define SPU_FEATURE_GRTC_CC_ResetValue (0x00100010UL) /*!< Reset value of CC[24] register.                                   */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GRTC_CC_SECATTR_Pos (4UL)      /*!< Position of SECATTR field.                                           */
  #define SPU_FEATURE_GRTC_CC_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_CC_SECATTR_Pos) /*!< Bit mask of SECATTR field.           */
  #define SPU_FEATURE_GRTC_CC_SECATTR_Min (0x0UL)    /*!< Min enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GRTC_CC_SECATTR_Max (0x1UL)    /*!< Max enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GRTC_CC_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                         */
  #define SPU_FEATURE_GRTC_CC_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                 */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GRTC_CC_LOCK_Pos (8UL)         /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_GRTC_CC_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_CC_LOCK_Pos) /*!< Bit mask of LOCK field.                    */
  #define SPU_FEATURE_GRTC_CC_LOCK_Min (0x0UL)       /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GRTC_CC_LOCK_Max (0x1UL)       /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GRTC_CC_LOCK_Unlocked (0x0UL)  /*!< Feature permissions can be updated                                   */
  #define SPU_FEATURE_GRTC_CC_LOCK_Locked (0x1UL)    /*!< Feature permissions can not be changed until the next reset          */


/* SPU_FEATURE_GRTC_PWMCONFIG: Security Configuration for PWMCONFIG of GRTC */
  #define SPU_FEATURE_GRTC_PWMCONFIG_ResetValue (0x00100010UL) /*!< Reset value of PWMCONFIG register.                         */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                         */
  #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Pos) /*!< Bit mask of SECATTR
                                                                            field.*/
  #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                           */
  #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                           */
  #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                  */
  #define SPU_FEATURE_GRTC_PWMCONFIG_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                          */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Pos (8UL)  /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Pos) /*!< Bit mask of LOCK field.      */
  #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                                 */
  #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                                 */
  #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                             */
  #define SPU_FEATURE_GRTC_PWMCONFIG_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset      */


/* SPU_FEATURE_GRTC_CLK: Security configuration for CLKOUT/CLKCFG of GRTC */
  #define SPU_FEATURE_GRTC_CLK_ResetValue (0x00100010UL) /*!< Reset value of CLK register.                                     */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GRTC_CLK_SECATTR_Pos (4UL)     /*!< Position of SECATTR field.                                           */
  #define SPU_FEATURE_GRTC_CLK_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_CLK_SECATTR_Pos) /*!< Bit mask of SECATTR field.         */
  #define SPU_FEATURE_GRTC_CLK_SECATTR_Min (0x0UL)   /*!< Min enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GRTC_CLK_SECATTR_Max (0x1UL)   /*!< Max enumerator value of SECATTR field.                               */
  #define SPU_FEATURE_GRTC_CLK_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                        */
  #define SPU_FEATURE_GRTC_CLK_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GRTC_CLK_LOCK_Pos (8UL)        /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_GRTC_CLK_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_CLK_LOCK_Pos) /*!< Bit mask of LOCK field.                  */
  #define SPU_FEATURE_GRTC_CLK_LOCK_Min (0x0UL)      /*!< Min enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GRTC_CLK_LOCK_Max (0x1UL)      /*!< Max enumerator value of LOCK field.                                  */
  #define SPU_FEATURE_GRTC_CLK_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                   */
  #define SPU_FEATURE_GRTC_CLK_LOCK_Locked (0x1UL)   /*!< Feature permissions can not be changed until the next reset          */


/* SPU_FEATURE_GRTC_SYSCOUNTER: Security configuration for SYSCOUNTERL/SYSCOUNTERH of GRTC */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00100010UL) /*!< Reset value of SYSCOUNTER register.                       */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                        */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos) /*!< Bit mask of SECATTR
                                                                            field.*/
  #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                          */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                          */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                 */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                         */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos (8UL) /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos) /*!< Bit mask of LOCK field.    */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                                */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                                */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                            */
  #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset     */


/* SPU_FEATURE_GRTC_INTERRUPT: Security configuration for interrupt n of GRTC */
  #define SPU_FEATURE_GRTC_INTERRUPT_MaxCount (16UL) /*!< Max size of INTERRUPT[16] array.                                     */
  #define SPU_FEATURE_GRTC_INTERRUPT_MaxIndex (15UL) /*!< Max index of INTERRUPT[16] array.                                    */
  #define SPU_FEATURE_GRTC_INTERRUPT_MinIndex (0UL)  /*!< Min index of INTERRUPT[16] array.                                    */
  #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00100010UL) /*!< Reset value of INTERRUPT[16] register.                     */

/* SECATTR @Bit 4 : SECATTR feature */
  #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                         */
  #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR
                                                                            field.*/
  #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                           */
  #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                           */
  #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                  */
  #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                          */

/* LOCK @Bit 8 : LOCK feature */
  #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos (8UL)  /*!< Position of LOCK field.                                              */
  #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field.      */
  #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                                 */
  #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                                 */
  #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                             */
  #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset      */



/* =================================================== Struct SPU_FEATURE ==================================================== */
/**
  * @brief FEATURE [SPU_FEATURE] (unspecified)
  */
typedef union {
  struct {
    __IM uint32_t RESERVED[32];
    __IOM NRF_SPU_FEATURE_DPPIC_Type DPPIC;          /*!< (@ 0x00000080) (unspecified)                                         */
    __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[2];     /*!< (@ 0x00000100) (unspecified)                                         */
    __IM uint32_t RESERVED1[32];
    #if defined(_GNUC_)
      #pragma GCC diagnostic push
      #pragma GCC diagnostic ignored "-Wpedantic"
    #endif
    union {
      __IOM NRF_SPU_FEATURE_GPIO_Type GPIO[3];       /*!< (@ 0x00000200) (unspecified)                                         */
      struct {
        __IM uint32_t RESERVED2[96];
        __IOM NRF_SPU_FEATURE_CRACEN_Type CRACEN;    /*!< (@ 0x00000380) (unspecified)                                         */
      };
    };
    #if defined(_GNUC_)
      #pragma GCC diagnostic pop
    #endif
    __IM uint32_t RESERVED3[223];
    __IOM NRF_SPU_FEATURE_GRTC_Type GRTC;            /*!< (@ 0x00000700) (unspecified)                                         */
  };
} NRF_SPU_FEATURE_Type;                              /*!< Size = 1984 (0x7C0)                                                  */

/* ======================================================= Struct SPU ======================================================== */
/**
  * @brief System protection unit
  */
  typedef struct {                                   /*!< SPU Structure                                                        */
    __IM uint32_t RESERVED[64];
    __IOM uint32_t EVENTS_PERIPHACCERR;              /*!< (@ 0x00000100) A security violation has been detected on one or
                                                                         several peripherals*/
    __IM uint32_t RESERVED1[127];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED2[61];
    __IOM NRF_SPU_PERIPHACCERR_Type PERIPHACCERR;    /*!< (@ 0x00000404) (unspecified)                                         */
    __IM uint32_t RESERVED3[62];
    __IOM NRF_SPU_PERIPH_Type PERIPH[64];            /*!< (@ 0x00000500) (unspecified)                                         */
    __IOM NRF_SPU_FEATURE_Type FEATURE;              /*!< (@ 0x00000600) (unspecified)                                         */
  } NRF_SPU_Type;                                    /*!< Size = 3520 (0xDC0)                                                  */

/* SPU_EVENTS_PERIPHACCERR: A security violation has been detected on one or several peripherals */
  #define SPU_EVENTS_PERIPHACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PERIPHACCERR register.                  */

/* EVENTS_PERIPHACCERR @Bit 0 : A security violation has been detected on one or several peripherals */
  #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field.                    */
  #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit
                                                                            mask of EVENTS_PERIPHACCERR field.*/
  #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_PERIPHACCERR field.      */
  #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_PERIPHACCERR field.      */
  #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated                            */
  #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated                                   */


/* SPU_INTEN: Enable or disable interrupt */
  #define SPU_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */

/* PERIPHACCERR @Bit 0 : Enable or disable interrupt for event PERIPHACCERR */
  #define SPU_INTEN_PERIPHACCERR_Pos (0UL)           /*!< Position of PERIPHACCERR field.                                      */
  #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field.                */
  #define SPU_INTEN_PERIPHACCERR_Min (0x0UL)         /*!< Min enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTEN_PERIPHACCERR_Max (0x1UL)         /*!< Max enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL)    /*!< Disable                                                              */
  #define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL)     /*!< Enable                                                               */


/* SPU_INTENSET: Enable interrupt */
  #define SPU_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* PERIPHACCERR @Bit 0 : Write '1' to enable interrupt for event PERIPHACCERR */
  #define SPU_INTENSET_PERIPHACCERR_Pos (0UL)        /*!< Position of PERIPHACCERR field.                                      */
  #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field.          */
  #define SPU_INTENSET_PERIPHACCERR_Min (0x0UL)      /*!< Min enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTENSET_PERIPHACCERR_Max (0x1UL)      /*!< Max enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTENSET_PERIPHACCERR_Set (0x1UL)      /*!< Enable                                                               */
  #define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */


/* SPU_INTENCLR: Disable interrupt */
  #define SPU_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* PERIPHACCERR @Bit 0 : Write '1' to disable interrupt for event PERIPHACCERR */
  #define SPU_INTENCLR_PERIPHACCERR_Pos (0UL)        /*!< Position of PERIPHACCERR field.                                      */
  #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field.          */
  #define SPU_INTENCLR_PERIPHACCERR_Min (0x0UL)      /*!< Min enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTENCLR_PERIPHACCERR_Max (0x1UL)      /*!< Max enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL)    /*!< Disable                                                              */
  #define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */


/* SPU_INTPEND: Pending interrupts */
  #define SPU_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */

/* PERIPHACCERR @Bit 0 : Read pending status of interrupt for event PERIPHACCERR */
  #define SPU_INTPEND_PERIPHACCERR_Pos (0UL)         /*!< Position of PERIPHACCERR field.                                      */
  #define SPU_INTPEND_PERIPHACCERR_Msk (0x1UL << SPU_INTPEND_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field.            */
  #define SPU_INTPEND_PERIPHACCERR_Min (0x0UL)       /*!< Min enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTPEND_PERIPHACCERR_Max (0x1UL)       /*!< Max enumerator value of PERIPHACCERR field.                          */
  #define SPU_INTPEND_PERIPHACCERR_NotPending (0x0UL) /*!< Read: Not pending                                                   */
  #define SPU_INTPEND_PERIPHACCERR_Pending (0x1UL)   /*!< Read: Pending                                                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            SWI                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct SWI ======================================================== */
/**
  * @brief Software interrupt
  */
  typedef struct {                                   /*!< SWI Structure                                                        */
    __IM uint32_t RESERVED;
  } NRF_SWI_Type;                                    /*!< Size = 4 (0x004)                                                     */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            TAD                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct TAD ======================================================== */
/**
  * @brief Trace and debug control
  */
  typedef struct {                                   /*!< TAD Structure                                                        */
    __IM uint32_t RESERVED[256];
    __IOM uint32_t SYSPWRUPREQ;                      /*!< (@ 0x00000400) System power-up request                               */
    __IOM uint32_t DBGPWRUPREQ;                      /*!< (@ 0x00000404) Debug power-up request                                */
    __IM uint32_t RESERVED1[62];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs         */
    __IM uint32_t RESERVED2[5];
    __IOM uint32_t TRACEPORTSPEED;                   /*!< (@ 0x00000518) Trace port speed                                      */
    __IM uint32_t RESERVED3;
    __IOM uint32_t TINSTANCE;                        /*!< (@ 0x00000520) SW-DP Target instance                                 */
  } NRF_TAD_Type;                                    /*!< Size = 1316 (0x524)                                                  */

/* TAD_SYSPWRUPREQ: System power-up request */
  #define TAD_SYSPWRUPREQ_ResetValue (0x00000000UL)  /*!< Reset value of SYSPWRUPREQ register.                                 */

/* ACTIVE @Bit 0 : Activate power-up request */
  #define TAD_SYSPWRUPREQ_ACTIVE_Pos (0UL)           /*!< Position of ACTIVE field.                                            */
  #define TAD_SYSPWRUPREQ_ACTIVE_Msk (0x1UL << TAD_SYSPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.                      */
  #define TAD_SYSPWRUPREQ_ACTIVE_Min (0x0UL)         /*!< Min enumerator value of ACTIVE field.                                */
  #define TAD_SYSPWRUPREQ_ACTIVE_Max (0x1UL)         /*!< Max enumerator value of ACTIVE field.                                */
  #define TAD_SYSPWRUPREQ_ACTIVE_NotActive (0x0UL)   /*!< Power-up request not active                                          */
  #define TAD_SYSPWRUPREQ_ACTIVE_Active (0x1UL)      /*!< Power-up request active                                              */


/* TAD_DBGPWRUPREQ: Debug power-up request */
  #define TAD_DBGPWRUPREQ_ResetValue (0x00000000UL)  /*!< Reset value of DBGPWRUPREQ register.                                 */

/* ACTIVE @Bit 0 : Activate power-up request */
  #define TAD_DBGPWRUPREQ_ACTIVE_Pos (0UL)           /*!< Position of ACTIVE field.                                            */
  #define TAD_DBGPWRUPREQ_ACTIVE_Msk (0x1UL << TAD_DBGPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.                      */
  #define TAD_DBGPWRUPREQ_ACTIVE_Min (0x0UL)         /*!< Min enumerator value of ACTIVE field.                                */
  #define TAD_DBGPWRUPREQ_ACTIVE_Max (0x1UL)         /*!< Max enumerator value of ACTIVE field.                                */
  #define TAD_DBGPWRUPREQ_ACTIVE_NotActive (0x0UL)   /*!< Power-up request not active                                          */
  #define TAD_DBGPWRUPREQ_ACTIVE_Active (0x1UL)      /*!< Power-up request active                                              */


/* TAD_ENABLE: Enable debug domain and aquire selected GPIOs */
  #define TAD_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bit 0 : (unspecified) */
  #define TAD_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
  #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
  #define TAD_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
  #define TAD_ENABLE_ENABLE_Max (0x1UL)              /*!< Max enumerator value of ENABLE field.                                */
  #define TAD_ENABLE_ENABLE_DISABLED (0x0UL)         /*!< Disable debug domain and release selected GPIOs                      */
  #define TAD_ENABLE_ENABLE_ENABLED (0x1UL)          /*!< Enable debug domain and aquire selected GPIOs                        */


/* TAD_TRACEPORTSPEED: Trace port speed */
  #define TAD_TRACEPORTSPEED_ResetValue (0x00000000UL) /*!< Reset value of TRACEPORTSPEED register.                            */

/* TRACEPORTSPEED @Bits 0..1 : Trace port speed is divided from CPU clock. The TRACECLK pin output will be divided again by two
                               from the trace port clock. */

  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field.                                   */
  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED
                                                                            field.*/
  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Min (0x0UL) /*!< Min enumerator value of TRACEPORTSPEED field.                     */
  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Max (0x3UL) /*!< Max enumerator value of TRACEPORTSPEED field.                     */
  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV1 (0x0UL) /*!< Trace port speed equals CPU clock                                */
  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV2 (0x1UL) /*!< Trace port speed equals CPU clock divided by 2                   */
  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV4 (0x2UL) /*!< Trace port speed equals CPU clock divided by 4                   */
  #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_DIV32 (0x3UL) /*!< Trace port speed equals CPU clock divided by 32                 */


/* TAD_TINSTANCE: SW-DP Target instance */
  #define TAD_TINSTANCE_ResetValue (0x00000000UL)    /*!< Reset value of TINSTANCE register.                                   */

/* TINSTANCE @Bits 0..3 : TINSTANCE bits are used in the SW-DP DLPIDR.TINSTANCE field. */
  #define TAD_TINSTANCE_TINSTANCE_Pos (0UL)          /*!< Position of TINSTANCE field.                                         */
  #define TAD_TINSTANCE_TINSTANCE_Msk (0xFUL << TAD_TINSTANCE_TINSTANCE_Pos) /*!< Bit mask of TINSTANCE field.                 */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           TAMPC                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct TAMPC_ACTIVESHIELD ================================================ */
/**
  * @brief ACTIVESHIELD [TAMPC_ACTIVESHIELD] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CHEN;                              /*!< (@ 0x00000000) Active shield detector channel enable register.       */
} NRF_TAMPC_ACTIVESHIELD_Type;                       /*!< Size = 4 (0x004)                                                     */

/* TAMPC_ACTIVESHIELD_CHEN: Active shield detector channel enable register. */
  #define TAMPC_ACTIVESHIELD_CHEN_ResetValue (0x00000000UL) /*!< Reset value of CHEN register.                                 */

/* CH0 @Bit 0 : Enable or disable active shield channel 0. */
  #define TAMPC_ACTIVESHIELD_CHEN_CH0_Pos (0UL)      /*!< Position of CH0 field.                                               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH0_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH0_Pos) /*!< Bit mask of CH0 field.               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH0_Min (0x0UL)    /*!< Min enumerator value of CH0 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH0_Max (0x1UL)    /*!< Max enumerator value of CH0 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel.                                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel.                                                     */

/* CH1 @Bit 1 : Enable or disable active shield channel 1. */
  #define TAMPC_ACTIVESHIELD_CHEN_CH1_Pos (1UL)      /*!< Position of CH1 field.                                               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH1_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH1_Pos) /*!< Bit mask of CH1 field.               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH1_Min (0x0UL)    /*!< Min enumerator value of CH1 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH1_Max (0x1UL)    /*!< Max enumerator value of CH1 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel.                                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel.                                                     */

/* CH2 @Bit 2 : Enable or disable active shield channel 2. */
  #define TAMPC_ACTIVESHIELD_CHEN_CH2_Pos (2UL)      /*!< Position of CH2 field.                                               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH2_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH2_Pos) /*!< Bit mask of CH2 field.               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH2_Min (0x0UL)    /*!< Min enumerator value of CH2 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH2_Max (0x1UL)    /*!< Max enumerator value of CH2 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel.                                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel.                                                     */

/* CH3 @Bit 3 : Enable or disable active shield channel 3. */
  #define TAMPC_ACTIVESHIELD_CHEN_CH3_Pos (3UL)      /*!< Position of CH3 field.                                               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH3_Msk (0x1UL << TAMPC_ACTIVESHIELD_CHEN_CH3_Pos) /*!< Bit mask of CH3 field.               */
  #define TAMPC_ACTIVESHIELD_CHEN_CH3_Min (0x0UL)    /*!< Min enumerator value of CH3 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH3_Max (0x1UL)    /*!< Max enumerator value of CH3 field.                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel.                                                   */
  #define TAMPC_ACTIVESHIELD_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel.                                                     */



/* ============================================ Struct TAMPC_PROTECT_DOMAIN_DBGEN ============================================ */
/**
  * @brief DBGEN [TAMPC_PROTECT_DOMAIN_DBGEN] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for invasive (halting) debug enable
                                                                         for the local debug components within domain n.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for invasive (halting) debug enable for
                                                                         domain n.*/
} NRF_TAMPC_PROTECT_DOMAIN_DBGEN_Type;               /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_DOMAIN_DBGEN_CTRL: Control register for invasive (halting) debug enable for the local debug components within
                                     domain n. */

  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                         */

/* VALUE @Bit 0 : Set value of dbgen signal. */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                        */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                            */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                           */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                          */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                            */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                              */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                    */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.            */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.              */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.           */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                           */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Pos) /*!< Bit mask of KEY
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                             */


/* TAMPC_PROTECT_DOMAIN_DBGEN_STATUS: Status register for invasive (halting) debug enable for domain n. */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                     */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                      */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Pos) /*!< Bit mask of
                                                                            ERROR field.*/
  #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                      */
  #define TAMPC_PROTECT_DOMAIN_DBGEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                           */



/* ============================================ Struct TAMPC_PROTECT_DOMAIN_NIDEN ============================================ */
/**
  * @brief NIDEN [TAMPC_PROTECT_DOMAIN_NIDEN] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for non-invasive debug enable for the
                                                                         local debug components within domain n.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for non-invasive debug enable for
                                                                         domain n.*/
} NRF_TAMPC_PROTECT_DOMAIN_NIDEN_Type;               /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_DOMAIN_NIDEN_CTRL: Control register for non-invasive debug enable for the local debug components within domain
                                     n. */

  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                         */

/* VALUE @Bit 0 : Set value of niden signal. */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                        */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                            */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                           */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                          */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                            */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                              */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                    */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.            */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.              */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.           */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                           */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                             */


/* TAMPC_PROTECT_DOMAIN_NIDEN_STATUS: Status register for non-invasive debug enable for domain n. */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                     */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                      */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Pos) /*!< Bit mask of
                                                                            ERROR field.*/
  #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                      */
  #define TAMPC_PROTECT_DOMAIN_NIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                           */



/* =========================================== Struct TAMPC_PROTECT_DOMAIN_SPIDEN ============================================ */
/**
  * @brief SPIDEN [TAMPC_PROTECT_DOMAIN_SPIDEN] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for secure priviliged invasive
                                                                         (halting) debug enable for the local debug components
                                                                         within domain n.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for secure priviliged invasive
                                                                         (halting) debug enable for domain n.*/
} NRF_TAMPC_PROTECT_DOMAIN_SPIDEN_Type;              /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL: Control register for secure priviliged invasive (halting) debug enable for the local debug
                                      components within domain n. */

  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                        */

/* VALUE @Bit 0 : Set value of spiden signal. */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                       */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Pos) /*!< Bit mask of
                                                                            VALUE field.*/
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                         */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                         */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                           */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                          */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                         */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                           */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                           */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                           */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                             */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                   */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.     */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.     */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.           */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.             */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.          */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                          */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                          */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                          */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                            */


/* TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS: Status register for secure priviliged invasive (halting) debug enable for domain n. */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                    */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                     */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Pos) /*!< Bit mask of
                                                                            ERROR field.*/
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                       */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                       */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                     */
  #define TAMPC_PROTECT_DOMAIN_SPIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                          */



/* =========================================== Struct TAMPC_PROTECT_DOMAIN_SPNIDEN =========================================== */
/**
  * @brief SPNIDEN [TAMPC_PROTECT_DOMAIN_SPNIDEN] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for secure priviliged non-invasive
                                                                         debug enable for the local debug components within
                                                                         domain n.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for secure priviliged non-invasive
                                                                         debug enable for domain n.*/
} NRF_TAMPC_PROTECT_DOMAIN_SPNIDEN_Type;             /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL: Control register for secure priviliged non-invasive debug enable for the local debug
                                       components within domain n. */

  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                       */

/* VALUE @Bit 0 : Set value of spniden signal. */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                      */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Pos) /*!< Bit mask of
                                                                            VALUE field.*/
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                        */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                        */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                          */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                         */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                        */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                          */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                          */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                          */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                            */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                  */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.    */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.    */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.          */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.            */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.         */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                         */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Pos) /*!< Bit mask of KEY
                                                                            field.*/
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                         */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                         */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                           */


/* TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS: Status register for secure priviliged non-invasive debug enable for domain n. */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                   */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                    */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Pos) /*!< Bit mask
                                                                            of ERROR field.*/
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                      */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                      */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                    */
  #define TAMPC_PROTECT_DOMAIN_SPNIDEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                         */



/* =============================================== Struct TAMPC_PROTECT_DOMAIN =============================================== */
/**
  * @brief DOMAIN [TAMPC_PROTECT_DOMAIN] (unspecified)
  */
typedef struct {
  __IOM NRF_TAMPC_PROTECT_DOMAIN_DBGEN_Type DBGEN;   /*!< (@ 0x00000000) (unspecified)                                         */
  __IOM NRF_TAMPC_PROTECT_DOMAIN_NIDEN_Type NIDEN;   /*!< (@ 0x00000008) (unspecified)                                         */
  __IOM NRF_TAMPC_PROTECT_DOMAIN_SPIDEN_Type SPIDEN; /*!< (@ 0x00000010) (unspecified)                                         */
  __IOM NRF_TAMPC_PROTECT_DOMAIN_SPNIDEN_Type SPNIDEN; /*!< (@ 0x00000018) (unspecified)                                       */
} NRF_TAMPC_PROTECT_DOMAIN_Type;                     /*!< Size = 32 (0x020)                                                    */
  #define TAMPC_PROTECT_DOMAIN_MaxCount (1UL)        /*!< Size of DOMAIN[1] array.                                             */
  #define TAMPC_PROTECT_DOMAIN_MaxIndex (0UL)        /*!< Max index of DOMAIN[1] array.                                        */
  #define TAMPC_PROTECT_DOMAIN_MinIndex (0UL)        /*!< Min index of DOMAIN[1] array.                                        */


/* ============================================== Struct TAMPC_PROTECT_AP_DBGEN ============================================== */
/**
  * @brief DBGEN [TAMPC_PROTECT_AP_DBGEN] (unspecified)
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register to enable invasive (halting) debug in
                                                                         domain n's access port.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for invasive (halting) debug enable for
                                                                         domain n's access port.*/
} NRF_TAMPC_PROTECT_AP_DBGEN_Type;                   /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_AP_DBGEN_CTRL: Control register to enable invasive (halting) debug in domain n's access port. */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                             */

/* VALUE @Bit 0 : Set value of dbgen signal. */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                            */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE field. */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                              */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                              */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                                */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                               */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                              */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field.    */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                                */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                                */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                                */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                                  */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                        */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Pos) /*!< Bit
                                                                            mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.          */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.          */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.                */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.                  */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.               */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                               */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field.    */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                               */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                               */
  #define TAMPC_PROTECT_AP_DBGEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                                 */


/* TAMPC_PROTECT_AP_DBGEN_STATUS: Status register for invasive (halting) debug enable for domain n's access port. */
  #define TAMPC_PROTECT_AP_DBGEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                         */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                          */
  #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR
                                                                            field.*/
  #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                            */
  #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                            */
  #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                          */
  #define TAMPC_PROTECT_AP_DBGEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                               */



/* ================================================= Struct TAMPC_PROTECT_AP ================================================= */
/**
  * @brief AP [TAMPC_PROTECT_AP] (unspecified)
  */
typedef struct {
  __IOM NRF_TAMPC_PROTECT_AP_DBGEN_Type DBGEN;       /*!< (@ 0x00000000) (unspecified)                                         */
  __IM  uint32_t  RESERVED[2];
} NRF_TAMPC_PROTECT_AP_Type;                         /*!< Size = 16 (0x010)                                                    */
  #define TAMPC_PROTECT_AP_MaxCount (1UL)            /*!< Size of AP[1] array.                                                 */
  #define TAMPC_PROTECT_AP_MaxIndex (0UL)            /*!< Max index of AP[1] array.                                            */
  #define TAMPC_PROTECT_AP_MinIndex (0UL)            /*!< Min index of AP[1] array.                                            */


/* ============================================ Struct TAMPC_PROTECT_ACTIVESHIELD ============================================ */
/**
  * @brief ACTIVESHIELD [TAMPC_PROTECT_ACTIVESHIELD] Enable active shield detector.
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for active shield detector enable
                                                                         signal.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for active shield detector enable
                                                                         signal.*/
} NRF_TAMPC_PROTECT_ACTIVESHIELD_Type;               /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_ACTIVESHIELD_CTRL: Control register for active shield detector enable signal. */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                         */

/* VALUE @Bit 0 : Set value of active shield enable signal. */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                        */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                            */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                           */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                          */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Pos) /*!< Bit mask of LOCK
                                                                            field.*/
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                            */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                              */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                    */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.            */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.              */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.           */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                           */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Pos) /*!< Bit mask of KEY
                                                                            field.*/
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_ACTIVESHIELD_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                             */


/* TAMPC_PROTECT_ACTIVESHIELD_STATUS: Status register for active shield detector enable signal. */
  #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                     */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                      */
  #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Pos) /*!< Bit mask of
                                                                            ERROR field.*/
  #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                      */
  #define TAMPC_PROTECT_ACTIVESHIELD_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                           */



/* ============================================= Struct TAMPC_PROTECT_CRACENTAMP ============================================= */
/**
  * @brief CRACENTAMP [TAMPC_PROTECT_CRACENTAMP] Enable tamper detector from CRACEN.
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for CRACEN tamper detector enable
                                                                         signal.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for CRACEN tamper detector enable
                                                                         signal.*/
} NRF_TAMPC_PROTECT_CRACENTAMP_Type;                 /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_CRACENTAMP_CTRL: Control register for CRACEN tamper detector enable signal. */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register.                           */

/* VALUE @Bit 0 : Set value of CRACEN tamper detector enable signal. */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                          */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                            */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                            */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                              */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                             */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                            */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field.*/
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                              */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                              */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                              */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                                */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                      */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Pos) /*!<
                                                                            Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.        */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.        */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.              */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.                */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.             */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                             */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Pos) /*!< Bit mask of KEY field.*/
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                             */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                             */
  #define TAMPC_PROTECT_CRACENTAMP_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                               */


/* TAMPC_PROTECT_CRACENTAMP_STATUS: Status register for CRACEN tamper detector enable signal. */
  #define TAMPC_PROTECT_CRACENTAMP_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                       */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                        */
  #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Pos) /*!< Bit mask of ERROR
                                                                            field.*/
  #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                          */
  #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                          */
  #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                        */
  #define TAMPC_PROTECT_CRACENTAMP_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                             */



/* ========================================== Struct TAMPC_PROTECT_GLITCHSLOWDOMAIN ========================================== */
/**
  * @brief GLITCHSLOWDOMAIN [TAMPC_PROTECT_GLITCHSLOWDOMAIN] Enable slow domain glitch detectors.
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for slow domain glitch detectors
                                                                         enable signal.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for slow domain glitch detectors enable
                                                                         signal.*/
} NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type;           /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL: Control register for slow domain glitch detectors enable signal. */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register.                     */

/* VALUE @Bit 0 : Set value of slow domain glitch detectors enable signal. */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                    */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Pos) /*!< Bit mask
                                                                            of VALUE field.*/
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                      */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                      */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                        */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                       */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                      */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Pos) /*!< Bit mask of
                                                                            LOCK field.*/
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                        */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                        */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                        */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                          */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.  */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.  */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.        */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.          */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.       */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                       */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Pos) /*!< Bit mask of
                                                                            KEY field.*/
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                       */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                       */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                         */


/* TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS: Status register for slow domain glitch detectors enable signal. */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                 */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                  */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Pos) /*!< Bit
                                                                            mask of ERROR field.*/
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                    */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                    */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                  */
  #define TAMPC_PROTECT_GLITCHSLOWDOMAIN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                       */



/* ========================================== Struct TAMPC_PROTECT_GLITCHFASTDOMAIN ========================================== */
/**
  * @brief GLITCHFASTDOMAIN [TAMPC_PROTECT_GLITCHFASTDOMAIN] Enable fast domain glitch detectors.
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for fast domain glitch detectors
                                                                         enable signal.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for fast domain glitch detectors enable
                                                                         signal.*/
} NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type;           /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL: Control register for fast domain glitch detectors enable signal. */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register.                     */

/* VALUE @Bit 0 : Set value of fast domain glitch detector's enable signal. */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                    */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Pos) /*!< Bit mask
                                                                            of VALUE field.*/
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                      */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                      */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                        */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                       */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                      */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Pos) /*!< Bit mask of
                                                                            LOCK field.*/
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                        */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                        */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                        */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                          */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.  */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.  */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.        */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.          */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.       */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                       */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Pos) /*!< Bit mask of
                                                                            KEY field.*/
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                       */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                       */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                         */


/* TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS: Status register for fast domain glitch detectors enable signal. */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                 */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                  */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Pos) /*!< Bit
                                                                            mask of ERROR field.*/
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                    */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                    */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                  */
  #define TAMPC_PROTECT_GLITCHFASTDOMAIN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                       */



/* ============================================= Struct TAMPC_PROTECT_EXTRESETEN ============================================= */
/**
  * @brief EXTRESETEN [TAMPC_PROTECT_EXTRESETEN] Trigger a reset when tamper is detected by the external tamper detectors.
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for external tamper reset enable
                                                                         signal.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for external tamper reset enable
                                                                         signal.*/
} NRF_TAMPC_PROTECT_EXTRESETEN_Type;                 /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_EXTRESETEN_CTRL: Control register for external tamper reset enable signal. */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                           */

/* VALUE @Bit 0 : Set value of external tamper reset enable signal. */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                          */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                            */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                            */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                              */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                             */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                            */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field.*/
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                              */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                              */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                              */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                                */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                      */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Pos) /*!<
                                                                            Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.        */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.        */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.              */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.                */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.             */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                             */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field.*/
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                             */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                             */
  #define TAMPC_PROTECT_EXTRESETEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                               */


/* TAMPC_PROTECT_EXTRESETEN_STATUS: Status register for external tamper reset enable signal. */
  #define TAMPC_PROTECT_EXTRESETEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                       */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                        */
  #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR
                                                                            field.*/
  #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                          */
  #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                          */
  #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                        */
  #define TAMPC_PROTECT_EXTRESETEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                             */



/* ============================================= Struct TAMPC_PROTECT_INTRESETEN ============================================= */
/**
  * @brief INTRESETEN [TAMPC_PROTECT_INTRESETEN] Trigger a reset when tamper is detected by the glitch detectors, signal
            protector or CRACEN tamper detector.

  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for internal tamper reset enable
                                                                         signal.*/
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for internal tamper reset enable
                                                                         signal.*/
} NRF_TAMPC_PROTECT_INTRESETEN_Type;                 /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_INTRESETEN_CTRL: Control register for internal tamper reset enable signal. */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_ResetValue (0x00000011UL) /*!< Reset value of CTRL register.                           */

/* VALUE @Bit 0 : Set value of internal tamper reset enable signal. */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                          */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/
  #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                            */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                            */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                              */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                             */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                            */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Pos) /*!< Bit mask of LOCK field.*/
  #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                              */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                              */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                              */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                                */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                      */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Pos) /*!<
                                                                            Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.        */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.        */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.              */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.                */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.             */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                             */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Pos) /*!< Bit mask of KEY field.*/
  #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                             */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                             */
  #define TAMPC_PROTECT_INTRESETEN_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                               */


/* TAMPC_PROTECT_INTRESETEN_STATUS: Status register for internal tamper reset enable signal. */
  #define TAMPC_PROTECT_INTRESETEN_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                       */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                        */
  #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Pos) /*!< Bit mask of ERROR
                                                                            field.*/
  #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                          */
  #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                          */
  #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                        */
  #define TAMPC_PROTECT_INTRESETEN_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                             */



/* ============================================ Struct TAMPC_PROTECT_ERASEPROTECT ============================================ */
/**
  * @brief ERASEPROTECT [TAMPC_PROTECT_ERASEPROTECT] Device erase protection.
  */
typedef struct {
  __IOM uint32_t  CTRL;                              /*!< (@ 0x00000000) Control register for erase protection.                */
  __IOM uint32_t  STATUS;                            /*!< (@ 0x00000004) Status register for eraseprotect.                     */
} NRF_TAMPC_PROTECT_ERASEPROTECT_Type;               /*!< Size = 8 (0x008)                                                     */

/* TAMPC_PROTECT_ERASEPROTECT_CTRL: Control register for erase protection. */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_ResetValue (0x00000010UL) /*!< Reset value of CTRL register.                         */

/* VALUE @Bit 0 : Set value of eraseprotect signal. */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                                        */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Msk (0x1UL << TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Min (0x0UL) /*!< Min enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Max (0x1UL) /*!< Max enumerator value of VALUE field.                          */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_Low (0x0UL) /*!< Signal is logic 0.                                            */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_VALUE_High (0x1UL) /*!< Signal is logic 1.                                           */

/* LOCK @Bit 1 : Lock this register to prevent changes to the VALUE field until next reset. */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Pos (1UL) /*!< Position of LOCK field.                                          */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Msk (0x1UL << TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Pos) /*!< Bit mask of LOCK
                                                                            field.*/
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                            */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                            */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_LOCK_Enabled (0x1UL) /*!< Lock enabled.                                              */

/* WRITEPROTECTION @Bits 4..7 : The write protection must be cleared to allow updates to the VALUE field. */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Pos (4UL) /*!< Position of WRITEPROTECTION field.                    */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Msk (0xFUL << TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Pos)
                                                                            /*!< Bit mask of WRITEPROTECTION field.*/
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Min (0x0UL) /*!< Min enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Max (0xFUL) /*!< Max enumerator value of WRITEPROTECTION field.      */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Disabled (0x0UL) /*!< Read: Write protection is disabled.            */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Enabled (0x1UL) /*!< Read: Write protection is enabled.              */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_WRITEPROTECTION_Clear (0xFUL) /*!< Write: Value to clear write protection.           */

/* KEY @Bits 16..31 : Required write key for upper 16 bits. Must be included in all register write operations. */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Pos (16UL) /*!< Position of KEY field.                                           */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Msk (0xFFFFUL << TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Pos) /*!< Bit mask of KEY
                                                                            field.*/
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Min (0x50FAUL) /*!< Min enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_Max (0x50FAUL) /*!< Max enumerator value of KEY field.                           */
  #define TAMPC_PROTECT_ERASEPROTECT_CTRL_KEY_KEY (0x50FAUL) /*!< Write key value.                                             */


/* TAMPC_PROTECT_ERASEPROTECT_STATUS: Status register for eraseprotect. */
  #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                     */

/* ERROR @Bit 0 : Error detection status. */
  #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Pos (0UL) /*!< Position of ERROR field.                                      */
  #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Msk (0x1UL << TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Pos) /*!< Bit mask of
                                                                            ERROR field.*/
  #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Min (0x0UL) /*!< Min enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Max (0x1UL) /*!< Max enumerator value of ERROR field.                        */
  #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_NoError (0x0UL) /*!< No error detected.                                      */
  #define TAMPC_PROTECT_ERASEPROTECT_STATUS_ERROR_Error (0x1UL) /*!< Error detected.                                           */



/* ================================================== Struct TAMPC_PROTECT =================================================== */
/**
  * @brief PROTECT [TAMPC_PROTECT] (unspecified)
  */
typedef union {
  struct {
    __IOM NRF_TAMPC_PROTECT_DOMAIN_Type DOMAIN[1];   /*!< (@ 0x00000000) (unspecified)                                         */
    __IM uint32_t RESERVED[120];
    __IOM NRF_TAMPC_PROTECT_AP_Type AP[1];           /*!< (@ 0x00000200) (unspecified)                                         */
    __IM uint32_t RESERVED1[124];
    __IOM NRF_TAMPC_PROTECT_ACTIVESHIELD_Type ACTIVESHIELD; /*!< (@ 0x00000400) Enable active shield detector.                 */
    __IM uint32_t RESERVED2[12];
    __IOM NRF_TAMPC_PROTECT_CRACENTAMP_Type CRACENTAMP; /*!< (@ 0x00000438) Enable tamper detector from CRACEN.                */
    __IOM NRF_TAMPC_PROTECT_GLITCHSLOWDOMAIN_Type GLITCHSLOWDOMAIN; /*!< (@ 0x00000440) Enable slow domain glitch detectors.   */
    __IOM NRF_TAMPC_PROTECT_GLITCHFASTDOMAIN_Type GLITCHFASTDOMAIN; /*!< (@ 0x00000448) Enable fast domain glitch detectors.   */
    __IM uint32_t RESERVED3[8];
    __IOM NRF_TAMPC_PROTECT_EXTRESETEN_Type EXTRESETEN; /*!< (@ 0x00000470) Trigger a reset when tamper is detected by the
                                                                            external tamper detectors.*/
    __IOM NRF_TAMPC_PROTECT_INTRESETEN_Type INTRESETEN; /*!< (@ 0x00000478) Trigger a reset when tamper is detected by the
                                                                            glitch detectors, signal protector or CRACEN tamper
                                                                            detector.*/
    __IOM NRF_TAMPC_PROTECT_ERASEPROTECT_Type ERASEPROTECT; /*!< (@ 0x00000480) Device erase protection.                       */
  };
} NRF_TAMPC_PROTECT_Type;                            /*!< Size = 1160 (0x488)                                                  */

/* ====================================================== Struct TAMPC ======================================================= */
/**
  * @brief Tamper controller
  */
  typedef struct {                                   /*!< TAMPC Structure                                                      */
    __IM uint32_t RESERVED[64];
    __IOM uint32_t EVENTS_TAMPER;                    /*!< (@ 0x00000100) Tamper controller detected an error.                  */
    __IOM uint32_t EVENTS_WRITEERROR;                /*!< (@ 0x00000104) Attempt to write a VALUE in PROTECT registers without
                                                                         clearing the WRITEPROTECT.*/
    __IM uint32_t RESERVED1[126];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED2[60];
    __IOM uint32_t STATUS;                           /*!< (@ 0x00000400) The tamper controller status.                         */
    __IOM NRF_TAMPC_ACTIVESHIELD_Type ACTIVESHIELD;  /*!< (@ 0x00000404) (unspecified)                                         */
    __IM uint32_t RESERVED3[62];
    __IOM NRF_TAMPC_PROTECT_Type PROTECT;            /*!< (@ 0x00000500) (unspecified)                                         */
  } NRF_TAMPC_Type;                                  /*!< Size = 2440 (0x988)                                                  */

/* TAMPC_EVENTS_TAMPER: Tamper controller detected an error. */
  #define TAMPC_EVENTS_TAMPER_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TAMPER register.                            */

/* EVENTS_TAMPER @Bit 0 : Tamper controller detected an error. */
  #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Pos (0UL) /*!< Position of EVENTS_TAMPER field.                                    */
  #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Msk (0x1UL << TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Pos) /*!< Bit mask of EVENTS_TAMPER
                                                                            field.*/
  #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Min (0x0UL) /*!< Min enumerator value of EVENTS_TAMPER field.                      */
  #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Max (0x1UL) /*!< Max enumerator value of EVENTS_TAMPER field.                      */
  #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define TAMPC_EVENTS_TAMPER_EVENTS_TAMPER_Generated (0x1UL) /*!< Event generated                                             */


/* TAMPC_EVENTS_WRITEERROR: Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT. */
  #define TAMPC_EVENTS_WRITEERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WRITEERROR register.                    */

/* EVENTS_WRITEERROR @Bit 0 : Attempt to write a VALUE in PROTECT registers without clearing the WRITEPROTECT. */
  #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Pos (0UL) /*!< Position of EVENTS_WRITEERROR field.                        */
  #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Msk (0x1UL << TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Pos) /*!< Bit mask
                                                                            of EVENTS_WRITEERROR field.*/
  #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_WRITEERROR field.          */
  #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_WRITEERROR field.          */
  #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_NotGenerated (0x0UL) /*!< Event not generated                              */
  #define TAMPC_EVENTS_WRITEERROR_EVENTS_WRITEERROR_Generated (0x1UL) /*!< Event generated                                     */


/* TAMPC_INTEN: Enable or disable interrupt */
  #define TAMPC_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */

/* TAMPER @Bit 0 : Enable or disable interrupt for event TAMPER */
  #define TAMPC_INTEN_TAMPER_Pos (0UL)               /*!< Position of TAMPER field.                                            */
  #define TAMPC_INTEN_TAMPER_Msk (0x1UL << TAMPC_INTEN_TAMPER_Pos) /*!< Bit mask of TAMPER field.                              */
  #define TAMPC_INTEN_TAMPER_Min (0x0UL)             /*!< Min enumerator value of TAMPER field.                                */
  #define TAMPC_INTEN_TAMPER_Max (0x1UL)             /*!< Max enumerator value of TAMPER field.                                */
  #define TAMPC_INTEN_TAMPER_Disabled (0x0UL)        /*!< Disable                                                              */
  #define TAMPC_INTEN_TAMPER_Enabled (0x1UL)         /*!< Enable                                                               */

/* WRITEERROR @Bit 1 : Enable or disable interrupt for event WRITEERROR */
  #define TAMPC_INTEN_WRITEERROR_Pos (1UL)           /*!< Position of WRITEERROR field.                                        */
  #define TAMPC_INTEN_WRITEERROR_Msk (0x1UL << TAMPC_INTEN_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field.                  */
  #define TAMPC_INTEN_WRITEERROR_Min (0x0UL)         /*!< Min enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTEN_WRITEERROR_Max (0x1UL)         /*!< Max enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTEN_WRITEERROR_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TAMPC_INTEN_WRITEERROR_Enabled (0x1UL)     /*!< Enable                                                               */


/* TAMPC_INTENSET: Enable interrupt */
  #define TAMPC_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */

/* TAMPER @Bit 0 : Write '1' to enable interrupt for event TAMPER */
  #define TAMPC_INTENSET_TAMPER_Pos (0UL)            /*!< Position of TAMPER field.                                            */
  #define TAMPC_INTENSET_TAMPER_Msk (0x1UL << TAMPC_INTENSET_TAMPER_Pos) /*!< Bit mask of TAMPER field.                        */
  #define TAMPC_INTENSET_TAMPER_Min (0x0UL)          /*!< Min enumerator value of TAMPER field.                                */
  #define TAMPC_INTENSET_TAMPER_Max (0x1UL)          /*!< Max enumerator value of TAMPER field.                                */
  #define TAMPC_INTENSET_TAMPER_Set (0x1UL)          /*!< Enable                                                               */
  #define TAMPC_INTENSET_TAMPER_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TAMPC_INTENSET_TAMPER_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* WRITEERROR @Bit 1 : Write '1' to enable interrupt for event WRITEERROR */
  #define TAMPC_INTENSET_WRITEERROR_Pos (1UL)        /*!< Position of WRITEERROR field.                                        */
  #define TAMPC_INTENSET_WRITEERROR_Msk (0x1UL << TAMPC_INTENSET_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field.            */
  #define TAMPC_INTENSET_WRITEERROR_Min (0x0UL)      /*!< Min enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTENSET_WRITEERROR_Max (0x1UL)      /*!< Max enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTENSET_WRITEERROR_Set (0x1UL)      /*!< Enable                                                               */
  #define TAMPC_INTENSET_WRITEERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TAMPC_INTENSET_WRITEERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */


/* TAMPC_INTENCLR: Disable interrupt */
  #define TAMPC_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */

/* TAMPER @Bit 0 : Write '1' to disable interrupt for event TAMPER */
  #define TAMPC_INTENCLR_TAMPER_Pos (0UL)            /*!< Position of TAMPER field.                                            */
  #define TAMPC_INTENCLR_TAMPER_Msk (0x1UL << TAMPC_INTENCLR_TAMPER_Pos) /*!< Bit mask of TAMPER field.                        */
  #define TAMPC_INTENCLR_TAMPER_Min (0x0UL)          /*!< Min enumerator value of TAMPER field.                                */
  #define TAMPC_INTENCLR_TAMPER_Max (0x1UL)          /*!< Max enumerator value of TAMPER field.                                */
  #define TAMPC_INTENCLR_TAMPER_Clear (0x1UL)        /*!< Disable                                                              */
  #define TAMPC_INTENCLR_TAMPER_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TAMPC_INTENCLR_TAMPER_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* WRITEERROR @Bit 1 : Write '1' to disable interrupt for event WRITEERROR */
  #define TAMPC_INTENCLR_WRITEERROR_Pos (1UL)        /*!< Position of WRITEERROR field.                                        */
  #define TAMPC_INTENCLR_WRITEERROR_Msk (0x1UL << TAMPC_INTENCLR_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field.            */
  #define TAMPC_INTENCLR_WRITEERROR_Min (0x0UL)      /*!< Min enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTENCLR_WRITEERROR_Max (0x1UL)      /*!< Max enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTENCLR_WRITEERROR_Clear (0x1UL)    /*!< Disable                                                              */
  #define TAMPC_INTENCLR_WRITEERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TAMPC_INTENCLR_WRITEERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */


/* TAMPC_INTPEND: Pending interrupts */
  #define TAMPC_INTPEND_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND register.                                     */

/* TAMPER @Bit 0 : Read pending status of interrupt for event TAMPER */
  #define TAMPC_INTPEND_TAMPER_Pos (0UL)             /*!< Position of TAMPER field.                                            */
  #define TAMPC_INTPEND_TAMPER_Msk (0x1UL << TAMPC_INTPEND_TAMPER_Pos) /*!< Bit mask of TAMPER field.                          */
  #define TAMPC_INTPEND_TAMPER_Min (0x0UL)           /*!< Min enumerator value of TAMPER field.                                */
  #define TAMPC_INTPEND_TAMPER_Max (0x1UL)           /*!< Max enumerator value of TAMPER field.                                */
  #define TAMPC_INTPEND_TAMPER_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
  #define TAMPC_INTPEND_TAMPER_Pending (0x1UL)       /*!< Read: Pending                                                        */

/* WRITEERROR @Bit 1 : Read pending status of interrupt for event WRITEERROR */
  #define TAMPC_INTPEND_WRITEERROR_Pos (1UL)         /*!< Position of WRITEERROR field.                                        */
  #define TAMPC_INTPEND_WRITEERROR_Msk (0x1UL << TAMPC_INTPEND_WRITEERROR_Pos) /*!< Bit mask of WRITEERROR field.              */
  #define TAMPC_INTPEND_WRITEERROR_Min (0x0UL)       /*!< Min enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTPEND_WRITEERROR_Max (0x1UL)       /*!< Max enumerator value of WRITEERROR field.                            */
  #define TAMPC_INTPEND_WRITEERROR_NotPending (0x0UL) /*!< Read: Not pending                                                   */
  #define TAMPC_INTPEND_WRITEERROR_Pending (0x1UL)   /*!< Read: Pending                                                        */


/* TAMPC_STATUS: The tamper controller status. */
  #define TAMPC_STATUS_ResetValue (0x00000000UL)     /*!< Reset value of STATUS register.                                      */

/* ACTIVESHIELD @Bit 0 : Active shield detector detected an error. */
  #define TAMPC_STATUS_ACTIVESHIELD_Pos (0UL)        /*!< Position of ACTIVESHIELD field.                                      */
  #define TAMPC_STATUS_ACTIVESHIELD_Msk (0x1UL << TAMPC_STATUS_ACTIVESHIELD_Pos) /*!< Bit mask of ACTIVESHIELD field.          */
  #define TAMPC_STATUS_ACTIVESHIELD_Min (0x0UL)      /*!< Min enumerator value of ACTIVESHIELD field.                          */
  #define TAMPC_STATUS_ACTIVESHIELD_Max (0x1UL)      /*!< Max enumerator value of ACTIVESHIELD field.                          */
  #define TAMPC_STATUS_ACTIVESHIELD_NotDetected (0x0UL) /*!< Not detected.                                                     */
  #define TAMPC_STATUS_ACTIVESHIELD_Detected (0x1UL) /*!< Detected.                                                            */

/* PROTECT @Bit 4 : Error detected for the protected signals. */
  #define TAMPC_STATUS_PROTECT_Pos (4UL)             /*!< Position of PROTECT field.                                           */
  #define TAMPC_STATUS_PROTECT_Msk (0x1UL << TAMPC_STATUS_PROTECT_Pos) /*!< Bit mask of PROTECT field.                         */
  #define TAMPC_STATUS_PROTECT_Min (0x0UL)           /*!< Min enumerator value of PROTECT field.                               */
  #define TAMPC_STATUS_PROTECT_Max (0x1UL)           /*!< Max enumerator value of PROTECT field.                               */
  #define TAMPC_STATUS_PROTECT_NotDetected (0x0UL)   /*!< Not detected.                                                        */
  #define TAMPC_STATUS_PROTECT_Detected (0x1UL)      /*!< Detected.                                                            */

/* CRACENTAMP @Bit 5 : CRACEN detected an error. */
  #define TAMPC_STATUS_CRACENTAMP_Pos (5UL)          /*!< Position of CRACENTAMP field.                                        */
  #define TAMPC_STATUS_CRACENTAMP_Msk (0x1UL << TAMPC_STATUS_CRACENTAMP_Pos) /*!< Bit mask of CRACENTAMP field.                */
  #define TAMPC_STATUS_CRACENTAMP_Min (0x0UL)        /*!< Min enumerator value of CRACENTAMP field.                            */
  #define TAMPC_STATUS_CRACENTAMP_Max (0x1UL)        /*!< Max enumerator value of CRACENTAMP field.                            */
  #define TAMPC_STATUS_CRACENTAMP_NotDetected (0x0UL) /*!< Not detected.                                                       */
  #define TAMPC_STATUS_CRACENTAMP_Detected (0x1UL)   /*!< Detected.                                                            */

/* GLITCHSLOWDOMAIN0 @Bit 8 : Slow domain glitch detector 0 detected an error. */
  #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Pos (8UL)   /*!< Position of GLITCHSLOWDOMAIN0 field.                                 */
  #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Msk (0x1UL << TAMPC_STATUS_GLITCHSLOWDOMAIN0_Pos) /*!< Bit mask of GLITCHSLOWDOMAIN0
                                                                            field.*/
  #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Min (0x0UL) /*!< Min enumerator value of GLITCHSLOWDOMAIN0 field.                     */
  #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Max (0x1UL) /*!< Max enumerator value of GLITCHSLOWDOMAIN0 field.                     */
  #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_NotDetected (0x0UL) /*!< Not detected.                                                */
  #define TAMPC_STATUS_GLITCHSLOWDOMAIN0_Detected (0x1UL) /*!< Detected.                                                       */

/* GLITCHFASTDOMAIN0 @Bit 12 : Fast domain glitch detector 0 detected an error. */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Pos (12UL)  /*!< Position of GLITCHFASTDOMAIN0 field.                                 */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN0_Pos) /*!< Bit mask of GLITCHFASTDOMAIN0
                                                                            field.*/
  #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN0 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN0 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN0_NotDetected (0x0UL) /*!< Not detected.                                                */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN0_Detected (0x1UL) /*!< Detected.                                                       */

/* GLITCHFASTDOMAIN1 @Bit 13 : Fast domain glitch detector 1 detected an error. */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Pos (13UL)  /*!< Position of GLITCHFASTDOMAIN1 field.                                 */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN1_Pos) /*!< Bit mask of GLITCHFASTDOMAIN1
                                                                            field.*/
  #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN1 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN1 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN1_NotDetected (0x0UL) /*!< Not detected.                                                */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN1_Detected (0x1UL) /*!< Detected.                                                       */

/* GLITCHFASTDOMAIN2 @Bit 14 : Fast domain glitch detector 2 detected an error. */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Pos (14UL)  /*!< Position of GLITCHFASTDOMAIN2 field.                                 */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN2_Pos) /*!< Bit mask of GLITCHFASTDOMAIN2
                                                                            field.*/
  #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN2 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN2 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN2_NotDetected (0x0UL) /*!< Not detected.                                                */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN2_Detected (0x1UL) /*!< Detected.                                                       */

/* GLITCHFASTDOMAIN3 @Bit 15 : Fast domain glitch detector 3 detected an error. */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Pos (15UL)  /*!< Position of GLITCHFASTDOMAIN3 field.                                 */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Msk (0x1UL << TAMPC_STATUS_GLITCHFASTDOMAIN3_Pos) /*!< Bit mask of GLITCHFASTDOMAIN3
                                                                            field.*/
  #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Min (0x0UL) /*!< Min enumerator value of GLITCHFASTDOMAIN3 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Max (0x1UL) /*!< Max enumerator value of GLITCHFASTDOMAIN3 field.                     */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN3_NotDetected (0x0UL) /*!< Not detected.                                                */
  #define TAMPC_STATUS_GLITCHFASTDOMAIN3_Detected (0x1UL) /*!< Detected.                                                       */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           TEMP                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct TEMP ======================================================= */
/**
  * @brief Temperature Sensor
  */
  typedef struct {                                   /*!< TEMP Structure                                                       */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start temperature measurement                         */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop temperature measurement                          */
    __IM uint32_t RESERVED[30];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED1[30];
    __IOM uint32_t EVENTS_DATARDY;                   /*!< (@ 0x00000100) Temperature measurement complete, data ready          */
    __IM uint32_t RESERVED2[31];
    __IOM uint32_t PUBLISH_DATARDY;                  /*!< (@ 0x00000180) Publish configuration for event DATARDY               */
    __IM uint32_t RESERVED3[96];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED4[127];
    __IM int32_t  TEMP;                              /*!< (@ 0x00000508) Temperature in degC (0.25deg steps)                   */
    __IM uint32_t RESERVED5[5];
    __IOM uint32_t A0;                               /*!< (@ 0x00000520) Slope of 1st piece wise linear function               */
    __IOM uint32_t A1;                               /*!< (@ 0x00000524) Slope of 2nd piece wise linear function               */
    __IOM uint32_t A2;                               /*!< (@ 0x00000528) Slope of 3rd piece wise linear function               */
    __IOM uint32_t A3;                               /*!< (@ 0x0000052C) Slope of 4th piece wise linear function               */
    __IOM uint32_t A4;                               /*!< (@ 0x00000530) Slope of 5th piece wise linear function               */
    __IOM uint32_t A5;                               /*!< (@ 0x00000534) Slope of 6th piece wise linear function               */
    __IOM uint32_t A6;                               /*!< (@ 0x00000538) Slope of 7th piece wise linear function               */
    __IM uint32_t RESERVED6;
    __IOM uint32_t B0;                               /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function         */
    __IOM uint32_t B1;                               /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function         */
    __IOM uint32_t B2;                               /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function         */
    __IOM uint32_t B3;                               /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function         */
    __IOM uint32_t B4;                               /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function         */
    __IOM uint32_t B5;                               /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function         */
    __IOM uint32_t B6;                               /*!< (@ 0x00000558) y-intercept of 7th piece wise linear function         */
    __IM uint32_t RESERVED7;
    __IOM uint32_t T0;                               /*!< (@ 0x00000560) End point of 1st piece wise linear function           */
    __IOM uint32_t T1;                               /*!< (@ 0x00000564) End point of 2nd piece wise linear function           */
    __IOM uint32_t T2;                               /*!< (@ 0x00000568) End point of 3rd piece wise linear function           */
    __IOM uint32_t T3;                               /*!< (@ 0x0000056C) End point of 4th piece wise linear function           */
    __IOM uint32_t T4;                               /*!< (@ 0x00000570) End point of 5th piece wise linear function           */
    __IOM uint32_t T5;                               /*!< (@ 0x00000574) End point of 6th piece wise linear function           */
  } NRF_TEMP_Type;                                   /*!< Size = 1400 (0x578)                                                  */

/* TEMP_TASKS_START: Start temperature measurement */
  #define TEMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start temperature measurement */
  #define TEMP_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
  #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
  #define TEMP_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
  #define TEMP_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
  #define TEMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */


/* TEMP_TASKS_STOP: Stop temperature measurement */
  #define TEMP_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop temperature measurement */
  #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
  #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
  #define TEMP_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
  #define TEMP_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
  #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */


/* TEMP_SUBSCRIBE_START: Subscribe configuration for task START */
  #define TEMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define TEMP_SUBSCRIBE_START_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define TEMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TEMP_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
  #define TEMP_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define TEMP_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define TEMP_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define TEMP_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* TEMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define TEMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define TEMP_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define TEMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
  #define TEMP_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define TEMP_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define TEMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* TEMP_EVENTS_DATARDY: Temperature measurement complete, data ready */
  #define TEMP_EVENTS_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DATARDY register.                           */

/* EVENTS_DATARDY @Bit 0 : Temperature measurement complete, data ready */
  #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field.                                  */
  #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of
                                                                            EVENTS_DATARDY field.*/
  #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DATARDY field.                    */
  #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DATARDY field.                    */
  #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (0x1UL) /*!< Event generated                                            */


/* TEMP_PUBLISH_DATARDY: Publish configuration for event DATARDY */
  #define TEMP_PUBLISH_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DATARDY register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event DATARDY will publish to */
  #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define TEMP_PUBLISH_DATARDY_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define TEMP_PUBLISH_DATARDY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field.                        */
  #define TEMP_PUBLISH_DATARDY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define TEMP_PUBLISH_DATARDY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define TEMP_PUBLISH_DATARDY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define TEMP_PUBLISH_DATARDY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* TEMP_INTENSET: Enable interrupt */
  #define TEMP_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* DATARDY @Bit 0 : Write '1' to enable interrupt for event DATARDY */
  #define TEMP_INTENSET_DATARDY_Pos (0UL)            /*!< Position of DATARDY field.                                           */
  #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field.                       */
  #define TEMP_INTENSET_DATARDY_Min (0x0UL)          /*!< Min enumerator value of DATARDY field.                               */
  #define TEMP_INTENSET_DATARDY_Max (0x1UL)          /*!< Max enumerator value of DATARDY field.                               */
  #define TEMP_INTENSET_DATARDY_Set (0x1UL)          /*!< Enable                                                               */
  #define TEMP_INTENSET_DATARDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TEMP_INTENSET_DATARDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* TEMP_INTENCLR: Disable interrupt */
  #define TEMP_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* DATARDY @Bit 0 : Write '1' to disable interrupt for event DATARDY */
  #define TEMP_INTENCLR_DATARDY_Pos (0UL)            /*!< Position of DATARDY field.                                           */
  #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field.                       */
  #define TEMP_INTENCLR_DATARDY_Min (0x0UL)          /*!< Min enumerator value of DATARDY field.                               */
  #define TEMP_INTENCLR_DATARDY_Max (0x1UL)          /*!< Max enumerator value of DATARDY field.                               */
  #define TEMP_INTENCLR_DATARDY_Clear (0x1UL)        /*!< Disable                                                              */
  #define TEMP_INTENCLR_DATARDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TEMP_INTENCLR_DATARDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */


/* TEMP_TEMP: Temperature in degC (0.25deg steps) */
  #define TEMP_TEMP_ResetValue (0x00000000UL)        /*!< Reset value of TEMP register.                                        */

/* TEMP @Bits 0..31 : Temperature in degC (0.25deg steps) */
  #define TEMP_TEMP_TEMP_Pos (0UL)                   /*!< Position of TEMP field.                                              */
  #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field.                                 */


/* TEMP_A0: Slope of 1st piece wise linear function */
  #define TEMP_A0_ResetValue (0x000002D6UL)          /*!< Reset value of A0 register.                                          */

/* A0 @Bits 0..11 : Slope of 1st piece wise linear function */
  #define TEMP_A0_A0_Pos (0UL)                       /*!< Position of A0 field.                                                */
  #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field.                                                */


/* TEMP_A1: Slope of 2nd piece wise linear function */
  #define TEMP_A1_ResetValue (0x0000032DUL)          /*!< Reset value of A1 register.                                          */

/* A1 @Bits 0..11 : Slope of 2nd piece wise linear function */
  #define TEMP_A1_A1_Pos (0UL)                       /*!< Position of A1 field.                                                */
  #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field.                                                */


/* TEMP_A2: Slope of 3rd piece wise linear function */
  #define TEMP_A2_ResetValue (0x00000384UL)          /*!< Reset value of A2 register.                                          */

/* A2 @Bits 0..11 : Slope of 3rd piece wise linear function */
  #define TEMP_A2_A2_Pos (0UL)                       /*!< Position of A2 field.                                                */
  #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field.                                                */


/* TEMP_A3: Slope of 4th piece wise linear function */
  #define TEMP_A3_ResetValue (0x000003E9UL)          /*!< Reset value of A3 register.                                          */

/* A3 @Bits 0..11 : Slope of 4th piece wise linear function */
  #define TEMP_A3_A3_Pos (0UL)                       /*!< Position of A3 field.                                                */
  #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field.                                                */


/* TEMP_A4: Slope of 5th piece wise linear function */
  #define TEMP_A4_ResetValue (0x0000046FUL)          /*!< Reset value of A4 register.                                          */

/* A4 @Bits 0..11 : Slope of 5th piece wise linear function */
  #define TEMP_A4_A4_Pos (0UL)                       /*!< Position of A4 field.                                                */
  #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field.                                                */


/* TEMP_A5: Slope of 6th piece wise linear function */
  #define TEMP_A5_ResetValue (0x00000522UL)          /*!< Reset value of A5 register.                                          */

/* A5 @Bits 0..11 : Slope of 6th piece wise linear function */
  #define TEMP_A5_A5_Pos (0UL)                       /*!< Position of A5 field.                                                */
  #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field.                                                */


/* TEMP_A6: Slope of 7th piece wise linear function */
  #define TEMP_A6_ResetValue (0x000005B7UL)          /*!< Reset value of A6 register.                                          */

/* A6 @Bits 0..11 : Slope of 7th piece wise linear function */
  #define TEMP_A6_A6_Pos (0UL)                       /*!< Position of A6 field.                                                */
  #define TEMP_A6_A6_Msk (0xFFFUL << TEMP_A6_A6_Pos) /*!< Bit mask of A6 field.                                                */


/* TEMP_B0: y-intercept of 1st piece wise linear function */
  #define TEMP_B0_ResetValue (0x00000FD6UL)          /*!< Reset value of B0 register.                                          */

/* B0 @Bits 0..11 : y-intercept of 1st piece wise linear function */
  #define TEMP_B0_B0_Pos (0UL)                       /*!< Position of B0 field.                                                */
  #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field.                                                */


/* TEMP_B1: y-intercept of 2nd piece wise linear function */
  #define TEMP_B1_ResetValue (0x00000F76UL)          /*!< Reset value of B1 register.                                          */

/* B1 @Bits 0..11 : y-intercept of 2nd piece wise linear function */
  #define TEMP_B1_B1_Pos (0UL)                       /*!< Position of B1 field.                                                */
  #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field.                                                */


/* TEMP_B2: y-intercept of 3rd piece wise linear function */
  #define TEMP_B2_ResetValue (0x00000F8AUL)          /*!< Reset value of B2 register.                                          */

/* B2 @Bits 0..11 : y-intercept of 3rd piece wise linear function */
  #define TEMP_B2_B2_Pos (0UL)                       /*!< Position of B2 field.                                                */
  #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field.                                                */


/* TEMP_B3: y-intercept of 4th piece wise linear function */
  #define TEMP_B3_ResetValue (0x00000FF8UL)          /*!< Reset value of B3 register.                                          */

/* B3 @Bits 0..11 : y-intercept of 4th piece wise linear function */
  #define TEMP_B3_B3_Pos (0UL)                       /*!< Position of B3 field.                                                */
  #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field.                                                */


/* TEMP_B4: y-intercept of 5th piece wise linear function */
  #define TEMP_B4_ResetValue (0x000000CCUL)          /*!< Reset value of B4 register.                                          */

/* B4 @Bits 0..11 : y-intercept of 5th piece wise linear function */
  #define TEMP_B4_B4_Pos (0UL)                       /*!< Position of B4 field.                                                */
  #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field.                                                */


/* TEMP_B5: y-intercept of 6th piece wise linear function */
  #define TEMP_B5_ResetValue (0x00000207UL)          /*!< Reset value of B5 register.                                          */

/* B5 @Bits 0..11 : y-intercept of 6th piece wise linear function */
  #define TEMP_B5_B5_Pos (0UL)                       /*!< Position of B5 field.                                                */
  #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field.                                                */


/* TEMP_B6: y-intercept of 7th piece wise linear function */
  #define TEMP_B6_ResetValue (0x00000558UL)          /*!< Reset value of B6 register.                                          */

/* B6 @Bits 0..11 : y-intercept of 7th piece wise linear function */
  #define TEMP_B6_B6_Pos (0UL)                       /*!< Position of B6 field.                                                */
  #define TEMP_B6_B6_Msk (0xFFFUL << TEMP_B6_B6_Pos) /*!< Bit mask of B6 field.                                                */


/* TEMP_T0: End point of 1st piece wise linear function */
  #define TEMP_T0_ResetValue (0x000000E2UL)          /*!< Reset value of T0 register.                                          */

/* T0 @Bits 0..7 : End point of 1st piece wise linear function */
  #define TEMP_T0_T0_Pos (0UL)                       /*!< Position of T0 field.                                                */
  #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos)  /*!< Bit mask of T0 field.                                                */


/* TEMP_T1: End point of 2nd piece wise linear function */
  #define TEMP_T1_ResetValue (0x00000002UL)          /*!< Reset value of T1 register.                                          */

/* T1 @Bits 0..7 : End point of 2nd piece wise linear function */
  #define TEMP_T1_T1_Pos (0UL)                       /*!< Position of T1 field.                                                */
  #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos)  /*!< Bit mask of T1 field.                                                */


/* TEMP_T2: End point of 3rd piece wise linear function */
  #define TEMP_T2_ResetValue (0x0000001FUL)          /*!< Reset value of T2 register.                                          */

/* T2 @Bits 0..7 : End point of 3rd piece wise linear function */
  #define TEMP_T2_T2_Pos (0UL)                       /*!< Position of T2 field.                                                */
  #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos)  /*!< Bit mask of T2 field.                                                */


/* TEMP_T3: End point of 4th piece wise linear function */
  #define TEMP_T3_ResetValue (0x00000038UL)          /*!< Reset value of T3 register.                                          */

/* T3 @Bits 0..7 : End point of 4th piece wise linear function */
  #define TEMP_T3_T3_Pos (0UL)                       /*!< Position of T3 field.                                                */
  #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos)  /*!< Bit mask of T3 field.                                                */


/* TEMP_T4: End point of 5th piece wise linear function */
  #define TEMP_T4_ResetValue (0x0000004FUL)          /*!< Reset value of T4 register.                                          */

/* T4 @Bits 0..7 : End point of 5th piece wise linear function */
  #define TEMP_T4_T4_Pos (0UL)                       /*!< Position of T4 field.                                                */
  #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos)  /*!< Bit mask of T4 field.                                                */


/* TEMP_T5: End point of 6th piece wise linear function */
  #define TEMP_T5_ResetValue (0x00000066UL)          /*!< Reset value of T5 register.                                          */

/* T5 @Bits 0..7 : End point of 6th piece wise linear function */
  #define TEMP_T5_T5_Pos (0UL)                       /*!< Position of T5 field.                                                */
  #define TEMP_T5_T5_Msk (0xFFUL << TEMP_T5_T5_Pos)  /*!< Bit mask of T5 field.                                                */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           TIMER                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ====================================================== Struct TIMER ======================================================= */
/**
  * @brief Timer/Counter
  */
  typedef struct {                                   /*!< TIMER Structure                                                      */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start Timer                                           */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop Timer                                            */
    __OM uint32_t TASKS_COUNT;                       /*!< (@ 0x00000008) Increment Timer (Counter mode only)                   */
    __OM uint32_t TASKS_CLEAR;                       /*!< (@ 0x0000000C) Clear time                                            */
    __IM uint32_t RESERVED[12];
    __OM uint32_t TASKS_CAPTURE[8];                  /*!< (@ 0x00000040) Capture Timer value to CC[n] register                 */
    __IM uint32_t RESERVED1[8];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IOM uint32_t SUBSCRIBE_COUNT;                  /*!< (@ 0x00000088) Subscribe configuration for task COUNT                */
    __IOM uint32_t SUBSCRIBE_CLEAR;                  /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR                */
    __IM uint32_t RESERVED2[12];
    __IOM uint32_t SUBSCRIBE_CAPTURE[8];             /*!< (@ 0x000000C0) Subscribe configuration for task CAPTURE[n]           */
    __IM uint32_t RESERVED3[24];
    __IOM uint32_t EVENTS_COMPARE[8];                /*!< (@ 0x00000140) Compare event on CC[n] match                          */
    __IM uint32_t RESERVED4[24];
    __IOM uint32_t PUBLISH_COMPARE[8];               /*!< (@ 0x000001C0) Publish configuration for event COMPARE[n]            */
    __IM uint32_t RESERVED5[8];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED6[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED7[126];
    __IOM uint32_t MODE;                             /*!< (@ 0x00000504) Timer mode selection                                  */
    __IOM uint32_t BITMODE;                          /*!< (@ 0x00000508) Configure the number of bits used by the TIMER        */
    __IM uint32_t RESERVED8;
    __IOM uint32_t PRESCALER;                        /*!< (@ 0x00000510) Timer prescaler register                              */
    __IM uint32_t RESERVED9[11];
    __IOM uint32_t CC[8];                            /*!< (@ 0x00000540) Capture/Compare register n                            */
    __IM uint32_t RESERVED10[8];
    __IOM uint32_t ONESHOTEN[8];                     /*!< (@ 0x00000580) Enable one-shot operation for Capture/Compare channel
                                                                         n*/
  } NRF_TIMER_Type;                                  /*!< Size = 1440 (0x5A0)                                                  */

/* TIMER_TASKS_START: Start Timer */
  #define TIMER_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */

/* TASKS_START @Bit 0 : Start Timer */
  #define TIMER_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
  #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
  #define TIMER_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
  #define TIMER_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
  #define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */


/* TIMER_TASKS_STOP: Stop Timer */
  #define TIMER_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop Timer */
  #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
  #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
  #define TIMER_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
  #define TIMER_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
  #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */


/* TIMER_TASKS_COUNT: Increment Timer (Counter mode only) */
  #define TIMER_TASKS_COUNT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_COUNT register.                                */

/* TASKS_COUNT @Bit 0 : Increment Timer (Counter mode only) */
  #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL)    /*!< Position of TASKS_COUNT field.                                       */
  #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field.   */
  #define TIMER_TASKS_COUNT_TASKS_COUNT_Min (0x1UL)  /*!< Min enumerator value of TASKS_COUNT field.                           */
  #define TIMER_TASKS_COUNT_TASKS_COUNT_Max (0x1UL)  /*!< Max enumerator value of TASKS_COUNT field.                           */
  #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task                                                      */


/* TIMER_TASKS_CLEAR: Clear time */
  #define TIMER_TASKS_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEAR register.                                */

/* TASKS_CLEAR @Bit 0 : Clear time */
  #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)    /*!< Position of TASKS_CLEAR field.                                       */
  #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field.   */
  #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL)  /*!< Min enumerator value of TASKS_CLEAR field.                           */
  #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL)  /*!< Max enumerator value of TASKS_CLEAR field.                           */
  #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task                                                      */


/* TIMER_TASKS_CAPTURE: Capture Timer value to CC[n] register */
  #define TIMER_TASKS_CAPTURE_MaxCount (8UL)         /*!< Max size of TASKS_CAPTURE[8] array.                                  */
  #define TIMER_TASKS_CAPTURE_MaxIndex (7UL)         /*!< Max index of TASKS_CAPTURE[8] array.                                 */
  #define TIMER_TASKS_CAPTURE_MinIndex (0UL)         /*!< Min index of TASKS_CAPTURE[8] array.                                 */
  #define TIMER_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[8] register.                         */

/* TASKS_CAPTURE @Bit 0 : Capture Timer value to CC[n] register */
  #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field.                                    */
  #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE
                                                                            field.*/
  #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field.                      */
  #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field.                      */
  #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task                                                  */


/* TIMER_SUBSCRIBE_START: Subscribe configuration for task START */
  #define TIMER_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define TIMER_SUBSCRIBE_START_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define TIMER_SUBSCRIBE_START_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TIMER_SUBSCRIBE_START_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                      */
  #define TIMER_SUBSCRIBE_START_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_START_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* TIMER_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define TIMER_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define TIMER_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define TIMER_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                        */
  #define TIMER_SUBSCRIBE_STOP_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_STOP_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
  #define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */


/* TIMER_SUBSCRIBE_COUNT: Subscribe configuration for task COUNT */
  #define TIMER_SUBSCRIBE_COUNT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_COUNT register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task COUNT will subscribe to */
  #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define TIMER_SUBSCRIBE_COUNT_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define TIMER_SUBSCRIBE_COUNT_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field.                      */
  #define TIMER_SUBSCRIBE_COUNT_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_COUNT_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* TIMER_SUBSCRIBE_CLEAR: Subscribe configuration for task CLEAR */
  #define TIMER_SUBSCRIBE_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLEAR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that task CLEAR will subscribe to */
  #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field.                      */
  #define TIMER_SUBSCRIBE_CLEAR_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_CLEAR_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* TIMER_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */
  #define TIMER_SUBSCRIBE_CAPTURE_MaxCount (8UL)     /*!< Max size of SUBSCRIBE_CAPTURE[8] array.                              */
  #define TIMER_SUBSCRIBE_CAPTURE_MaxIndex (7UL)     /*!< Max index of SUBSCRIBE_CAPTURE[8] array.                             */
  #define TIMER_SUBSCRIBE_CAPTURE_MinIndex (0UL)     /*!< Min index of SUBSCRIBE_CAPTURE[8] array.                             */
  #define TIMER_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[8] register.                 */

/* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */
  #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field.                  */
  #define TIMER_SUBSCRIBE_CAPTURE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_CAPTURE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* TIMER_EVENTS_COMPARE: Compare event on CC[n] match */
  #define TIMER_EVENTS_COMPARE_MaxCount (8UL)        /*!< Max size of EVENTS_COMPARE[8] array.                                 */
  #define TIMER_EVENTS_COMPARE_MaxIndex (7UL)        /*!< Max index of EVENTS_COMPARE[8] array.                                */
  #define TIMER_EVENTS_COMPARE_MinIndex (0UL)        /*!< Min index of EVENTS_COMPARE[8] array.                                */
  #define TIMER_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[8] register.                       */

/* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */
  #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field.                                 */
  #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of
                                                                            EVENTS_COMPARE field.*/
  #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field.                   */
  #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field.                   */
  #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated                                    */
  #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated                                           */


/* TIMER_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */
  #define TIMER_PUBLISH_COMPARE_MaxCount (8UL)       /*!< Max size of PUBLISH_COMPARE[8] array.                                */
  #define TIMER_PUBLISH_COMPARE_MaxIndex (7UL)       /*!< Max index of PUBLISH_COMPARE[8] array.                               */
  #define TIMER_PUBLISH_COMPARE_MinIndex (0UL)       /*!< Min index of PUBLISH_COMPARE[8] array.                               */
  #define TIMER_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[8] register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */
  #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define TIMER_PUBLISH_COMPARE_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define TIMER_PUBLISH_COMPARE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field.                      */
  #define TIMER_PUBLISH_COMPARE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define TIMER_PUBLISH_COMPARE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* TIMER_SHORTS: Shortcuts between local events and tasks */
  #define TIMER_SHORTS_ResetValue (0x00000000UL)     /*!< Reset value of SHORTS register.                                      */

/* COMPARE0_CLEAR @Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
  #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL)      /*!< Position of COMPARE0_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE0_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE0_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE0_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE0_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE1_CLEAR @Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
  #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL)      /*!< Position of COMPARE1_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE1_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE1_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE1_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE1_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE2_CLEAR @Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
  #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL)      /*!< Position of COMPARE2_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE2_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE2_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE2_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE2_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE3_CLEAR @Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
  #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL)      /*!< Position of COMPARE3_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE3_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE3_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE3_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE3_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE4_CLEAR @Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
  #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL)      /*!< Position of COMPARE4_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE4_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE4_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE4_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE4_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE5_CLEAR @Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
  #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL)      /*!< Position of COMPARE5_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE5_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE5_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE5_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE5_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE6_CLEAR @Bit 6 : Shortcut between event COMPARE[6] and task CLEAR */
  #define TIMER_SHORTS_COMPARE6_CLEAR_Pos (6UL)      /*!< Position of COMPARE6_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE6_CLEAR_Pos) /*!< Bit mask of COMPARE6_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE6_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE6_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE6_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE6_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE6_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE6_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE7_CLEAR @Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */
  #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL)      /*!< Position of COMPARE7_CLEAR field.                                    */
  #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field.    */
  #define TIMER_SHORTS_COMPARE7_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE7_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE7_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE7_CLEAR field.                        */
  #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
  #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */

/* COMPARE0_STOP @Bit 16 : Shortcut between event COMPARE[0] and task STOP */
  #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL)      /*!< Position of COMPARE0_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field.       */
  #define TIMER_SHORTS_COMPARE0_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE0_STOP field.                         */
  #define TIMER_SHORTS_COMPARE0_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE0_STOP field.                         */
  #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* COMPARE1_STOP @Bit 17 : Shortcut between event COMPARE[1] and task STOP */
  #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL)      /*!< Position of COMPARE1_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field.       */
  #define TIMER_SHORTS_COMPARE1_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE1_STOP field.                         */
  #define TIMER_SHORTS_COMPARE1_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE1_STOP field.                         */
  #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* COMPARE2_STOP @Bit 18 : Shortcut between event COMPARE[2] and task STOP */
  #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL)      /*!< Position of COMPARE2_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field.       */
  #define TIMER_SHORTS_COMPARE2_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE2_STOP field.                         */
  #define TIMER_SHORTS_COMPARE2_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE2_STOP field.                         */
  #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* COMPARE3_STOP @Bit 19 : Shortcut between event COMPARE[3] and task STOP */
  #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL)      /*!< Position of COMPARE3_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field.       */
  #define TIMER_SHORTS_COMPARE3_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE3_STOP field.                         */
  #define TIMER_SHORTS_COMPARE3_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE3_STOP field.                         */
  #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* COMPARE4_STOP @Bit 20 : Shortcut between event COMPARE[4] and task STOP */
  #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL)      /*!< Position of COMPARE4_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field.       */
  #define TIMER_SHORTS_COMPARE4_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE4_STOP field.                         */
  #define TIMER_SHORTS_COMPARE4_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE4_STOP field.                         */
  #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* COMPARE5_STOP @Bit 21 : Shortcut between event COMPARE[5] and task STOP */
  #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL)      /*!< Position of COMPARE5_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field.       */
  #define TIMER_SHORTS_COMPARE5_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE5_STOP field.                         */
  #define TIMER_SHORTS_COMPARE5_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE5_STOP field.                         */
  #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* COMPARE6_STOP @Bit 22 : Shortcut between event COMPARE[6] and task STOP */
  #define TIMER_SHORTS_COMPARE6_STOP_Pos (22UL)      /*!< Position of COMPARE6_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE6_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE6_STOP_Pos) /*!< Bit mask of COMPARE6_STOP field.       */
  #define TIMER_SHORTS_COMPARE6_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE6_STOP field.                         */
  #define TIMER_SHORTS_COMPARE6_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE6_STOP field.                         */
  #define TIMER_SHORTS_COMPARE6_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE6_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* COMPARE7_STOP @Bit 23 : Shortcut between event COMPARE[7] and task STOP */
  #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL)      /*!< Position of COMPARE7_STOP field.                                     */
  #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field.       */
  #define TIMER_SHORTS_COMPARE7_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE7_STOP field.                         */
  #define TIMER_SHORTS_COMPARE7_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE7_STOP field.                         */
  #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TIMER_SHORTS_COMPARE7_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */


/* TIMER_INTEN: Enable or disable interrupt */
  #define TIMER_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */

/* COMPARE0 @Bit 16 : Enable or disable interrupt for event COMPARE[0] */
  #define TIMER_INTEN_COMPARE0_Pos (16UL)            /*!< Position of COMPARE0 field.                                          */
  #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
  #define TIMER_INTEN_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
  #define TIMER_INTEN_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
  #define TIMER_INTEN_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE1 @Bit 17 : Enable or disable interrupt for event COMPARE[1] */
  #define TIMER_INTEN_COMPARE1_Pos (17UL)            /*!< Position of COMPARE1 field.                                          */
  #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
  #define TIMER_INTEN_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
  #define TIMER_INTEN_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
  #define TIMER_INTEN_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE2 @Bit 18 : Enable or disable interrupt for event COMPARE[2] */
  #define TIMER_INTEN_COMPARE2_Pos (18UL)            /*!< Position of COMPARE2 field.                                          */
  #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
  #define TIMER_INTEN_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
  #define TIMER_INTEN_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
  #define TIMER_INTEN_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE3 @Bit 19 : Enable or disable interrupt for event COMPARE[3] */
  #define TIMER_INTEN_COMPARE3_Pos (19UL)            /*!< Position of COMPARE3 field.                                          */
  #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
  #define TIMER_INTEN_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
  #define TIMER_INTEN_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
  #define TIMER_INTEN_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE4 @Bit 20 : Enable or disable interrupt for event COMPARE[4] */
  #define TIMER_INTEN_COMPARE4_Pos (20UL)            /*!< Position of COMPARE4 field.                                          */
  #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
  #define TIMER_INTEN_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
  #define TIMER_INTEN_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
  #define TIMER_INTEN_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE5 @Bit 21 : Enable or disable interrupt for event COMPARE[5] */
  #define TIMER_INTEN_COMPARE5_Pos (21UL)            /*!< Position of COMPARE5 field.                                          */
  #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
  #define TIMER_INTEN_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
  #define TIMER_INTEN_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
  #define TIMER_INTEN_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE6 @Bit 22 : Enable or disable interrupt for event COMPARE[6] */
  #define TIMER_INTEN_COMPARE6_Pos (22UL)            /*!< Position of COMPARE6 field.                                          */
  #define TIMER_INTEN_COMPARE6_Msk (0x1UL << TIMER_INTEN_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
  #define TIMER_INTEN_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
  #define TIMER_INTEN_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
  #define TIMER_INTEN_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */

/* COMPARE7 @Bit 23 : Enable or disable interrupt for event COMPARE[7] */
  #define TIMER_INTEN_COMPARE7_Pos (23UL)            /*!< Position of COMPARE7 field.                                          */
  #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
  #define TIMER_INTEN_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
  #define TIMER_INTEN_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
  #define TIMER_INTEN_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TIMER_INTEN_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */


/* TIMER_INTENSET: Enable interrupt */
  #define TIMER_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */

/* COMPARE0 @Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
  #define TIMER_INTENSET_COMPARE0_Pos (16UL)         /*!< Position of COMPARE0 field.                                          */
  #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define TIMER_INTENSET_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define TIMER_INTENSET_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define TIMER_INTENSET_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
  #define TIMER_INTENSET_COMPARE1_Pos (17UL)         /*!< Position of COMPARE1 field.                                          */
  #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define TIMER_INTENSET_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define TIMER_INTENSET_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define TIMER_INTENSET_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
  #define TIMER_INTENSET_COMPARE2_Pos (18UL)         /*!< Position of COMPARE2 field.                                          */
  #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define TIMER_INTENSET_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define TIMER_INTENSET_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define TIMER_INTENSET_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
  #define TIMER_INTENSET_COMPARE3_Pos (19UL)         /*!< Position of COMPARE3 field.                                          */
  #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define TIMER_INTENSET_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define TIMER_INTENSET_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define TIMER_INTENSET_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
  #define TIMER_INTENSET_COMPARE4_Pos (20UL)         /*!< Position of COMPARE4 field.                                          */
  #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define TIMER_INTENSET_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define TIMER_INTENSET_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define TIMER_INTENSET_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
  #define TIMER_INTENSET_COMPARE5_Pos (21UL)         /*!< Position of COMPARE5 field.                                          */
  #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define TIMER_INTENSET_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define TIMER_INTENSET_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define TIMER_INTENSET_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 22 : Write '1' to enable interrupt for event COMPARE[6] */
  #define TIMER_INTENSET_COMPARE6_Pos (22UL)         /*!< Position of COMPARE6 field.                                          */
  #define TIMER_INTENSET_COMPARE6_Msk (0x1UL << TIMER_INTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define TIMER_INTENSET_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define TIMER_INTENSET_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define TIMER_INTENSET_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */
  #define TIMER_INTENSET_COMPARE7_Pos (23UL)         /*!< Position of COMPARE7 field.                                          */
  #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define TIMER_INTENSET_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define TIMER_INTENSET_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define TIMER_INTENSET_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
  #define TIMER_INTENSET_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENSET_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */


/* TIMER_INTENCLR: Disable interrupt */
  #define TIMER_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */

/* COMPARE0 @Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
  #define TIMER_INTENCLR_COMPARE0_Pos (16UL)         /*!< Position of COMPARE0 field.                                          */
  #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
  #define TIMER_INTENCLR_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
  #define TIMER_INTENCLR_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
  #define TIMER_INTENCLR_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE1 @Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
  #define TIMER_INTENCLR_COMPARE1_Pos (17UL)         /*!< Position of COMPARE1 field.                                          */
  #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
  #define TIMER_INTENCLR_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
  #define TIMER_INTENCLR_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
  #define TIMER_INTENCLR_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE2 @Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
  #define TIMER_INTENCLR_COMPARE2_Pos (18UL)         /*!< Position of COMPARE2 field.                                          */
  #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
  #define TIMER_INTENCLR_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
  #define TIMER_INTENCLR_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
  #define TIMER_INTENCLR_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE3 @Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
  #define TIMER_INTENCLR_COMPARE3_Pos (19UL)         /*!< Position of COMPARE3 field.                                          */
  #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
  #define TIMER_INTENCLR_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
  #define TIMER_INTENCLR_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
  #define TIMER_INTENCLR_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE4 @Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
  #define TIMER_INTENCLR_COMPARE4_Pos (20UL)         /*!< Position of COMPARE4 field.                                          */
  #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
  #define TIMER_INTENCLR_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
  #define TIMER_INTENCLR_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
  #define TIMER_INTENCLR_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE5 @Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
  #define TIMER_INTENCLR_COMPARE5_Pos (21UL)         /*!< Position of COMPARE5 field.                                          */
  #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
  #define TIMER_INTENCLR_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
  #define TIMER_INTENCLR_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
  #define TIMER_INTENCLR_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE6 @Bit 22 : Write '1' to disable interrupt for event COMPARE[6] */
  #define TIMER_INTENCLR_COMPARE6_Pos (22UL)         /*!< Position of COMPARE6 field.                                          */
  #define TIMER_INTENCLR_COMPARE6_Msk (0x1UL << TIMER_INTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
  #define TIMER_INTENCLR_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
  #define TIMER_INTENCLR_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
  #define TIMER_INTENCLR_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* COMPARE7 @Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */
  #define TIMER_INTENCLR_COMPARE7_Pos (23UL)         /*!< Position of COMPARE7 field.                                          */
  #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
  #define TIMER_INTENCLR_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
  #define TIMER_INTENCLR_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
  #define TIMER_INTENCLR_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
  #define TIMER_INTENCLR_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TIMER_INTENCLR_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */


/* TIMER_MODE: Timer mode selection */
  #define TIMER_MODE_ResetValue (0x00000000UL)       /*!< Reset value of MODE register.                                        */

/* MODE @Bits 0..1 : Timer mode */
  #define TIMER_MODE_MODE_Pos (0UL)                  /*!< Position of MODE field.                                              */
  #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                      */
  #define TIMER_MODE_MODE_Min (0x0UL)                /*!< Min enumerator value of MODE field.                                  */
  #define TIMER_MODE_MODE_Max (0x2UL)                /*!< Max enumerator value of MODE field.                                  */
  #define TIMER_MODE_MODE_Timer (0x0UL)              /*!< Select Timer mode                                                    */
  #define TIMER_MODE_MODE_Counter (0x1UL)            /*!< Select Counter mode                                                  */
  #define TIMER_MODE_MODE_LowPowerCounter (0x2UL)    /*!< Select Low Power Counter mode                                        */


/* TIMER_BITMODE: Configure the number of bits used by the TIMER */
  #define TIMER_BITMODE_ResetValue (0x00000000UL)    /*!< Reset value of BITMODE register.                                     */

/* BITMODE @Bits 0..1 : Timer bit width */
  #define TIMER_BITMODE_BITMODE_Pos (0UL)            /*!< Position of BITMODE field.                                           */
  #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field.                       */
  #define TIMER_BITMODE_BITMODE_Min (0x0UL)          /*!< Min enumerator value of BITMODE field.                               */
  #define TIMER_BITMODE_BITMODE_Max (0x3UL)          /*!< Max enumerator value of BITMODE field.                               */
  #define TIMER_BITMODE_BITMODE_16Bit (0x0UL)        /*!< 16 bit timer bit width                                               */
  #define TIMER_BITMODE_BITMODE_08Bit (0x1UL)        /*!< 8 bit timer bit width                                                */
  #define TIMER_BITMODE_BITMODE_24Bit (0x2UL)        /*!< 24 bit timer bit width                                               */
  #define TIMER_BITMODE_BITMODE_32Bit (0x3UL)        /*!< 32 bit timer bit width                                               */


/* TIMER_PRESCALER: Timer prescaler register */
  #define TIMER_PRESCALER_ResetValue (0x00000004UL)  /*!< Reset value of PRESCALER register.                                   */

/* PRESCALER @Bits 0..3 : Prescaler value */
  #define TIMER_PRESCALER_PRESCALER_Pos (0UL)        /*!< Position of PRESCALER field.                                         */
  #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field.             */
  #define TIMER_PRESCALER_PRESCALER_Min (0x0UL)      /*!< Min value of PRESCALER field.                                        */
  #define TIMER_PRESCALER_PRESCALER_Max (0x9UL)      /*!< Max size of PRESCALER field.                                         */


/* TIMER_CC: Capture/Compare register n */
  #define TIMER_CC_MaxCount (8UL)                    /*!< Max size of CC[8] array.                                             */
  #define TIMER_CC_MaxIndex (7UL)                    /*!< Max index of CC[8] array.                                            */
  #define TIMER_CC_MinIndex (0UL)                    /*!< Min index of CC[8] array.                                            */
  #define TIMER_CC_ResetValue (0x00000000UL)         /*!< Reset value of CC[8] register.                                       */

/* CC @Bits 0..31 : Capture/Compare value */
  #define TIMER_CC_CC_Pos (0UL)                      /*!< Position of CC field.                                                */
  #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field.                                         */


/* TIMER_ONESHOTEN: Enable one-shot operation for Capture/Compare channel n */
  #define TIMER_ONESHOTEN_MaxCount (8UL)             /*!< Max size of ONESHOTEN[8] array.                                      */
  #define TIMER_ONESHOTEN_MaxIndex (7UL)             /*!< Max index of ONESHOTEN[8] array.                                     */
  #define TIMER_ONESHOTEN_MinIndex (0UL)             /*!< Min index of ONESHOTEN[8] array.                                     */
  #define TIMER_ONESHOTEN_ResetValue (0x00000000UL)  /*!< Reset value of ONESHOTEN[8] register.                                */

/* ONESHOTEN @Bit 0 : Enable one-shot operation */
  #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL)        /*!< Position of ONESHOTEN field.                                         */
  #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field.             */
  #define TIMER_ONESHOTEN_ONESHOTEN_Min (0x0UL)      /*!< Min enumerator value of ONESHOTEN field.                             */
  #define TIMER_ONESHOTEN_ONESHOTEN_Max (0x1UL)      /*!< Max enumerator value of ONESHOTEN field.                             */
  #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL)  /*!< Disable one-shot operation                                           */
  #define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL)   /*!< Enable one-shot operation                                            */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           TPIU                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct TPIU ======================================================= */
/**
  * @brief Trace Port Interface Unit
  */
  typedef struct {                                   /*!< TPIU Structure                                                       */
    __IM uint32_t RESERVED;
  } NRF_TPIU_Type;                                   /*!< Size = 4 (0x004)                                                     */

#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           TWIM                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct TWIM_TASKS_DMA_RX ================================================= */
/**
  * @brief RX [TWIM_TASKS_DMA_RX] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  START;                             /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See
                                                                         peripheral description for operation using easyDMA.*/
  __OM  uint32_t  STOP;                              /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an
                                                                         END event.*/
  __OM  uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000008) Enables the MATCH[n] event by setting the ENABLE[n] bit
                                                                         in the CONFIG register.*/
  __OM  uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000018) Disables the MATCH[n] event by clearing the ENABLE[n]
                                                                         bit in the CONFIG register.*/
} NRF_TWIM_TASKS_DMA_RX_Type;                        /*!< Size = 40 (0x028)                                                    */

/* TWIM_TASKS_DMA_RX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using
                             easyDMA. */

  #define TWIM_TASKS_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                                */

/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */
  #define TWIM_TASKS_DMA_RX_START_START_Pos (0UL)    /*!< Position of START field.                                             */
  #define TWIM_TASKS_DMA_RX_START_START_Msk (0x1UL << TWIM_TASKS_DMA_RX_START_START_Pos) /*!< Bit mask of START field.         */
  #define TWIM_TASKS_DMA_RX_START_START_Min (0x1UL)  /*!< Min enumerator value of START field.                                 */
  #define TWIM_TASKS_DMA_RX_START_START_Max (0x1UL)  /*!< Max enumerator value of START field.                                 */
  #define TWIM_TASKS_DMA_RX_START_START_Trigger (0x1UL) /*!< Trigger task                                                      */


/* TWIM_TASKS_DMA_RX_STOP: Stops operation using easyDMA. This does not trigger an END event. */
  #define TWIM_TASKS_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                                  */

/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */
  #define TWIM_TASKS_DMA_RX_STOP_STOP_Pos (0UL)      /*!< Position of STOP field.                                              */
  #define TWIM_TASKS_DMA_RX_STOP_STOP_Msk (0x1UL << TWIM_TASKS_DMA_RX_STOP_STOP_Pos) /*!< Bit mask of STOP field.              */
  #define TWIM_TASKS_DMA_RX_STOP_STOP_Min (0x1UL)    /*!< Min enumerator value of STOP field.                                  */
  #define TWIM_TASKS_DMA_RX_STOP_STOP_Max (0x1UL)    /*!< Max enumerator value of STOP field.                                  */
  #define TWIM_TASKS_DMA_RX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */


/* TWIM_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                                  */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                                 */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                                 */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.                 */

/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field.                              */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask
                                                                            of ENABLEMATCH field.*/
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field.                */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field.                */
  #define TWIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                          */


/* TWIM_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                                */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                               */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                               */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.               */

/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field.                           */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit
                                                                            mask of DISABLEMATCH field.*/
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field.             */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field.             */
  #define TWIM_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                        */



/* ================================================ Struct TWIM_TASKS_DMA_TX ================================================= */
/**
  * @brief TX [TWIM_TASKS_DMA_TX] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  START;                             /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See
                                                                         peripheral description for operation using easyDMA.*/
  __OM  uint32_t  STOP;                              /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an
                                                                         END event.*/
} NRF_TWIM_TASKS_DMA_TX_Type;                        /*!< Size = 8 (0x008)                                                     */

/* TWIM_TASKS_DMA_TX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using
                             easyDMA. */

  #define TWIM_TASKS_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                                */

/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */
  #define TWIM_TASKS_DMA_TX_START_START_Pos (0UL)    /*!< Position of START field.                                             */
  #define TWIM_TASKS_DMA_TX_START_START_Msk (0x1UL << TWIM_TASKS_DMA_TX_START_START_Pos) /*!< Bit mask of START field.         */
  #define TWIM_TASKS_DMA_TX_START_START_Min (0x1UL)  /*!< Min enumerator value of START field.                                 */
  #define TWIM_TASKS_DMA_TX_START_START_Max (0x1UL)  /*!< Max enumerator value of START field.                                 */
  #define TWIM_TASKS_DMA_TX_START_START_Trigger (0x1UL) /*!< Trigger task                                                      */


/* TWIM_TASKS_DMA_TX_STOP: Stops operation using easyDMA. This does not trigger an END event. */
  #define TWIM_TASKS_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                                  */

/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */
  #define TWIM_TASKS_DMA_TX_STOP_STOP_Pos (0UL)      /*!< Position of STOP field.                                              */
  #define TWIM_TASKS_DMA_TX_STOP_STOP_Msk (0x1UL << TWIM_TASKS_DMA_TX_STOP_STOP_Pos) /*!< Bit mask of STOP field.              */
  #define TWIM_TASKS_DMA_TX_STOP_STOP_Min (0x1UL)    /*!< Min enumerator value of STOP field.                                  */
  #define TWIM_TASKS_DMA_TX_STOP_STOP_Max (0x1UL)    /*!< Max enumerator value of STOP field.                                  */
  #define TWIM_TASKS_DMA_TX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */



/* ================================================== Struct TWIM_TASKS_DMA ================================================== */
/**
  * @brief TASKS_DMA [TWIM_TASKS_DMA] Peripheral tasks.
  */
typedef struct {
  __OM  NRF_TWIM_TASKS_DMA_RX_Type RX;               /*!< (@ 0x00000000) Peripheral tasks.                                     */
  __OM  NRF_TWIM_TASKS_DMA_TX_Type TX;               /*!< (@ 0x00000028) Peripheral tasks.                                     */
} NRF_TWIM_TASKS_DMA_Type;                           /*!< Size = 48 (0x030)                                                    */


/* ============================================== Struct TWIM_SUBSCRIBE_DMA_RX =============================================== */
/**
  * @brief RX [TWIM_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  START;                             /*!< (@ 0x00000000) Subscribe configuration for task START                */
  __IOM uint32_t  STOP;                              /*!< (@ 0x00000004) Subscribe configuration for task STOP                 */
  __IOM uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000008) Subscribe configuration for task ENABLEMATCH[n]       */
  __IOM uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000018) Subscribe configuration for task DISABLEMATCH[n]      */
} NRF_TWIM_SUBSCRIBE_DMA_RX_Type;                    /*!< Size = 40 (0x028)                                                    */

/* TWIM_SUBSCRIBE_DMA_RX_START: Subscribe configuration for task START */
  #define TWIM_SUBSCRIBE_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
  #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
  #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                        */
  #define TWIM_SUBSCRIBE_DMA_RX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Pos (31UL)  /*!< Position of EN field.                                                */
  #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_START_EN_Pos) /*!< Bit mask of EN field.          */
  #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Disabled (0x0UL) /*!< Disable subscription                                            */
  #define TWIM_SUBSCRIBE_DMA_RX_START_EN_Enabled (0x1UL) /*!< Enable subscription                                              */


/* TWIM_SUBSCRIBE_DMA_RX_STOP: Subscribe configuration for task STOP */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Pos) /*!< Bit mask of EN field.            */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription                                             */
  #define TWIM_SUBSCRIBE_DMA_RX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription                                               */


/* TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                              */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                             */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                             */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.             */

/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                      */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                  */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                   */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                           */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                              */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                              */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                      */
  #define TWIM_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                        */


/* TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                            */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                           */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                           */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.           */

/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                     */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                 */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                  */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                          */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                             */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                             */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                     */
  #define TWIM_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                       */



/* ============================================== Struct TWIM_SUBSCRIBE_DMA_TX =============================================== */
/**
  * @brief TX [TWIM_SUBSCRIBE_DMA_TX] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  START;                             /*!< (@ 0x00000000) Subscribe configuration for task START                */
  __IOM uint32_t  STOP;                              /*!< (@ 0x00000004) Subscribe configuration for task STOP                 */
} NRF_TWIM_SUBSCRIBE_DMA_TX_Type;                    /*!< Size = 8 (0x008)                                                     */

/* TWIM_SUBSCRIBE_DMA_TX_START: Subscribe configuration for task START */
  #define TWIM_SUBSCRIBE_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
  #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
  #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                        */
  #define TWIM_SUBSCRIBE_DMA_TX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Pos (31UL)  /*!< Position of EN field.                                                */
  #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_TX_START_EN_Pos) /*!< Bit mask of EN field.          */
  #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Disabled (0x0UL) /*!< Disable subscription                                            */
  #define TWIM_SUBSCRIBE_DMA_TX_START_EN_Enabled (0x1UL) /*!< Enable subscription                                              */


/* TWIM_SUBSCRIBE_DMA_TX_STOP: Subscribe configuration for task STOP */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Pos) /*!< Bit mask of EN field.            */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription                                             */
  #define TWIM_SUBSCRIBE_DMA_TX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription                                               */



/* ================================================ Struct TWIM_SUBSCRIBE_DMA ================================================ */
/**
  * @brief SUBSCRIBE_DMA [TWIM_SUBSCRIBE_DMA] Subscribe configuration for tasks
  */
typedef struct {
  __IOM NRF_TWIM_SUBSCRIBE_DMA_RX_Type RX;           /*!< (@ 0x00000000) Subscribe configuration for tasks                     */
  __IOM NRF_TWIM_SUBSCRIBE_DMA_TX_Type TX;           /*!< (@ 0x00000028) Subscribe configuration for tasks                     */
} NRF_TWIM_SUBSCRIBE_DMA_Type;                       /*!< Size = 48 (0x030)                                                    */


/* ================================================ Struct TWIM_EVENTS_DMA_RX ================================================ */
/**
  * @brief RX [TWIM_EVENTS_DMA_RX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus.        */
} NRF_TWIM_EVENTS_DMA_RX_Type;                       /*!< Size = 28 (0x01C)                                                    */

/* TWIM_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */
  #define TWIM_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define TWIM_EVENTS_DMA_RX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define TWIM_EVENTS_DMA_RX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define TWIM_EVENTS_DMA_RX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define TWIM_EVENTS_DMA_RX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define TWIM_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define TWIM_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* TWIM_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define TWIM_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define TWIM_EVENTS_DMA_RX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define TWIM_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << TWIM_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define TWIM_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define TWIM_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define TWIM_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIM_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* TWIM_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */
  #define TWIM_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */


/* TWIM_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */
  #define TWIM_EVENTS_DMA_RX_MATCH_MaxCount (4UL)    /*!< Max size of MATCH[4] array.                                          */
  #define TWIM_EVENTS_DMA_RX_MATCH_MaxIndex (3UL)    /*!< Max index of MATCH[4] array.                                         */
  #define TWIM_EVENTS_DMA_RX_MATCH_MinIndex (0UL)    /*!< Min index of MATCH[4] array.                                         */
  #define TWIM_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                            */

/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */
  #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL)   /*!< Position of MATCH field.                                             */
  #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << TWIM_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field.       */
  #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field.                                 */
  #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field.                                 */
  #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIM_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated                                                */



/* ================================================ Struct TWIM_EVENTS_DMA_TX ================================================ */
/**
  * @brief TX [TWIM_EVENTS_DMA_TX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
} NRF_TWIM_EVENTS_DMA_TX_Type;                       /*!< Size = 12 (0x00C)                                                    */

/* TWIM_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */
  #define TWIM_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define TWIM_EVENTS_DMA_TX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define TWIM_EVENTS_DMA_TX_END_END_Msk (0x1UL << TWIM_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define TWIM_EVENTS_DMA_TX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define TWIM_EVENTS_DMA_TX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define TWIM_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define TWIM_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* TWIM_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define TWIM_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define TWIM_EVENTS_DMA_TX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define TWIM_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << TWIM_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define TWIM_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define TWIM_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define TWIM_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIM_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* TWIM_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */
  #define TWIM_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define TWIM_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */



/* ================================================= Struct TWIM_EVENTS_DMA ================================================== */
/**
  * @brief EVENTS_DMA [TWIM_EVENTS_DMA] Peripheral events.
  */
typedef struct {
  __IOM NRF_TWIM_EVENTS_DMA_RX_Type RX;              /*!< (@ 0x00000000) Peripheral events.                                    */
  __IOM NRF_TWIM_EVENTS_DMA_TX_Type TX;              /*!< (@ 0x0000001C) Peripheral events.                                    */
} NRF_TWIM_EVENTS_DMA_Type;                          /*!< Size = 40 (0x028)                                                    */


/* =============================================== Struct TWIM_PUBLISH_DMA_RX ================================================ */
/**
  * @brief RX [TWIM_PUBLISH_DMA_RX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Publish configuration for event MATCH[n]              */
} NRF_TWIM_PUBLISH_DMA_RX_Type;                      /*!< Size = 28 (0x01C)                                                    */

/* TWIM_PUBLISH_DMA_RX_END: Publish configuration for event END */
  #define TWIM_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define TWIM_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_DMA_RX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define TWIM_PUBLISH_DMA_RX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_RX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define TWIM_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* TWIM_PUBLISH_DMA_RX_READY: Publish configuration for event READY */
  #define TWIM_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define TWIM_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_DMA_RX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define TWIM_PUBLISH_DMA_RX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_RX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define TWIM_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* TWIM_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define TWIM_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */


/* TWIM_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */
  #define TWIM_PUBLISH_DMA_RX_MATCH_MaxCount (4UL)   /*!< Max size of MATCH[4] array.                                          */
  #define TWIM_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL)   /*!< Max index of MATCH[4] array.                                         */
  #define TWIM_PUBLISH_DMA_RX_MATCH_MinIndex (0UL)   /*!< Min index of MATCH[4] array.                                         */
  #define TWIM_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */
  #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define TWIM_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field.              */
  #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define TWIM_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */



/* =============================================== Struct TWIM_PUBLISH_DMA_TX ================================================ */
/**
  * @brief TX [TWIM_PUBLISH_DMA_TX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
} NRF_TWIM_PUBLISH_DMA_TX_Type;                      /*!< Size = 12 (0x00C)                                                    */

/* TWIM_PUBLISH_DMA_TX_END: Publish configuration for event END */
  #define TWIM_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define TWIM_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_DMA_TX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define TWIM_PUBLISH_DMA_TX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_TX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define TWIM_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* TWIM_PUBLISH_DMA_TX_READY: Publish configuration for event READY */
  #define TWIM_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define TWIM_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_DMA_TX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define TWIM_PUBLISH_DMA_TX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_TX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define TWIM_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* TWIM_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define TWIM_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */



/* ================================================= Struct TWIM_PUBLISH_DMA ================================================= */
/**
  * @brief PUBLISH_DMA [TWIM_PUBLISH_DMA] Publish configuration for events
  */
typedef struct {
  __IOM NRF_TWIM_PUBLISH_DMA_RX_Type RX;             /*!< (@ 0x00000000) Publish configuration for events                      */
  __IOM NRF_TWIM_PUBLISH_DMA_TX_Type TX;             /*!< (@ 0x0000001C) Publish configuration for events                      */
} NRF_TWIM_PUBLISH_DMA_Type;                         /*!< Size = 40 (0x028)                                                    */


/* ==================================================== Struct TWIM_PSEL ===================================================== */
/**
  * @brief PSEL [TWIM_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  SCL;                               /*!< (@ 0x00000000) Pin select for SCL signal                             */
  __IOM uint32_t  SDA;                               /*!< (@ 0x00000004) Pin select for SDA signal                             */
} NRF_TWIM_PSEL_Type;                                /*!< Size = 8 (0x008)                                                     */

/* TWIM_PSEL_SCL: Pin select for SCL signal */
  #define TWIM_PSEL_SCL_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCL register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define TWIM_PSEL_SCL_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define TWIM_PSEL_SCL_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define TWIM_PSEL_SCL_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define TWIM_PSEL_SCL_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define TWIM_PSEL_SCL_PORT_Msk (0x7UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define TWIM_PSEL_SCL_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define TWIM_PSEL_SCL_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define TWIM_PSEL_SCL_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define TWIM_PSEL_SCL_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define TWIM_PSEL_SCL_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* TWIM_PSEL_SDA: Pin select for SDA signal */
  #define TWIM_PSEL_SDA_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SDA register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define TWIM_PSEL_SDA_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define TWIM_PSEL_SDA_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define TWIM_PSEL_SDA_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define TWIM_PSEL_SDA_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define TWIM_PSEL_SDA_PORT_Msk (0x7UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define TWIM_PSEL_SDA_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define TWIM_PSEL_SDA_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define TWIM_PSEL_SDA_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define TWIM_PSEL_SDA_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define TWIM_PSEL_SDA_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */



/* ================================================ Struct TWIM_DMA_RX_MATCH ================================================= */
/**
  * @brief MATCH [TWIM_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Configure individual match events                     */
  __IOM uint32_t  CANDIDATE[4];                      /*!< (@ 0x00000004) The data to look for - any match will trigger the
                                                                         MATCH[n] event, if enabled.*/
} NRF_TWIM_DMA_RX_MATCH_Type;                        /*!< Size = 20 (0x014)                                                    */

/* TWIM_DMA_RX_MATCH_CONFIG: Configure individual match events */
  #define TWIM_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                              */

/* ENABLE0 @Bit 0 : Enable match filter 0 */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field.                                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE1 @Bit 1 : Enable match filter 1 */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field.                                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE2 @Bit 2 : Enable match filter 2 */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field.                                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE3 @Bit 3 : Enable match filter 3 */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field.                                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                             */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field.                                        */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0
                                                                            field.*/
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field.                                        */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1
                                                                            field.*/
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field.                                        */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2
                                                                            field.*/
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field.                                        */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3
                                                                            field.*/
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field.                           */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */


/* TWIM_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */
  #define TWIM_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array.                                      */
  #define TWIM_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array.                                     */
  #define TWIM_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array.                                     */
  #define TWIM_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register.                     */

/* DATA @Bits 0..31 : Data to look for */
  #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field.                                              */
  #define TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA
                                                                            field.*/



/* =================================================== Struct TWIM_DMA_RX ==================================================== */
/**
  * @brief RX [TWIM_DMA_RX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
  __IOM NRF_TWIM_DMA_RX_MATCH_Type MATCH;            /*!< (@ 0x00000024) Registers to control the behavior of the pattern
                                                                         matcher engine*/
} NRF_TWIM_DMA_RX_Type;                              /*!< Size = 56 (0x038)                                                    */

/* TWIM_DMA_RX_PTR: RAM buffer start address */
  #define TWIM_DMA_RX_PTR_ResetValue (0x20000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define TWIM_DMA_RX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define TWIM_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* TWIM_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */
  #define TWIM_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define TWIM_DMA_RX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define TWIM_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define TWIM_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define TWIM_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* TWIM_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define TWIM_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define TWIM_DMA_RX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define TWIM_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define TWIM_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define TWIM_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* TWIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define TWIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* TWIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define TWIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* =================================================== Struct TWIM_DMA_TX ==================================================== */
/**
  * @brief TX [TWIM_DMA_TX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_TWIM_DMA_TX_Type;                              /*!< Size = 36 (0x024)                                                    */

/* TWIM_DMA_TX_PTR: RAM buffer start address */
  #define TWIM_DMA_TX_PTR_ResetValue (0x20000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define TWIM_DMA_TX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define TWIM_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* TWIM_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */
  #define TWIM_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define TWIM_DMA_TX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define TWIM_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define TWIM_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define TWIM_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* TWIM_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define TWIM_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define TWIM_DMA_TX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define TWIM_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define TWIM_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define TWIM_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* TWIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define TWIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* TWIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define TWIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* ===================================================== Struct TWIM_DMA ===================================================== */
/**
  * @brief DMA [TWIM_DMA] (unspecified)
  */
typedef struct {
  __IOM NRF_TWIM_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
  __IOM NRF_TWIM_DMA_TX_Type TX;                     /*!< (@ 0x00000038) (unspecified)                                         */
} NRF_TWIM_DMA_Type;                                 /*!< Size = 92 (0x05C)                                                    */

/* ======================================================= Struct TWIM ======================================================= */
/**
  * @brief I2C compatible Two-Wire Master Interface with EasyDMA
  */
  typedef struct {                                   /*!< TWIM Structure                                                       */
    __IM uint32_t RESERVED;
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop TWI transaction. Must be issued while the TWI
                                                                         master is not suspended.*/
    __IM uint32_t RESERVED1;
    __OM uint32_t TASKS_SUSPEND;                     /*!< (@ 0x0000000C) Suspend TWI transaction                               */
    __OM uint32_t TASKS_RESUME;                      /*!< (@ 0x00000010) Resume TWI transaction                                */
    __IM uint32_t RESERVED2[5];
    __OM NRF_TWIM_TASKS_DMA_Type TASKS_DMA;          /*!< (@ 0x00000028) Peripheral tasks.                                     */
    __IM uint32_t RESERVED3[11];
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED4;
    __IOM uint32_t SUBSCRIBE_SUSPEND;                /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND              */
    __IOM uint32_t SUBSCRIBE_RESUME;                 /*!< (@ 0x00000090) Subscribe configuration for task RESUME               */
    __IM uint32_t RESERVED5[5];
    __IOM NRF_TWIM_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks                     */
    __IM uint32_t RESERVED6[11];
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) TWI stopped                                           */
    __IM uint32_t RESERVED7[3];
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000114) TWI error                                             */
    __IM uint32_t RESERVED8[4];
    __IOM uint32_t EVENTS_SUSPENDED;                 /*!< (@ 0x00000128) SUSPEND task has been issued, TWI traffic is now
                                                                         suspended.*/
    __IM uint32_t RESERVED9[2];
    __IOM uint32_t EVENTS_LASTRX;                    /*!< (@ 0x00000134) Byte boundary, starting to receive the last byte      */
    __IOM uint32_t EVENTS_LASTTX;                    /*!< (@ 0x00000138) Byte boundary, starting to transmit the last byte     */
    __IM uint32_t RESERVED10[4];
    __IOM NRF_TWIM_EVENTS_DMA_Type EVENTS_DMA;       /*!< (@ 0x0000014C) Peripheral events.                                    */
    __IM uint32_t RESERVED11[4];
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
    __IM uint32_t RESERVED12[3];
    __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x00000194) Publish configuration for event ERROR                 */
    __IM uint32_t RESERVED13[4];
    __IOM uint32_t PUBLISH_SUSPENDED;                /*!< (@ 0x000001A8) Publish configuration for event SUSPENDED             */
    __IM uint32_t RESERVED14[2];
    __IOM uint32_t PUBLISH_LASTRX;                   /*!< (@ 0x000001B4) Publish configuration for event LASTRX                */
    __IOM uint32_t PUBLISH_LASTTX;                   /*!< (@ 0x000001B8) Publish configuration for event LASTTX                */
    __IM uint32_t RESERVED15[4];
    __IOM NRF_TWIM_PUBLISH_DMA_Type PUBLISH_DMA;     /*!< (@ 0x000001CC) Publish configuration for events                      */
    __IM uint32_t RESERVED16[3];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED17[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED18[110];
    __IOM uint32_t ERRORSRC;                         /*!< (@ 0x000004C4) Error source                                          */
    __IM uint32_t RESERVED19[14];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable TWIM                                           */
    __IM uint32_t RESERVED20[8];
    __IOM uint32_t FREQUENCY;                        /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK source
                                                                         selected.*/
    __IM uint32_t RESERVED21[24];
    __IOM uint32_t ADDRESS;                          /*!< (@ 0x00000588) Address used in the TWI transfer                      */
    __IM uint32_t RESERVED22[29];
    __IOM NRF_TWIM_PSEL_Type PSEL;                   /*!< (@ 0x00000600) (unspecified)                                         */
    __IM uint32_t RESERVED23[62];
    __IOM NRF_TWIM_DMA_Type DMA;                     /*!< (@ 0x00000700) (unspecified)                                         */
  } NRF_TWIM_Type;                                   /*!< Size = 1884 (0x75C)                                                  */

/* TWIM_TASKS_STOP: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
  #define TWIM_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
  #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
  #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
  #define TWIM_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
  #define TWIM_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
  #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */


/* TWIM_TASKS_SUSPEND: Suspend TWI transaction */
  #define TWIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register.                             */

/* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */
  #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field.                                     */
  #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND
                                                                            field.*/
  #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field.                       */
  #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field.                       */
  #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task                                                   */


/* TWIM_TASKS_RESUME: Resume TWI transaction */
  #define TWIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register.                               */

/* TASKS_RESUME @Bit 0 : Resume TWI transaction */
  #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)   /*!< Position of TASKS_RESUME field.                                      */
  #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/
  #define TWIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field.                          */
  #define TWIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field.                          */
  #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task                                                     */


/* TWIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define TWIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define TWIM_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define TWIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
  #define TWIM_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* TWIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */
  #define TWIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */
  #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field.                    */
  #define TWIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* TWIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */
  #define TWIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */
  #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define TWIM_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define TWIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field.                      */
  #define TWIM_SUBSCRIBE_RESUME_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_RESUME_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* TWIM_EVENTS_STOPPED: TWI stopped */
  #define TWIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */

/* EVENTS_STOPPED @Bit 0 : TWI stopped */
  #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
  #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
                                                                            EVENTS_STOPPED field.*/
  #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
  #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
  #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */


/* TWIM_EVENTS_ERROR: TWI error */
  #define TWIM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                               */

/* EVENTS_ERROR @Bit 0 : TWI error */
  #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)   /*!< Position of EVENTS_ERROR field.                                      */
  #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/
  #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                          */
  #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                          */
  #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                */


/* TWIM_EVENTS_SUSPENDED: SUSPEND task has been issued, TWI traffic is now suspended. */
  #define TWIM_EVENTS_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SUSPENDED register.                       */

/* EVENTS_SUSPENDED @Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
  #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field.                            */
  #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of
                                                                            EVENTS_SUSPENDED field.*/
  #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SUSPENDED field.              */
  #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SUSPENDED field.              */
  #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated                                 */
  #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated                                        */


/* TWIM_EVENTS_LASTRX: Byte boundary, starting to receive the last byte */
  #define TWIM_EVENTS_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTRX register.                             */

/* EVENTS_LASTRX @Bit 0 : Byte boundary, starting to receive the last byte */
  #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field.                                     */
  #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX
                                                                            field.*/
  #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTRX field.                       */
  #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTRX field.                       */
  #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated                                              */


/* TWIM_EVENTS_LASTTX: Byte boundary, starting to transmit the last byte */
  #define TWIM_EVENTS_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTTX register.                             */

/* EVENTS_LASTTX @Bit 0 : Byte boundary, starting to transmit the last byte */
  #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field.                                     */
  #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX
                                                                            field.*/
  #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTTX field.                       */
  #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTTX field.                       */
  #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated                                       */
  #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated                                              */


/* TWIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define TWIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define TWIM_PUBLISH_STOPPED_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define TWIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
  #define TWIM_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* TWIM_PUBLISH_ERROR: Publish configuration for event ERROR */
  #define TWIM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
  #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define TWIM_PUBLISH_ERROR_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define TWIM_PUBLISH_ERROR_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_ERROR_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                            */
  #define TWIM_PUBLISH_ERROR_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_ERROR_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* TWIM_PUBLISH_SUSPENDED: Publish configuration for event SUSPENDED */
  #define TWIM_PUBLISH_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SUSPENDED register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that event SUSPENDED will publish to */
  #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define TWIM_PUBLISH_SUSPENDED_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define TWIM_PUBLISH_SUSPENDED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field.                    */
  #define TWIM_PUBLISH_SUSPENDED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_SUSPENDED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
  #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */


/* TWIM_PUBLISH_LASTRX: Publish configuration for event LASTRX */
  #define TWIM_PUBLISH_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTRX register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event LASTRX will publish to */
  #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define TWIM_PUBLISH_LASTRX_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define TWIM_PUBLISH_LASTRX_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field.                          */
  #define TWIM_PUBLISH_LASTRX_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_LASTRX_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* TWIM_PUBLISH_LASTTX: Publish configuration for event LASTTX */
  #define TWIM_PUBLISH_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTTX register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event LASTTX will publish to */
  #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define TWIM_PUBLISH_LASTTX_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define TWIM_PUBLISH_LASTTX_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field.                          */
  #define TWIM_PUBLISH_LASTTX_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_LASTTX_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* TWIM_SHORTS: Shortcuts between local events and tasks */
  #define TWIM_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* LASTTX_DMA_RX_START @Bit 7 : Shortcut between event LASTTX and task DMA.RX.START */
  #define TWIM_SHORTS_LASTTX_DMA_RX_START_Pos (7UL)  /*!< Position of LASTTX_DMA_RX_START field.                               */
  #define TWIM_SHORTS_LASTTX_DMA_RX_START_Msk (0x1UL << TWIM_SHORTS_LASTTX_DMA_RX_START_Pos) /*!< Bit mask of
                                                                            LASTTX_DMA_RX_START field.*/
  #define TWIM_SHORTS_LASTTX_DMA_RX_START_Min (0x0UL) /*!< Min enumerator value of LASTTX_DMA_RX_START field.                  */
  #define TWIM_SHORTS_LASTTX_DMA_RX_START_Max (0x1UL) /*!< Max enumerator value of LASTTX_DMA_RX_START field.                  */
  #define TWIM_SHORTS_LASTTX_DMA_RX_START_Disabled (0x0UL) /*!< Disable shortcut                                               */
  #define TWIM_SHORTS_LASTTX_DMA_RX_START_Enabled (0x1UL) /*!< Enable shortcut                                                 */

/* LASTTX_SUSPEND @Bit 8 : Shortcut between event LASTTX and task SUSPEND */
  #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL)       /*!< Position of LASTTX_SUSPEND field.                                    */
  #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field.      */
  #define TWIM_SHORTS_LASTTX_SUSPEND_Min (0x0UL)     /*!< Min enumerator value of LASTTX_SUSPEND field.                        */
  #define TWIM_SHORTS_LASTTX_SUSPEND_Max (0x1UL)     /*!< Max enumerator value of LASTTX_SUSPEND field.                        */
  #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut                                                    */
  #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut                                                      */

/* LASTTX_STOP @Bit 9 : Shortcut between event LASTTX and task STOP */
  #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL)          /*!< Position of LASTTX_STOP field.                                       */
  #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field.               */
  #define TWIM_SHORTS_LASTTX_STOP_Min (0x0UL)        /*!< Min enumerator value of LASTTX_STOP field.                           */
  #define TWIM_SHORTS_LASTTX_STOP_Max (0x1UL)        /*!< Max enumerator value of LASTTX_STOP field.                           */
  #define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
  #define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */

/* LASTRX_DMA_TX_START @Bit 10 : Shortcut between event LASTRX and task DMA.TX.START */
  #define TWIM_SHORTS_LASTRX_DMA_TX_START_Pos (10UL) /*!< Position of LASTRX_DMA_TX_START field.                               */
  #define TWIM_SHORTS_LASTRX_DMA_TX_START_Msk (0x1UL << TWIM_SHORTS_LASTRX_DMA_TX_START_Pos) /*!< Bit mask of
                                                                            LASTRX_DMA_TX_START field.*/
  #define TWIM_SHORTS_LASTRX_DMA_TX_START_Min (0x0UL) /*!< Min enumerator value of LASTRX_DMA_TX_START field.                  */
  #define TWIM_SHORTS_LASTRX_DMA_TX_START_Max (0x1UL) /*!< Max enumerator value of LASTRX_DMA_TX_START field.                  */
  #define TWIM_SHORTS_LASTRX_DMA_TX_START_Disabled (0x0UL) /*!< Disable shortcut                                               */
  #define TWIM_SHORTS_LASTRX_DMA_TX_START_Enabled (0x1UL) /*!< Enable shortcut                                                 */

/* LASTRX_STOP @Bit 12 : Shortcut between event LASTRX and task STOP */
  #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL)         /*!< Position of LASTRX_STOP field.                                       */
  #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field.               */
  #define TWIM_SHORTS_LASTRX_STOP_Min (0x0UL)        /*!< Min enumerator value of LASTRX_STOP field.                           */
  #define TWIM_SHORTS_LASTRX_STOP_Max (0x1UL)        /*!< Max enumerator value of LASTRX_STOP field.                           */
  #define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
  #define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */

/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows
                                               daisy-chaining match events. */

  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.   */
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows
                                               daisy-chaining match events. */

  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.   */
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows
                                               daisy-chaining match events. */

  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.   */
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows
                                               daisy-chaining match events. */

  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.   */
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3
                                                                            field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                  */


/* TWIM_INTEN: Enable or disable interrupt */
  #define TWIM_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */

/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
  #define TWIM_INTEN_STOPPED_Pos (1UL)               /*!< Position of STOPPED field.                                           */
  #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                             */
  #define TWIM_INTEN_STOPPED_Min (0x0UL)             /*!< Min enumerator value of STOPPED field.                               */
  #define TWIM_INTEN_STOPPED_Max (0x1UL)             /*!< Max enumerator value of STOPPED field.                               */
  #define TWIM_INTEN_STOPPED_Disabled (0x0UL)        /*!< Disable                                                              */
  #define TWIM_INTEN_STOPPED_Enabled (0x1UL)         /*!< Enable                                                               */

/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */
  #define TWIM_INTEN_ERROR_Pos (5UL)                 /*!< Position of ERROR field.                                             */
  #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                   */
  #define TWIM_INTEN_ERROR_Min (0x0UL)               /*!< Min enumerator value of ERROR field.                                 */
  #define TWIM_INTEN_ERROR_Max (0x1UL)               /*!< Max enumerator value of ERROR field.                                 */
  #define TWIM_INTEN_ERROR_Disabled (0x0UL)          /*!< Disable                                                              */
  #define TWIM_INTEN_ERROR_Enabled (0x1UL)           /*!< Enable                                                               */

/* SUSPENDED @Bit 10 : Enable or disable interrupt for event SUSPENDED */
  #define TWIM_INTEN_SUSPENDED_Pos (10UL)            /*!< Position of SUSPENDED field.                                         */
  #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field.                       */
  #define TWIM_INTEN_SUSPENDED_Min (0x0UL)           /*!< Min enumerator value of SUSPENDED field.                             */
  #define TWIM_INTEN_SUSPENDED_Max (0x1UL)           /*!< Max enumerator value of SUSPENDED field.                             */
  #define TWIM_INTEN_SUSPENDED_Disabled (0x0UL)      /*!< Disable                                                              */
  #define TWIM_INTEN_SUSPENDED_Enabled (0x1UL)       /*!< Enable                                                               */

/* LASTRX @Bit 13 : Enable or disable interrupt for event LASTRX */
  #define TWIM_INTEN_LASTRX_Pos (13UL)               /*!< Position of LASTRX field.                                            */
  #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field.                                */
  #define TWIM_INTEN_LASTRX_Min (0x0UL)              /*!< Min enumerator value of LASTRX field.                                */
  #define TWIM_INTEN_LASTRX_Max (0x1UL)              /*!< Max enumerator value of LASTRX field.                                */
  #define TWIM_INTEN_LASTRX_Disabled (0x0UL)         /*!< Disable                                                              */
  #define TWIM_INTEN_LASTRX_Enabled (0x1UL)          /*!< Enable                                                               */

/* LASTTX @Bit 14 : Enable or disable interrupt for event LASTTX */
  #define TWIM_INTEN_LASTTX_Pos (14UL)               /*!< Position of LASTTX field.                                            */
  #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field.                                */
  #define TWIM_INTEN_LASTTX_Min (0x0UL)              /*!< Min enumerator value of LASTTX field.                                */
  #define TWIM_INTEN_LASTTX_Max (0x1UL)              /*!< Max enumerator value of LASTTX field.                                */
  #define TWIM_INTEN_LASTTX_Disabled (0x0UL)         /*!< Disable                                                              */
  #define TWIM_INTEN_LASTTX_Enabled (0x1UL)          /*!< Enable                                                               */

/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */
  #define TWIM_INTEN_DMARXEND_Pos (19UL)             /*!< Position of DMARXEND field.                                          */
  #define TWIM_INTEN_DMARXEND_Msk (0x1UL << TWIM_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                          */
  #define TWIM_INTEN_DMARXEND_Min (0x0UL)            /*!< Min enumerator value of DMARXEND field.                              */
  #define TWIM_INTEN_DMARXEND_Max (0x1UL)            /*!< Max enumerator value of DMARXEND field.                              */
  #define TWIM_INTEN_DMARXEND_Disabled (0x0UL)       /*!< Disable                                                              */
  #define TWIM_INTEN_DMARXEND_Enabled (0x1UL)        /*!< Enable                                                               */

/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */
  #define TWIM_INTEN_DMARXREADY_Pos (20UL)           /*!< Position of DMARXREADY field.                                        */
  #define TWIM_INTEN_DMARXREADY_Msk (0x1UL << TWIM_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.                    */
  #define TWIM_INTEN_DMARXREADY_Min (0x0UL)          /*!< Min enumerator value of DMARXREADY field.                            */
  #define TWIM_INTEN_DMARXREADY_Max (0x1UL)          /*!< Max enumerator value of DMARXREADY field.                            */
  #define TWIM_INTEN_DMARXREADY_Disabled (0x0UL)     /*!< Disable                                                              */
  #define TWIM_INTEN_DMARXREADY_Enabled (0x1UL)      /*!< Enable                                                               */

/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */
  #define TWIM_INTEN_DMARXBUSERROR_Pos (21UL)        /*!< Position of DMARXBUSERROR field.                                     */
  #define TWIM_INTEN_DMARXBUSERROR_Msk (0x1UL << TWIM_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.           */
  #define TWIM_INTEN_DMARXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define TWIM_INTEN_DMARXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define TWIM_INTEN_DMARXBUSERROR_Disabled (0x0UL)  /*!< Disable                                                              */
  #define TWIM_INTEN_DMARXBUSERROR_Enabled (0x1UL)   /*!< Enable                                                               */

/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */
  #define TWIM_INTEN_DMARXMATCH0_Pos (22UL)          /*!< Position of DMARXMATCH0 field.                                       */
  #define TWIM_INTEN_DMARXMATCH0_Msk (0x1UL << TWIM_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.                 */
  #define TWIM_INTEN_DMARXMATCH0_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define TWIM_INTEN_DMARXMATCH0_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define TWIM_INTEN_DMARXMATCH0_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIM_INTEN_DMARXMATCH0_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */
  #define TWIM_INTEN_DMARXMATCH1_Pos (23UL)          /*!< Position of DMARXMATCH1 field.                                       */
  #define TWIM_INTEN_DMARXMATCH1_Msk (0x1UL << TWIM_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.                 */
  #define TWIM_INTEN_DMARXMATCH1_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define TWIM_INTEN_DMARXMATCH1_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define TWIM_INTEN_DMARXMATCH1_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIM_INTEN_DMARXMATCH1_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */
  #define TWIM_INTEN_DMARXMATCH2_Pos (24UL)          /*!< Position of DMARXMATCH2 field.                                       */
  #define TWIM_INTEN_DMARXMATCH2_Msk (0x1UL << TWIM_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.                 */
  #define TWIM_INTEN_DMARXMATCH2_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define TWIM_INTEN_DMARXMATCH2_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define TWIM_INTEN_DMARXMATCH2_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIM_INTEN_DMARXMATCH2_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */
  #define TWIM_INTEN_DMARXMATCH3_Pos (25UL)          /*!< Position of DMARXMATCH3 field.                                       */
  #define TWIM_INTEN_DMARXMATCH3_Msk (0x1UL << TWIM_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.                 */
  #define TWIM_INTEN_DMARXMATCH3_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define TWIM_INTEN_DMARXMATCH3_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define TWIM_INTEN_DMARXMATCH3_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIM_INTEN_DMARXMATCH3_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */
  #define TWIM_INTEN_DMATXEND_Pos (26UL)             /*!< Position of DMATXEND field.                                          */
  #define TWIM_INTEN_DMATXEND_Msk (0x1UL << TWIM_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                          */
  #define TWIM_INTEN_DMATXEND_Min (0x0UL)            /*!< Min enumerator value of DMATXEND field.                              */
  #define TWIM_INTEN_DMATXEND_Max (0x1UL)            /*!< Max enumerator value of DMATXEND field.                              */
  #define TWIM_INTEN_DMATXEND_Disabled (0x0UL)       /*!< Disable                                                              */
  #define TWIM_INTEN_DMATXEND_Enabled (0x1UL)        /*!< Enable                                                               */

/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */
  #define TWIM_INTEN_DMATXREADY_Pos (27UL)           /*!< Position of DMATXREADY field.                                        */
  #define TWIM_INTEN_DMATXREADY_Msk (0x1UL << TWIM_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.                    */
  #define TWIM_INTEN_DMATXREADY_Min (0x0UL)          /*!< Min enumerator value of DMATXREADY field.                            */
  #define TWIM_INTEN_DMATXREADY_Max (0x1UL)          /*!< Max enumerator value of DMATXREADY field.                            */
  #define TWIM_INTEN_DMATXREADY_Disabled (0x0UL)     /*!< Disable                                                              */
  #define TWIM_INTEN_DMATXREADY_Enabled (0x1UL)      /*!< Enable                                                               */

/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */
  #define TWIM_INTEN_DMATXBUSERROR_Pos (28UL)        /*!< Position of DMATXBUSERROR field.                                     */
  #define TWIM_INTEN_DMATXBUSERROR_Msk (0x1UL << TWIM_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.           */
  #define TWIM_INTEN_DMATXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define TWIM_INTEN_DMATXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define TWIM_INTEN_DMATXBUSERROR_Disabled (0x0UL)  /*!< Disable                                                              */
  #define TWIM_INTEN_DMATXBUSERROR_Enabled (0x1UL)   /*!< Enable                                                               */


/* TWIM_INTENSET: Enable interrupt */
  #define TWIM_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
  #define TWIM_INTENSET_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
  #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define TWIM_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define TWIM_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define TWIM_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
  #define TWIM_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */
  #define TWIM_INTENSET_ERROR_Pos (5UL)              /*!< Position of ERROR field.                                             */
  #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
  #define TWIM_INTENSET_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
  #define TWIM_INTENSET_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
  #define TWIM_INTENSET_ERROR_Set (0x1UL)            /*!< Enable                                                               */
  #define TWIM_INTENSET_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* SUSPENDED @Bit 10 : Write '1' to enable interrupt for event SUSPENDED */
  #define TWIM_INTENSET_SUSPENDED_Pos (10UL)         /*!< Position of SUSPENDED field.                                         */
  #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field.                 */
  #define TWIM_INTENSET_SUSPENDED_Min (0x0UL)        /*!< Min enumerator value of SUSPENDED field.                             */
  #define TWIM_INTENSET_SUSPENDED_Max (0x1UL)        /*!< Max enumerator value of SUSPENDED field.                             */
  #define TWIM_INTENSET_SUSPENDED_Set (0x1UL)        /*!< Enable                                                               */
  #define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* LASTRX @Bit 13 : Write '1' to enable interrupt for event LASTRX */
  #define TWIM_INTENSET_LASTRX_Pos (13UL)            /*!< Position of LASTRX field.                                            */
  #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field.                          */
  #define TWIM_INTENSET_LASTRX_Min (0x0UL)           /*!< Min enumerator value of LASTRX field.                                */
  #define TWIM_INTENSET_LASTRX_Max (0x1UL)           /*!< Max enumerator value of LASTRX field.                                */
  #define TWIM_INTENSET_LASTRX_Set (0x1UL)           /*!< Enable                                                               */
  #define TWIM_INTENSET_LASTRX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_LASTRX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* LASTTX @Bit 14 : Write '1' to enable interrupt for event LASTTX */
  #define TWIM_INTENSET_LASTTX_Pos (14UL)            /*!< Position of LASTTX field.                                            */
  #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field.                          */
  #define TWIM_INTENSET_LASTTX_Min (0x0UL)           /*!< Min enumerator value of LASTTX field.                                */
  #define TWIM_INTENSET_LASTTX_Max (0x1UL)           /*!< Max enumerator value of LASTTX field.                                */
  #define TWIM_INTENSET_LASTTX_Set (0x1UL)           /*!< Enable                                                               */
  #define TWIM_INTENSET_LASTTX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_LASTTX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */
  #define TWIM_INTENSET_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define TWIM_INTENSET_DMARXEND_Msk (0x1UL << TWIM_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define TWIM_INTENSET_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define TWIM_INTENSET_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define TWIM_INTENSET_DMARXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define TWIM_INTENSET_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */
  #define TWIM_INTENSET_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define TWIM_INTENSET_DMARXREADY_Msk (0x1UL << TWIM_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define TWIM_INTENSET_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define TWIM_INTENSET_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define TWIM_INTENSET_DMARXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define TWIM_INTENSET_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */
  #define TWIM_INTENSET_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define TWIM_INTENSET_DMARXBUSERROR_Msk (0x1UL << TWIM_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define TWIM_INTENSET_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define TWIM_INTENSET_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define TWIM_INTENSET_DMARXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define TWIM_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIM_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */
  #define TWIM_INTENSET_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define TWIM_INTENSET_DMARXMATCH0_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define TWIM_INTENSET_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define TWIM_INTENSET_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define TWIM_INTENSET_DMARXMATCH0_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIM_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */
  #define TWIM_INTENSET_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define TWIM_INTENSET_DMARXMATCH1_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define TWIM_INTENSET_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define TWIM_INTENSET_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define TWIM_INTENSET_DMARXMATCH1_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIM_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */
  #define TWIM_INTENSET_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define TWIM_INTENSET_DMARXMATCH2_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define TWIM_INTENSET_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define TWIM_INTENSET_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define TWIM_INTENSET_DMARXMATCH2_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIM_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */
  #define TWIM_INTENSET_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define TWIM_INTENSET_DMARXMATCH3_Msk (0x1UL << TWIM_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define TWIM_INTENSET_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define TWIM_INTENSET_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define TWIM_INTENSET_DMARXMATCH3_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIM_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */
  #define TWIM_INTENSET_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define TWIM_INTENSET_DMATXEND_Msk (0x1UL << TWIM_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define TWIM_INTENSET_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define TWIM_INTENSET_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define TWIM_INTENSET_DMATXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define TWIM_INTENSET_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */
  #define TWIM_INTENSET_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define TWIM_INTENSET_DMATXREADY_Msk (0x1UL << TWIM_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define TWIM_INTENSET_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define TWIM_INTENSET_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define TWIM_INTENSET_DMATXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define TWIM_INTENSET_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIM_INTENSET_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */
  #define TWIM_INTENSET_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define TWIM_INTENSET_DMATXBUSERROR_Msk (0x1UL << TWIM_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define TWIM_INTENSET_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define TWIM_INTENSET_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define TWIM_INTENSET_DMATXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define TWIM_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIM_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* TWIM_INTENCLR: Disable interrupt */
  #define TWIM_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
  #define TWIM_INTENCLR_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
  #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define TWIM_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define TWIM_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define TWIM_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
  #define TWIM_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */
  #define TWIM_INTENCLR_ERROR_Pos (5UL)              /*!< Position of ERROR field.                                             */
  #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
  #define TWIM_INTENCLR_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
  #define TWIM_INTENCLR_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
  #define TWIM_INTENCLR_ERROR_Clear (0x1UL)          /*!< Disable                                                              */
  #define TWIM_INTENCLR_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* SUSPENDED @Bit 10 : Write '1' to disable interrupt for event SUSPENDED */
  #define TWIM_INTENCLR_SUSPENDED_Pos (10UL)         /*!< Position of SUSPENDED field.                                         */
  #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field.                 */
  #define TWIM_INTENCLR_SUSPENDED_Min (0x0UL)        /*!< Min enumerator value of SUSPENDED field.                             */
  #define TWIM_INTENCLR_SUSPENDED_Max (0x1UL)        /*!< Max enumerator value of SUSPENDED field.                             */
  #define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL)      /*!< Disable                                                              */
  #define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* LASTRX @Bit 13 : Write '1' to disable interrupt for event LASTRX */
  #define TWIM_INTENCLR_LASTRX_Pos (13UL)            /*!< Position of LASTRX field.                                            */
  #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field.                          */
  #define TWIM_INTENCLR_LASTRX_Min (0x0UL)           /*!< Min enumerator value of LASTRX field.                                */
  #define TWIM_INTENCLR_LASTRX_Max (0x1UL)           /*!< Max enumerator value of LASTRX field.                                */
  #define TWIM_INTENCLR_LASTRX_Clear (0x1UL)         /*!< Disable                                                              */
  #define TWIM_INTENCLR_LASTRX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_LASTRX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* LASTTX @Bit 14 : Write '1' to disable interrupt for event LASTTX */
  #define TWIM_INTENCLR_LASTTX_Pos (14UL)            /*!< Position of LASTTX field.                                            */
  #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field.                          */
  #define TWIM_INTENCLR_LASTTX_Min (0x0UL)           /*!< Min enumerator value of LASTTX field.                                */
  #define TWIM_INTENCLR_LASTTX_Max (0x1UL)           /*!< Max enumerator value of LASTTX field.                                */
  #define TWIM_INTENCLR_LASTTX_Clear (0x1UL)         /*!< Disable                                                              */
  #define TWIM_INTENCLR_LASTTX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_LASTTX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */
  #define TWIM_INTENCLR_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define TWIM_INTENCLR_DMARXEND_Msk (0x1UL << TWIM_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define TWIM_INTENCLR_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define TWIM_INTENCLR_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define TWIM_INTENCLR_DMARXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */
  #define TWIM_INTENCLR_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define TWIM_INTENCLR_DMARXREADY_Msk (0x1UL << TWIM_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define TWIM_INTENCLR_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define TWIM_INTENCLR_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define TWIM_INTENCLR_DMARXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */
  #define TWIM_INTENCLR_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define TWIM_INTENCLR_DMARXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define TWIM_INTENCLR_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define TWIM_INTENCLR_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define TWIM_INTENCLR_DMARXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIM_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */
  #define TWIM_INTENCLR_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define TWIM_INTENCLR_DMARXMATCH0_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define TWIM_INTENCLR_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH0_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */
  #define TWIM_INTENCLR_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define TWIM_INTENCLR_DMARXMATCH1_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define TWIM_INTENCLR_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH1_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */
  #define TWIM_INTENCLR_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define TWIM_INTENCLR_DMARXMATCH2_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define TWIM_INTENCLR_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH2_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */
  #define TWIM_INTENCLR_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define TWIM_INTENCLR_DMARXMATCH3_Msk (0x1UL << TWIM_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define TWIM_INTENCLR_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define TWIM_INTENCLR_DMARXMATCH3_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */
  #define TWIM_INTENCLR_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define TWIM_INTENCLR_DMATXEND_Msk (0x1UL << TWIM_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define TWIM_INTENCLR_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define TWIM_INTENCLR_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define TWIM_INTENCLR_DMATXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */
  #define TWIM_INTENCLR_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define TWIM_INTENCLR_DMATXREADY_Msk (0x1UL << TWIM_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define TWIM_INTENCLR_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define TWIM_INTENCLR_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define TWIM_INTENCLR_DMATXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIM_INTENCLR_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */
  #define TWIM_INTENCLR_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define TWIM_INTENCLR_DMATXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define TWIM_INTENCLR_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define TWIM_INTENCLR_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define TWIM_INTENCLR_DMATXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define TWIM_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIM_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* TWIM_ERRORSRC: Error source */
  #define TWIM_ERRORSRC_ResetValue (0x00000000UL)    /*!< Reset value of ERRORSRC register.                                    */

/* OVERRUN @Bit 0 : Overrun error */
  #define TWIM_ERRORSRC_OVERRUN_Pos (0UL)            /*!< Position of OVERRUN field.                                           */
  #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field.                       */
  #define TWIM_ERRORSRC_OVERRUN_Min (0x0UL)          /*!< Min enumerator value of OVERRUN field.                               */
  #define TWIM_ERRORSRC_OVERRUN_Max (0x1UL)          /*!< Max enumerator value of OVERRUN field.                               */
  #define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL)  /*!< Error did not occur                                                  */
  #define TWIM_ERRORSRC_OVERRUN_Received (0x1UL)     /*!< Error occurred                                                       */

/* ANACK @Bit 1 : NACK received after sending the address (write '1' to clear) */
  #define TWIM_ERRORSRC_ANACK_Pos (1UL)              /*!< Position of ANACK field.                                             */
  #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field.                             */
  #define TWIM_ERRORSRC_ANACK_Min (0x0UL)            /*!< Min enumerator value of ANACK field.                                 */
  #define TWIM_ERRORSRC_ANACK_Max (0x1UL)            /*!< Max enumerator value of ANACK field.                                 */
  #define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL)    /*!< Error did not occur                                                  */
  #define TWIM_ERRORSRC_ANACK_Received (0x1UL)       /*!< Error occurred                                                       */

/* DNACK @Bit 2 : NACK received after sending a data byte (write '1' to clear) */
  #define TWIM_ERRORSRC_DNACK_Pos (2UL)              /*!< Position of DNACK field.                                             */
  #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field.                             */
  #define TWIM_ERRORSRC_DNACK_Min (0x0UL)            /*!< Min enumerator value of DNACK field.                                 */
  #define TWIM_ERRORSRC_DNACK_Max (0x1UL)            /*!< Max enumerator value of DNACK field.                                 */
  #define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL)    /*!< Error did not occur                                                  */
  #define TWIM_ERRORSRC_DNACK_Received (0x1UL)       /*!< Error occurred                                                       */


/* TWIM_ENABLE: Enable TWIM */
  #define TWIM_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..3 : Enable or disable TWIM */
  #define TWIM_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
  #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
  #define TWIM_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
  #define TWIM_ENABLE_ENABLE_Max (0x6UL)             /*!< Max enumerator value of ENABLE field.                                */
  #define TWIM_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable TWIM                                                         */
  #define TWIM_ENABLE_ENABLE_Enabled (0x6UL)         /*!< Enable TWIM                                                          */


/* TWIM_FREQUENCY: TWI frequency. Accuracy depends on the HFCLK source selected. */
  #define TWIM_FREQUENCY_ResetValue (0x04000000UL)   /*!< Reset value of FREQUENCY register.                                   */

/* FREQUENCY @Bits 0..31 : TWI master clock frequency */
  #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL)         /*!< Position of FREQUENCY field.                                         */
  #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field.        */
  #define TWIM_FREQUENCY_FREQUENCY_Min (0x1980000UL) /*!< Min enumerator value of FREQUENCY field.                             */
  #define TWIM_FREQUENCY_FREQUENCY_Max (0x6400000UL) /*!< Max enumerator value of FREQUENCY field.                             */
  #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps                                                           */
  #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps                                                           */
  #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps                                                           */


/* TWIM_ADDRESS: Address used in the TWI transfer */
  #define TWIM_ADDRESS_ResetValue (0x00000000UL)     /*!< Reset value of ADDRESS register.                                     */

/* ADDRESS @Bits 0..6 : Address used in the TWI transfer */
  #define TWIM_ADDRESS_ADDRESS_Pos (0UL)             /*!< Position of ADDRESS field.                                           */
  #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                        */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           TWIS                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct TWIS_TASKS_DMA_RX ================================================= */
/**
  * @brief RX [TWIS_TASKS_DMA_RX] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000000) Enables the MATCH[n] event by setting the ENABLE[n] bit
                                                                         in the CONFIG register.*/
  __OM  uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000010) Disables the MATCH[n] event by clearing the ENABLE[n]
                                                                         bit in the CONFIG register.*/
} NRF_TWIS_TASKS_DMA_RX_Type;                        /*!< Size = 32 (0x020)                                                    */

/* TWIS_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                                  */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                                 */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                                 */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.                 */

/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field.                              */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask
                                                                            of ENABLEMATCH field.*/
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field.                */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field.                */
  #define TWIS_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                          */


/* TWIS_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                                */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                               */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                               */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.               */

/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field.                           */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit
                                                                            mask of DISABLEMATCH field.*/
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field.             */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field.             */
  #define TWIS_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                        */



/* ================================================== Struct TWIS_TASKS_DMA ================================================== */
/**
  * @brief TASKS_DMA [TWIS_TASKS_DMA] Peripheral tasks.
  */
typedef struct {
  __OM  NRF_TWIS_TASKS_DMA_RX_Type RX;               /*!< (@ 0x00000000) Peripheral tasks.                                     */
} NRF_TWIS_TASKS_DMA_Type;                           /*!< Size = 32 (0x020)                                                    */


/* ============================================== Struct TWIS_SUBSCRIBE_DMA_RX =============================================== */
/**
  * @brief RX [TWIS_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000000) Subscribe configuration for task ENABLEMATCH[n]       */
  __IOM uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000010) Subscribe configuration for task DISABLEMATCH[n]      */
} NRF_TWIS_SUBSCRIBE_DMA_RX_Type;                    /*!< Size = 32 (0x020)                                                    */

/* TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                              */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                             */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                             */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.             */

/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                      */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                  */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                   */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                           */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                              */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                              */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                      */
  #define TWIS_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                        */


/* TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                            */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                           */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                           */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.           */

/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                     */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                 */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                  */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                          */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                             */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                             */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                     */
  #define TWIS_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                       */



/* ================================================ Struct TWIS_SUBSCRIBE_DMA ================================================ */
/**
  * @brief SUBSCRIBE_DMA [TWIS_SUBSCRIBE_DMA] Subscribe configuration for tasks
  */
typedef struct {
  __IOM NRF_TWIS_SUBSCRIBE_DMA_RX_Type RX;           /*!< (@ 0x00000000) Subscribe configuration for tasks                     */
} NRF_TWIS_SUBSCRIBE_DMA_Type;                       /*!< Size = 32 (0x020)                                                    */


/* ================================================ Struct TWIS_EVENTS_DMA_RX ================================================ */
/**
  * @brief RX [TWIS_EVENTS_DMA_RX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus.        */
} NRF_TWIS_EVENTS_DMA_RX_Type;                       /*!< Size = 28 (0x01C)                                                    */

/* TWIS_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */
  #define TWIS_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define TWIS_EVENTS_DMA_RX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define TWIS_EVENTS_DMA_RX_END_END_Msk (0x1UL << TWIS_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define TWIS_EVENTS_DMA_RX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define TWIS_EVENTS_DMA_RX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define TWIS_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define TWIS_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* TWIS_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define TWIS_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define TWIS_EVENTS_DMA_RX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define TWIS_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << TWIS_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define TWIS_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define TWIS_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define TWIS_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIS_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* TWIS_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */
  #define TWIS_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define TWIS_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */


/* TWIS_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */
  #define TWIS_EVENTS_DMA_RX_MATCH_MaxCount (4UL)    /*!< Max size of MATCH[4] array.                                          */
  #define TWIS_EVENTS_DMA_RX_MATCH_MaxIndex (3UL)    /*!< Max index of MATCH[4] array.                                         */
  #define TWIS_EVENTS_DMA_RX_MATCH_MinIndex (0UL)    /*!< Min index of MATCH[4] array.                                         */
  #define TWIS_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                            */

/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */
  #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL)   /*!< Position of MATCH field.                                             */
  #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << TWIS_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field.       */
  #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field.                                 */
  #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field.                                 */
  #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIS_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated                                                */



/* ================================================ Struct TWIS_EVENTS_DMA_TX ================================================ */
/**
  * @brief TX [TWIS_EVENTS_DMA_TX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
} NRF_TWIS_EVENTS_DMA_TX_Type;                       /*!< Size = 12 (0x00C)                                                    */

/* TWIS_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */
  #define TWIS_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                   */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define TWIS_EVENTS_DMA_TX_END_END_Pos (0UL)       /*!< Position of END field.                                               */
  #define TWIS_EVENTS_DMA_TX_END_END_Msk (0x1UL << TWIS_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field.                 */
  #define TWIS_EVENTS_DMA_TX_END_END_Min (0x0UL)     /*!< Min enumerator value of END field.                                   */
  #define TWIS_EVENTS_DMA_TX_END_END_Max (0x1UL)     /*!< Max enumerator value of END field.                                   */
  #define TWIS_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
  #define TWIS_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated                                                    */


/* TWIS_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                              to be written to prepare for the next sequence. */

  #define TWIS_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                               */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define TWIS_EVENTS_DMA_TX_READY_READY_Pos (0UL)   /*!< Position of READY field.                                             */
  #define TWIS_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << TWIS_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field.       */
  #define TWIS_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                 */
  #define TWIS_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                 */
  #define TWIS_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIS_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated                                                */


/* TWIS_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */
  #define TWIS_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                         */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
  #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
                                                                            field.*/
  #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
  #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                        */
  #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                   */
  #define TWIS_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                          */



/* ================================================= Struct TWIS_EVENTS_DMA ================================================== */
/**
  * @brief EVENTS_DMA [TWIS_EVENTS_DMA] Peripheral events.
  */
typedef struct {
  __IOM NRF_TWIS_EVENTS_DMA_RX_Type RX;              /*!< (@ 0x00000000) Peripheral events.                                    */
  __IOM NRF_TWIS_EVENTS_DMA_TX_Type TX;              /*!< (@ 0x0000001C) Peripheral events.                                    */
} NRF_TWIS_EVENTS_DMA_Type;                          /*!< Size = 40 (0x028)                                                    */


/* =============================================== Struct TWIS_PUBLISH_DMA_RX ================================================ */
/**
  * @brief RX [TWIS_PUBLISH_DMA_RX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Publish configuration for event MATCH[n]              */
} NRF_TWIS_PUBLISH_DMA_RX_Type;                      /*!< Size = 28 (0x01C)                                                    */

/* TWIS_PUBLISH_DMA_RX_END: Publish configuration for event END */
  #define TWIS_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define TWIS_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_DMA_RX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define TWIS_PUBLISH_DMA_RX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_RX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define TWIS_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* TWIS_PUBLISH_DMA_RX_READY: Publish configuration for event READY */
  #define TWIS_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define TWIS_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_DMA_RX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define TWIS_PUBLISH_DMA_RX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_RX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define TWIS_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* TWIS_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define TWIS_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */


/* TWIS_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */
  #define TWIS_PUBLISH_DMA_RX_MATCH_MaxCount (4UL)   /*!< Max size of MATCH[4] array.                                          */
  #define TWIS_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL)   /*!< Max index of MATCH[4] array.                                         */
  #define TWIS_PUBLISH_DMA_RX_MATCH_MinIndex (0UL)   /*!< Min index of MATCH[4] array.                                         */
  #define TWIS_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */
  #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define TWIS_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field.              */
  #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define TWIS_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */



/* =============================================== Struct TWIS_PUBLISH_DMA_TX ================================================ */
/**
  * @brief TX [TWIS_PUBLISH_DMA_TX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
} NRF_TWIS_PUBLISH_DMA_TX_Type;                      /*!< Size = 12 (0x00C)                                                    */

/* TWIS_PUBLISH_DMA_TX_END: Publish configuration for event END */
  #define TWIS_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define TWIS_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_DMA_TX_END_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field.                  */
  #define TWIS_PUBLISH_DMA_TX_END_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_TX_END_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define TWIS_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* TWIS_PUBLISH_DMA_TX_READY: Publish configuration for event READY */
  #define TWIS_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
  #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                          */
  #define TWIS_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_DMA_TX_READY_EN_Pos (31UL)    /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field.              */
  #define TWIS_PUBLISH_DMA_TX_READY_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_TX_READY_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
  #define TWIS_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */


/* TWIS_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
  #define TWIS_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */



/* ================================================= Struct TWIS_PUBLISH_DMA ================================================= */
/**
  * @brief PUBLISH_DMA [TWIS_PUBLISH_DMA] Publish configuration for events
  */
typedef struct {
  __IOM NRF_TWIS_PUBLISH_DMA_RX_Type RX;             /*!< (@ 0x00000000) Publish configuration for events                      */
  __IOM NRF_TWIS_PUBLISH_DMA_TX_Type TX;             /*!< (@ 0x0000001C) Publish configuration for events                      */
} NRF_TWIS_PUBLISH_DMA_Type;                         /*!< Size = 40 (0x028)                                                    */


/* ==================================================== Struct TWIS_PSEL ===================================================== */
/**
  * @brief PSEL [TWIS_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  SCL;                               /*!< (@ 0x00000000) Pin select for SCL signal                             */
  __IOM uint32_t  SDA;                               /*!< (@ 0x00000004) Pin select for SDA signal                             */
} NRF_TWIS_PSEL_Type;                                /*!< Size = 8 (0x008)                                                     */

/* TWIS_PSEL_SCL: Pin select for SCL signal */
  #define TWIS_PSEL_SCL_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCL register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define TWIS_PSEL_SCL_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define TWIS_PSEL_SCL_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define TWIS_PSEL_SCL_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define TWIS_PSEL_SCL_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define TWIS_PSEL_SCL_PORT_Msk (0x7UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define TWIS_PSEL_SCL_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define TWIS_PSEL_SCL_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define TWIS_PSEL_SCL_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define TWIS_PSEL_SCL_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define TWIS_PSEL_SCL_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */


/* TWIS_PSEL_SDA: Pin select for SDA signal */
  #define TWIS_PSEL_SDA_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SDA register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define TWIS_PSEL_SDA_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
  #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field.                                  */
  #define TWIS_PSEL_SDA_PIN_Min (0x00UL)             /*!< Min value of PIN field.                                              */
  #define TWIS_PSEL_SDA_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define TWIS_PSEL_SDA_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
  #define TWIS_PSEL_SDA_PORT_Msk (0x7UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field.                                */
  #define TWIS_PSEL_SDA_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
  #define TWIS_PSEL_SDA_PORT_Max (0x7UL)             /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define TWIS_PSEL_SDA_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
  #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
  #define TWIS_PSEL_SDA_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
  #define TWIS_PSEL_SDA_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
  #define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
  #define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */



/* ================================================ Struct TWIS_DMA_RX_MATCH ================================================= */
/**
  * @brief MATCH [TWIS_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Configure individual match events                     */
  __IOM uint32_t  CANDIDATE[4];                      /*!< (@ 0x00000004) The data to look for - any match will trigger the
                                                                         MATCH[n] event, if enabled.*/
} NRF_TWIS_DMA_RX_MATCH_Type;                        /*!< Size = 20 (0x014)                                                    */

/* TWIS_DMA_RX_MATCH_CONFIG: Configure individual match events */
  #define TWIS_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                              */

/* ENABLE0 @Bit 0 : Enable match filter 0 */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field.                                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field. */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE1 @Bit 1 : Enable match filter 1 */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field.                                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field. */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE2 @Bit 2 : Enable match filter 2 */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field.                                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field. */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ENABLE3 @Bit 3 : Enable match filter 3 */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field.                                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field. */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                             */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled                                         */
  #define TWIS_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled                                           */

/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or sticky */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field.                                        */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0
                                                                            field.*/
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or sticky */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field.                                        */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1
                                                                            field.*/
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or sticky */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field.                                        */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2
                                                                            field.*/
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */

/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or sticky */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field.                                        */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3
                                                                            field.*/
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field.                           */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task          */
  #define TWIS_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received   */


/* TWIS_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */
  #define TWIS_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array.                                      */
  #define TWIS_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array.                                     */
  #define TWIS_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array.                                     */
  #define TWIS_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register.                     */

/* DATA @Bits 0..31 : Data to look for */
  #define TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field.                                              */
  #define TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA
                                                                            field.*/



/* =================================================== Struct TWIS_DMA_RX ==================================================== */
/**
  * @brief RX [TWIS_DMA_RX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IOM uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
  __IOM NRF_TWIS_DMA_RX_MATCH_Type MATCH;            /*!< (@ 0x00000024) Registers to control the behavior of the pattern
                                                                         matcher engine*/
} NRF_TWIS_DMA_RX_Type;                              /*!< Size = 56 (0x038)                                                    */

/* TWIS_DMA_RX_PTR: RAM buffer start address */
  #define TWIS_DMA_RX_PTR_ResetValue (0x00000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define TWIS_DMA_RX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define TWIS_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* TWIS_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */
  #define TWIS_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define TWIS_DMA_RX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define TWIS_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define TWIS_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define TWIS_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* TWIS_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define TWIS_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define TWIS_DMA_RX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define TWIS_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define TWIS_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define TWIS_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* TWIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define TWIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* TWIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define TWIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* =================================================== Struct TWIS_DMA_TX ==================================================== */
/**
  * @brief TX [TWIS_DMA_TX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IOM uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_TWIS_DMA_TX_Type;                              /*!< Size = 36 (0x024)                                                    */

/* TWIS_DMA_TX_PTR: RAM buffer start address */
  #define TWIS_DMA_TX_PTR_ResetValue (0x00000000UL)  /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define TWIS_DMA_TX_PTR_PTR_Pos (0UL)              /*!< Position of PTR field.                                               */
  #define TWIS_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                        */


/* TWIS_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */
  #define TWIS_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                    */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define TWIS_DMA_TX_MAXCNT_MAXCNT_Pos (0UL)        /*!< Position of MAXCNT field.                                            */
  #define TWIS_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.             */
  #define TWIS_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL)   /*!< Min value of MAXCNT field.                                           */
  #define TWIS_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL)   /*!< Max size of MAXCNT field.                                            */


/* TWIS_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after each
                        MATCH event. */

  #define TWIS_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                    */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define TWIS_DMA_TX_AMOUNT_AMOUNT_Pos (0UL)        /*!< Position of AMOUNT field.                                            */
  #define TWIS_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.             */
  #define TWIS_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL)   /*!< Min value of AMOUNT field.                                           */
  #define TWIS_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL)   /*!< Max size of AMOUNT field.                                            */


/* TWIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define TWIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */

/* ENABLE @Bit 0 : (unspecified) */
  #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
  #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
  #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
  #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
  #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */


/* TWIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define TWIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
  #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* ===================================================== Struct TWIS_DMA ===================================================== */
/**
  * @brief DMA [TWIS_DMA] (unspecified)
  */
typedef struct {
  __IOM NRF_TWIS_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
  __IOM NRF_TWIS_DMA_TX_Type TX;                     /*!< (@ 0x00000038) (unspecified)                                         */
} NRF_TWIS_DMA_Type;                                 /*!< Size = 92 (0x05C)                                                    */

/* ======================================================= Struct TWIS ======================================================= */
/**
  * @brief I2C compatible Two-Wire Slave Interface with EasyDMA
  */
  typedef struct {                                   /*!< TWIS Structure                                                       */
    __IM uint32_t RESERVED;
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop TWI transaction                                  */
    __IM uint32_t RESERVED1;
    __OM uint32_t TASKS_SUSPEND;                     /*!< (@ 0x0000000C) Suspend TWI transaction                               */
    __OM uint32_t TASKS_RESUME;                      /*!< (@ 0x00000010) Resume TWI transaction                                */
    __IM uint32_t RESERVED2[3];
    __OM uint32_t TASKS_PREPARERX;                   /*!< (@ 0x00000020) Prepare the TWI slave to respond to a write command   */
    __OM uint32_t TASKS_PREPARETX;                   /*!< (@ 0x00000024) Prepare the TWI slave to respond to a read command    */
    __IM uint32_t RESERVED3[2];
    __OM NRF_TWIS_TASKS_DMA_Type TASKS_DMA;          /*!< (@ 0x00000030) Peripheral tasks.                                     */
    __IM uint32_t RESERVED4[13];
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED5;
    __IOM uint32_t SUBSCRIBE_SUSPEND;                /*!< (@ 0x0000008C) Subscribe configuration for task SUSPEND              */
    __IOM uint32_t SUBSCRIBE_RESUME;                 /*!< (@ 0x00000090) Subscribe configuration for task RESUME               */
    __IM uint32_t RESERVED6[3];
    __IOM uint32_t SUBSCRIBE_PREPARERX;              /*!< (@ 0x000000A0) Subscribe configuration for task PREPARERX            */
    __IOM uint32_t SUBSCRIBE_PREPARETX;              /*!< (@ 0x000000A4) Subscribe configuration for task PREPARETX            */
    __IM uint32_t RESERVED7[2];
    __IOM NRF_TWIS_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000B0) Subscribe configuration for tasks                     */
    __IM uint32_t RESERVED8[13];
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) TWI stopped                                           */
    __IM uint32_t RESERVED9[3];
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000114) TWI error                                             */
    __IM uint32_t RESERVED10[9];
    __IOM uint32_t EVENTS_WRITE;                     /*!< (@ 0x0000013C) Write command received                                */
    __IOM uint32_t EVENTS_READ;                      /*!< (@ 0x00000140) Read command received                                 */
    __IM uint32_t RESERVED11[2];
    __IOM NRF_TWIS_EVENTS_DMA_Type EVENTS_DMA;       /*!< (@ 0x0000014C) Peripheral events.                                    */
    __IM uint32_t RESERVED12[4];
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
    __IM uint32_t RESERVED13[3];
    __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x00000194) Publish configuration for event ERROR                 */
    __IM uint32_t RESERVED14[9];
    __IOM uint32_t PUBLISH_WRITE;                    /*!< (@ 0x000001BC) Publish configuration for event WRITE                 */
    __IOM uint32_t PUBLISH_READ;                     /*!< (@ 0x000001C0) Publish configuration for event READ                  */
    __IM uint32_t RESERVED15[2];
    __IOM NRF_TWIS_PUBLISH_DMA_Type PUBLISH_DMA;     /*!< (@ 0x000001CC) Publish configuration for events                      */
    __IM uint32_t RESERVED16[3];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED17[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED18[113];
    __IOM uint32_t ERRORSRC;                         /*!< (@ 0x000004D0) Error source                                          */
    __IM uint32_t MATCH;                             /*!< (@ 0x000004D4) Status register indicating which address had a match  */
    __IM uint32_t RESERVED19[10];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable TWIS                                           */
    __IM uint32_t RESERVED20[33];
    __IOM uint32_t ADDRESS[2];                       /*!< (@ 0x00000588) TWI slave address n                                   */
    __IM uint32_t RESERVED21;
    __IOM uint32_t CONFIG;                           /*!< (@ 0x00000594) Configuration register for the address match mechanism*/
    __IM uint32_t RESERVED22[10];
    __IOM uint32_t ORC;                              /*!< (@ 0x000005C0) Over-read character. Character sent out in case of an
                                                                         over-read of the transmit buffer.*/
    __IM uint32_t RESERVED23[15];
    __IOM NRF_TWIS_PSEL_Type PSEL;                   /*!< (@ 0x00000600) (unspecified)                                         */
    __IM uint32_t RESERVED24[62];
    __IOM NRF_TWIS_DMA_Type DMA;                     /*!< (@ 0x00000700) (unspecified)                                         */
  } NRF_TWIS_Type;                                   /*!< Size = 1884 (0x75C)                                                  */

/* TWIS_TASKS_STOP: Stop TWI transaction */
  #define TWIS_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop TWI transaction */
  #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
  #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
  #define TWIS_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
  #define TWIS_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
  #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */


/* TWIS_TASKS_SUSPEND: Suspend TWI transaction */
  #define TWIS_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register.                             */

/* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */
  #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field.                                     */
  #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND
                                                                            field.*/
  #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field.                       */
  #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field.                       */
  #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task                                                   */


/* TWIS_TASKS_RESUME: Resume TWI transaction */
  #define TWIS_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register.                               */

/* TASKS_RESUME @Bit 0 : Resume TWI transaction */
  #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL)   /*!< Position of TASKS_RESUME field.                                      */
  #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/
  #define TWIS_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field.                          */
  #define TWIS_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field.                          */
  #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task                                                     */


/* TWIS_TASKS_PREPARERX: Prepare the TWI slave to respond to a write command */
  #define TWIS_TASKS_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARERX register.                         */

/* TASKS_PREPARERX @Bit 0 : Prepare the TWI slave to respond to a write command */
  #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field.                               */
  #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of
                                                                            TASKS_PREPARERX field.*/
  #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARERX field.                 */
  #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARERX field.                 */
  #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task                                               */


/* TWIS_TASKS_PREPARETX: Prepare the TWI slave to respond to a read command */
  #define TWIS_TASKS_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARETX register.                         */

/* TASKS_PREPARETX @Bit 0 : Prepare the TWI slave to respond to a read command */
  #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field.                               */
  #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of
                                                                            TASKS_PREPARETX field.*/
  #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARETX field.                 */
  #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARETX field.                 */
  #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task                                               */


/* TWIS_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define TWIS_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define TWIS_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define TWIS_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
  #define TWIS_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* TWIS_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */
  #define TWIS_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register.                     */

/* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */
  #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
  #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
  #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Min (0x00UL)  /*!< Min value of CHIDX field.                                            */
  #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL)       /*!< Position of EN field.                                                */
  #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field.                    */
  #define TWIS_SUBSCRIBE_SUSPEND_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_SUSPEND_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
  #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */


/* TWIS_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */
  #define TWIS_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */
  #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
  #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
  #define TWIS_SUBSCRIBE_RESUME_CHIDX_Min (0x00UL)   /*!< Min value of CHIDX field.                                            */
  #define TWIS_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field.                      */
  #define TWIS_SUBSCRIBE_RESUME_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_RESUME_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* TWIS_SUBSCRIBE_PREPARERX: Subscribe configuration for task PREPARERX */
  #define TWIS_SUBSCRIBE_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARERX register.                 */

/* CHIDX @Bits 0..7 : DPPI channel that task PREPARERX will subscribe to */
  #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field.                */
  #define TWIS_SUBSCRIBE_PREPARERX_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_PREPARERX_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
  #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */


/* TWIS_SUBSCRIBE_PREPARETX: Subscribe configuration for task PREPARETX */
  #define TWIS_SUBSCRIBE_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARETX register.                 */

/* CHIDX @Bits 0..7 : DPPI channel that task PREPARETX will subscribe to */
  #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field.                */
  #define TWIS_SUBSCRIBE_PREPARETX_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_PREPARETX_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
  #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */


/* TWIS_EVENTS_STOPPED: TWI stopped */
  #define TWIS_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */

/* EVENTS_STOPPED @Bit 0 : TWI stopped */
  #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
  #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
                                                                            EVENTS_STOPPED field.*/
  #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
  #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
  #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
  #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */


/* TWIS_EVENTS_ERROR: TWI error */
  #define TWIS_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                               */

/* EVENTS_ERROR @Bit 0 : TWI error */
  #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)   /*!< Position of EVENTS_ERROR field.                                      */
  #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/
  #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                          */
  #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                          */
  #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                */


/* TWIS_EVENTS_WRITE: Write command received */
  #define TWIS_EVENTS_WRITE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WRITE register.                               */

/* EVENTS_WRITE @Bit 0 : Write command received */
  #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL)   /*!< Position of EVENTS_WRITE field.                                      */
  #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field.*/
  #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Min (0x0UL) /*!< Min enumerator value of EVENTS_WRITE field.                          */
  #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Max (0x1UL) /*!< Max enumerator value of EVENTS_WRITE field.                          */
  #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated                                         */
  #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated                                                */


/* TWIS_EVENTS_READ: Read command received */
  #define TWIS_EVENTS_READ_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READ register.                                 */

/* EVENTS_READ @Bit 0 : Read command received */
  #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL)     /*!< Position of EVENTS_READ field.                                       */
  #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field.     */
  #define TWIS_EVENTS_READ_EVENTS_READ_Min (0x0UL)   /*!< Min enumerator value of EVENTS_READ field.                           */
  #define TWIS_EVENTS_READ_EVENTS_READ_Max (0x1UL)   /*!< Max enumerator value of EVENTS_READ field.                           */
  #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated                                           */
  #define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated                                                  */


/* TWIS_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define TWIS_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define TWIS_PUBLISH_STOPPED_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define TWIS_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
  #define TWIS_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* TWIS_PUBLISH_ERROR: Publish configuration for event ERROR */
  #define TWIS_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
  #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define TWIS_PUBLISH_ERROR_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define TWIS_PUBLISH_ERROR_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_ERROR_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                            */
  #define TWIS_PUBLISH_ERROR_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_ERROR_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* TWIS_PUBLISH_WRITE: Publish configuration for event WRITE */
  #define TWIS_PUBLISH_WRITE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_WRITE register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event WRITE will publish to */
  #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define TWIS_PUBLISH_WRITE_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define TWIS_PUBLISH_WRITE_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_WRITE_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field.                            */
  #define TWIS_PUBLISH_WRITE_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_WRITE_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* TWIS_PUBLISH_READ: Publish configuration for event READ */
  #define TWIS_PUBLISH_READ_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READ register.                               */

/* CHIDX @Bits 0..7 : DPPI channel that event READ will publish to */
  #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define TWIS_PUBLISH_READ_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define TWIS_PUBLISH_READ_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define TWIS_PUBLISH_READ_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field.                              */
  #define TWIS_PUBLISH_READ_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_READ_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define TWIS_PUBLISH_READ_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define TWIS_PUBLISH_READ_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* TWIS_SHORTS: Shortcuts between local events and tasks */
  #define TWIS_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */

/* WRITE_SUSPEND @Bit 13 : Shortcut between event WRITE and task SUSPEND */
  #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL)       /*!< Position of WRITE_SUSPEND field.                                     */
  #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field.         */
  #define TWIS_SHORTS_WRITE_SUSPEND_Min (0x0UL)      /*!< Min enumerator value of WRITE_SUSPEND field.                         */
  #define TWIS_SHORTS_WRITE_SUSPEND_Max (0x1UL)      /*!< Max enumerator value of WRITE_SUSPEND field.                         */
  #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut                                                     */
  #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL)  /*!< Enable shortcut                                                      */

/* READ_SUSPEND @Bit 14 : Shortcut between event READ and task SUSPEND */
  #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL)        /*!< Position of READ_SUSPEND field.                                      */
  #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field.            */
  #define TWIS_SHORTS_READ_SUSPEND_Min (0x0UL)       /*!< Min enumerator value of READ_SUSPEND field.                          */
  #define TWIS_SHORTS_READ_SUSPEND_Max (0x1UL)       /*!< Max enumerator value of READ_SUSPEND field.                          */
  #define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
  #define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL)   /*!< Enable shortcut                                                      */

/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows
                                               daisy-chaining match events. */

  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.   */
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows
                                               daisy-chaining match events. */

  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.   */
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows
                                               daisy-chaining match events. */

  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.   */
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows
                                               daisy-chaining match events. */

  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.   */
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                         DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                 */
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                   */

/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field. */
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIS_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field. */
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIS_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field. */
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIS_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field. */
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3
                                                                            field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define TWIS_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                  */


/* TWIS_INTEN: Enable or disable interrupt */
  #define TWIS_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */

/* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
  #define TWIS_INTEN_STOPPED_Pos (1UL)               /*!< Position of STOPPED field.                                           */
  #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                             */
  #define TWIS_INTEN_STOPPED_Min (0x0UL)             /*!< Min enumerator value of STOPPED field.                               */
  #define TWIS_INTEN_STOPPED_Max (0x1UL)             /*!< Max enumerator value of STOPPED field.                               */
  #define TWIS_INTEN_STOPPED_Disabled (0x0UL)        /*!< Disable                                                              */
  #define TWIS_INTEN_STOPPED_Enabled (0x1UL)         /*!< Enable                                                               */

/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */
  #define TWIS_INTEN_ERROR_Pos (5UL)                 /*!< Position of ERROR field.                                             */
  #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                   */
  #define TWIS_INTEN_ERROR_Min (0x0UL)               /*!< Min enumerator value of ERROR field.                                 */
  #define TWIS_INTEN_ERROR_Max (0x1UL)               /*!< Max enumerator value of ERROR field.                                 */
  #define TWIS_INTEN_ERROR_Disabled (0x0UL)          /*!< Disable                                                              */
  #define TWIS_INTEN_ERROR_Enabled (0x1UL)           /*!< Enable                                                               */

/* WRITE @Bit 15 : Enable or disable interrupt for event WRITE */
  #define TWIS_INTEN_WRITE_Pos (15UL)                /*!< Position of WRITE field.                                             */
  #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field.                                   */
  #define TWIS_INTEN_WRITE_Min (0x0UL)               /*!< Min enumerator value of WRITE field.                                 */
  #define TWIS_INTEN_WRITE_Max (0x1UL)               /*!< Max enumerator value of WRITE field.                                 */
  #define TWIS_INTEN_WRITE_Disabled (0x0UL)          /*!< Disable                                                              */
  #define TWIS_INTEN_WRITE_Enabled (0x1UL)           /*!< Enable                                                               */

/* READ @Bit 16 : Enable or disable interrupt for event READ */
  #define TWIS_INTEN_READ_Pos (16UL)                 /*!< Position of READ field.                                              */
  #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field.                                      */
  #define TWIS_INTEN_READ_Min (0x0UL)                /*!< Min enumerator value of READ field.                                  */
  #define TWIS_INTEN_READ_Max (0x1UL)                /*!< Max enumerator value of READ field.                                  */
  #define TWIS_INTEN_READ_Disabled (0x0UL)           /*!< Disable                                                              */
  #define TWIS_INTEN_READ_Enabled (0x1UL)            /*!< Enable                                                               */

/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */
  #define TWIS_INTEN_DMARXEND_Pos (19UL)             /*!< Position of DMARXEND field.                                          */
  #define TWIS_INTEN_DMARXEND_Msk (0x1UL << TWIS_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                          */
  #define TWIS_INTEN_DMARXEND_Min (0x0UL)            /*!< Min enumerator value of DMARXEND field.                              */
  #define TWIS_INTEN_DMARXEND_Max (0x1UL)            /*!< Max enumerator value of DMARXEND field.                              */
  #define TWIS_INTEN_DMARXEND_Disabled (0x0UL)       /*!< Disable                                                              */
  #define TWIS_INTEN_DMARXEND_Enabled (0x1UL)        /*!< Enable                                                               */

/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */
  #define TWIS_INTEN_DMARXREADY_Pos (20UL)           /*!< Position of DMARXREADY field.                                        */
  #define TWIS_INTEN_DMARXREADY_Msk (0x1UL << TWIS_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.                    */
  #define TWIS_INTEN_DMARXREADY_Min (0x0UL)          /*!< Min enumerator value of DMARXREADY field.                            */
  #define TWIS_INTEN_DMARXREADY_Max (0x1UL)          /*!< Max enumerator value of DMARXREADY field.                            */
  #define TWIS_INTEN_DMARXREADY_Disabled (0x0UL)     /*!< Disable                                                              */
  #define TWIS_INTEN_DMARXREADY_Enabled (0x1UL)      /*!< Enable                                                               */

/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */
  #define TWIS_INTEN_DMARXBUSERROR_Pos (21UL)        /*!< Position of DMARXBUSERROR field.                                     */
  #define TWIS_INTEN_DMARXBUSERROR_Msk (0x1UL << TWIS_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.           */
  #define TWIS_INTEN_DMARXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define TWIS_INTEN_DMARXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define TWIS_INTEN_DMARXBUSERROR_Disabled (0x0UL)  /*!< Disable                                                              */
  #define TWIS_INTEN_DMARXBUSERROR_Enabled (0x1UL)   /*!< Enable                                                               */

/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */
  #define TWIS_INTEN_DMARXMATCH0_Pos (22UL)          /*!< Position of DMARXMATCH0 field.                                       */
  #define TWIS_INTEN_DMARXMATCH0_Msk (0x1UL << TWIS_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.                 */
  #define TWIS_INTEN_DMARXMATCH0_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define TWIS_INTEN_DMARXMATCH0_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define TWIS_INTEN_DMARXMATCH0_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIS_INTEN_DMARXMATCH0_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */
  #define TWIS_INTEN_DMARXMATCH1_Pos (23UL)          /*!< Position of DMARXMATCH1 field.                                       */
  #define TWIS_INTEN_DMARXMATCH1_Msk (0x1UL << TWIS_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.                 */
  #define TWIS_INTEN_DMARXMATCH1_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define TWIS_INTEN_DMARXMATCH1_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define TWIS_INTEN_DMARXMATCH1_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIS_INTEN_DMARXMATCH1_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */
  #define TWIS_INTEN_DMARXMATCH2_Pos (24UL)          /*!< Position of DMARXMATCH2 field.                                       */
  #define TWIS_INTEN_DMARXMATCH2_Msk (0x1UL << TWIS_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.                 */
  #define TWIS_INTEN_DMARXMATCH2_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define TWIS_INTEN_DMARXMATCH2_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define TWIS_INTEN_DMARXMATCH2_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIS_INTEN_DMARXMATCH2_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */
  #define TWIS_INTEN_DMARXMATCH3_Pos (25UL)          /*!< Position of DMARXMATCH3 field.                                       */
  #define TWIS_INTEN_DMARXMATCH3_Msk (0x1UL << TWIS_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.                 */
  #define TWIS_INTEN_DMARXMATCH3_Min (0x0UL)         /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define TWIS_INTEN_DMARXMATCH3_Max (0x1UL)         /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define TWIS_INTEN_DMARXMATCH3_Disabled (0x0UL)    /*!< Disable                                                              */
  #define TWIS_INTEN_DMARXMATCH3_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */
  #define TWIS_INTEN_DMATXEND_Pos (26UL)             /*!< Position of DMATXEND field.                                          */
  #define TWIS_INTEN_DMATXEND_Msk (0x1UL << TWIS_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                          */
  #define TWIS_INTEN_DMATXEND_Min (0x0UL)            /*!< Min enumerator value of DMATXEND field.                              */
  #define TWIS_INTEN_DMATXEND_Max (0x1UL)            /*!< Max enumerator value of DMATXEND field.                              */
  #define TWIS_INTEN_DMATXEND_Disabled (0x0UL)       /*!< Disable                                                              */
  #define TWIS_INTEN_DMATXEND_Enabled (0x1UL)        /*!< Enable                                                               */

/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */
  #define TWIS_INTEN_DMATXREADY_Pos (27UL)           /*!< Position of DMATXREADY field.                                        */
  #define TWIS_INTEN_DMATXREADY_Msk (0x1UL << TWIS_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.                    */
  #define TWIS_INTEN_DMATXREADY_Min (0x0UL)          /*!< Min enumerator value of DMATXREADY field.                            */
  #define TWIS_INTEN_DMATXREADY_Max (0x1UL)          /*!< Max enumerator value of DMATXREADY field.                            */
  #define TWIS_INTEN_DMATXREADY_Disabled (0x0UL)     /*!< Disable                                                              */
  #define TWIS_INTEN_DMATXREADY_Enabled (0x1UL)      /*!< Enable                                                               */

/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */
  #define TWIS_INTEN_DMATXBUSERROR_Pos (28UL)        /*!< Position of DMATXBUSERROR field.                                     */
  #define TWIS_INTEN_DMATXBUSERROR_Msk (0x1UL << TWIS_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.           */
  #define TWIS_INTEN_DMATXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define TWIS_INTEN_DMATXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define TWIS_INTEN_DMATXBUSERROR_Disabled (0x0UL)  /*!< Disable                                                              */
  #define TWIS_INTEN_DMATXBUSERROR_Enabled (0x1UL)   /*!< Enable                                                               */


/* TWIS_INTENSET: Enable interrupt */
  #define TWIS_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */

/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
  #define TWIS_INTENSET_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
  #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define TWIS_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define TWIS_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define TWIS_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
  #define TWIS_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */
  #define TWIS_INTENSET_ERROR_Pos (5UL)              /*!< Position of ERROR field.                                             */
  #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
  #define TWIS_INTENSET_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
  #define TWIS_INTENSET_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
  #define TWIS_INTENSET_ERROR_Set (0x1UL)            /*!< Enable                                                               */
  #define TWIS_INTENSET_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* WRITE @Bit 15 : Write '1' to enable interrupt for event WRITE */
  #define TWIS_INTENSET_WRITE_Pos (15UL)             /*!< Position of WRITE field.                                             */
  #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field.                             */
  #define TWIS_INTENSET_WRITE_Min (0x0UL)            /*!< Min enumerator value of WRITE field.                                 */
  #define TWIS_INTENSET_WRITE_Max (0x1UL)            /*!< Max enumerator value of WRITE field.                                 */
  #define TWIS_INTENSET_WRITE_Set (0x1UL)            /*!< Enable                                                               */
  #define TWIS_INTENSET_WRITE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_WRITE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* READ @Bit 16 : Write '1' to enable interrupt for event READ */
  #define TWIS_INTENSET_READ_Pos (16UL)              /*!< Position of READ field.                                              */
  #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field.                                */
  #define TWIS_INTENSET_READ_Min (0x0UL)             /*!< Min enumerator value of READ field.                                  */
  #define TWIS_INTENSET_READ_Max (0x1UL)             /*!< Max enumerator value of READ field.                                  */
  #define TWIS_INTENSET_READ_Set (0x1UL)             /*!< Enable                                                               */
  #define TWIS_INTENSET_READ_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_READ_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */
  #define TWIS_INTENSET_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define TWIS_INTENSET_DMARXEND_Msk (0x1UL << TWIS_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define TWIS_INTENSET_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define TWIS_INTENSET_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define TWIS_INTENSET_DMARXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define TWIS_INTENSET_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */
  #define TWIS_INTENSET_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define TWIS_INTENSET_DMARXREADY_Msk (0x1UL << TWIS_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define TWIS_INTENSET_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define TWIS_INTENSET_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define TWIS_INTENSET_DMARXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define TWIS_INTENSET_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */
  #define TWIS_INTENSET_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define TWIS_INTENSET_DMARXBUSERROR_Msk (0x1UL << TWIS_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define TWIS_INTENSET_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define TWIS_INTENSET_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define TWIS_INTENSET_DMARXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define TWIS_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIS_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */
  #define TWIS_INTENSET_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define TWIS_INTENSET_DMARXMATCH0_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define TWIS_INTENSET_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define TWIS_INTENSET_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define TWIS_INTENSET_DMARXMATCH0_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIS_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */
  #define TWIS_INTENSET_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define TWIS_INTENSET_DMARXMATCH1_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define TWIS_INTENSET_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define TWIS_INTENSET_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define TWIS_INTENSET_DMARXMATCH1_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIS_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */
  #define TWIS_INTENSET_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define TWIS_INTENSET_DMARXMATCH2_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define TWIS_INTENSET_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define TWIS_INTENSET_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define TWIS_INTENSET_DMARXMATCH2_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIS_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */
  #define TWIS_INTENSET_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define TWIS_INTENSET_DMARXMATCH3_Msk (0x1UL << TWIS_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define TWIS_INTENSET_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define TWIS_INTENSET_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define TWIS_INTENSET_DMARXMATCH3_Set (0x1UL)      /*!< Enable                                                               */
  #define TWIS_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */
  #define TWIS_INTENSET_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define TWIS_INTENSET_DMATXEND_Msk (0x1UL << TWIS_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define TWIS_INTENSET_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define TWIS_INTENSET_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define TWIS_INTENSET_DMATXEND_Set (0x1UL)         /*!< Enable                                                               */
  #define TWIS_INTENSET_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */
  #define TWIS_INTENSET_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define TWIS_INTENSET_DMATXREADY_Msk (0x1UL << TWIS_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define TWIS_INTENSET_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define TWIS_INTENSET_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define TWIS_INTENSET_DMATXREADY_Set (0x1UL)       /*!< Enable                                                               */
  #define TWIS_INTENSET_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIS_INTENSET_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */
  #define TWIS_INTENSET_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define TWIS_INTENSET_DMATXBUSERROR_Msk (0x1UL << TWIS_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define TWIS_INTENSET_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define TWIS_INTENSET_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define TWIS_INTENSET_DMATXBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
  #define TWIS_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIS_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* TWIS_INTENCLR: Disable interrupt */
  #define TWIS_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */

/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
  #define TWIS_INTENCLR_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
  #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
  #define TWIS_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
  #define TWIS_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
  #define TWIS_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
  #define TWIS_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */
  #define TWIS_INTENCLR_ERROR_Pos (5UL)              /*!< Position of ERROR field.                                             */
  #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
  #define TWIS_INTENCLR_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
  #define TWIS_INTENCLR_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
  #define TWIS_INTENCLR_ERROR_Clear (0x1UL)          /*!< Disable                                                              */
  #define TWIS_INTENCLR_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* WRITE @Bit 15 : Write '1' to disable interrupt for event WRITE */
  #define TWIS_INTENCLR_WRITE_Pos (15UL)             /*!< Position of WRITE field.                                             */
  #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field.                             */
  #define TWIS_INTENCLR_WRITE_Min (0x0UL)            /*!< Min enumerator value of WRITE field.                                 */
  #define TWIS_INTENCLR_WRITE_Max (0x1UL)            /*!< Max enumerator value of WRITE field.                                 */
  #define TWIS_INTENCLR_WRITE_Clear (0x1UL)          /*!< Disable                                                              */
  #define TWIS_INTENCLR_WRITE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_WRITE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* READ @Bit 16 : Write '1' to disable interrupt for event READ */
  #define TWIS_INTENCLR_READ_Pos (16UL)              /*!< Position of READ field.                                              */
  #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field.                                */
  #define TWIS_INTENCLR_READ_Min (0x0UL)             /*!< Min enumerator value of READ field.                                  */
  #define TWIS_INTENCLR_READ_Max (0x1UL)             /*!< Max enumerator value of READ field.                                  */
  #define TWIS_INTENCLR_READ_Clear (0x1UL)           /*!< Disable                                                              */
  #define TWIS_INTENCLR_READ_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_READ_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */
  #define TWIS_INTENCLR_DMARXEND_Pos (19UL)          /*!< Position of DMARXEND field.                                          */
  #define TWIS_INTENCLR_DMARXEND_Msk (0x1UL << TWIS_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                    */
  #define TWIS_INTENCLR_DMARXEND_Min (0x0UL)         /*!< Min enumerator value of DMARXEND field.                              */
  #define TWIS_INTENCLR_DMARXEND_Max (0x1UL)         /*!< Max enumerator value of DMARXEND field.                              */
  #define TWIS_INTENCLR_DMARXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMARXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMARXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */
  #define TWIS_INTENCLR_DMARXREADY_Pos (20UL)        /*!< Position of DMARXREADY field.                                        */
  #define TWIS_INTENCLR_DMARXREADY_Msk (0x1UL << TWIS_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.              */
  #define TWIS_INTENCLR_DMARXREADY_Min (0x0UL)       /*!< Min enumerator value of DMARXREADY field.                            */
  #define TWIS_INTENCLR_DMARXREADY_Max (0x1UL)       /*!< Max enumerator value of DMARXREADY field.                            */
  #define TWIS_INTENCLR_DMARXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMARXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMARXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */
  #define TWIS_INTENCLR_DMARXBUSERROR_Pos (21UL)     /*!< Position of DMARXBUSERROR field.                                     */
  #define TWIS_INTENCLR_DMARXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.     */
  #define TWIS_INTENCLR_DMARXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define TWIS_INTENCLR_DMARXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define TWIS_INTENCLR_DMARXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIS_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */

/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */
  #define TWIS_INTENCLR_DMARXMATCH0_Pos (22UL)       /*!< Position of DMARXMATCH0 field.                                       */
  #define TWIS_INTENCLR_DMARXMATCH0_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.           */
  #define TWIS_INTENCLR_DMARXMATCH0_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH0_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH0_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMARXMATCH0_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */
  #define TWIS_INTENCLR_DMARXMATCH1_Pos (23UL)       /*!< Position of DMARXMATCH1 field.                                       */
  #define TWIS_INTENCLR_DMARXMATCH1_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.           */
  #define TWIS_INTENCLR_DMARXMATCH1_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH1_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH1_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMARXMATCH1_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */
  #define TWIS_INTENCLR_DMARXMATCH2_Pos (24UL)       /*!< Position of DMARXMATCH2 field.                                       */
  #define TWIS_INTENCLR_DMARXMATCH2_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.           */
  #define TWIS_INTENCLR_DMARXMATCH2_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH2_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH2_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMARXMATCH2_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */
  #define TWIS_INTENCLR_DMARXMATCH3_Pos (25UL)       /*!< Position of DMARXMATCH3 field.                                       */
  #define TWIS_INTENCLR_DMARXMATCH3_Msk (0x1UL << TWIS_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.           */
  #define TWIS_INTENCLR_DMARXMATCH3_Min (0x0UL)      /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH3_Max (0x1UL)      /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define TWIS_INTENCLR_DMARXMATCH3_Clear (0x1UL)    /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMARXMATCH3_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */
  #define TWIS_INTENCLR_DMATXEND_Pos (26UL)          /*!< Position of DMATXEND field.                                          */
  #define TWIS_INTENCLR_DMATXEND_Msk (0x1UL << TWIS_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                    */
  #define TWIS_INTENCLR_DMATXEND_Min (0x0UL)         /*!< Min enumerator value of DMATXEND field.                              */
  #define TWIS_INTENCLR_DMATXEND_Max (0x1UL)         /*!< Max enumerator value of DMATXEND field.                              */
  #define TWIS_INTENCLR_DMATXEND_Clear (0x1UL)       /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMATXEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMATXEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */
  #define TWIS_INTENCLR_DMATXREADY_Pos (27UL)        /*!< Position of DMATXREADY field.                                        */
  #define TWIS_INTENCLR_DMATXREADY_Msk (0x1UL << TWIS_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.              */
  #define TWIS_INTENCLR_DMATXREADY_Min (0x0UL)       /*!< Min enumerator value of DMATXREADY field.                            */
  #define TWIS_INTENCLR_DMATXREADY_Max (0x1UL)       /*!< Max enumerator value of DMATXREADY field.                            */
  #define TWIS_INTENCLR_DMATXREADY_Clear (0x1UL)     /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMATXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define TWIS_INTENCLR_DMATXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */
  #define TWIS_INTENCLR_DMATXBUSERROR_Pos (28UL)     /*!< Position of DMATXBUSERROR field.                                     */
  #define TWIS_INTENCLR_DMATXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.     */
  #define TWIS_INTENCLR_DMATXBUSERROR_Min (0x0UL)    /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define TWIS_INTENCLR_DMATXBUSERROR_Max (0x1UL)    /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define TWIS_INTENCLR_DMATXBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
  #define TWIS_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define TWIS_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* TWIS_ERRORSRC: Error source */
  #define TWIS_ERRORSRC_ResetValue (0x00000000UL)    /*!< Reset value of ERRORSRC register.                                    */

/* OVERFLOW @Bit 0 : RX buffer overflow detected, and prevented */
  #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL)           /*!< Position of OVERFLOW field.                                          */
  #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field.                    */
  #define TWIS_ERRORSRC_OVERFLOW_Min (0x0UL)         /*!< Min enumerator value of OVERFLOW field.                              */
  #define TWIS_ERRORSRC_OVERFLOW_Max (0x1UL)         /*!< Max enumerator value of OVERFLOW field.                              */
  #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur                                                  */
  #define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL)    /*!< Error occurred                                                       */

/* DNACK @Bit 2 : NACK sent after receiving a data byte */
  #define TWIS_ERRORSRC_DNACK_Pos (2UL)              /*!< Position of DNACK field.                                             */
  #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field.                             */
  #define TWIS_ERRORSRC_DNACK_Min (0x0UL)            /*!< Min enumerator value of DNACK field.                                 */
  #define TWIS_ERRORSRC_DNACK_Max (0x1UL)            /*!< Max enumerator value of DNACK field.                                 */
  #define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL)    /*!< Error did not occur                                                  */
  #define TWIS_ERRORSRC_DNACK_Received (0x1UL)       /*!< Error occurred                                                       */

/* OVERREAD @Bit 3 : TX buffer over-read detected, and prevented */
  #define TWIS_ERRORSRC_OVERREAD_Pos (3UL)           /*!< Position of OVERREAD field.                                          */
  #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field.                    */
  #define TWIS_ERRORSRC_OVERREAD_Min (0x0UL)         /*!< Min enumerator value of OVERREAD field.                              */
  #define TWIS_ERRORSRC_OVERREAD_Max (0x1UL)         /*!< Max enumerator value of OVERREAD field.                              */
  #define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur                                                  */
  #define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL)    /*!< Error occurred                                                       */


/* TWIS_MATCH: Status register indicating which address had a match */
  #define TWIS_MATCH_ResetValue (0x00000000UL)       /*!< Reset value of MATCH register.                                       */

/* MATCH @Bit 0 : Indication of which address in ADDRESS that matched the incoming address */
  #define TWIS_MATCH_MATCH_Pos (0UL)                 /*!< Position of MATCH field.                                             */
  #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field.                                   */
  #define TWIS_MATCH_MATCH_Min (0x0UL)               /*!< Min value of MATCH field.                                            */
  #define TWIS_MATCH_MATCH_Max (0x1UL)               /*!< Max size of MATCH field.                                             */


/* TWIS_ENABLE: Enable TWIS */
  #define TWIS_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..3 : Enable or disable TWIS */
  #define TWIS_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
  #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
  #define TWIS_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
  #define TWIS_ENABLE_ENABLE_Max (0x9UL)             /*!< Max enumerator value of ENABLE field.                                */
  #define TWIS_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable TWIS                                                         */
  #define TWIS_ENABLE_ENABLE_Enabled (0x9UL)         /*!< Enable TWIS                                                          */


/* TWIS_ADDRESS: TWI slave address n */
  #define TWIS_ADDRESS_MaxCount (2UL)                /*!< Max size of ADDRESS[2] array.                                        */
  #define TWIS_ADDRESS_MaxIndex (1UL)                /*!< Max index of ADDRESS[2] array.                                       */
  #define TWIS_ADDRESS_MinIndex (0UL)                /*!< Min index of ADDRESS[2] array.                                       */
  #define TWIS_ADDRESS_ResetValue (0x00000000UL)     /*!< Reset value of ADDRESS[2] register.                                  */

/* ADDRESS @Bits 0..6 : TWI slave address */
  #define TWIS_ADDRESS_ADDRESS_Pos (0UL)             /*!< Position of ADDRESS field.                                           */
  #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                        */


/* TWIS_CONFIG: Configuration register for the address match mechanism */
  #define TWIS_CONFIG_ResetValue (0x00000001UL)      /*!< Reset value of CONFIG register.                                      */

/* ADDRESS0 @Bit 0 : Enable or disable address matching on ADDRESS[0] */
  #define TWIS_CONFIG_ADDRESS0_Pos (0UL)             /*!< Position of ADDRESS0 field.                                          */
  #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field.                        */
  #define TWIS_CONFIG_ADDRESS0_Min (0x0UL)           /*!< Min enumerator value of ADDRESS0 field.                              */
  #define TWIS_CONFIG_ADDRESS0_Max (0x1UL)           /*!< Max enumerator value of ADDRESS0 field.                              */
  #define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL)      /*!< Disabled                                                             */
  #define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL)       /*!< Enabled                                                              */

/* ADDRESS1 @Bit 1 : Enable or disable address matching on ADDRESS[1] */
  #define TWIS_CONFIG_ADDRESS1_Pos (1UL)             /*!< Position of ADDRESS1 field.                                          */
  #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field.                        */
  #define TWIS_CONFIG_ADDRESS1_Min (0x0UL)           /*!< Min enumerator value of ADDRESS1 field.                              */
  #define TWIS_CONFIG_ADDRESS1_Max (0x1UL)           /*!< Max enumerator value of ADDRESS1 field.                              */
  #define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL)      /*!< Disabled                                                             */
  #define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL)       /*!< Enabled                                                              */


/* TWIS_ORC: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
  #define TWIS_ORC_ResetValue (0x00000000UL)         /*!< Reset value of ORC register.                                         */

/* ORC @Bits 0..7 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
  #define TWIS_ORC_ORC_Pos (0UL)                     /*!< Position of ORC field.                                               */
  #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field.                                            */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           UARTE                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================ Struct UARTE_TASKS_DMA_RX ================================================ */
/**
  * @brief RX [UARTE_TASKS_DMA_RX] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  START;                             /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See
                                                                         peripheral description for operation using easyDMA.*/
  __OM  uint32_t  STOP;                              /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an
                                                                         END event.*/
  __OM  uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000008) Enables the MATCH[n] event by setting the ENABLE[n] bit
                                                                         in the CONFIG register.*/
  __OM  uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000018) Disables the MATCH[n] event by clearing the ENABLE[n]
                                                                         bit in the CONFIG register.*/
} NRF_UARTE_TASKS_DMA_RX_Type;                       /*!< Size = 40 (0x028)                                                    */

/* UARTE_TASKS_DMA_RX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using
                              easyDMA. */

  #define UARTE_TASKS_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                               */

/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */
  #define UARTE_TASKS_DMA_RX_START_START_Pos (0UL)   /*!< Position of START field.                                             */
  #define UARTE_TASKS_DMA_RX_START_START_Msk (0x1UL << UARTE_TASKS_DMA_RX_START_START_Pos) /*!< Bit mask of START field.       */
  #define UARTE_TASKS_DMA_RX_START_START_Min (0x1UL) /*!< Min enumerator value of START field.                                 */
  #define UARTE_TASKS_DMA_RX_START_START_Max (0x1UL) /*!< Max enumerator value of START field.                                 */
  #define UARTE_TASKS_DMA_RX_START_START_Trigger (0x1UL) /*!< Trigger task                                                     */


/* UARTE_TASKS_DMA_RX_STOP: Stops operation using easyDMA. This does not trigger an END event. */
  #define UARTE_TASKS_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                                 */

/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */
  #define UARTE_TASKS_DMA_RX_STOP_STOP_Pos (0UL)     /*!< Position of STOP field.                                              */
  #define UARTE_TASKS_DMA_RX_STOP_STOP_Msk (0x1UL << UARTE_TASKS_DMA_RX_STOP_STOP_Pos) /*!< Bit mask of STOP field.            */
  #define UARTE_TASKS_DMA_RX_STOP_STOP_Min (0x1UL)   /*!< Min enumerator value of STOP field.                                  */
  #define UARTE_TASKS_DMA_RX_STOP_STOP_Max (0x1UL)   /*!< Max enumerator value of STOP field.                                  */
  #define UARTE_TASKS_DMA_RX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task                                                       */


/* UARTE_TASKS_DMA_RX_ENABLEMATCH: Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                                 */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                                */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                                */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.                */

/* ENABLEMATCH @Bit 0 : Enables the MATCH[n] event by setting the ENABLE[n] bit in the CONFIG register. */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos (0UL) /*!< Position of ENABLEMATCH field.                             */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk (0x1UL << UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Pos) /*!< Bit mask
                                                                            of ENABLEMATCH field.*/
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Min (0x1UL) /*!< Min enumerator value of ENABLEMATCH field.               */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Max (0x1UL) /*!< Max enumerator value of ENABLEMATCH field.               */
  #define UARTE_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                         */


/* UARTE_TASKS_DMA_RX_DISABLEMATCH: Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                               */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                              */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                              */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.              */

/* DISABLEMATCH @Bit 0 : Disables the MATCH[n] event by clearing the ENABLE[n] bit in the CONFIG register. */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos (0UL) /*!< Position of DISABLEMATCH field.                          */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Msk (0x1UL << UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Pos) /*!< Bit
                                                                            mask of DISABLEMATCH field.*/
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Min (0x1UL) /*!< Min enumerator value of DISABLEMATCH field.            */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Max (0x1UL) /*!< Max enumerator value of DISABLEMATCH field.            */
  #define UARTE_TASKS_DMA_RX_DISABLEMATCH_DISABLEMATCH_Trigger (0x1UL) /*!< Trigger task                                       */



/* ================================================ Struct UARTE_TASKS_DMA_TX ================================================ */
/**
  * @brief TX [UARTE_TASKS_DMA_TX] Peripheral tasks.
  */
typedef struct {
  __OM  uint32_t  START;                             /*!< (@ 0x00000000) Starts operation using easyDMA to load the values. See
                                                                         peripheral description for operation using easyDMA.*/
  __OM  uint32_t  STOP;                              /*!< (@ 0x00000004) Stops operation using easyDMA. This does not trigger an
                                                                         END event.*/
} NRF_UARTE_TASKS_DMA_TX_Type;                       /*!< Size = 8 (0x008)                                                     */

/* UARTE_TASKS_DMA_TX_START: Starts operation using easyDMA to load the values. See peripheral description for operation using
                              easyDMA. */

  #define UARTE_TASKS_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                               */

/* START @Bit 0 : Starts operation using easyDMA to load the values. See peripheral description for operation using easyDMA. */
  #define UARTE_TASKS_DMA_TX_START_START_Pos (0UL)   /*!< Position of START field.                                             */
  #define UARTE_TASKS_DMA_TX_START_START_Msk (0x1UL << UARTE_TASKS_DMA_TX_START_START_Pos) /*!< Bit mask of START field.       */
  #define UARTE_TASKS_DMA_TX_START_START_Min (0x1UL) /*!< Min enumerator value of START field.                                 */
  #define UARTE_TASKS_DMA_TX_START_START_Max (0x1UL) /*!< Max enumerator value of START field.                                 */
  #define UARTE_TASKS_DMA_TX_START_START_Trigger (0x1UL) /*!< Trigger task                                                     */


/* UARTE_TASKS_DMA_TX_STOP: Stops operation using easyDMA. This does not trigger an END event. */
  #define UARTE_TASKS_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                                 */

/* STOP @Bit 0 : Stops operation using easyDMA. This does not trigger an END event. */
  #define UARTE_TASKS_DMA_TX_STOP_STOP_Pos (0UL)     /*!< Position of STOP field.                                              */
  #define UARTE_TASKS_DMA_TX_STOP_STOP_Msk (0x1UL << UARTE_TASKS_DMA_TX_STOP_STOP_Pos) /*!< Bit mask of STOP field.            */
  #define UARTE_TASKS_DMA_TX_STOP_STOP_Min (0x1UL)   /*!< Min enumerator value of STOP field.                                  */
  #define UARTE_TASKS_DMA_TX_STOP_STOP_Max (0x1UL)   /*!< Max enumerator value of STOP field.                                  */
  #define UARTE_TASKS_DMA_TX_STOP_STOP_Trigger (0x1UL) /*!< Trigger task                                                       */



/* ================================================= Struct UARTE_TASKS_DMA ================================================== */
/**
  * @brief TASKS_DMA [UARTE_TASKS_DMA] Peripheral tasks.
  */
typedef struct {
  __OM  NRF_UARTE_TASKS_DMA_RX_Type RX;              /*!< (@ 0x00000000) Peripheral tasks.                                     */
  __OM  NRF_UARTE_TASKS_DMA_TX_Type TX;              /*!< (@ 0x00000028) Peripheral tasks.                                     */
} NRF_UARTE_TASKS_DMA_Type;                          /*!< Size = 48 (0x030)                                                    */


/* ============================================== Struct UARTE_SUBSCRIBE_DMA_RX ============================================== */
/**
  * @brief RX [UARTE_SUBSCRIBE_DMA_RX] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  START;                             /*!< (@ 0x00000000) Subscribe configuration for task START                */
  __IOM uint32_t  STOP;                              /*!< (@ 0x00000004) Subscribe configuration for task STOP                 */
  __IOM uint32_t  ENABLEMATCH[4];                    /*!< (@ 0x00000008) Subscribe configuration for task ENABLEMATCH[n]       */
  __IOM uint32_t  DISABLEMATCH[4];                   /*!< (@ 0x00000018) Subscribe configuration for task DISABLEMATCH[n]      */
} NRF_UARTE_SUBSCRIBE_DMA_RX_Type;                   /*!< Size = 40 (0x028)                                                    */

/* UARTE_SUBSCRIBE_DMA_RX_START: Subscribe configuration for task START */
  #define UARTE_SUBSCRIBE_DMA_RX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define UARTE_SUBSCRIBE_DMA_RX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_START_EN_Pos) /*!< Bit mask of EN field.        */
  #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Disabled (0x0UL) /*!< Disable subscription                                           */
  #define UARTE_SUBSCRIBE_DMA_RX_START_EN_Enabled (0x1UL) /*!< Enable subscription                                             */


/* UARTE_SUBSCRIBE_DMA_RX_STOP: Subscribe configuration for task STOP */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                        */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Pos (31UL)  /*!< Position of EN field.                                                */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Pos) /*!< Bit mask of EN field.          */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription                                            */
  #define UARTE_SUBSCRIBE_DMA_RX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription                                              */


/* UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH: Subscribe configuration for task ENABLEMATCH[n] */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxCount (4UL) /*!< Max size of ENABLEMATCH[4] array.                             */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MaxIndex (3UL) /*!< Max index of ENABLEMATCH[4] array.                            */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_MinIndex (0UL) /*!< Min index of ENABLEMATCH[4] array.                            */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of ENABLEMATCH[4] register.            */

/* CHIDX @Bits 0..7 : DPPI channel that task ENABLEMATCH[n] will subscribe to */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                     */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Pos) /*!< Bit mask of
                                                                            CHIDX field.*/
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                 */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                  */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                          */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                             */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                             */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                     */
  #define UARTE_SUBSCRIBE_DMA_RX_ENABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                       */


/* UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH: Subscribe configuration for task DISABLEMATCH[n] */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxCount (4UL) /*!< Max size of DISABLEMATCH[4] array.                           */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MaxIndex (3UL) /*!< Max index of DISABLEMATCH[4] array.                          */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_MinIndex (0UL) /*!< Min index of DISABLEMATCH[4] array.                          */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_ResetValue (0x00000000UL) /*!< Reset value of DISABLEMATCH[4] register.          */

/* CHIDX @Bits 0..7 : DPPI channel that task DISABLEMATCH[n] will subscribe to */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                    */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Pos) /*!< Bit mask
                                                                            of CHIDX field.*/
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                 */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos (31UL) /*!< Position of EN field.                                         */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Pos) /*!< Bit mask of EN
                                                                            field.*/
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                            */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                            */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Disabled (0x0UL) /*!< Disable subscription                                    */
  #define UARTE_SUBSCRIBE_DMA_RX_DISABLEMATCH_EN_Enabled (0x1UL) /*!< Enable subscription                                      */



/* ============================================== Struct UARTE_SUBSCRIBE_DMA_TX ============================================== */
/**
  * @brief TX [UARTE_SUBSCRIBE_DMA_TX] Subscribe configuration for tasks
  */
typedef struct {
  __IOM uint32_t  START;                             /*!< (@ 0x00000000) Subscribe configuration for task START                */
  __IOM uint32_t  STOP;                              /*!< (@ 0x00000004) Subscribe configuration for task STOP                 */
} NRF_UARTE_SUBSCRIBE_DMA_TX_Type;                   /*!< Size = 8 (0x008)                                                     */

/* UARTE_SUBSCRIBE_DMA_TX_START: Subscribe configuration for task START */
  #define UARTE_SUBSCRIBE_DMA_TX_START_ResetValue (0x00000000UL) /*!< Reset value of START register.                           */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
  #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                       */
  #define UARTE_SUBSCRIBE_DMA_TX_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Pos (31UL) /*!< Position of EN field.                                                */
  #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_TX_START_EN_Pos) /*!< Bit mask of EN field.        */
  #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
  #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
  #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Disabled (0x0UL) /*!< Disable subscription                                           */
  #define UARTE_SUBSCRIBE_DMA_TX_START_EN_Enabled (0x1UL) /*!< Enable subscription                                             */


/* UARTE_SUBSCRIBE_DMA_TX_STOP: Subscribe configuration for task STOP */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_ResetValue (0x00000000UL) /*!< Reset value of STOP register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                        */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Pos (31UL)  /*!< Position of EN field.                                                */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Msk (0x1UL << UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Pos) /*!< Bit mask of EN field.          */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Disabled (0x0UL) /*!< Disable subscription                                            */
  #define UARTE_SUBSCRIBE_DMA_TX_STOP_EN_Enabled (0x1UL) /*!< Enable subscription                                              */



/* =============================================== Struct UARTE_SUBSCRIBE_DMA ================================================ */
/**
  * @brief SUBSCRIBE_DMA [UARTE_SUBSCRIBE_DMA] Subscribe configuration for tasks
  */
typedef struct {
  __IOM NRF_UARTE_SUBSCRIBE_DMA_RX_Type RX;          /*!< (@ 0x00000000) Subscribe configuration for tasks                     */
  __IOM NRF_UARTE_SUBSCRIBE_DMA_TX_Type TX;          /*!< (@ 0x00000028) Subscribe configuration for tasks                     */
} NRF_UARTE_SUBSCRIBE_DMA_Type;                      /*!< Size = 48 (0x030)                                                    */


/* =============================================== Struct UARTE_EVENTS_DMA_RX ================================================ */
/**
  * @brief RX [UARTE_EVENTS_DMA_RX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Pattern match is detected on the DMA data bus.        */
} NRF_UARTE_EVENTS_DMA_RX_Type;                      /*!< Size = 28 (0x01C)                                                    */

/* UARTE_EVENTS_DMA_RX_END: Generated after all MAXCNT bytes have been transferred */
  #define UARTE_EVENTS_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define UARTE_EVENTS_DMA_RX_END_END_Pos (0UL)      /*!< Position of END field.                                               */
  #define UARTE_EVENTS_DMA_RX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_RX_END_END_Pos) /*!< Bit mask of END field.               */
  #define UARTE_EVENTS_DMA_RX_END_END_Min (0x0UL)    /*!< Min enumerator value of END field.                                   */
  #define UARTE_EVENTS_DMA_RX_END_END_Max (0x1UL)    /*!< Max enumerator value of END field.                                   */
  #define UARTE_EVENTS_DMA_RX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                            */
  #define UARTE_EVENTS_DMA_RX_END_END_Generated (0x1UL) /*!< Event generated                                                   */


/* UARTE_EVENTS_DMA_RX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                               to be written to prepare for the next sequence. */

  #define UARTE_EVENTS_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define UARTE_EVENTS_DMA_RX_READY_READY_Pos (0UL)  /*!< Position of READY field.                                             */
  #define UARTE_EVENTS_DMA_RX_READY_READY_Msk (0x1UL << UARTE_EVENTS_DMA_RX_READY_READY_Pos) /*!< Bit mask of READY field.     */
  #define UARTE_EVENTS_DMA_RX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                */
  #define UARTE_EVENTS_DMA_RX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                */
  #define UARTE_EVENTS_DMA_RX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define UARTE_EVENTS_DMA_RX_READY_READY_Generated (0x1UL) /*!< Event generated                                               */


/* UARTE_EVENTS_DMA_RX_BUSERROR: An error occured during the bus transfer. */
  #define UARTE_EVENTS_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                     */
  #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk (0x1UL << UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of
                                                                            BUSERROR field.*/
  #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                       */
  #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                       */
  #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define UARTE_EVENTS_DMA_RX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                         */


/* UARTE_EVENTS_DMA_RX_MATCH: Pattern match is detected on the DMA data bus. */
  #define UARTE_EVENTS_DMA_RX_MATCH_MaxCount (4UL)   /*!< Max size of MATCH[4] array.                                          */
  #define UARTE_EVENTS_DMA_RX_MATCH_MaxIndex (3UL)   /*!< Max index of MATCH[4] array.                                         */
  #define UARTE_EVENTS_DMA_RX_MATCH_MinIndex (0UL)   /*!< Min index of MATCH[4] array.                                         */
  #define UARTE_EVENTS_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                           */

/* MATCH @Bit 0 : Pattern match is detected on the DMA data bus. */
  #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Pos (0UL)  /*!< Position of MATCH field.                                             */
  #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Msk (0x1UL << UARTE_EVENTS_DMA_RX_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field.     */
  #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Min (0x0UL) /*!< Min enumerator value of MATCH field.                                */
  #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Max (0x1UL) /*!< Max enumerator value of MATCH field.                                */
  #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define UARTE_EVENTS_DMA_RX_MATCH_MATCH_Generated (0x1UL) /*!< Event generated                                               */



/* =============================================== Struct UARTE_EVENTS_DMA_TX ================================================ */
/**
  * @brief TX [UARTE_EVENTS_DMA_TX] Peripheral events.
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Generated after all MAXCNT bytes have been transferred*/
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Generated when EasyDMA has buffered the .PTR and
                                                                         .MAXCNT registers for the channel, allowing them to be
                                                                         written to prepare for the next sequence.*/
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) An error occured during the bus transfer.             */
} NRF_UARTE_EVENTS_DMA_TX_Type;                      /*!< Size = 12 (0x00C)                                                    */

/* UARTE_EVENTS_DMA_TX_END: Generated after all MAXCNT bytes have been transferred */
  #define UARTE_EVENTS_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                  */

/* END @Bit 0 : Generated after all MAXCNT bytes have been transferred */
  #define UARTE_EVENTS_DMA_TX_END_END_Pos (0UL)      /*!< Position of END field.                                               */
  #define UARTE_EVENTS_DMA_TX_END_END_Msk (0x1UL << UARTE_EVENTS_DMA_TX_END_END_Pos) /*!< Bit mask of END field.               */
  #define UARTE_EVENTS_DMA_TX_END_END_Min (0x0UL)    /*!< Min enumerator value of END field.                                   */
  #define UARTE_EVENTS_DMA_TX_END_END_Max (0x1UL)    /*!< Max enumerator value of END field.                                   */
  #define UARTE_EVENTS_DMA_TX_END_END_NotGenerated (0x0UL) /*!< Event not generated                                            */
  #define UARTE_EVENTS_DMA_TX_END_END_Generated (0x1UL) /*!< Event generated                                                   */


/* UARTE_EVENTS_DMA_TX_READY: Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them
                               to be written to prepare for the next sequence. */

  #define UARTE_EVENTS_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                              */

/* READY @Bit 0 : Generated when EasyDMA has buffered the .PTR and .MAXCNT registers for the channel, allowing them to be
                  written to prepare for the next sequence. */

  #define UARTE_EVENTS_DMA_TX_READY_READY_Pos (0UL)  /*!< Position of READY field.                                             */
  #define UARTE_EVENTS_DMA_TX_READY_READY_Msk (0x1UL << UARTE_EVENTS_DMA_TX_READY_READY_Pos) /*!< Bit mask of READY field.     */
  #define UARTE_EVENTS_DMA_TX_READY_READY_Min (0x0UL) /*!< Min enumerator value of READY field.                                */
  #define UARTE_EVENTS_DMA_TX_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                                */
  #define UARTE_EVENTS_DMA_TX_READY_READY_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define UARTE_EVENTS_DMA_TX_READY_READY_Generated (0x1UL) /*!< Event generated                                               */


/* UARTE_EVENTS_DMA_TX_BUSERROR: An error occured during the bus transfer. */
  #define UARTE_EVENTS_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                        */

/* BUSERROR @Bit 0 : An error occured during the bus transfer. */
  #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                     */
  #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Msk (0x1UL << UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Pos) /*!< Bit mask of
                                                                            BUSERROR field.*/
  #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                       */
  #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Max (0x1UL) /*!< Max enumerator value of BUSERROR field.                       */
  #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define UARTE_EVENTS_DMA_TX_BUSERROR_BUSERROR_Generated (0x1UL) /*!< Event generated                                         */



/* ================================================= Struct UARTE_EVENTS_DMA ================================================= */
/**
  * @brief EVENTS_DMA [UARTE_EVENTS_DMA] Peripheral events.
  */
typedef struct {
  __IOM NRF_UARTE_EVENTS_DMA_RX_Type RX;             /*!< (@ 0x00000000) Peripheral events.                                    */
  __IOM NRF_UARTE_EVENTS_DMA_TX_Type TX;             /*!< (@ 0x0000001C) Peripheral events.                                    */
} NRF_UARTE_EVENTS_DMA_Type;                         /*!< Size = 40 (0x028)                                                    */


/* =============================================== Struct UARTE_PUBLISH_DMA_RX =============================================== */
/**
  * @brief RX [UARTE_PUBLISH_DMA_RX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
  __IOM uint32_t  MATCH[4];                          /*!< (@ 0x0000000C) Publish configuration for event MATCH[n]              */
} NRF_UARTE_PUBLISH_DMA_RX_Type;                     /*!< Size = 28 (0x01C)                                                    */

/* UARTE_PUBLISH_DMA_RX_END: Publish configuration for event END */
  #define UARTE_PUBLISH_DMA_RX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define UARTE_PUBLISH_DMA_RX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_DMA_RX_END_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_DMA_RX_END_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_END_EN_Pos) /*!< Bit mask of EN field.                */
  #define UARTE_PUBLISH_DMA_RX_END_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_RX_END_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_RX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define UARTE_PUBLISH_DMA_RX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* UARTE_PUBLISH_DMA_RX_READY: Publish configuration for event READY */
  #define UARTE_PUBLISH_DMA_RX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define UARTE_PUBLISH_DMA_RX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_DMA_RX_READY_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_DMA_RX_READY_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_READY_EN_Pos) /*!< Bit mask of EN field.            */
  #define UARTE_PUBLISH_DMA_RX_READY_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_RX_READY_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_RX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
  #define UARTE_PUBLISH_DMA_RX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */


/* UARTE_PUBLISH_DMA_RX_BUSERROR: Publish configuration for event BUSERROR */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                          */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                      */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                       */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                               */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.      */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                  */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                  */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                            */
  #define UARTE_PUBLISH_DMA_RX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                              */


/* UARTE_PUBLISH_DMA_RX_MATCH: Publish configuration for event MATCH[n] */
  #define UARTE_PUBLISH_DMA_RX_MATCH_MaxCount (4UL)  /*!< Max size of MATCH[4] array.                                          */
  #define UARTE_PUBLISH_DMA_RX_MATCH_MaxIndex (3UL)  /*!< Max index of MATCH[4] array.                                         */
  #define UARTE_PUBLISH_DMA_RX_MATCH_MinIndex (0UL)  /*!< Min index of MATCH[4] array.                                         */
  #define UARTE_PUBLISH_DMA_RX_MATCH_ResetValue (0x00000000UL) /*!< Reset value of MATCH[4] register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event MATCH[n] will publish to */
  #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define UARTE_PUBLISH_DMA_RX_MATCH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_RX_MATCH_EN_Pos) /*!< Bit mask of EN field.            */
  #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
  #define UARTE_PUBLISH_DMA_RX_MATCH_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */



/* =============================================== Struct UARTE_PUBLISH_DMA_TX =============================================== */
/**
  * @brief TX [UARTE_PUBLISH_DMA_TX] Publish configuration for events
  */
typedef struct {
  __IOM uint32_t  END;                               /*!< (@ 0x00000000) Publish configuration for event END                   */
  __IOM uint32_t  READY;                             /*!< (@ 0x00000004) Publish configuration for event READY                 */
  __IOM uint32_t  BUSERROR;                          /*!< (@ 0x00000008) Publish configuration for event BUSERROR              */
} NRF_UARTE_PUBLISH_DMA_TX_Type;                     /*!< Size = 12 (0x00C)                                                    */

/* UARTE_PUBLISH_DMA_TX_END: Publish configuration for event END */
  #define UARTE_PUBLISH_DMA_TX_END_ResetValue (0x00000000UL) /*!< Reset value of END register.                                 */

/* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
  #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
  #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                           */
  #define UARTE_PUBLISH_DMA_TX_END_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_DMA_TX_END_EN_Pos (31UL)     /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_DMA_TX_END_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_END_EN_Pos) /*!< Bit mask of EN field.                */
  #define UARTE_PUBLISH_DMA_TX_END_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_TX_END_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_TX_END_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
  #define UARTE_PUBLISH_DMA_TX_END_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */


/* UARTE_PUBLISH_DMA_TX_READY: Publish configuration for event READY */
  #define UARTE_PUBLISH_DMA_TX_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                             */

/* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
  #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define UARTE_PUBLISH_DMA_TX_READY_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_DMA_TX_READY_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_DMA_TX_READY_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_READY_EN_Pos) /*!< Bit mask of EN field.            */
  #define UARTE_PUBLISH_DMA_TX_READY_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_TX_READY_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_DMA_TX_READY_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
  #define UARTE_PUBLISH_DMA_TX_READY_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */


/* UARTE_PUBLISH_DMA_TX_BUSERROR: Publish configuration for event BUSERROR */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_ResetValue (0x00000000UL) /*!< Reset value of BUSERROR register.                       */

/* CHIDX @Bits 0..7 : DPPI channel that event BUSERROR will publish to */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                          */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
                                                                            field.*/
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                      */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                       */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                               */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Pos) /*!< Bit mask of EN field.      */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                  */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                  */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                            */
  #define UARTE_PUBLISH_DMA_TX_BUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                              */



/* ================================================ Struct UARTE_PUBLISH_DMA ================================================= */
/**
  * @brief PUBLISH_DMA [UARTE_PUBLISH_DMA] Publish configuration for events
  */
typedef struct {
  __IOM NRF_UARTE_PUBLISH_DMA_RX_Type RX;            /*!< (@ 0x00000000) Publish configuration for events                      */
  __IOM NRF_UARTE_PUBLISH_DMA_TX_Type TX;            /*!< (@ 0x0000001C) Publish configuration for events                      */
} NRF_UARTE_PUBLISH_DMA_Type;                        /*!< Size = 40 (0x028)                                                    */


/* ==================================================== Struct UARTE_PSEL ==================================================== */
/**
  * @brief PSEL [UARTE_PSEL] (unspecified)
  */
typedef struct {
  __IOM uint32_t  TXD;                               /*!< (@ 0x00000000) Pin select for TXD signal                             */
  __IOM uint32_t  CTS;                               /*!< (@ 0x00000004) Pin select for CTS signal                             */
  __IOM uint32_t  RXD;                               /*!< (@ 0x00000008) Pin select for RXD signal                             */
  __IOM uint32_t  RTS;                               /*!< (@ 0x0000000C) Pin select for RTS signal                             */
} NRF_UARTE_PSEL_Type;                               /*!< Size = 16 (0x010)                                                    */

/* UARTE_PSEL_TXD: Pin select for TXD signal */
  #define UARTE_PSEL_TXD_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of TXD register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define UARTE_PSEL_TXD_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define UARTE_PSEL_TXD_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define UARTE_PSEL_TXD_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define UARTE_PSEL_TXD_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define UARTE_PSEL_TXD_PORT_Msk (0x7UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define UARTE_PSEL_TXD_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define UARTE_PSEL_TXD_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define UARTE_PSEL_TXD_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define UARTE_PSEL_TXD_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_TXD_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */


/* UARTE_PSEL_CTS: Pin select for CTS signal */
  #define UARTE_PSEL_CTS_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of CTS register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define UARTE_PSEL_CTS_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define UARTE_PSEL_CTS_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define UARTE_PSEL_CTS_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define UARTE_PSEL_CTS_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define UARTE_PSEL_CTS_PORT_Msk (0x7UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define UARTE_PSEL_CTS_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define UARTE_PSEL_CTS_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define UARTE_PSEL_CTS_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define UARTE_PSEL_CTS_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_CTS_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */


/* UARTE_PSEL_RXD: Pin select for RXD signal */
  #define UARTE_PSEL_RXD_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of RXD register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define UARTE_PSEL_RXD_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define UARTE_PSEL_RXD_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define UARTE_PSEL_RXD_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define UARTE_PSEL_RXD_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define UARTE_PSEL_RXD_PORT_Msk (0x7UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define UARTE_PSEL_RXD_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define UARTE_PSEL_RXD_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define UARTE_PSEL_RXD_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define UARTE_PSEL_RXD_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_RXD_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */


/* UARTE_PSEL_RTS: Pin select for RTS signal */
  #define UARTE_PSEL_RTS_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of RTS register.                                         */

/* PIN @Bits 0..4 : Pin number */
  #define UARTE_PSEL_RTS_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
  #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field.                                */
  #define UARTE_PSEL_RTS_PIN_Min (0x00UL)            /*!< Min value of PIN field.                                              */
  #define UARTE_PSEL_RTS_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */

/* PORT @Bits 5..7 : Port number */
  #define UARTE_PSEL_RTS_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
  #define UARTE_PSEL_RTS_PORT_Msk (0x7UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field.                              */
  #define UARTE_PSEL_RTS_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
  #define UARTE_PSEL_RTS_PORT_Max (0x7UL)            /*!< Max size of PORT field.                                              */

/* CONNECT @Bit 31 : Connection */
  #define UARTE_PSEL_RTS_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
  #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
  #define UARTE_PSEL_RTS_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_RTS_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
  #define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
  #define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */



/* ================================================ Struct UARTE_DMA_RX_MATCH ================================================ */
/**
  * @brief MATCH [UARTE_DMA_RX_MATCH] Registers to control the behavior of the pattern matcher engine
  */
typedef struct {
  __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Configure individual match events                     */
  __IOM uint32_t  CANDIDATE[4];                      /*!< (@ 0x00000004) The data to look for - any match will trigger the
                                                                         MATCH[n] event, if enabled.*/
} NRF_UARTE_DMA_RX_MATCH_Type;                       /*!< Size = 20 (0x014)                                                    */

/* UARTE_DMA_RX_MATCH_CONFIG: Configure individual match events */
  #define UARTE_DMA_RX_MATCH_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                             */

/* ENABLE0 @Bit 0 : Enable match filter 0 */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Pos (0UL) /*!< Position of ENABLE0 field.                                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) /*!< Bit mask of ENABLE0
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled (0x0UL) /*!< Match filter disabled                                        */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled (0x1UL) /*!< Match filter enabled                                          */

/* ENABLE1 @Bit 1 : Enable match filter 1 */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Pos (1UL) /*!< Position of ENABLE1 field.                                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) /*!< Bit mask of ENABLE1
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled (0x0UL) /*!< Match filter disabled                                        */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled (0x1UL) /*!< Match filter enabled                                          */

/* ENABLE2 @Bit 2 : Enable match filter 2 */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Pos (2UL) /*!< Position of ENABLE2 field.                                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) /*!< Bit mask of ENABLE2
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled (0x0UL) /*!< Match filter disabled                                        */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled (0x1UL) /*!< Match filter enabled                                          */

/* ENABLE3 @Bit 3 : Enable match filter 3 */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Pos (3UL) /*!< Position of ENABLE3 field.                                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) /*!< Bit mask of ENABLE3
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                            */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled (0x0UL) /*!< Match filter disabled                                        */
  #define UARTE_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled (0x1UL) /*!< Match filter enabled                                          */

/* ONESHOT0 @Bit 16 : Configure match filter 0 as one-shot or continous */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos (16UL) /*!< Position of ONESHOT0 field.                                       */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) /*!< Bit mask of ONESHOT0
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Min (0x0UL) /*!< Min enumerator value of ONESHOT0 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Max (0x1UL) /*!< Max enumerator value of ONESHOT0 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task         */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received  */

/* ONESHOT1 @Bit 17 : Configure match filter 1 as one-shot or continous */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos (17UL) /*!< Position of ONESHOT1 field.                                       */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) /*!< Bit mask of ONESHOT1
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Min (0x0UL) /*!< Min enumerator value of ONESHOT1 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Max (0x1UL) /*!< Max enumerator value of ONESHOT1 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task         */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received  */

/* ONESHOT2 @Bit 18 : Configure match filter 2 as one-shot or continous */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos (18UL) /*!< Position of ONESHOT2 field.                                       */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) /*!< Bit mask of ONESHOT2
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Min (0x0UL) /*!< Min enumerator value of ONESHOT2 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Max (0x1UL) /*!< Max enumerator value of ONESHOT2 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task         */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received  */

/* ONESHOT3 @Bit 19 : Configure match filter 3 as one-shot or continous */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos (19UL) /*!< Position of ONESHOT3 field.                                       */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk (0x1UL << UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) /*!< Bit mask of ONESHOT3
                                                                            field.*/
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Min (0x0UL) /*!< Min enumerator value of ONESHOT3 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Max (0x1UL) /*!< Max enumerator value of ONESHOT3 field.                          */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Continuous (0x0UL) /*!< Match filter stays enabled until disabled by task         */
  #define UARTE_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot (0x1UL) /*!< Match filter stays enabled until next data word is received  */


/* UARTE_DMA_RX_MATCH_CANDIDATE: The data to look for - any match will trigger the MATCH[n] event, if enabled. */
  #define UARTE_DMA_RX_MATCH_CANDIDATE_MaxCount (4UL) /*!< Max size of CANDIDATE[4] array.                                     */
  #define UARTE_DMA_RX_MATCH_CANDIDATE_MaxIndex (3UL) /*!< Max index of CANDIDATE[4] array.                                    */
  #define UARTE_DMA_RX_MATCH_CANDIDATE_MinIndex (0UL) /*!< Min index of CANDIDATE[4] array.                                    */
  #define UARTE_DMA_RX_MATCH_CANDIDATE_ResetValue (0x00000000UL) /*!< Reset value of CANDIDATE[4] register.                    */

/* DATA @Bits 0..7 : Data to look for */
  #define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Pos (0UL) /*!< Position of DATA field.                                             */
  #define UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Msk (0xFFUL << UARTE_DMA_RX_MATCH_CANDIDATE_DATA_Pos) /*!< Bit mask of DATA field. */



/* =================================================== Struct UARTE_DMA_RX =================================================== */
/**
  * @brief RX [UARTE_DMA_RX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
  __IOM NRF_UARTE_DMA_RX_MATCH_Type MATCH;           /*!< (@ 0x00000024) Registers to control the behavior of the pattern
                                                                         matcher engine*/
} NRF_UARTE_DMA_RX_Type;                             /*!< Size = 56 (0x038)                                                    */

/* UARTE_DMA_RX_PTR: RAM buffer start address */
  #define UARTE_DMA_RX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define UARTE_DMA_RX_PTR_PTR_Pos (0UL)             /*!< Position of PTR field.                                               */
  #define UARTE_DMA_RX_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                      */


/* UARTE_DMA_RX_MAXCNT: Maximum number of bytes in channel buffer */
  #define UARTE_DMA_RX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                   */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define UARTE_DMA_RX_MAXCNT_MAXCNT_Pos (0UL)       /*!< Position of MAXCNT field.                                            */
  #define UARTE_DMA_RX_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_DMA_RX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.           */
  #define UARTE_DMA_RX_MAXCNT_MAXCNT_Min (0x0001UL)  /*!< Min value of MAXCNT field.                                           */
  #define UARTE_DMA_RX_MAXCNT_MAXCNT_Max (0xFFFFUL)  /*!< Max size of MAXCNT field.                                            */


/* UARTE_DMA_RX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after
                         each MATCH event. */

  #define UARTE_DMA_RX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                   */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define UARTE_DMA_RX_AMOUNT_AMOUNT_Pos (0UL)       /*!< Position of AMOUNT field.                                            */
  #define UARTE_DMA_RX_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_DMA_RX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.           */
  #define UARTE_DMA_RX_AMOUNT_AMOUNT_Min (0x0001UL)  /*!< Min value of AMOUNT field.                                           */
  #define UARTE_DMA_RX_AMOUNT_AMOUNT_Max (0xFFFFUL)  /*!< Max size of AMOUNT field.                                            */


/* UARTE_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define UARTE_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.         */

/* ENABLE @Bit 0 : (unspecified) */
  #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                     */
  #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                       */
  #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                       */
  #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                */
  #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                  */


/* UARTE_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define UARTE_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                 */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                       */
  #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* =================================================== Struct UARTE_DMA_TX =================================================== */
/**
  * @brief TX [UARTE_DMA_TX] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PTR;                               /*!< (@ 0x00000004) RAM buffer start address                              */
  __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000008) Maximum number of bytes in channel buffer             */
  __IM  uint32_t  AMOUNT;                            /*!< (@ 0x0000000C) Number of bytes transferred in the last transaction,
                                                                         updated after the END event. Also updated after each
                                                                         MATCH event.*/
  __IM  uint32_t  RESERVED1[3];
  __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x0000001C) Terminate the transaction if a BUSERROR event is
                                                                         detected.*/
  __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000020) Address of transaction that generated the last BUSERROR
                                                                         event.*/
} NRF_UARTE_DMA_TX_Type;                             /*!< Size = 36 (0x024)                                                    */

/* UARTE_DMA_TX_PTR: RAM buffer start address */
  #define UARTE_DMA_TX_PTR_ResetValue (0x20000000UL) /*!< Reset value of PTR register.                                         */

/* PTR @Bits 0..31 : RAM buffer start address for this EasyDMA channel. This address is a word aligned Data RAM address. */
  #define UARTE_DMA_TX_PTR_PTR_Pos (0UL)             /*!< Position of PTR field.                                               */
  #define UARTE_DMA_TX_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_DMA_TX_PTR_PTR_Pos) /*!< Bit mask of PTR field.                      */


/* UARTE_DMA_TX_MAXCNT: Maximum number of bytes in channel buffer */
  #define UARTE_DMA_TX_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                   */

/* MAXCNT @Bits 0..15 : Maximum number of bytes in channel buffer */
  #define UARTE_DMA_TX_MAXCNT_MAXCNT_Pos (0UL)       /*!< Position of MAXCNT field.                                            */
  #define UARTE_DMA_TX_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_DMA_TX_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.           */
  #define UARTE_DMA_TX_MAXCNT_MAXCNT_Min (0x0001UL)  /*!< Min value of MAXCNT field.                                           */
  #define UARTE_DMA_TX_MAXCNT_MAXCNT_Max (0xFFFFUL)  /*!< Max size of MAXCNT field.                                            */


/* UARTE_DMA_TX_AMOUNT: Number of bytes transferred in the last transaction, updated after the END event. Also updated after
                         each MATCH event. */

  #define UARTE_DMA_TX_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                   */

/* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
  #define UARTE_DMA_TX_AMOUNT_AMOUNT_Pos (0UL)       /*!< Position of AMOUNT field.                                            */
  #define UARTE_DMA_TX_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_DMA_TX_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.           */
  #define UARTE_DMA_TX_AMOUNT_AMOUNT_Min (0x0001UL)  /*!< Min value of AMOUNT field.                                           */
  #define UARTE_DMA_TX_AMOUNT_AMOUNT_Max (0xFFFFUL)  /*!< Max size of AMOUNT field.                                            */


/* UARTE_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
  #define UARTE_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.         */

/* ENABLE @Bit 0 : (unspecified) */
  #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                     */
  #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
                                                                            ENABLE field.*/
  #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                       */
  #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                       */
  #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                */
  #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                  */


/* UARTE_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
  #define UARTE_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                 */

/* ADDRESS @Bits 0..31 : (unspecified) */
  #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                       */
  #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
                                                                            ADDRESS field.*/



/* ==================================================== Struct UARTE_DMA ===================================================== */
/**
  * @brief DMA [UARTE_DMA] (unspecified)
  */
typedef struct {
  __IOM NRF_UARTE_DMA_RX_Type RX;                    /*!< (@ 0x00000000) (unspecified)                                         */
  __IOM NRF_UARTE_DMA_TX_Type TX;                    /*!< (@ 0x00000038) (unspecified)                                         */
} NRF_UARTE_DMA_Type;                                /*!< Size = 92 (0x05C)                                                    */

/* ====================================================== Struct UARTE ======================================================= */
/**
  * @brief UART with EasyDMA
  */
  typedef struct {                                   /*!< UARTE Structure                                                      */
    __IM uint32_t RESERVED[7];
    __OM uint32_t TASKS_FLUSHRX;                     /*!< (@ 0x0000001C) Flush RX FIFO into RX buffer                          */
    __IM uint32_t RESERVED1[2];
    __OM NRF_UARTE_TASKS_DMA_Type TASKS_DMA;         /*!< (@ 0x00000028) Peripheral tasks.                                     */
    __IM uint32_t RESERVED2[17];
    __IOM uint32_t SUBSCRIBE_FLUSHRX;                /*!< (@ 0x0000009C) Subscribe configuration for task FLUSHRX              */
    __IM uint32_t RESERVED3[2];
    __IOM NRF_UARTE_SUBSCRIBE_DMA_Type SUBSCRIBE_DMA; /*!< (@ 0x000000A8) Subscribe configuration for tasks                    */
    __IM uint32_t RESERVED4[10];
    __IOM uint32_t EVENTS_CTS;                       /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send.            */
    __IOM uint32_t EVENTS_NCTS;                      /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send.     */
    __IM uint32_t RESERVED5;
    __IOM uint32_t EVENTS_TXDRDY;                    /*!< (@ 0x0000010C) Data sent from TXD                                    */
    __IOM uint32_t EVENTS_RXDRDY;                    /*!< (@ 0x00000110) Data received in RXD (but potentially not yet
                                                                         transferred to Data RAM)*/
    __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000114) Error detected                                        */
    __IM uint32_t RESERVED6[3];
    __IOM uint32_t EVENTS_RXTO;                      /*!< (@ 0x00000124) Receiver timeout                                      */
    __IM uint32_t RESERVED7[2];
    __IOM uint32_t EVENTS_TXSTOPPED;                 /*!< (@ 0x00000130) Transmitter stopped                                   */
    __IM uint32_t RESERVED8[6];
    __IOM NRF_UARTE_EVENTS_DMA_Type EVENTS_DMA;      /*!< (@ 0x0000014C) Peripheral events.                                    */
    __IOM uint32_t EVENTS_FRAMETIMEOUT;              /*!< (@ 0x00000174) Timed out due to bus being idle while receiving data. */
    __IM uint32_t RESERVED9[2];
    __IOM uint32_t PUBLISH_CTS;                      /*!< (@ 0x00000180) Publish configuration for event CTS                   */
    __IOM uint32_t PUBLISH_NCTS;                     /*!< (@ 0x00000184) Publish configuration for event NCTS                  */
    __IM uint32_t RESERVED10;
    __IOM uint32_t PUBLISH_TXDRDY;                   /*!< (@ 0x0000018C) Publish configuration for event TXDRDY                */
    __IOM uint32_t PUBLISH_RXDRDY;                   /*!< (@ 0x00000190) Publish configuration for event RXDRDY                */
    __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x00000194) Publish configuration for event ERROR                 */
    __IM uint32_t RESERVED11[3];
    __IOM uint32_t PUBLISH_RXTO;                     /*!< (@ 0x000001A4) Publish configuration for event RXTO                  */
    __IM uint32_t RESERVED12[2];
    __IOM uint32_t PUBLISH_TXSTOPPED;                /*!< (@ 0x000001B0) Publish configuration for event TXSTOPPED             */
    __IM uint32_t RESERVED13[6];
    __IOM NRF_UARTE_PUBLISH_DMA_Type PUBLISH_DMA;    /*!< (@ 0x000001CC) Publish configuration for events                      */
    __IOM uint32_t PUBLISH_FRAMETIMEOUT;             /*!< (@ 0x000001F4) Publish configuration for event FRAMETIMEOUT          */
    __IM uint32_t RESERVED14[2];
    __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
    __IM uint32_t RESERVED15[63];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED16[93];
    __IOM uint32_t ERRORSRC;                         /*!< (@ 0x00000480) Error source                                          */
    __IM uint32_t RESERVED17[31];
    __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable UART                                           */
    __IM uint32_t RESERVED18[8];
    __IOM uint32_t BAUDRATE;                         /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
                                                                         selected.*/
    __IM uint32_t RESERVED19[17];
    __IOM uint32_t CONFIG;                           /*!< (@ 0x0000056C) Configuration of parity, hardware flow control,
                                                                         framesize, and packet timeout.*/
    __IM uint32_t RESERVED20;
    __IOM uint32_t ADDRESS;                          /*!< (@ 0x00000574) Set the address of the UARTE for RX when used in 9 bit
                                                                         data frame mode.*/
    __IOM uint32_t FRAMETIMEOUT;                     /*!< (@ 0x00000578) Set the number of UARTE bits to count before triggering
                                                                         packet timeout.*/
    __IM uint32_t RESERVED21[34];
    __IOM NRF_UARTE_PSEL_Type PSEL;                  /*!< (@ 0x00000604) (unspecified)                                         */
    __IM uint32_t RESERVED22[59];
    __IOM NRF_UARTE_DMA_Type DMA;                    /*!< (@ 0x00000700) (unspecified)                                         */
  } NRF_UARTE_Type;                                  /*!< Size = 1884 (0x75C)                                                  */

/* UARTE_TASKS_FLUSHRX: Flush RX FIFO into RX buffer */
  #define UARTE_TASKS_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHRX register.                            */

/* TASKS_FLUSHRX @Bit 0 : Flush RX FIFO into RX buffer */
  #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field.                                    */
  #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX
                                                                            field.*/
  #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHRX field.                      */
  #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHRX field.                      */
  #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task                                                  */


/* UARTE_SUBSCRIBE_FLUSHRX: Subscribe configuration for task FLUSHRX */
  #define UARTE_SUBSCRIBE_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_FLUSHRX register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that task FLUSHRX will subscribe to */
  #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field.                  */
  #define UARTE_SUBSCRIBE_FLUSHRX_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define UARTE_SUBSCRIBE_FLUSHRX_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
  #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */


/* UARTE_EVENTS_CTS: CTS is activated (set low). Clear To Send. */
  #define UARTE_EVENTS_CTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTS register.                                  */

/* EVENTS_CTS @Bit 0 : CTS is activated (set low). Clear To Send. */
  #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL)      /*!< Position of EVENTS_CTS field.                                        */
  #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field.        */
  #define UARTE_EVENTS_CTS_EVENTS_CTS_Min (0x0UL)    /*!< Min enumerator value of EVENTS_CTS field.                            */
  #define UARTE_EVENTS_CTS_EVENTS_CTS_Max (0x1UL)    /*!< Max enumerator value of EVENTS_CTS field.                            */
  #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated                                            */
  #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated                                                   */


/* UARTE_EVENTS_NCTS: CTS is deactivated (set high). Not Clear To Send. */
  #define UARTE_EVENTS_NCTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NCTS register.                                */

/* EVENTS_NCTS @Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
  #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL)    /*!< Position of EVENTS_NCTS field.                                       */
  #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field.   */
  #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Min (0x0UL)  /*!< Min enumerator value of EVENTS_NCTS field.                           */
  #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Max (0x1UL)  /*!< Max enumerator value of EVENTS_NCTS field.                           */
  #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated                                                 */


/* UARTE_EVENTS_TXDRDY: Data sent from TXD */
  #define UARTE_EVENTS_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDRDY register.                            */

/* EVENTS_TXDRDY @Bit 0 : Data sent from TXD */
  #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field.                                    */
  #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY
                                                                            field.*/
  #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDRDY field.                      */
  #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDRDY field.                      */
  #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated                                             */


/* UARTE_EVENTS_RXDRDY: Data received in RXD (but potentially not yet transferred to Data RAM) */
  #define UARTE_EVENTS_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXDRDY register.                            */

/* EVENTS_RXDRDY @Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
  #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field.                                    */
  #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY
                                                                            field.*/
  #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXDRDY field.                      */
  #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXDRDY field.                      */
  #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated                                             */


/* UARTE_EVENTS_ERROR: Error detected */
  #define UARTE_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                              */

/* EVENTS_ERROR @Bit 0 : Error detected */
  #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)  /*!< Position of EVENTS_ERROR field.                                      */
  #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR
                                                                            field.*/
  #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                         */
  #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                         */
  #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                        */
  #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                               */


/* UARTE_EVENTS_RXTO: Receiver timeout */
  #define UARTE_EVENTS_RXTO_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXTO register.                                */

/* EVENTS_RXTO @Bit 0 : Receiver timeout */
  #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL)    /*!< Position of EVENTS_RXTO field.                                       */
  #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field.   */
  #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Min (0x0UL)  /*!< Min enumerator value of EVENTS_RXTO field.                           */
  #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Max (0x1UL)  /*!< Max enumerator value of EVENTS_RXTO field.                           */
  #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated                                          */
  #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated                                                 */


/* UARTE_EVENTS_TXSTOPPED: Transmitter stopped */
  #define UARTE_EVENTS_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXSTOPPED register.                      */

/* EVENTS_TXSTOPPED @Bit 0 : Transmitter stopped */
  #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field.                           */
  #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of
                                                                            EVENTS_TXSTOPPED field.*/
  #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXSTOPPED field.             */
  #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXSTOPPED field.             */
  #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated                                */
  #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated                                       */


/* UARTE_EVENTS_FRAMETIMEOUT: Timed out due to bus being idle while receiving data. */
  #define UARTE_EVENTS_FRAMETIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMETIMEOUT register.                */

/* EVENTS_FRAMETIMEOUT @Bit 0 : Timed out due to bus being idle while receiving data. */
  #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Pos (0UL) /*!< Position of EVENTS_FRAMETIMEOUT field.                  */
  #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Msk (0x1UL << UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Pos) /*!<
                                                                            Bit mask of EVENTS_FRAMETIMEOUT field.*/
  #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMETIMEOUT field.    */
  #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMETIMEOUT field.    */
  #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_NotGenerated (0x0UL) /*!< Event not generated                          */
  #define UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Generated (0x1UL) /*!< Event generated                                 */


/* UARTE_PUBLISH_CTS: Publish configuration for event CTS */
  #define UARTE_PUBLISH_CTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTS register.                                */

/* CHIDX @Bits 0..7 : DPPI channel that event CTS will publish to */
  #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
  #define UARTE_PUBLISH_CTS_CHIDX_Min (0x00UL)       /*!< Min value of CHIDX field.                                            */
  #define UARTE_PUBLISH_CTS_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_CTS_EN_Pos (31UL)            /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field.                              */
  #define UARTE_PUBLISH_CTS_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_CTS_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
  #define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */


/* UARTE_PUBLISH_NCTS: Publish configuration for event NCTS */
  #define UARTE_PUBLISH_NCTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NCTS register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event NCTS will publish to */
  #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define UARTE_PUBLISH_NCTS_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define UARTE_PUBLISH_NCTS_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_NCTS_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field.                            */
  #define UARTE_PUBLISH_NCTS_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_NCTS_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* UARTE_PUBLISH_TXDRDY: Publish configuration for event TXDRDY */
  #define UARTE_PUBLISH_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXDRDY register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event TXDRDY will publish to */
  #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define UARTE_PUBLISH_TXDRDY_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define UARTE_PUBLISH_TXDRDY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field.                        */
  #define UARTE_PUBLISH_TXDRDY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_TXDRDY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* UARTE_PUBLISH_RXDRDY: Publish configuration for event RXDRDY */
  #define UARTE_PUBLISH_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXDRDY register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event RXDRDY will publish to */
  #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
  #define UARTE_PUBLISH_RXDRDY_CHIDX_Min (0x00UL)    /*!< Min value of CHIDX field.                                            */
  #define UARTE_PUBLISH_RXDRDY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field.                        */
  #define UARTE_PUBLISH_RXDRDY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_RXDRDY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
  #define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */


/* UARTE_PUBLISH_ERROR: Publish configuration for event ERROR */
  #define UARTE_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
  #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define UARTE_PUBLISH_ERROR_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define UARTE_PUBLISH_ERROR_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_ERROR_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                          */
  #define UARTE_PUBLISH_ERROR_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_ERROR_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* UARTE_PUBLISH_RXTO: Publish configuration for event RXTO */
  #define UARTE_PUBLISH_RXTO_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXTO register.                              */

/* CHIDX @Bits 0..7 : DPPI channel that event RXTO will publish to */
  #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define UARTE_PUBLISH_RXTO_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define UARTE_PUBLISH_RXTO_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_RXTO_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field.                            */
  #define UARTE_PUBLISH_RXTO_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_RXTO_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
  #define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */


/* UARTE_PUBLISH_TXSTOPPED: Publish configuration for event TXSTOPPED */
  #define UARTE_PUBLISH_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXSTOPPED register.                    */

/* CHIDX @Bits 0..7 : DPPI channel that event TXSTOPPED will publish to */
  #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
  #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                            */
  #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field.                  */
  #define UARTE_PUBLISH_TXSTOPPED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_TXSTOPPED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
  #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */


/* UARTE_PUBLISH_FRAMETIMEOUT: Publish configuration for event FRAMETIMEOUT */
  #define UARTE_PUBLISH_FRAMETIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMETIMEOUT register.              */

/* CHIDX @Bits 0..7 : DPPI channel that event FRAMETIMEOUT will publish to */
  #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
  #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
  #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field.                                         */
  #define UARTE_PUBLISH_FRAMETIMEOUT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */

/* EN @Bit 31 : (unspecified) */
  #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Pos (31UL)   /*!< Position of EN field.                                                */
  #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Msk (0x1UL << UARTE_PUBLISH_FRAMETIMEOUT_EN_Pos) /*!< Bit mask of EN field.            */
  #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
  #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
  #define UARTE_PUBLISH_FRAMETIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */


/* UARTE_SHORTS: Shortcuts between local events and tasks */
  #define UARTE_SHORTS_ResetValue (0x00000000UL)     /*!< Reset value of SHORTS register.                                      */

/* DMA_RX_END_DMA_RX_START @Bit 5 : Shortcut between event DMA.RX.END and task DMA.RX.START */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Pos (5UL) /*!< Position of DMA_RX_END_DMA_RX_START field.                       */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Msk (0x1UL << UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Pos) /*!< Bit mask of
                                                                            DMA_RX_END_DMA_RX_START field.*/
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Min (0x0UL) /*!< Min enumerator value of DMA_RX_END_DMA_RX_START field.         */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Max (0x1UL) /*!< Max enumerator value of DMA_RX_END_DMA_RX_START field.         */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Disabled (0x0UL) /*!< Disable shortcut                                          */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Enabled (0x1UL) /*!< Enable shortcut                                            */

/* DMA_RX_END_DMA_RX_STOP @Bit 6 : Shortcut between event DMA.RX.END and task DMA.RX.STOP */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Pos (6UL) /*!< Position of DMA_RX_END_DMA_RX_STOP field.                         */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Msk (0x1UL << UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Pos) /*!< Bit mask of
                                                                            DMA_RX_END_DMA_RX_STOP field.*/
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_RX_END_DMA_RX_STOP field.           */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_RX_END_DMA_RX_STOP field.           */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Disabled (0x0UL) /*!< Disable shortcut                                           */
  #define UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Enabled (0x1UL) /*!< Enable shortcut                                             */

/* DMA_TX_END_DMA_TX_STOP @Bit 18 : Shortcut between event DMA.TX.END and task DMA.TX.STOP */
  #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Pos (18UL) /*!< Position of DMA_TX_END_DMA_TX_STOP field.                        */
  #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Msk (0x1UL << UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Pos) /*!< Bit mask of
                                                                            DMA_TX_END_DMA_TX_STOP field.*/
  #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Min (0x0UL) /*!< Min enumerator value of DMA_TX_END_DMA_TX_STOP field.           */
  #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Max (0x1UL) /*!< Max enumerator value of DMA_TX_END_DMA_TX_STOP field.           */
  #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Disabled (0x0UL) /*!< Disable shortcut                                           */
  #define UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Enabled (0x1UL) /*!< Enable shortcut                                             */

/* DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 @Bit 21 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[1] Allows
                                               daisy-chaining match events. */

  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos (21UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.  */
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 @Bit 22 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[2] Allows
                                               daisy-chaining match events. */

  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos (22UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.  */
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 @Bit 23 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[3] Allows
                                               daisy-chaining match events. */

  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos (23UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.  */
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 @Bit 24 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.ENABLEMATCH[0] Allows
                                               daisy-chaining match events. */

  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos (24UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.  */
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Pos) /*!<
                                                                            Bit mask of DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                          DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                                */
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                  */

/* DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 @Bit 25 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos (25UL) /*!< Position of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Pos)
                                                                            /*!< Bit mask of DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Min (0x0UL) /*!< Min enumerator value of
                                                                           DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Max (0x1UL) /*!< Max enumerator value of
                                                                           DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Disabled (0x0UL) /*!< Disable shortcut                               */
  #define UARTE_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Enabled (0x1UL) /*!< Enable shortcut                                 */

/* DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 @Bit 26 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos (26UL) /*!< Position of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Pos)
                                                                            /*!< Bit mask of DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Min (0x0UL) /*!< Min enumerator value of
                                                                           DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Max (0x1UL) /*!< Max enumerator value of
                                                                           DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Disabled (0x0UL) /*!< Disable shortcut                               */
  #define UARTE_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Enabled (0x1UL) /*!< Enable shortcut                                 */

/* DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 @Bit 27 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos (27UL) /*!< Position of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Pos)
                                                                            /*!< Bit mask of DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Min (0x0UL) /*!< Min enumerator value of
                                                                           DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Max (0x1UL) /*!< Max enumerator value of
                                                                           DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Disabled (0x0UL) /*!< Disable shortcut                               */
  #define UARTE_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Enabled (0x1UL) /*!< Enable shortcut                                 */

/* DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 @Bit 28 : Shortcut between event DMA.RX.MATCH[n] and task DMA.RX.DISABLEMATCH[n] */
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos (28UL) /*!< Position of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk (0x1UL << UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Pos)
                                                                            /*!< Bit mask of DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3
                                                                            field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Min (0x0UL) /*!< Min enumerator value of
                                                                           DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Max (0x1UL) /*!< Max enumerator value of
                                                                           DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3 field.*/
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Disabled (0x0UL) /*!< Disable shortcut                               */
  #define UARTE_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Enabled (0x1UL) /*!< Enable shortcut                                 */

/* FRAMETIMEOUT_DMA_RX_STOP @Bit 29 : Shortcut between event FRAMETIMEOUT and task DMA.RX.STOP */
  #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Pos (29UL) /*!< Position of FRAMETIMEOUT_DMA_RX_STOP field.                    */
  #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Msk (0x1UL << UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Pos) /*!< Bit mask of
                                                                            FRAMETIMEOUT_DMA_RX_STOP field.*/
  #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Min (0x0UL) /*!< Min enumerator value of FRAMETIMEOUT_DMA_RX_STOP field.       */
  #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Max (0x1UL) /*!< Max enumerator value of FRAMETIMEOUT_DMA_RX_STOP field.       */
  #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Disabled (0x0UL) /*!< Disable shortcut                                         */
  #define UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Enabled (0x1UL) /*!< Enable shortcut                                           */


/* UARTE_INTEN: Enable or disable interrupt */
  #define UARTE_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */

/* CTS @Bit 0 : Enable or disable interrupt for event CTS */
  #define UARTE_INTEN_CTS_Pos (0UL)                  /*!< Position of CTS field.                                               */
  #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field.                                       */
  #define UARTE_INTEN_CTS_Min (0x0UL)                /*!< Min enumerator value of CTS field.                                   */
  #define UARTE_INTEN_CTS_Max (0x1UL)                /*!< Max enumerator value of CTS field.                                   */
  #define UARTE_INTEN_CTS_Disabled (0x0UL)           /*!< Disable                                                              */
  #define UARTE_INTEN_CTS_Enabled (0x1UL)            /*!< Enable                                                               */

/* NCTS @Bit 1 : Enable or disable interrupt for event NCTS */
  #define UARTE_INTEN_NCTS_Pos (1UL)                 /*!< Position of NCTS field.                                              */
  #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field.                                    */
  #define UARTE_INTEN_NCTS_Min (0x0UL)               /*!< Min enumerator value of NCTS field.                                  */
  #define UARTE_INTEN_NCTS_Max (0x1UL)               /*!< Max enumerator value of NCTS field.                                  */
  #define UARTE_INTEN_NCTS_Disabled (0x0UL)          /*!< Disable                                                              */
  #define UARTE_INTEN_NCTS_Enabled (0x1UL)           /*!< Enable                                                               */

/* TXDRDY @Bit 3 : Enable or disable interrupt for event TXDRDY */
  #define UARTE_INTEN_TXDRDY_Pos (3UL)               /*!< Position of TXDRDY field.                                            */
  #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field.                              */
  #define UARTE_INTEN_TXDRDY_Min (0x0UL)             /*!< Min enumerator value of TXDRDY field.                                */
  #define UARTE_INTEN_TXDRDY_Max (0x1UL)             /*!< Max enumerator value of TXDRDY field.                                */
  #define UARTE_INTEN_TXDRDY_Disabled (0x0UL)        /*!< Disable                                                              */
  #define UARTE_INTEN_TXDRDY_Enabled (0x1UL)         /*!< Enable                                                               */

/* RXDRDY @Bit 4 : Enable or disable interrupt for event RXDRDY */
  #define UARTE_INTEN_RXDRDY_Pos (4UL)               /*!< Position of RXDRDY field.                                            */
  #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field.                              */
  #define UARTE_INTEN_RXDRDY_Min (0x0UL)             /*!< Min enumerator value of RXDRDY field.                                */
  #define UARTE_INTEN_RXDRDY_Max (0x1UL)             /*!< Max enumerator value of RXDRDY field.                                */
  #define UARTE_INTEN_RXDRDY_Disabled (0x0UL)        /*!< Disable                                                              */
  #define UARTE_INTEN_RXDRDY_Enabled (0x1UL)         /*!< Enable                                                               */

/* ERROR @Bit 5 : Enable or disable interrupt for event ERROR */
  #define UARTE_INTEN_ERROR_Pos (5UL)                /*!< Position of ERROR field.                                             */
  #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                 */
  #define UARTE_INTEN_ERROR_Min (0x0UL)              /*!< Min enumerator value of ERROR field.                                 */
  #define UARTE_INTEN_ERROR_Max (0x1UL)              /*!< Max enumerator value of ERROR field.                                 */
  #define UARTE_INTEN_ERROR_Disabled (0x0UL)         /*!< Disable                                                              */
  #define UARTE_INTEN_ERROR_Enabled (0x1UL)          /*!< Enable                                                               */

/* RXTO @Bit 9 : Enable or disable interrupt for event RXTO */
  #define UARTE_INTEN_RXTO_Pos (9UL)                 /*!< Position of RXTO field.                                              */
  #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field.                                    */
  #define UARTE_INTEN_RXTO_Min (0x0UL)               /*!< Min enumerator value of RXTO field.                                  */
  #define UARTE_INTEN_RXTO_Max (0x1UL)               /*!< Max enumerator value of RXTO field.                                  */
  #define UARTE_INTEN_RXTO_Disabled (0x0UL)          /*!< Disable                                                              */
  #define UARTE_INTEN_RXTO_Enabled (0x1UL)           /*!< Enable                                                               */

/* TXSTOPPED @Bit 12 : Enable or disable interrupt for event TXSTOPPED */
  #define UARTE_INTEN_TXSTOPPED_Pos (12UL)           /*!< Position of TXSTOPPED field.                                         */
  #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field.                     */
  #define UARTE_INTEN_TXSTOPPED_Min (0x0UL)          /*!< Min enumerator value of TXSTOPPED field.                             */
  #define UARTE_INTEN_TXSTOPPED_Max (0x1UL)          /*!< Max enumerator value of TXSTOPPED field.                             */
  #define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL)     /*!< Disable                                                              */
  #define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL)      /*!< Enable                                                               */

/* DMARXEND @Bit 19 : Enable or disable interrupt for event DMARXEND */
  #define UARTE_INTEN_DMARXEND_Pos (19UL)            /*!< Position of DMARXEND field.                                          */
  #define UARTE_INTEN_DMARXEND_Msk (0x1UL << UARTE_INTEN_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                        */
  #define UARTE_INTEN_DMARXEND_Min (0x0UL)           /*!< Min enumerator value of DMARXEND field.                              */
  #define UARTE_INTEN_DMARXEND_Max (0x1UL)           /*!< Max enumerator value of DMARXEND field.                              */
  #define UARTE_INTEN_DMARXEND_Disabled (0x0UL)      /*!< Disable                                                              */
  #define UARTE_INTEN_DMARXEND_Enabled (0x1UL)       /*!< Enable                                                               */

/* DMARXREADY @Bit 20 : Enable or disable interrupt for event DMARXREADY */
  #define UARTE_INTEN_DMARXREADY_Pos (20UL)          /*!< Position of DMARXREADY field.                                        */
  #define UARTE_INTEN_DMARXREADY_Msk (0x1UL << UARTE_INTEN_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.                  */
  #define UARTE_INTEN_DMARXREADY_Min (0x0UL)         /*!< Min enumerator value of DMARXREADY field.                            */
  #define UARTE_INTEN_DMARXREADY_Max (0x1UL)         /*!< Max enumerator value of DMARXREADY field.                            */
  #define UARTE_INTEN_DMARXREADY_Disabled (0x0UL)    /*!< Disable                                                              */
  #define UARTE_INTEN_DMARXREADY_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMARXBUSERROR @Bit 21 : Enable or disable interrupt for event DMARXBUSERROR */
  #define UARTE_INTEN_DMARXBUSERROR_Pos (21UL)       /*!< Position of DMARXBUSERROR field.                                     */
  #define UARTE_INTEN_DMARXBUSERROR_Msk (0x1UL << UARTE_INTEN_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.         */
  #define UARTE_INTEN_DMARXBUSERROR_Min (0x0UL)      /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define UARTE_INTEN_DMARXBUSERROR_Max (0x1UL)      /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define UARTE_INTEN_DMARXBUSERROR_Disabled (0x0UL) /*!< Disable                                                              */
  #define UARTE_INTEN_DMARXBUSERROR_Enabled (0x1UL)  /*!< Enable                                                               */

/* DMARXMATCH0 @Bit 22 : Enable or disable interrupt for event DMARXMATCH[0] */
  #define UARTE_INTEN_DMARXMATCH0_Pos (22UL)         /*!< Position of DMARXMATCH0 field.                                       */
  #define UARTE_INTEN_DMARXMATCH0_Msk (0x1UL << UARTE_INTEN_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.               */
  #define UARTE_INTEN_DMARXMATCH0_Min (0x0UL)        /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define UARTE_INTEN_DMARXMATCH0_Max (0x1UL)        /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define UARTE_INTEN_DMARXMATCH0_Disabled (0x0UL)   /*!< Disable                                                              */
  #define UARTE_INTEN_DMARXMATCH0_Enabled (0x1UL)    /*!< Enable                                                               */

/* DMARXMATCH1 @Bit 23 : Enable or disable interrupt for event DMARXMATCH[1] */
  #define UARTE_INTEN_DMARXMATCH1_Pos (23UL)         /*!< Position of DMARXMATCH1 field.                                       */
  #define UARTE_INTEN_DMARXMATCH1_Msk (0x1UL << UARTE_INTEN_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.               */
  #define UARTE_INTEN_DMARXMATCH1_Min (0x0UL)        /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define UARTE_INTEN_DMARXMATCH1_Max (0x1UL)        /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define UARTE_INTEN_DMARXMATCH1_Disabled (0x0UL)   /*!< Disable                                                              */
  #define UARTE_INTEN_DMARXMATCH1_Enabled (0x1UL)    /*!< Enable                                                               */

/* DMARXMATCH2 @Bit 24 : Enable or disable interrupt for event DMARXMATCH[2] */
  #define UARTE_INTEN_DMARXMATCH2_Pos (24UL)         /*!< Position of DMARXMATCH2 field.                                       */
  #define UARTE_INTEN_DMARXMATCH2_Msk (0x1UL << UARTE_INTEN_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.               */
  #define UARTE_INTEN_DMARXMATCH2_Min (0x0UL)        /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define UARTE_INTEN_DMARXMATCH2_Max (0x1UL)        /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define UARTE_INTEN_DMARXMATCH2_Disabled (0x0UL)   /*!< Disable                                                              */
  #define UARTE_INTEN_DMARXMATCH2_Enabled (0x1UL)    /*!< Enable                                                               */

/* DMARXMATCH3 @Bit 25 : Enable or disable interrupt for event DMARXMATCH[3] */
  #define UARTE_INTEN_DMARXMATCH3_Pos (25UL)         /*!< Position of DMARXMATCH3 field.                                       */
  #define UARTE_INTEN_DMARXMATCH3_Msk (0x1UL << UARTE_INTEN_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.               */
  #define UARTE_INTEN_DMARXMATCH3_Min (0x0UL)        /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define UARTE_INTEN_DMARXMATCH3_Max (0x1UL)        /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define UARTE_INTEN_DMARXMATCH3_Disabled (0x0UL)   /*!< Disable                                                              */
  #define UARTE_INTEN_DMARXMATCH3_Enabled (0x1UL)    /*!< Enable                                                               */

/* DMATXEND @Bit 26 : Enable or disable interrupt for event DMATXEND */
  #define UARTE_INTEN_DMATXEND_Pos (26UL)            /*!< Position of DMATXEND field.                                          */
  #define UARTE_INTEN_DMATXEND_Msk (0x1UL << UARTE_INTEN_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                        */
  #define UARTE_INTEN_DMATXEND_Min (0x0UL)           /*!< Min enumerator value of DMATXEND field.                              */
  #define UARTE_INTEN_DMATXEND_Max (0x1UL)           /*!< Max enumerator value of DMATXEND field.                              */
  #define UARTE_INTEN_DMATXEND_Disabled (0x0UL)      /*!< Disable                                                              */
  #define UARTE_INTEN_DMATXEND_Enabled (0x1UL)       /*!< Enable                                                               */

/* DMATXREADY @Bit 27 : Enable or disable interrupt for event DMATXREADY */
  #define UARTE_INTEN_DMATXREADY_Pos (27UL)          /*!< Position of DMATXREADY field.                                        */
  #define UARTE_INTEN_DMATXREADY_Msk (0x1UL << UARTE_INTEN_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.                  */
  #define UARTE_INTEN_DMATXREADY_Min (0x0UL)         /*!< Min enumerator value of DMATXREADY field.                            */
  #define UARTE_INTEN_DMATXREADY_Max (0x1UL)         /*!< Max enumerator value of DMATXREADY field.                            */
  #define UARTE_INTEN_DMATXREADY_Disabled (0x0UL)    /*!< Disable                                                              */
  #define UARTE_INTEN_DMATXREADY_Enabled (0x1UL)     /*!< Enable                                                               */

/* DMATXBUSERROR @Bit 28 : Enable or disable interrupt for event DMATXBUSERROR */
  #define UARTE_INTEN_DMATXBUSERROR_Pos (28UL)       /*!< Position of DMATXBUSERROR field.                                     */
  #define UARTE_INTEN_DMATXBUSERROR_Msk (0x1UL << UARTE_INTEN_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.         */
  #define UARTE_INTEN_DMATXBUSERROR_Min (0x0UL)      /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define UARTE_INTEN_DMATXBUSERROR_Max (0x1UL)      /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define UARTE_INTEN_DMATXBUSERROR_Disabled (0x0UL) /*!< Disable                                                              */
  #define UARTE_INTEN_DMATXBUSERROR_Enabled (0x1UL)  /*!< Enable                                                               */

/* FRAMETIMEOUT @Bit 29 : Enable or disable interrupt for event FRAMETIMEOUT */
  #define UARTE_INTEN_FRAMETIMEOUT_Pos (29UL)        /*!< Position of FRAMETIMEOUT field.                                      */
  #define UARTE_INTEN_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTEN_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field.            */
  #define UARTE_INTEN_FRAMETIMEOUT_Min (0x0UL)       /*!< Min enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_INTEN_FRAMETIMEOUT_Max (0x1UL)       /*!< Max enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_INTEN_FRAMETIMEOUT_Disabled (0x0UL)  /*!< Disable                                                              */
  #define UARTE_INTEN_FRAMETIMEOUT_Enabled (0x1UL)   /*!< Enable                                                               */


/* UARTE_INTENSET: Enable interrupt */
  #define UARTE_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */

/* CTS @Bit 0 : Write '1' to enable interrupt for event CTS */
  #define UARTE_INTENSET_CTS_Pos (0UL)               /*!< Position of CTS field.                                               */
  #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field.                                 */
  #define UARTE_INTENSET_CTS_Min (0x0UL)             /*!< Min enumerator value of CTS field.                                   */
  #define UARTE_INTENSET_CTS_Max (0x1UL)             /*!< Max enumerator value of CTS field.                                   */
  #define UARTE_INTENSET_CTS_Set (0x1UL)             /*!< Enable                                                               */
  #define UARTE_INTENSET_CTS_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_CTS_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* NCTS @Bit 1 : Write '1' to enable interrupt for event NCTS */
  #define UARTE_INTENSET_NCTS_Pos (1UL)              /*!< Position of NCTS field.                                              */
  #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field.                              */
  #define UARTE_INTENSET_NCTS_Min (0x0UL)            /*!< Min enumerator value of NCTS field.                                  */
  #define UARTE_INTENSET_NCTS_Max (0x1UL)            /*!< Max enumerator value of NCTS field.                                  */
  #define UARTE_INTENSET_NCTS_Set (0x1UL)            /*!< Enable                                                               */
  #define UARTE_INTENSET_NCTS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_NCTS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* TXDRDY @Bit 3 : Write '1' to enable interrupt for event TXDRDY */
  #define UARTE_INTENSET_TXDRDY_Pos (3UL)            /*!< Position of TXDRDY field.                                            */
  #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field.                        */
  #define UARTE_INTENSET_TXDRDY_Min (0x0UL)          /*!< Min enumerator value of TXDRDY field.                                */
  #define UARTE_INTENSET_TXDRDY_Max (0x1UL)          /*!< Max enumerator value of TXDRDY field.                                */
  #define UARTE_INTENSET_TXDRDY_Set (0x1UL)          /*!< Enable                                                               */
  #define UARTE_INTENSET_TXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_TXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* RXDRDY @Bit 4 : Write '1' to enable interrupt for event RXDRDY */
  #define UARTE_INTENSET_RXDRDY_Pos (4UL)            /*!< Position of RXDRDY field.                                            */
  #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field.                        */
  #define UARTE_INTENSET_RXDRDY_Min (0x0UL)          /*!< Min enumerator value of RXDRDY field.                                */
  #define UARTE_INTENSET_RXDRDY_Max (0x1UL)          /*!< Max enumerator value of RXDRDY field.                                */
  #define UARTE_INTENSET_RXDRDY_Set (0x1UL)          /*!< Enable                                                               */
  #define UARTE_INTENSET_RXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_RXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ERROR @Bit 5 : Write '1' to enable interrupt for event ERROR */
  #define UARTE_INTENSET_ERROR_Pos (5UL)             /*!< Position of ERROR field.                                             */
  #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                           */
  #define UARTE_INTENSET_ERROR_Min (0x0UL)           /*!< Min enumerator value of ERROR field.                                 */
  #define UARTE_INTENSET_ERROR_Max (0x1UL)           /*!< Max enumerator value of ERROR field.                                 */
  #define UARTE_INTENSET_ERROR_Set (0x1UL)           /*!< Enable                                                               */
  #define UARTE_INTENSET_ERROR_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_ERROR_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* RXTO @Bit 9 : Write '1' to enable interrupt for event RXTO */
  #define UARTE_INTENSET_RXTO_Pos (9UL)              /*!< Position of RXTO field.                                              */
  #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field.                              */
  #define UARTE_INTENSET_RXTO_Min (0x0UL)            /*!< Min enumerator value of RXTO field.                                  */
  #define UARTE_INTENSET_RXTO_Max (0x1UL)            /*!< Max enumerator value of RXTO field.                                  */
  #define UARTE_INTENSET_RXTO_Set (0x1UL)            /*!< Enable                                                               */
  #define UARTE_INTENSET_RXTO_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_RXTO_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* TXSTOPPED @Bit 12 : Write '1' to enable interrupt for event TXSTOPPED */
  #define UARTE_INTENSET_TXSTOPPED_Pos (12UL)        /*!< Position of TXSTOPPED field.                                         */
  #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field.               */
  #define UARTE_INTENSET_TXSTOPPED_Min (0x0UL)       /*!< Min enumerator value of TXSTOPPED field.                             */
  #define UARTE_INTENSET_TXSTOPPED_Max (0x1UL)       /*!< Max enumerator value of TXSTOPPED field.                             */
  #define UARTE_INTENSET_TXSTOPPED_Set (0x1UL)       /*!< Enable                                                               */
  #define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to enable interrupt for event DMARXEND */
  #define UARTE_INTENSET_DMARXEND_Pos (19UL)         /*!< Position of DMARXEND field.                                          */
  #define UARTE_INTENSET_DMARXEND_Msk (0x1UL << UARTE_INTENSET_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                  */
  #define UARTE_INTENSET_DMARXEND_Min (0x0UL)        /*!< Min enumerator value of DMARXEND field.                              */
  #define UARTE_INTENSET_DMARXEND_Max (0x1UL)        /*!< Max enumerator value of DMARXEND field.                              */
  #define UARTE_INTENSET_DMARXEND_Set (0x1UL)        /*!< Enable                                                               */
  #define UARTE_INTENSET_DMARXEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_DMARXEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to enable interrupt for event DMARXREADY */
  #define UARTE_INTENSET_DMARXREADY_Pos (20UL)       /*!< Position of DMARXREADY field.                                        */
  #define UARTE_INTENSET_DMARXREADY_Msk (0x1UL << UARTE_INTENSET_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.            */
  #define UARTE_INTENSET_DMARXREADY_Min (0x0UL)      /*!< Min enumerator value of DMARXREADY field.                            */
  #define UARTE_INTENSET_DMARXREADY_Max (0x1UL)      /*!< Max enumerator value of DMARXREADY field.                            */
  #define UARTE_INTENSET_DMARXREADY_Set (0x1UL)      /*!< Enable                                                               */
  #define UARTE_INTENSET_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_DMARXREADY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to enable interrupt for event DMARXBUSERROR */
  #define UARTE_INTENSET_DMARXBUSERROR_Pos (21UL)    /*!< Position of DMARXBUSERROR field.                                     */
  #define UARTE_INTENSET_DMARXBUSERROR_Msk (0x1UL << UARTE_INTENSET_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.   */
  #define UARTE_INTENSET_DMARXBUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define UARTE_INTENSET_DMARXBUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define UARTE_INTENSET_DMARXBUSERROR_Set (0x1UL)   /*!< Enable                                                               */
  #define UARTE_INTENSET_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define UARTE_INTENSET_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* DMARXMATCH0 @Bit 22 : Write '1' to enable interrupt for event DMARXMATCH[0] */
  #define UARTE_INTENSET_DMARXMATCH0_Pos (22UL)      /*!< Position of DMARXMATCH0 field.                                       */
  #define UARTE_INTENSET_DMARXMATCH0_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.         */
  #define UARTE_INTENSET_DMARXMATCH0_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define UARTE_INTENSET_DMARXMATCH0_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define UARTE_INTENSET_DMARXMATCH0_Set (0x1UL)     /*!< Enable                                                               */
  #define UARTE_INTENSET_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENSET_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to enable interrupt for event DMARXMATCH[1] */
  #define UARTE_INTENSET_DMARXMATCH1_Pos (23UL)      /*!< Position of DMARXMATCH1 field.                                       */
  #define UARTE_INTENSET_DMARXMATCH1_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.         */
  #define UARTE_INTENSET_DMARXMATCH1_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define UARTE_INTENSET_DMARXMATCH1_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define UARTE_INTENSET_DMARXMATCH1_Set (0x1UL)     /*!< Enable                                                               */
  #define UARTE_INTENSET_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENSET_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to enable interrupt for event DMARXMATCH[2] */
  #define UARTE_INTENSET_DMARXMATCH2_Pos (24UL)      /*!< Position of DMARXMATCH2 field.                                       */
  #define UARTE_INTENSET_DMARXMATCH2_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.         */
  #define UARTE_INTENSET_DMARXMATCH2_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define UARTE_INTENSET_DMARXMATCH2_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define UARTE_INTENSET_DMARXMATCH2_Set (0x1UL)     /*!< Enable                                                               */
  #define UARTE_INTENSET_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENSET_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to enable interrupt for event DMARXMATCH[3] */
  #define UARTE_INTENSET_DMARXMATCH3_Pos (25UL)      /*!< Position of DMARXMATCH3 field.                                       */
  #define UARTE_INTENSET_DMARXMATCH3_Msk (0x1UL << UARTE_INTENSET_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.         */
  #define UARTE_INTENSET_DMARXMATCH3_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define UARTE_INTENSET_DMARXMATCH3_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define UARTE_INTENSET_DMARXMATCH3_Set (0x1UL)     /*!< Enable                                                               */
  #define UARTE_INTENSET_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENSET_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to enable interrupt for event DMATXEND */
  #define UARTE_INTENSET_DMATXEND_Pos (26UL)         /*!< Position of DMATXEND field.                                          */
  #define UARTE_INTENSET_DMATXEND_Msk (0x1UL << UARTE_INTENSET_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                  */
  #define UARTE_INTENSET_DMATXEND_Min (0x0UL)        /*!< Min enumerator value of DMATXEND field.                              */
  #define UARTE_INTENSET_DMATXEND_Max (0x1UL)        /*!< Max enumerator value of DMATXEND field.                              */
  #define UARTE_INTENSET_DMATXEND_Set (0x1UL)        /*!< Enable                                                               */
  #define UARTE_INTENSET_DMATXEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_DMATXEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to enable interrupt for event DMATXREADY */
  #define UARTE_INTENSET_DMATXREADY_Pos (27UL)       /*!< Position of DMATXREADY field.                                        */
  #define UARTE_INTENSET_DMATXREADY_Msk (0x1UL << UARTE_INTENSET_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.            */
  #define UARTE_INTENSET_DMATXREADY_Min (0x0UL)      /*!< Min enumerator value of DMATXREADY field.                            */
  #define UARTE_INTENSET_DMATXREADY_Max (0x1UL)      /*!< Max enumerator value of DMATXREADY field.                            */
  #define UARTE_INTENSET_DMATXREADY_Set (0x1UL)      /*!< Enable                                                               */
  #define UARTE_INTENSET_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define UARTE_INTENSET_DMATXREADY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to enable interrupt for event DMATXBUSERROR */
  #define UARTE_INTENSET_DMATXBUSERROR_Pos (28UL)    /*!< Position of DMATXBUSERROR field.                                     */
  #define UARTE_INTENSET_DMATXBUSERROR_Msk (0x1UL << UARTE_INTENSET_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.   */
  #define UARTE_INTENSET_DMATXBUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define UARTE_INTENSET_DMATXBUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define UARTE_INTENSET_DMATXBUSERROR_Set (0x1UL)   /*!< Enable                                                               */
  #define UARTE_INTENSET_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define UARTE_INTENSET_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* FRAMETIMEOUT @Bit 29 : Write '1' to enable interrupt for event FRAMETIMEOUT */
  #define UARTE_INTENSET_FRAMETIMEOUT_Pos (29UL)     /*!< Position of FRAMETIMEOUT field.                                      */
  #define UARTE_INTENSET_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTENSET_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field.      */
  #define UARTE_INTENSET_FRAMETIMEOUT_Min (0x0UL)    /*!< Min enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_INTENSET_FRAMETIMEOUT_Max (0x1UL)    /*!< Max enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_INTENSET_FRAMETIMEOUT_Set (0x1UL)    /*!< Enable                                                               */
  #define UARTE_INTENSET_FRAMETIMEOUT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define UARTE_INTENSET_FRAMETIMEOUT_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* UARTE_INTENCLR: Disable interrupt */
  #define UARTE_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */

/* CTS @Bit 0 : Write '1' to disable interrupt for event CTS */
  #define UARTE_INTENCLR_CTS_Pos (0UL)               /*!< Position of CTS field.                                               */
  #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field.                                 */
  #define UARTE_INTENCLR_CTS_Min (0x0UL)             /*!< Min enumerator value of CTS field.                                   */
  #define UARTE_INTENCLR_CTS_Max (0x1UL)             /*!< Max enumerator value of CTS field.                                   */
  #define UARTE_INTENCLR_CTS_Clear (0x1UL)           /*!< Disable                                                              */
  #define UARTE_INTENCLR_CTS_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_CTS_Enabled (0x1UL)         /*!< Read: Enabled                                                        */

/* NCTS @Bit 1 : Write '1' to disable interrupt for event NCTS */
  #define UARTE_INTENCLR_NCTS_Pos (1UL)              /*!< Position of NCTS field.                                              */
  #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field.                              */
  #define UARTE_INTENCLR_NCTS_Min (0x0UL)            /*!< Min enumerator value of NCTS field.                                  */
  #define UARTE_INTENCLR_NCTS_Max (0x1UL)            /*!< Max enumerator value of NCTS field.                                  */
  #define UARTE_INTENCLR_NCTS_Clear (0x1UL)          /*!< Disable                                                              */
  #define UARTE_INTENCLR_NCTS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_NCTS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* TXDRDY @Bit 3 : Write '1' to disable interrupt for event TXDRDY */
  #define UARTE_INTENCLR_TXDRDY_Pos (3UL)            /*!< Position of TXDRDY field.                                            */
  #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field.                        */
  #define UARTE_INTENCLR_TXDRDY_Min (0x0UL)          /*!< Min enumerator value of TXDRDY field.                                */
  #define UARTE_INTENCLR_TXDRDY_Max (0x1UL)          /*!< Max enumerator value of TXDRDY field.                                */
  #define UARTE_INTENCLR_TXDRDY_Clear (0x1UL)        /*!< Disable                                                              */
  #define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* RXDRDY @Bit 4 : Write '1' to disable interrupt for event RXDRDY */
  #define UARTE_INTENCLR_RXDRDY_Pos (4UL)            /*!< Position of RXDRDY field.                                            */
  #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field.                        */
  #define UARTE_INTENCLR_RXDRDY_Min (0x0UL)          /*!< Min enumerator value of RXDRDY field.                                */
  #define UARTE_INTENCLR_RXDRDY_Max (0x1UL)          /*!< Max enumerator value of RXDRDY field.                                */
  #define UARTE_INTENCLR_RXDRDY_Clear (0x1UL)        /*!< Disable                                                              */
  #define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */

/* ERROR @Bit 5 : Write '1' to disable interrupt for event ERROR */
  #define UARTE_INTENCLR_ERROR_Pos (5UL)             /*!< Position of ERROR field.                                             */
  #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                           */
  #define UARTE_INTENCLR_ERROR_Min (0x0UL)           /*!< Min enumerator value of ERROR field.                                 */
  #define UARTE_INTENCLR_ERROR_Max (0x1UL)           /*!< Max enumerator value of ERROR field.                                 */
  #define UARTE_INTENCLR_ERROR_Clear (0x1UL)         /*!< Disable                                                              */
  #define UARTE_INTENCLR_ERROR_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_ERROR_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* RXTO @Bit 9 : Write '1' to disable interrupt for event RXTO */
  #define UARTE_INTENCLR_RXTO_Pos (9UL)              /*!< Position of RXTO field.                                              */
  #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field.                              */
  #define UARTE_INTENCLR_RXTO_Min (0x0UL)            /*!< Min enumerator value of RXTO field.                                  */
  #define UARTE_INTENCLR_RXTO_Max (0x1UL)            /*!< Max enumerator value of RXTO field.                                  */
  #define UARTE_INTENCLR_RXTO_Clear (0x1UL)          /*!< Disable                                                              */
  #define UARTE_INTENCLR_RXTO_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_RXTO_Enabled (0x1UL)        /*!< Read: Enabled                                                        */

/* TXSTOPPED @Bit 12 : Write '1' to disable interrupt for event TXSTOPPED */
  #define UARTE_INTENCLR_TXSTOPPED_Pos (12UL)        /*!< Position of TXSTOPPED field.                                         */
  #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field.               */
  #define UARTE_INTENCLR_TXSTOPPED_Min (0x0UL)       /*!< Min enumerator value of TXSTOPPED field.                             */
  #define UARTE_INTENCLR_TXSTOPPED_Max (0x1UL)       /*!< Max enumerator value of TXSTOPPED field.                             */
  #define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL)     /*!< Disable                                                              */
  #define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* DMARXEND @Bit 19 : Write '1' to disable interrupt for event DMARXEND */
  #define UARTE_INTENCLR_DMARXEND_Pos (19UL)         /*!< Position of DMARXEND field.                                          */
  #define UARTE_INTENCLR_DMARXEND_Msk (0x1UL << UARTE_INTENCLR_DMARXEND_Pos) /*!< Bit mask of DMARXEND field.                  */
  #define UARTE_INTENCLR_DMARXEND_Min (0x0UL)        /*!< Min enumerator value of DMARXEND field.                              */
  #define UARTE_INTENCLR_DMARXEND_Max (0x1UL)        /*!< Max enumerator value of DMARXEND field.                              */
  #define UARTE_INTENCLR_DMARXEND_Clear (0x1UL)      /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMARXEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_DMARXEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMARXREADY @Bit 20 : Write '1' to disable interrupt for event DMARXREADY */
  #define UARTE_INTENCLR_DMARXREADY_Pos (20UL)       /*!< Position of DMARXREADY field.                                        */
  #define UARTE_INTENCLR_DMARXREADY_Msk (0x1UL << UARTE_INTENCLR_DMARXREADY_Pos) /*!< Bit mask of DMARXREADY field.            */
  #define UARTE_INTENCLR_DMARXREADY_Min (0x0UL)      /*!< Min enumerator value of DMARXREADY field.                            */
  #define UARTE_INTENCLR_DMARXREADY_Max (0x1UL)      /*!< Max enumerator value of DMARXREADY field.                            */
  #define UARTE_INTENCLR_DMARXREADY_Clear (0x1UL)    /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMARXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_DMARXREADY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMARXBUSERROR @Bit 21 : Write '1' to disable interrupt for event DMARXBUSERROR */
  #define UARTE_INTENCLR_DMARXBUSERROR_Pos (21UL)    /*!< Position of DMARXBUSERROR field.                                     */
  #define UARTE_INTENCLR_DMARXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_DMARXBUSERROR_Pos) /*!< Bit mask of DMARXBUSERROR field.   */
  #define UARTE_INTENCLR_DMARXBUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMARXBUSERROR field.                         */
  #define UARTE_INTENCLR_DMARXBUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMARXBUSERROR field.                         */
  #define UARTE_INTENCLR_DMARXBUSERROR_Clear (0x1UL) /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMARXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define UARTE_INTENCLR_DMARXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* DMARXMATCH0 @Bit 22 : Write '1' to disable interrupt for event DMARXMATCH[0] */
  #define UARTE_INTENCLR_DMARXMATCH0_Pos (22UL)      /*!< Position of DMARXMATCH0 field.                                       */
  #define UARTE_INTENCLR_DMARXMATCH0_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH0_Pos) /*!< Bit mask of DMARXMATCH0 field.         */
  #define UARTE_INTENCLR_DMARXMATCH0_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH0 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH0_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH0 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH0_Clear (0x1UL)   /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMARXMATCH0_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENCLR_DMARXMATCH0_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMARXMATCH1 @Bit 23 : Write '1' to disable interrupt for event DMARXMATCH[1] */
  #define UARTE_INTENCLR_DMARXMATCH1_Pos (23UL)      /*!< Position of DMARXMATCH1 field.                                       */
  #define UARTE_INTENCLR_DMARXMATCH1_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH1_Pos) /*!< Bit mask of DMARXMATCH1 field.         */
  #define UARTE_INTENCLR_DMARXMATCH1_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH1 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH1_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH1 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH1_Clear (0x1UL)   /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMARXMATCH1_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENCLR_DMARXMATCH1_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMARXMATCH2 @Bit 24 : Write '1' to disable interrupt for event DMARXMATCH[2] */
  #define UARTE_INTENCLR_DMARXMATCH2_Pos (24UL)      /*!< Position of DMARXMATCH2 field.                                       */
  #define UARTE_INTENCLR_DMARXMATCH2_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH2_Pos) /*!< Bit mask of DMARXMATCH2 field.         */
  #define UARTE_INTENCLR_DMARXMATCH2_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH2 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH2_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH2 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH2_Clear (0x1UL)   /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMARXMATCH2_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENCLR_DMARXMATCH2_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMARXMATCH3 @Bit 25 : Write '1' to disable interrupt for event DMARXMATCH[3] */
  #define UARTE_INTENCLR_DMARXMATCH3_Pos (25UL)      /*!< Position of DMARXMATCH3 field.                                       */
  #define UARTE_INTENCLR_DMARXMATCH3_Msk (0x1UL << UARTE_INTENCLR_DMARXMATCH3_Pos) /*!< Bit mask of DMARXMATCH3 field.         */
  #define UARTE_INTENCLR_DMARXMATCH3_Min (0x0UL)     /*!< Min enumerator value of DMARXMATCH3 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH3_Max (0x1UL)     /*!< Max enumerator value of DMARXMATCH3 field.                           */
  #define UARTE_INTENCLR_DMARXMATCH3_Clear (0x1UL)   /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMARXMATCH3_Disabled (0x0UL) /*!< Read: Disabled                                                      */
  #define UARTE_INTENCLR_DMARXMATCH3_Enabled (0x1UL) /*!< Read: Enabled                                                        */

/* DMATXEND @Bit 26 : Write '1' to disable interrupt for event DMATXEND */
  #define UARTE_INTENCLR_DMATXEND_Pos (26UL)         /*!< Position of DMATXEND field.                                          */
  #define UARTE_INTENCLR_DMATXEND_Msk (0x1UL << UARTE_INTENCLR_DMATXEND_Pos) /*!< Bit mask of DMATXEND field.                  */
  #define UARTE_INTENCLR_DMATXEND_Min (0x0UL)        /*!< Min enumerator value of DMATXEND field.                              */
  #define UARTE_INTENCLR_DMATXEND_Max (0x1UL)        /*!< Max enumerator value of DMATXEND field.                              */
  #define UARTE_INTENCLR_DMATXEND_Clear (0x1UL)      /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMATXEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_DMATXEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */

/* DMATXREADY @Bit 27 : Write '1' to disable interrupt for event DMATXREADY */
  #define UARTE_INTENCLR_DMATXREADY_Pos (27UL)       /*!< Position of DMATXREADY field.                                        */
  #define UARTE_INTENCLR_DMATXREADY_Msk (0x1UL << UARTE_INTENCLR_DMATXREADY_Pos) /*!< Bit mask of DMATXREADY field.            */
  #define UARTE_INTENCLR_DMATXREADY_Min (0x0UL)      /*!< Min enumerator value of DMATXREADY field.                            */
  #define UARTE_INTENCLR_DMATXREADY_Max (0x1UL)      /*!< Max enumerator value of DMATXREADY field.                            */
  #define UARTE_INTENCLR_DMATXREADY_Clear (0x1UL)    /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMATXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                       */
  #define UARTE_INTENCLR_DMATXREADY_Enabled (0x1UL)  /*!< Read: Enabled                                                        */

/* DMATXBUSERROR @Bit 28 : Write '1' to disable interrupt for event DMATXBUSERROR */
  #define UARTE_INTENCLR_DMATXBUSERROR_Pos (28UL)    /*!< Position of DMATXBUSERROR field.                                     */
  #define UARTE_INTENCLR_DMATXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_DMATXBUSERROR_Pos) /*!< Bit mask of DMATXBUSERROR field.   */
  #define UARTE_INTENCLR_DMATXBUSERROR_Min (0x0UL)   /*!< Min enumerator value of DMATXBUSERROR field.                         */
  #define UARTE_INTENCLR_DMATXBUSERROR_Max (0x1UL)   /*!< Max enumerator value of DMATXBUSERROR field.                         */
  #define UARTE_INTENCLR_DMATXBUSERROR_Clear (0x1UL) /*!< Disable                                                              */
  #define UARTE_INTENCLR_DMATXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                    */
  #define UARTE_INTENCLR_DMATXBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                      */

/* FRAMETIMEOUT @Bit 29 : Write '1' to disable interrupt for event FRAMETIMEOUT */
  #define UARTE_INTENCLR_FRAMETIMEOUT_Pos (29UL)     /*!< Position of FRAMETIMEOUT field.                                      */
  #define UARTE_INTENCLR_FRAMETIMEOUT_Msk (0x1UL << UARTE_INTENCLR_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field.      */
  #define UARTE_INTENCLR_FRAMETIMEOUT_Min (0x0UL)    /*!< Min enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_INTENCLR_FRAMETIMEOUT_Max (0x1UL)    /*!< Max enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_INTENCLR_FRAMETIMEOUT_Clear (0x1UL)  /*!< Disable                                                              */
  #define UARTE_INTENCLR_FRAMETIMEOUT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
  #define UARTE_INTENCLR_FRAMETIMEOUT_Enabled (0x1UL) /*!< Read: Enabled                                                       */


/* UARTE_ERRORSRC: Error source */
  #define UARTE_ERRORSRC_ResetValue (0x00000000UL)   /*!< Reset value of ERRORSRC register.                                    */

/* OVERRUN @Bit 0 : Overrun error */
  #define UARTE_ERRORSRC_OVERRUN_Pos (0UL)           /*!< Position of OVERRUN field.                                           */
  #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field.                     */
  #define UARTE_ERRORSRC_OVERRUN_Min (0x0UL)         /*!< Min enumerator value of OVERRUN field.                               */
  #define UARTE_ERRORSRC_OVERRUN_Max (0x1UL)         /*!< Max enumerator value of OVERRUN field.                               */
  #define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL)  /*!< Read: error not present                                              */
  #define UARTE_ERRORSRC_OVERRUN_Present (0x1UL)     /*!< Read: error present                                                  */

/* PARITY @Bit 1 : Parity error */
  #define UARTE_ERRORSRC_PARITY_Pos (1UL)            /*!< Position of PARITY field.                                            */
  #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field.                        */
  #define UARTE_ERRORSRC_PARITY_Min (0x0UL)          /*!< Min enumerator value of PARITY field.                                */
  #define UARTE_ERRORSRC_PARITY_Max (0x1UL)          /*!< Max enumerator value of PARITY field.                                */
  #define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL)   /*!< Read: error not present                                              */
  #define UARTE_ERRORSRC_PARITY_Present (0x1UL)      /*!< Read: error present                                                  */

/* FRAMING @Bit 2 : Framing error occurred */
  #define UARTE_ERRORSRC_FRAMING_Pos (2UL)           /*!< Position of FRAMING field.                                           */
  #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field.                     */
  #define UARTE_ERRORSRC_FRAMING_Min (0x0UL)         /*!< Min enumerator value of FRAMING field.                               */
  #define UARTE_ERRORSRC_FRAMING_Max (0x1UL)         /*!< Max enumerator value of FRAMING field.                               */
  #define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL)  /*!< Read: error not present                                              */
  #define UARTE_ERRORSRC_FRAMING_Present (0x1UL)     /*!< Read: error present                                                  */

/* BREAK @Bit 3 : Break condition */
  #define UARTE_ERRORSRC_BREAK_Pos (3UL)             /*!< Position of BREAK field.                                             */
  #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field.                           */
  #define UARTE_ERRORSRC_BREAK_Min (0x0UL)           /*!< Min enumerator value of BREAK field.                                 */
  #define UARTE_ERRORSRC_BREAK_Max (0x1UL)           /*!< Max enumerator value of BREAK field.                                 */
  #define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL)    /*!< Read: error not present                                              */
  #define UARTE_ERRORSRC_BREAK_Present (0x1UL)       /*!< Read: error present                                                  */


/* UARTE_ENABLE: Enable UART */
  #define UARTE_ENABLE_ResetValue (0x00000000UL)     /*!< Reset value of ENABLE register.                                      */

/* ENABLE @Bits 0..3 : Enable or disable UARTE */
  #define UARTE_ENABLE_ENABLE_Pos (0UL)              /*!< Position of ENABLE field.                                            */
  #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                            */
  #define UARTE_ENABLE_ENABLE_Min (0x0UL)            /*!< Min enumerator value of ENABLE field.                                */
  #define UARTE_ENABLE_ENABLE_Max (0x8UL)            /*!< Max enumerator value of ENABLE field.                                */
  #define UARTE_ENABLE_ENABLE_Disabled (0x0UL)       /*!< Disable UARTE                                                        */
  #define UARTE_ENABLE_ENABLE_Enabled (0x8UL)        /*!< Enable UARTE                                                         */


/* UARTE_BAUDRATE: Baud rate. Accuracy depends on the HFCLK source selected. */
  #define UARTE_BAUDRATE_ResetValue (0x04000000UL)   /*!< Reset value of BAUDRATE register.                                    */

/* BAUDRATE @Bits 0..31 : Baud rate */
  #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL)          /*!< Position of BAUDRATE field.                                          */
  #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field.           */
  #define UARTE_BAUDRATE_BAUDRATE_Min (0x4F000UL)    /*!< Min enumerator value of BAUDRATE field.                              */
  #define UARTE_BAUDRATE_BAUDRATE_Max (0x10000000UL) /*!< Max enumerator value of BAUDRATE field.                              */
  #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) when UARTE has 16 MHz peripheral
                                                               clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) when UARTE has 16 MHz peripheral
                                                               clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) when UARTE has 16 MHz peripheral
                                                               clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) when UARTE has 16 MHz peripheral
                                                               clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) when UARTE has 16 MHz peripheral
                                                                clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) when UARTE has 16 MHz peripheral
                                                                clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) when UARTE has 16 MHz peripheral
                                                                clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud when UARTE has 16 MHz peripheral clock frequency    */
  #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) when UARTE has 16 MHz peripheral
                                                                clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) when UARTE has 16 MHz peripheral
                                                                clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) when UARTE has 16 MHz peripheral
                                                                clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) when UARTE has 16 MHz peripheral
                                                                clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) when UARTE has 16 MHz
                                                                 peripheral clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) when UARTE has 16 MHz
                                                                 peripheral clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud when UARTE has 16 MHz peripheral clock frequency  */
  #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) when UARTE has 16 MHz
                                                                 peripheral clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) when UARTE has 16 MHz
                                                                 peripheral clock frequency*/
  #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud when UARTE has 16 MHz peripheral clock frequency       */


/* UARTE_CONFIG: Configuration of parity, hardware flow control, framesize, and packet timeout. */
  #define UARTE_CONFIG_ResetValue (0x00001000UL)     /*!< Reset value of CONFIG register.                                      */

/* HWFC @Bit 0 : Hardware flow control */
  #define UARTE_CONFIG_HWFC_Pos (0UL)                /*!< Position of HWFC field.                                              */
  #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field.                                  */
  #define UARTE_CONFIG_HWFC_Min (0x0UL)              /*!< Min enumerator value of HWFC field.                                  */
  #define UARTE_CONFIG_HWFC_Max (0x1UL)              /*!< Max enumerator value of HWFC field.                                  */
  #define UARTE_CONFIG_HWFC_Disabled (0x0UL)         /*!< Disabled                                                             */
  #define UARTE_CONFIG_HWFC_Enabled (0x1UL)          /*!< Enabled                                                              */

/* PARITY @Bits 1..3 : Parity */
  #define UARTE_CONFIG_PARITY_Pos (1UL)              /*!< Position of PARITY field.                                            */
  #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field.                            */
  #define UARTE_CONFIG_PARITY_Min (0x0UL)            /*!< Min enumerator value of PARITY field.                                */
  #define UARTE_CONFIG_PARITY_Max (0x7UL)            /*!< Max enumerator value of PARITY field.                                */
  #define UARTE_CONFIG_PARITY_Excluded (0x0UL)       /*!< Exclude parity bit                                                   */
  #define UARTE_CONFIG_PARITY_Included (0x7UL)       /*!< Include parity bit                                                   */

/* STOP @Bit 4 : Stop bits */
  #define UARTE_CONFIG_STOP_Pos (4UL)                /*!< Position of STOP field.                                              */
  #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field.                                  */
  #define UARTE_CONFIG_STOP_Min (0x0UL)              /*!< Min enumerator value of STOP field.                                  */
  #define UARTE_CONFIG_STOP_Max (0x1UL)              /*!< Max enumerator value of STOP field.                                  */
  #define UARTE_CONFIG_STOP_One (0x0UL)              /*!< One stop bit                                                         */
  #define UARTE_CONFIG_STOP_Two (0x1UL)              /*!< Two stop bits                                                        */

/* PARITYTYPE @Bit 8 : Even or odd parity type */
  #define UARTE_CONFIG_PARITYTYPE_Pos (8UL)          /*!< Position of PARITYTYPE field.                                        */
  #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field.                */
  #define UARTE_CONFIG_PARITYTYPE_Min (0x0UL)        /*!< Min enumerator value of PARITYTYPE field.                            */
  #define UARTE_CONFIG_PARITYTYPE_Max (0x1UL)        /*!< Max enumerator value of PARITYTYPE field.                            */
  #define UARTE_CONFIG_PARITYTYPE_Even (0x0UL)       /*!< Even parity                                                          */
  #define UARTE_CONFIG_PARITYTYPE_Odd (0x1UL)        /*!< Odd parity                                                           */

/* FRAMESIZE @Bits 9..12 : Set the data frame size */
  #define UARTE_CONFIG_FRAMESIZE_Pos (9UL)           /*!< Position of FRAMESIZE field.                                         */
  #define UARTE_CONFIG_FRAMESIZE_Msk (0xFUL << UARTE_CONFIG_FRAMESIZE_Pos) /*!< Bit mask of FRAMESIZE field.                   */
  #define UARTE_CONFIG_FRAMESIZE_Min (0x4UL)         /*!< Min enumerator value of FRAMESIZE field.                             */
  #define UARTE_CONFIG_FRAMESIZE_Max (0x9UL)         /*!< Max enumerator value of FRAMESIZE field.                             */
  #define UARTE_CONFIG_FRAMESIZE_9bit (0x9UL)        /*!< 9 bit data frame size. 9th bit is treated as address bit.            */
  #define UARTE_CONFIG_FRAMESIZE_8bit (0x8UL)        /*!< 8 bit data frame size.                                               */
  #define UARTE_CONFIG_FRAMESIZE_7bit (0x7UL)        /*!< 7 bit data frame size.                                               */
  #define UARTE_CONFIG_FRAMESIZE_6bit (0x6UL)        /*!< 6 bit data frame size.                                               */
  #define UARTE_CONFIG_FRAMESIZE_5bit (0x5UL)        /*!< 5 bit data frame size.                                               */
  #define UARTE_CONFIG_FRAMESIZE_4bit (0x4UL)        /*!< 4 bit data frame size.                                               */

/* ENDIAN @Bit 13 : Select if data is trimmed from MSB or LSB end when the data frame size is less than 8. */
  #define UARTE_CONFIG_ENDIAN_Pos (13UL)             /*!< Position of ENDIAN field.                                            */
  #define UARTE_CONFIG_ENDIAN_Msk (0x1UL << UARTE_CONFIG_ENDIAN_Pos) /*!< Bit mask of ENDIAN field.                            */
  #define UARTE_CONFIG_ENDIAN_Min (0x0UL)            /*!< Min enumerator value of ENDIAN field.                                */
  #define UARTE_CONFIG_ENDIAN_Max (0x1UL)            /*!< Max enumerator value of ENDIAN field.                                */
  #define UARTE_CONFIG_ENDIAN_MSB (0x0UL)            /*!< Data is trimmed from MSB end.                                        */
  #define UARTE_CONFIG_ENDIAN_LSB (0x1UL)            /*!< Data is trimmed from LSB end.                                        */

/* FRAMETIMEOUT @Bit 14 : Enable packet timeout. */
  #define UARTE_CONFIG_FRAMETIMEOUT_Pos (14UL)       /*!< Position of FRAMETIMEOUT field.                                      */
  #define UARTE_CONFIG_FRAMETIMEOUT_Msk (0x1UL << UARTE_CONFIG_FRAMETIMEOUT_Pos) /*!< Bit mask of FRAMETIMEOUT field.          */
  #define UARTE_CONFIG_FRAMETIMEOUT_Min (0x0UL)      /*!< Min enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_CONFIG_FRAMETIMEOUT_Max (0x1UL)      /*!< Max enumerator value of FRAMETIMEOUT field.                          */
  #define UARTE_CONFIG_FRAMETIMEOUT_DISABLED (0x0UL) /*!< Packet timeout is disabled.                                          */
  #define UARTE_CONFIG_FRAMETIMEOUT_ENABLED (0x1UL)  /*!< Packet timeout is enabled.                                           */
  #define UARTE_CONFIG_FRAMETIMEOUT_Disabled (0x0UL) /*!< Packet timeout is disabled.                                          */
  #define UARTE_CONFIG_FRAMETIMEOUT_Enabled (0x1UL)  /*!< Packet timeout is enabled.                                           */


/* UARTE_ADDRESS: Set the address of the UARTE for RX when used in 9 bit data frame mode. */
  #define UARTE_ADDRESS_ResetValue (0x00000000UL)    /*!< Reset value of ADDRESS register.                                     */

/* ADDRESS @Bits 0..7 : Set address */
  #define UARTE_ADDRESS_ADDRESS_Pos (0UL)            /*!< Position of ADDRESS field.                                           */
  #define UARTE_ADDRESS_ADDRESS_Msk (0xFFUL << UARTE_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                      */


/* UARTE_FRAMETIMEOUT: Set the number of UARTE bits to count before triggering packet timeout. */
  #define UARTE_FRAMETIMEOUT_ResetValue (0x00000010UL) /*!< Reset value of FRAMETIMEOUT register.                              */

/* COUNTERTOP @Bits 0..9 : Number of UARTE bits before timeout. */
  #define UARTE_FRAMETIMEOUT_COUNTERTOP_Pos (0UL)    /*!< Position of COUNTERTOP field.                                        */
  #define UARTE_FRAMETIMEOUT_COUNTERTOP_Msk (0x3FFUL << UARTE_FRAMETIMEOUT_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field.  */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                           UICR                                           ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* ================================================== Struct UICR_APPROTECT ================================================== */
/**
  * @brief APPROTECT [UICR_APPROTECT] Access Port Protection Registers
  */
typedef struct {
  __IOM uint32_t  PROTECT0;                          /*!< (@ 0x00000000) Access port protection                                */
  __IM  uint32_t  RESERVED[6];
  __IOM uint32_t  PROTECT1;                          /*!< (@ 0x0000001C) Access port protection                                */
} NRF_UICR_APPROTECT_Type;                           /*!< Size = 32 (0x020)                                                    */
  #define UICR_APPROTECT_MaxCount (1UL)              /*!< Size of APPROTECT[1] array.                                          */
  #define UICR_APPROTECT_MaxIndex (0UL)              /*!< Max index of APPROTECT[1] array.                                     */
  #define UICR_APPROTECT_MinIndex (0UL)              /*!< Min index of APPROTECT[1] array.                                     */

/* UICR_APPROTECT_PROTECT0: Access port protection */
  #define UICR_APPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register.                             */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_APPROTECT_PROTECT0_PALL_Pos (0UL)     /*!< Position of PALL field.                                              */
  #define UICR_APPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL field.     */
  #define UICR_APPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field.                             */
  #define UICR_APPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field.                             */
  #define UICR_APPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal
                                                                       protectors unlocked and under CPU control.*/


/* UICR_APPROTECT_PROTECT1: Access port protection */
  #define UICR_APPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register.                             */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_APPROTECT_PROTECT1_PALL_Pos (0UL)     /*!< Position of PALL field.                                              */
  #define UICR_APPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL field.     */
  #define UICR_APPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field.                             */
  #define UICR_APPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field.                             */
  #define UICR_APPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN DBGEN and NIDEN signal
                                                                       protectors unlocked and under CPU control.*/



/* =============================================== Struct UICR_SECUREAPPROTECT =============================================== */
/**
  * @brief SECUREAPPROTECT [UICR_SECUREAPPROTECT] Access Port Protection Registers
  */
typedef struct {
  __IOM uint32_t  PROTECT0;                          /*!< (@ 0x00000000) Access port protection                                */
  __IM  uint32_t  RESERVED[6];
  __IOM uint32_t  PROTECT1;                          /*!< (@ 0x0000001C) Access port protection register                       */
} NRF_UICR_SECUREAPPROTECT_Type;                     /*!< Size = 32 (0x020)                                                    */
  #define UICR_SECUREAPPROTECT_MaxCount (1UL)        /*!< Size of SECUREAPPROTECT[1] array.                                    */
  #define UICR_SECUREAPPROTECT_MaxIndex (0UL)        /*!< Max index of SECUREAPPROTECT[1] array.                               */
  #define UICR_SECUREAPPROTECT_MinIndex (0UL)        /*!< Min index of SECUREAPPROTECT[1] array.                               */

/* UICR_SECUREAPPROTECT_PROTECT0: Access port protection */
  #define UICR_SECUREAPPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register.                       */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Pos (0UL) /*!< Position of PALL field.                                            */
  #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL
                                                                            field.*/
  #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field.                       */
  #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field.                       */
  #define UICR_SECUREAPPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN
                                                                            signal protectors unlocked and under CPU control.*/


/* UICR_SECUREAPPROTECT_PROTECT1: Access port protection register */
  #define UICR_SECUREAPPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register.                       */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Pos (0UL) /*!< Position of PALL field.                                            */
  #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL
                                                                            field.*/
  #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field.                       */
  #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field.                       */
  #define UICR_SECUREAPPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.DOMAIN SPIDEN and SPNIDEN
                                                                            signal protectors unlocked and under CPU control.*/



/* ================================================ Struct UICR_AUXAPPROTECT ================================================= */
/**
  * @brief AUXAPPROTECT [UICR_AUXAPPROTECT] Access Port Protection Registers
  */
typedef struct {
  __IOM uint32_t  PROTECT0;                          /*!< (@ 0x00000000) Access port protection                                */
  __IM  uint32_t  RESERVED[6];
  __IOM uint32_t  PROTECT1;                          /*!< (@ 0x0000001C) Access port protection register                       */
} NRF_UICR_AUXAPPROTECT_Type;                        /*!< Size = 32 (0x020)                                                    */
  #define UICR_AUXAPPROTECT_MaxCount (1UL)           /*!< Size of AUXAPPROTECT[1] array.                                       */
  #define UICR_AUXAPPROTECT_MaxIndex (0UL)           /*!< Max index of AUXAPPROTECT[1] array.                                  */
  #define UICR_AUXAPPROTECT_MinIndex (0UL)           /*!< Min index of AUXAPPROTECT[1] array.                                  */

/* UICR_AUXAPPROTECT_PROTECT0: Access port protection */
  #define UICR_AUXAPPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register.                          */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_AUXAPPROTECT_PROTECT0_PALL_Pos (0UL)  /*!< Position of PALL field.                                              */
  #define UICR_AUXAPPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_AUXAPPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL
                                                                            field.*/
  #define UICR_AUXAPPROTECT_PROTECT0_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field.                          */
  #define UICR_AUXAPPROTECT_PROTECT0_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field.                          */
  #define UICR_AUXAPPROTECT_PROTECT0_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.AP DBGEN signal protector
                                                                          unlocked and under CPU control.*/


/* UICR_AUXAPPROTECT_PROTECT1: Access port protection register */
  #define UICR_AUXAPPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register.                          */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_AUXAPPROTECT_PROTECT1_PALL_Pos (0UL)  /*!< Position of PALL field.                                              */
  #define UICR_AUXAPPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_AUXAPPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL
                                                                            field.*/
  #define UICR_AUXAPPROTECT_PROTECT1_PALL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PALL field.                          */
  #define UICR_AUXAPPROTECT_PROTECT1_PALL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PALL field.                          */
  #define UICR_AUXAPPROTECT_PROTECT1_PALL_Unprotected (0xFFFFFFFFUL) /*!< Leaves TAMPC PROTECT.AP DBGEN signal protector
                                                                          unlocked and under CPU control.*/



/* ================================================ Struct UICR_ERASEPROTECT ================================================= */
/**
  * @brief ERASEPROTECT [UICR_ERASEPROTECT] Erase Protection Registers
  */
typedef struct {
  __IOM uint32_t  PROTECT0;                          /*!< (@ 0x00000000) Erase protection                                      */
  __IM  uint32_t  RESERVED[6];
  __IOM uint32_t  PROTECT1;                          /*!< (@ 0x0000001C) Erase protection                                      */
} NRF_UICR_ERASEPROTECT_Type;                        /*!< Size = 32 (0x020)                                                    */
  #define UICR_ERASEPROTECT_MaxCount (1UL)           /*!< Size of ERASEPROTECT[1] array.                                       */
  #define UICR_ERASEPROTECT_MaxIndex (0UL)           /*!< Max index of ERASEPROTECT[1] array.                                  */
  #define UICR_ERASEPROTECT_MinIndex (0UL)           /*!< Min index of ERASEPROTECT[1] array.                                  */

/* UICR_ERASEPROTECT_PROTECT0: Erase protection */
  #define UICR_ERASEPROTECT_PROTECT0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT0 register.                          */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_ERASEPROTECT_PROTECT0_PALL_Pos (0UL)  /*!< Position of PALL field.                                              */
  #define UICR_ERASEPROTECT_PROTECT0_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PROTECT0_PALL_Pos) /*!< Bit mask of PALL
                                                                            field.*/
  #define UICR_ERASEPROTECT_PROTECT0_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field.                          */
  #define UICR_ERASEPROTECT_PROTECT0_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field.                          */
  #define UICR_ERASEPROTECT_PROTECT0_PALL_Protected (0x50FA50FAUL) /*!< Erase protection is enabled and the signal protector is
                                                                        locked.*/


/* UICR_ERASEPROTECT_PROTECT1: Erase protection */
  #define UICR_ERASEPROTECT_PROTECT1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PROTECT1 register.                          */

/* PALL @Bits 0..31 : (unspecified) */
  #define UICR_ERASEPROTECT_PROTECT1_PALL_Pos (0UL)  /*!< Position of PALL field.                                              */
  #define UICR_ERASEPROTECT_PROTECT1_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PROTECT1_PALL_Pos) /*!< Bit mask of PALL
                                                                            field.*/
  #define UICR_ERASEPROTECT_PROTECT1_PALL_Min (0x50FA50FAUL) /*!< Min enumerator value of PALL field.                          */
  #define UICR_ERASEPROTECT_PROTECT1_PALL_Max (0x50FA50FAUL) /*!< Max enumerator value of PALL field.                          */
  #define UICR_ERASEPROTECT_PROTECT1_PALL_Protected (0x50FA50FAUL) /*!< Erase protection is enabled and the signal protector is
                                                                        locked.*/



/* =============================================== Struct UICR_USER_ROT_PUBKEY =============================================== */
/**
  * @brief PUBKEY [UICR_USER_ROT_PUBKEY] (unspecified)
  */
typedef struct {
  __IOM uint32_t  DIGEST[8];                         /*!< (@ 0x00000000) First 256 bits of SHA2-512 digest over RoT public key
                                                                         generation [n].*/
  __IOM uint32_t  REVOKE[3];                         /*!< (@ 0x00000020) Revocation status for RoT public key generation [n].  */
} NRF_UICR_USER_ROT_PUBKEY_Type;                     /*!< Size = 44 (0x02C)                                                    */
  #define UICR_USER_ROT_PUBKEY_MaxCount (4UL)        /*!< Size of PUBKEY[4] array.                                             */
  #define UICR_USER_ROT_PUBKEY_MaxIndex (3UL)        /*!< Max index of PUBKEY[4] array.                                        */
  #define UICR_USER_ROT_PUBKEY_MinIndex (0UL)        /*!< Min index of PUBKEY[4] array.                                        */

/* UICR_USER_ROT_PUBKEY_DIGEST: First 256 bits of SHA2-512 digest over RoT public key generation [n]. */
  #define UICR_USER_ROT_PUBKEY_DIGEST_MaxCount (8UL) /*!< Max size of DIGEST[8] array.                                         */
  #define UICR_USER_ROT_PUBKEY_DIGEST_MaxIndex (7UL) /*!< Max index of DIGEST[8] array.                                        */
  #define UICR_USER_ROT_PUBKEY_DIGEST_MinIndex (0UL) /*!< Min index of DIGEST[8] array.                                        */
  #define UICR_USER_ROT_PUBKEY_DIGEST_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIGEST[8] register.                        */

/* VALUE @Bits 0..31 : Value for word [o] in the key digest [n]. */
  #define UICR_USER_ROT_PUBKEY_DIGEST_VALUE_Pos (0UL) /*!< Position of VALUE field.                                            */
  #define UICR_USER_ROT_PUBKEY_DIGEST_VALUE_Msk (0xFFFFFFFFUL << UICR_USER_ROT_PUBKEY_DIGEST_VALUE_Pos) /*!< Bit mask of VALUE
                                                                            field.*/


/* UICR_USER_ROT_PUBKEY_REVOKE: Revocation status for RoT public key generation [n]. */
  #define UICR_USER_ROT_PUBKEY_REVOKE_MaxCount (3UL) /*!< Max size of REVOKE[3] array.                                         */
  #define UICR_USER_ROT_PUBKEY_REVOKE_MaxIndex (2UL) /*!< Max index of REVOKE[3] array.                                        */
  #define UICR_USER_ROT_PUBKEY_REVOKE_MinIndex (0UL) /*!< Min index of REVOKE[3] array.                                        */
  #define UICR_USER_ROT_PUBKEY_REVOKE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of REVOKE[3] register.                        */

/* STATUS @Bits 0..31 : Revocation status. */
  #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Pos (0UL) /*!< Position of STATUS field.                                          */
  #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Msk (0xFFFFFFFFUL << UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Pos) /*!< Bit mask of
                                                                            STATUS field.*/
  #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Min (0xFFFFFFFFUL) /*!< Min enumerator value of STATUS field.                     */
  #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_Max (0xFFFFFFFFUL) /*!< Max enumerator value of STATUS field.                     */
  #define UICR_USER_ROT_PUBKEY_REVOKE_STATUS_NotRevoked (0xFFFFFFFFUL) /*!< Key not revoked.                                   */



/* ============================================= Struct UICR_USER_ROT_AUTHOPKEY ============================================== */
/**
  * @brief AUTHOPKEY [UICR_USER_ROT_AUTHOPKEY] (unspecified)
  */
typedef struct {
  __IOM uint32_t  DIGEST[8];                         /*!< (@ 0x00000000) First 256 bits of SHA2-512 digest over RoT
                                                                         authenticated operation public key generation [n].*/
  __IOM uint32_t  REVOKE[3];                         /*!< (@ 0x00000020) Revocation status for RoT authenticated operation
                                                                         public key generation [n].*/
} NRF_UICR_USER_ROT_AUTHOPKEY_Type;                  /*!< Size = 44 (0x02C)                                                    */
  #define UICR_USER_ROT_AUTHOPKEY_MaxCount (4UL)     /*!< Size of AUTHOPKEY[4] array.                                          */
  #define UICR_USER_ROT_AUTHOPKEY_MaxIndex (3UL)     /*!< Max index of AUTHOPKEY[4] array.                                     */
  #define UICR_USER_ROT_AUTHOPKEY_MinIndex (0UL)     /*!< Min index of AUTHOPKEY[4] array.                                     */

/* UICR_USER_ROT_AUTHOPKEY_DIGEST: First 256 bits of SHA2-512 digest over RoT authenticated operation public key generation [n].
                                    */

  #define UICR_USER_ROT_AUTHOPKEY_DIGEST_MaxCount (8UL) /*!< Max size of DIGEST[8] array.                                      */
  #define UICR_USER_ROT_AUTHOPKEY_DIGEST_MaxIndex (7UL) /*!< Max index of DIGEST[8] array.                                     */
  #define UICR_USER_ROT_AUTHOPKEY_DIGEST_MinIndex (0UL) /*!< Min index of DIGEST[8] array.                                     */
  #define UICR_USER_ROT_AUTHOPKEY_DIGEST_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIGEST[8] register.                     */

/* VALUE @Bits 0..31 : Value for word [o] in the key digest [n]. */
  #define UICR_USER_ROT_AUTHOPKEY_DIGEST_VALUE_Pos (0UL) /*!< Position of VALUE field.                                         */
  #define UICR_USER_ROT_AUTHOPKEY_DIGEST_VALUE_Msk (0xFFFFFFFFUL << UICR_USER_ROT_AUTHOPKEY_DIGEST_VALUE_Pos) /*!< Bit mask of
                                                                            VALUE field.*/


/* UICR_USER_ROT_AUTHOPKEY_REVOKE: Revocation status for RoT authenticated operation public key generation [n]. */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_MaxCount (3UL) /*!< Max size of REVOKE[3] array.                                      */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_MaxIndex (2UL) /*!< Max index of REVOKE[3] array.                                     */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_MinIndex (0UL) /*!< Min index of REVOKE[3] array.                                     */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of REVOKE[3] register.                     */

/* STATUS @Bits 0..31 : Revocation status. */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Pos (0UL) /*!< Position of STATUS field.                                       */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Msk (0xFFFFFFFFUL << UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Pos) /*!< Bit mask of
                                                                            STATUS field.*/
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Min (0xFFFFFFFFUL) /*!< Min enumerator value of STATUS field.                  */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_Max (0xFFFFFFFFUL) /*!< Max enumerator value of STATUS field.                  */
  #define UICR_USER_ROT_AUTHOPKEY_REVOKE_STATUS_NotRevoked (0xFFFFFFFFUL) /*!< Key not revoked.                                */



/* ================================================== Struct UICR_USER_ROT =================================================== */
/**
  * @brief ROT [UICR_USER_ROT] Assets installed to establish initial Root of Trust in the device.
  */
typedef struct {
  __IOM NRF_UICR_USER_ROT_PUBKEY_Type PUBKEY[4];     /*!< (@ 0x00000000) (unspecified)                                         */
  __IOM NRF_UICR_USER_ROT_AUTHOPKEY_Type AUTHOPKEY[4]; /*!< (@ 0x000000B0) (unspecified)                                       */
} NRF_UICR_USER_ROT_Type;                            /*!< Size = 352 (0x160)                                                   */


/* ==================================================== Struct UICR_USER ===================================================== */
/**
  * @brief USER [UICR_USER] (unspecified)
  */
typedef struct {
  __IOM NRF_UICR_USER_ROT_Type ROT;                  /*!< (@ 0x00000000) Assets installed to establish initial Root of Trust in
                                                                         the device.*/
} NRF_UICR_USER_Type;                                /*!< Size = 352 (0x160)                                                   */

/* ======================================================= Struct UICR ======================================================= */
/**
  * @brief User Information Configuration Registers
  */
  typedef struct {                                   /*!< UICR Structure                                                       */
    __IOM NRF_UICR_APPROTECT_Type APPROTECT[1];      /*!< (@ 0x00000000) Access Port Protection Registers                      */
    __IOM NRF_UICR_SECUREAPPROTECT_Type SECUREAPPROTECT[1]; /*!< (@ 0x00000020) Access Port Protection Registers               */
    __IOM NRF_UICR_AUXAPPROTECT_Type AUXAPPROTECT[1]; /*!< (@ 0x00000040) Access Port Protection Registers                     */
    __IOM NRF_UICR_ERASEPROTECT_Type ERASEPROTECT[1]; /*!< (@ 0x00000060) Erase Protection Registers                           */
    __IOM uint32_t BOOTCONF;                         /*!< (@ 0x00000080) Immutable boot region configuration.                  */
    __IM uint32_t RESERVED[95];
    __IOM NRF_UICR_USER_Type USER;                   /*!< (@ 0x00000200) (unspecified)                                         */
    __IM uint32_t RESERVED1[104];
    __IOM uint32_t OTP[320];                         /*!< (@ 0x00000500) One time programmable memory                          */
  } NRF_UICR_Type;                                   /*!< Size = 2560 (0xA00)                                                  */

/* UICR_BOOTCONF: Immutable boot region configuration. */
  #define UICR_BOOTCONF_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of BOOTCONF register.                                    */

/* READ @Bit 0 : Read access. Must be enabled in order for the Arm Cortex CPU to start executing from RRAM. */
  #define UICR_BOOTCONF_READ_Pos (0UL)               /*!< Position of READ field.                                              */
  #define UICR_BOOTCONF_READ_Msk (0x1UL << UICR_BOOTCONF_READ_Pos) /*!< Bit mask of READ field.                                */
  #define UICR_BOOTCONF_READ_Min (0x0UL)             /*!< Min enumerator value of READ field.                                  */
  #define UICR_BOOTCONF_READ_Max (0x1UL)             /*!< Max enumerator value of READ field.                                  */
  #define UICR_BOOTCONF_READ_NotAllowed (0x0UL)      /*!< Reading from the region is not allowed.                              */
  #define UICR_BOOTCONF_READ_Allowed (0x1UL)         /*!< Reading from the region is allowed                                   */

/* WRITE @Bit 1 : Write access */
  #define UICR_BOOTCONF_WRITE_Pos (1UL)              /*!< Position of WRITE field.                                             */
  #define UICR_BOOTCONF_WRITE_Msk (0x1UL << UICR_BOOTCONF_WRITE_Pos) /*!< Bit mask of WRITE field.                             */
  #define UICR_BOOTCONF_WRITE_Min (0x0UL)            /*!< Min enumerator value of WRITE field.                                 */
  #define UICR_BOOTCONF_WRITE_Max (0x1UL)            /*!< Max enumerator value of WRITE field.                                 */
  #define UICR_BOOTCONF_WRITE_NotAllowed (0x0UL)     /*!< Writing to the region is not allowed                                 */
  #define UICR_BOOTCONF_WRITE_Allowed (0x1UL)        /*!< Writing to the region is allowed                                     */

/* EXECUTE @Bit 2 : Execute access */
  #define UICR_BOOTCONF_EXECUTE_Pos (2UL)            /*!< Position of EXECUTE field.                                           */
  #define UICR_BOOTCONF_EXECUTE_Msk (0x1UL << UICR_BOOTCONF_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.                       */
  #define UICR_BOOTCONF_EXECUTE_Min (0x0UL)          /*!< Min enumerator value of EXECUTE field.                               */
  #define UICR_BOOTCONF_EXECUTE_Max (0x1UL)          /*!< Max enumerator value of EXECUTE field.                               */
  #define UICR_BOOTCONF_EXECUTE_NotAllowed (0x0UL)   /*!< Executing code from the region is not allowed                        */
  #define UICR_BOOTCONF_EXECUTE_Allowed (0x1UL)      /*!< Executing code from the region is allowed                            */

/* SECURE @Bit 3 : Secure access */
  #define UICR_BOOTCONF_SECURE_Pos (3UL)             /*!< Position of SECURE field.                                            */
  #define UICR_BOOTCONF_SECURE_Msk (0x1UL << UICR_BOOTCONF_SECURE_Pos) /*!< Bit mask of SECURE field.                          */
  #define UICR_BOOTCONF_SECURE_Min (0x0UL)           /*!< Min enumerator value of SECURE field.                                */
  #define UICR_BOOTCONF_SECURE_Max (0x1UL)           /*!< Max enumerator value of SECURE field.                                */
  #define UICR_BOOTCONF_SECURE_NonSecure (0x0UL)     /*!< Both secure and non-secure access to region is allowed               */
  #define UICR_BOOTCONF_SECURE_Secure (0x1UL)        /*!< Only secure access to region is allowed                              */

/* WRITEONCE @Bit 12 : Write-once */
  #define UICR_BOOTCONF_WRITEONCE_Pos (12UL)         /*!< Position of WRITEONCE field.                                         */
  #define UICR_BOOTCONF_WRITEONCE_Msk (0x1UL << UICR_BOOTCONF_WRITEONCE_Pos) /*!< Bit mask of WRITEONCE field.                 */
  #define UICR_BOOTCONF_WRITEONCE_Min (0x0UL)        /*!< Min enumerator value of WRITEONCE field.                             */
  #define UICR_BOOTCONF_WRITEONCE_Max (0x1UL)        /*!< Max enumerator value of WRITEONCE field.                             */
  #define UICR_BOOTCONF_WRITEONCE_Disabled (0x0UL)   /*!< Write-once disabled                                                  */
  #define UICR_BOOTCONF_WRITEONCE_Enabled (0x1UL)    /*!< Write-once enabled                                                   */

/* LOCK @Bit 13 : Enable lock of configuration register */
  #define UICR_BOOTCONF_LOCK_Pos (13UL)              /*!< Position of LOCK field.                                              */
  #define UICR_BOOTCONF_LOCK_Msk (0x1UL << UICR_BOOTCONF_LOCK_Pos) /*!< Bit mask of LOCK field.                                */
  #define UICR_BOOTCONF_LOCK_Min (0x0UL)             /*!< Min enumerator value of LOCK field.                                  */
  #define UICR_BOOTCONF_LOCK_Max (0x1UL)             /*!< Max enumerator value of LOCK field.                                  */
  #define UICR_BOOTCONF_LOCK_Disabled (0x0UL)        /*!< Lock is disabled, and the RRAMC region configuration registers for the
                                                          immutable boot region are writable.*/
  #define UICR_BOOTCONF_LOCK_Enabled (0x1UL)         /*!< Lock is enabled, and the RRAMC configuration registers for the
                                                          immutable boot region are read-only.*/

/* SIZE @Bits 16..20 : Immutable boot region size */
  #define UICR_BOOTCONF_SIZE_Pos (16UL)              /*!< Position of SIZE field.                                              */
  #define UICR_BOOTCONF_SIZE_Msk (0x1FUL << UICR_BOOTCONF_SIZE_Pos) /*!< Bit mask of SIZE field.                               */


/* UICR_OTP: One time programmable memory */
  #define UICR_OTP_MaxCount (320UL)                  /*!< Max size of OTP[320] array.                                          */
  #define UICR_OTP_MaxIndex (319UL)                  /*!< Max index of OTP[320] array.                                         */
  #define UICR_OTP_MinIndex (0UL)                    /*!< Min index of OTP[320] array.                                         */
  #define UICR_OTP_ResetValue (0xFFFFFFFFUL)         /*!< Reset value of OTP[320] register.                                    */

/* OTP @Bits 0..31 : OTP word */
  #define UICR_OTP_OTP_Pos (0UL)                     /*!< Position of OTP field.                                               */
  #define UICR_OTP_OTP_Msk (0xFFFFFFFFUL << UICR_OTP_OTP_Pos) /*!< Bit mask of OTP field.                                      */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                      VDMADESCRIPTOR                                      ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ================================================== Struct VDMADESCRIPTOR ================================================== */
/**
  * @brief Job descriptor for vector-based DMA.
  */
  typedef struct {                                   /*!< VDMADESCRIPTOR Structure                                             */
    __IOM uint32_t PTR;                              /*!< (@ 0x00000000) Pointer to data buffer.                               */
    __IOM uint32_t CONFIG;                           /*!< (@ 0x00000004) Job configuration. Configuration of attributes and
                                                                         buffer length.*/
  } NRF_VDMADESCRIPTOR_Type;                         /*!< Size = 8 (0x008)                                                     */

/* VDMADESCRIPTOR_PTR: Pointer to data buffer. */
  #define VDMADESCRIPTOR_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register.                                       */

/* PTR @Bits 0..31 : Pointer to data buffer. */
  #define VDMADESCRIPTOR_PTR_PTR_Pos (0UL)           /*!< Position of PTR field.                                               */
  #define VDMADESCRIPTOR_PTR_PTR_Msk (0xFFFFFFFFUL << VDMADESCRIPTOR_PTR_PTR_Pos) /*!< Bit mask of PTR field.                  */


/* VDMADESCRIPTOR_CONFIG: Job configuration. Configuration of attributes and buffer length. */
  #define VDMADESCRIPTOR_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                                 */

/* CNT @Bits 0..23 : Maximum number of bytes in data buffer. */
  #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL)        /*!< Position of CNT field.                                               */
  #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field.              */

/* ATTRIBUTE @Bits 24..29 : Job attribute. */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field.                                         */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Msk (0x3FUL << VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos) /*!< Bit mask of ATTRIBUTE field.*/
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Min (0xBUL) /*!< Min enumerator value of ATTRIBUTE field.                            */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Max (0xEUL) /*!< Max enumerator value of ATTRIBUTE field.                            */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarHash (0x0BUL) /*!< Hash attribute                                                 */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarPrand (0x0CUL) /*!< Prand attribute                                               */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_AarIrk (0x0DUL) /*!< Irk attribute                                                   */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAlen (0x0BUL) /*!< Alen attribute                                                 */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMlen (0x0CUL) /*!< Mlen attribute                                                 */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmAdata (0x0DUL) /*!< Adata attribute                                               */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_CcmMdata (0x0EUL) /*!< Mdata attribute                                               */
  #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_EcbData (0x0BUL) /*!< EcbData attribute                                              */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                            VPR                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */

/* =================================================== Struct VPR_DEBUGIF ==================================================== */
/**
  * @brief DEBUGIF [VPR_DEBUGIF] (unspecified)
  */
typedef struct {
  __IM  uint32_t  RESERVED[4];
  __IOM uint32_t  DATA0;                             /*!< (@ 0x00000010) Abstract Data 0. Read/write data for argument 0       */
  __IOM uint32_t  DATA1;                             /*!< (@ 0x00000014) Abstract Data 1. Read/write data for argument 1       */
  __IM  uint32_t  RESERVED1[10];
  __IOM uint32_t  DMCONTROL;                         /*!< (@ 0x00000040) Debug Module Control                                  */
  __IM  uint32_t  DMSTATUS;                          /*!< (@ 0x00000044) Debug Module Status                                   */
  __IOM uint32_t  HARTINFO;                          /*!< (@ 0x00000048) Hart Information                                      */
  __IOM uint32_t  HALTSUM1;                          /*!< (@ 0x0000004C) Halt Summary 1                                        */
  __IOM uint32_t  HAWINDOWSEL;                       /*!< (@ 0x00000050) Hart Array Window Select                              */
  __IOM uint32_t  HAWINDOW;                          /*!< (@ 0x00000054) Hart Array Window                                     */
  __IOM uint32_t  ABSTRACTCS;                        /*!< (@ 0x00000058) Abstract Control and Status                           */
  __OM  uint32_t  ABSTRACTCMD;                       /*!< (@ 0x0000005C) Abstract command                                      */
  __IOM uint32_t  ABSTRACTAUTO;                      /*!< (@ 0x00000060) Abstract Command Autoexec                             */
  __IOM uint32_t  CONFSTRPTR[4];                     /*!< (@ 0x00000064) Configuration String Pointer [n]                      */
  __IOM uint32_t  NEXTDM;                            /*!< (@ 0x00000074) Next Debug Module                                     */
  __IM  uint32_t  RESERVED2[2];
  __IOM uint32_t  PROGBUF[16];                       /*!< (@ 0x00000080) Program Buffer [n]                                    */
  __IOM uint32_t  AUTHDATA;                          /*!< (@ 0x000000C0) Authentication Data                                   */
  __IM  uint32_t  RESERVED3[3];
  __IOM uint32_t  HALTSUM2;                          /*!< (@ 0x000000D0) Halt Summary 2                                        */
  __IOM uint32_t  HALTSUM3;                          /*!< (@ 0x000000D4) Halt Summary 3                                        */
  __IM  uint32_t  RESERVED4;
  __IOM uint32_t  SBADDRESS3;                        /*!< (@ 0x000000DC) System Bus Addres 127:96                              */
  __IOM uint32_t  SBCS;                              /*!< (@ 0x000000E0) System Bus Access Control and Status                  */
  __IOM uint32_t  SBADDRESS0;                        /*!< (@ 0x000000E4) System Bus Addres 31:0                                */
  __IOM uint32_t  SBADDRESS1;                        /*!< (@ 0x000000E8) System Bus Addres 63:32                               */
  __IOM uint32_t  SBADDRESS2;                        /*!< (@ 0x000000EC) System Bus Addres 95:64                               */
  __IOM uint32_t  SBDATA0;                           /*!< (@ 0x000000F0) System Bus Data 31:0                                  */
  __IOM uint32_t  SBDATA1;                           /*!< (@ 0x000000F4) System Bus Data 63:32                                 */
  __IOM uint32_t  SBDATA2;                           /*!< (@ 0x000000F8) System Bus Data 95:64                                 */
  __IOM uint32_t  SBDATA3;                           /*!< (@ 0x000000FC) System Bus Data 127:96                                */
  __IOM uint32_t  HALTSUM0;                          /*!< (@ 0x00000100) Halt summary 0                                        */
} NRF_VPR_DEBUGIF_Type;                              /*!< Size = 260 (0x104)                                                   */

/* VPR_DEBUGIF_DATA0: Abstract Data 0. Read/write data for argument 0 */
  #define VPR_DEBUGIF_DATA0_ResetValue (0x00000000UL) /*!< Reset value of DATA0 register.                                      */

/* DATA0 @Bits 0..31 : Abstract Data 0 */
  #define VPR_DEBUGIF_DATA0_DATA0_Pos (0UL)          /*!< Position of DATA0 field.                                             */
  #define VPR_DEBUGIF_DATA0_DATA0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA0_DATA0_Pos) /*!< Bit mask of DATA0 field.              */


/* VPR_DEBUGIF_DATA1: Abstract Data 1. Read/write data for argument 1 */
  #define VPR_DEBUGIF_DATA1_ResetValue (0x00000000UL) /*!< Reset value of DATA1 register.                                      */

/* DATA1 @Bits 0..31 : Abstract Data 1 */
  #define VPR_DEBUGIF_DATA1_DATA1_Pos (0UL)          /*!< Position of DATA1 field.                                             */
  #define VPR_DEBUGIF_DATA1_DATA1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA1_DATA1_Pos) /*!< Bit mask of DATA1 field.              */


/* VPR_DEBUGIF_DMCONTROL: Debug Module Control */
  #define VPR_DEBUGIF_DMCONTROL_ResetValue (0x00000000UL) /*!< Reset value of DMCONTROL register.                              */

/* DMACTIVE @Bit 0 : Reset signal for the debug module. */
  #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos (0UL)   /*!< Position of DMACTIVE field.                                          */
  #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos) /*!< Bit mask of DMACTIVE field.    */
  #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Min (0x0UL) /*!< Min enumerator value of DMACTIVE field.                              */
  #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Max (0x1UL) /*!< Max enumerator value of DMACTIVE field.                              */
  #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Disabled (0x0UL) /*!< Reset the debug module itself                                   */
  #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Enabled (0x1UL) /*!< Normal operation                                                 */

/* NDMRESET @Bit 1 : Reset signal output from the debug module to the system. */
  #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos (1UL)   /*!< Position of NDMRESET field.                                          */
  #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos) /*!< Bit mask of NDMRESET field.    */
  #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Min (0x0UL) /*!< Min enumerator value of NDMRESET field.                              */
  #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Max (0x1UL) /*!< Max enumerator value of NDMRESET field.                              */
  #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Inactive (0x0UL) /*!< Reset inactive                                                  */
  #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Active (0x1UL) /*!< Reset active                                                      */

/* CLRRESETHALTREQ @Bit 2 : Clear the halt on reset request. */
  #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos (2UL) /*!< Position of CLRRESETHALTREQ field.                              */
  #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos) /*!< Bit mask of
                                                                            CLRRESETHALTREQ field.*/
  #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of CLRRESETHALTREQ field.                */
  #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of CLRRESETHALTREQ field.                */
  #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0.                          */
  #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Clear (0x1UL) /*!< Clears the halt on reset request                            */

/* SETRESETHALTREQ @Bit 3 : Set the halt on reset request. */
  #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos (3UL) /*!< Position of SETRESETHALTREQ field.                              */
  #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos) /*!< Bit mask of
                                                                            SETRESETHALTREQ field.*/
  #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of SETRESETHALTREQ field.                */
  #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of SETRESETHALTREQ field.                */
  #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0.                          */
  #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Clear (0x1UL) /*!< Sets the halt on reset request                              */

/* HARTSELHI @Bits 6..15 : The high 10 bits of hartsel. */
  #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos (6UL)  /*!< Position of HARTSELHI field.                                         */
  #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos) /*!< Bit mask of HARTSELHI
                                                                            field.*/

/* HARTSELLO @Bits 16..25 : The low 10 bits of hartsel. */
  #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos (16UL) /*!< Position of HARTSELLO field.                                         */
  #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos) /*!< Bit mask of HARTSELLO
                                                                            field.*/

/* HASEL @Bit 26 : Definition of currently selected harts. */
  #define VPR_DEBUGIF_DMCONTROL_HASEL_Pos (26UL)     /*!< Position of HASEL field.                                             */
  #define VPR_DEBUGIF_DMCONTROL_HASEL_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HASEL_Pos) /*!< Bit mask of HASEL field.             */
  #define VPR_DEBUGIF_DMCONTROL_HASEL_Min (0x0UL)    /*!< Min enumerator value of HASEL field.                                 */
  #define VPR_DEBUGIF_DMCONTROL_HASEL_Max (0x1UL)    /*!< Max enumerator value of HASEL field.                                 */
  #define VPR_DEBUGIF_DMCONTROL_HASEL_Single (0x0UL) /*!< Single hart selected.                                                */
  #define VPR_DEBUGIF_DMCONTROL_HASEL_Multiple (0x1UL) /*!< Multiple harts selected                                            */

/* ACKHAVERESET @Bit 28 : Clear the havereset. */
  #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos (28UL) /*!< Position of ACKHAVERESET field.                                   */
  #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos) /*!< Bit mask of ACKHAVERESET
                                                                            field.*/
  #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Min (0x0UL) /*!< Min enumerator value of ACKHAVERESET field.                      */
  #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Max (0x1UL) /*!< Max enumerator value of ACKHAVERESET field.                      */
  #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_NoOperation (0x0UL) /*!< No operation when written 0.                             */
  #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Clear (0x1UL) /*!< Clears the havereset for selected harts.                       */

/* HARTRESET @Bit 29 : Reset harts. */
  #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos (29UL) /*!< Position of HARTRESET field.                                         */
  #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos) /*!< Bit mask of HARTRESET field. */
  #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Min (0x0UL) /*!< Min enumerator value of HARTRESET field.                            */
  #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Max (0x1UL) /*!< Max enumerator value of HARTRESET field.                            */
  #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Deasserted (0x0UL) /*!< Reset de-asserted.                                           */
  #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Asserted (0x1UL) /*!< Reset asserted.                                                */

/* RESUMEREQ @Bit 30 : Resume currently selected harts. */
  #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos (30UL) /*!< Position of RESUMEREQ field.                                         */
  #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos) /*!< Bit mask of RESUMEREQ field. */
  #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Min (0x0UL) /*!< Min enumerator value of RESUMEREQ field.                            */
  #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Max (0x1UL) /*!< Max enumerator value of RESUMEREQ field.                            */
  #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_NoOperation (0x0UL) /*!< No operation when written 0.                                */
  #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Resumed (0x1UL) /*!< Currently selected harts resumed.                               */

/* HALTREQ @Bit 31 : Halt currently selected harts. */
  #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos (31UL)   /*!< Position of HALTREQ field.                                           */
  #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos) /*!< Bit mask of HALTREQ field.       */
  #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Min (0x0UL)  /*!< Min enumerator value of HALTREQ field.                               */
  #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Max (0x1UL)  /*!< Max enumerator value of HALTREQ field.                               */
  #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Clear (0x0UL) /*!< Clears halt request bit for all currently selected harts.           */
  #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Halt (0x1UL) /*!< Currently selected harts halted.                                     */


/* VPR_DEBUGIF_DMSTATUS: Debug Module Status */
  #define VPR_DEBUGIF_DMSTATUS_ResetValue (0x00400082UL) /*!< Reset value of DMSTATUS register.                                */

/* VERSION @Bits 0..3 : Version of the debug module. */
  #define VPR_DEBUGIF_DMSTATUS_VERSION_Pos (0UL)     /*!< Position of VERSION field.                                           */
  #define VPR_DEBUGIF_DMSTATUS_VERSION_Msk (0xFUL << VPR_DEBUGIF_DMSTATUS_VERSION_Pos) /*!< Bit mask of VERSION field.         */
  #define VPR_DEBUGIF_DMSTATUS_VERSION_Min (0x0UL)   /*!< Min enumerator value of VERSION field.                               */
  #define VPR_DEBUGIF_DMSTATUS_VERSION_Max (0xFUL)   /*!< Max enumerator value of VERSION field.                               */
  #define VPR_DEBUGIF_DMSTATUS_VERSION_NotPresent (0x0UL) /*!< Debug module not present.                                       */
  #define VPR_DEBUGIF_DMSTATUS_VERSION_V011 (0x1UL)  /*!< There is a Debug Module and it conforms to version 0.11 of this
                                                          specifcation.*/
  #define VPR_DEBUGIF_DMSTATUS_VERSION_V013 (0x2UL)  /*!< There is a Debug Module and it conforms to version 0.13 of this
                                                          specifcation.*/
  #define VPR_DEBUGIF_DMSTATUS_VERSION_NonConform (0xFUL) /*!< There is a Debug Module but it does not conform to any available
                                                               version of the spec.*/

/* CONFSTRPTRVALID @Bit 4 : Configuration string. */
  #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos (4UL) /*!< Position of CONFSTRPTRVALID field.                               */
  #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos) /*!< Bit mask of
                                                                            CONFSTRPTRVALID field.*/
  #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Min (0x0UL) /*!< Min enumerator value of CONFSTRPTRVALID field.                 */
  #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Max (0x1UL) /*!< Max enumerator value of CONFSTRPTRVALID field.                 */
  #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_NotRelevant (0x0UL) /*!< The confstrptr0..confstrptr3 holds information which is
                                                                        not relevant to the configuration string.*/
  #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Address (0x1UL) /*!< The confstrptr0..confstrptr3 holds the address of the
                                                                    configuration string.*/

/* HASRESETHALTREQ @Bit 5 : Halt-on-reset support status. */
  #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos (5UL) /*!< Position of HASRESETHALTREQ field.                               */
  #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos) /*!< Bit mask of
                                                                            HASRESETHALTREQ field.*/
  #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of HASRESETHALTREQ field.                 */
  #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of HASRESETHALTREQ field.                 */
  #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_No (0x0UL) /*!< Halt-on-reset is supported.                                     */
  #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Yes (0x1UL) /*!< Halt-on-reset is not supported.                                */

/* AUTHBUSY @Bit 6 : Authentication busy status. */
  #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos (6UL)    /*!< Position of AUTHBUSY field.                                          */
  #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos) /*!< Bit mask of AUTHBUSY field.      */
  #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Min (0x0UL)  /*!< Min enumerator value of AUTHBUSY field.                              */
  #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Max (0x1UL)  /*!< Max enumerator value of AUTHBUSY field.                              */
  #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_No (0x0UL)   /*!< The authentication module is ready.                                  */
  #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Yes (0x1UL)  /*!< The authentication module is busy.                                   */

/* AUTHENTICATED @Bit 7 : Authentication status. */
  #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos (7UL) /*!< Position of AUTHENTICATED field.                                   */
  #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos) /*!< Bit mask of
                                                                            AUTHENTICATED field.*/
  #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Min (0x0UL) /*!< Min enumerator value of AUTHENTICATED field.                     */
  #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Max (0x1UL) /*!< Max enumerator value of AUTHENTICATED field.                     */
  #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_No (0x0UL) /*!< Authentication required before using the debug module.            */
  #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Yes (0x1UL) /*!< Authentication passed.                                           */

/* ANYHALTED @Bit 8 : Any currently selected harts halted status. */
  #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos (8UL)   /*!< Position of ANYHALTED field.                                         */
  #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos) /*!< Bit mask of ANYHALTED field.   */
  #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Min (0x0UL) /*!< Min enumerator value of ANYHALTED field.                             */
  #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Max (0x1UL) /*!< Max enumerator value of ANYHALTED field.                             */
  #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_No (0x0UL)  /*!< None of the currently selected harts halted.                         */
  #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Yes (0x1UL) /*!< Any of the currently selected harts halted.                          */

/* ALLHALTED @Bit 9 : All currently selected harts halted status. */
  #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos (9UL)   /*!< Position of ALLHALTED field.                                         */
  #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos) /*!< Bit mask of ALLHALTED field.   */
  #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Min (0x0UL) /*!< Min enumerator value of ALLHALTED field.                             */
  #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Max (0x1UL) /*!< Max enumerator value of ALLHALTED field.                             */
  #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_No (0x0UL)  /*!< Not all of the currently selected harts halted.                      */
  #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Yes (0x1UL) /*!< All of the currently selected harts halted.                          */

/* ANYRUNNING @Bit 10 : Any currently selected harts running status. */
  #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos (10UL) /*!< Position of ANYRUNNING field.                                        */
  #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos) /*!< Bit mask of ANYRUNNING field.*/
  #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Min (0x0UL) /*!< Min enumerator value of ANYRUNNING field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Max (0x1UL) /*!< Max enumerator value of ANYRUNNING field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_No (0x0UL) /*!< None of the currently selected harts running.                        */
  #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Yes (0x1UL) /*!< Any of the currently selected harts running.                        */

/* ALLRUNNING @Bit 11 : All currently selected harts running status. */
  #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos (11UL) /*!< Position of ALLRUNNING field.                                        */
  #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos) /*!< Bit mask of ALLRUNNING field.*/
  #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Min (0x0UL) /*!< Min enumerator value of ALLRUNNING field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Max (0x1UL) /*!< Max enumerator value of ALLRUNNING field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_No (0x0UL) /*!< Not all of the currently selected harts running.                     */
  #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Yes (0x1UL) /*!< All of the currently selected harts running.                        */

/* ANYUNAVAIL @Bit 12 : Any currently selected harts unavailable status. */
  #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos (12UL) /*!< Position of ANYUNAVAIL field.                                        */
  #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos) /*!< Bit mask of ANYUNAVAIL field.*/
  #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ANYUNAVAIL field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ANYUNAVAIL field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_No (0x0UL) /*!< None of the currently selected harts unavailable.                    */
  #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Yes (0x1UL) /*!< Any of the currently selected harts unavailable.                    */

/* ALLUNAVAIL @Bit 13 : All currently selected harts unavailable status. */
  #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos (13UL) /*!< Position of ALLUNAVAIL field.                                        */
  #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos) /*!< Bit mask of ALLUNAVAIL field.*/
  #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ALLUNAVAIL field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ALLUNAVAIL field.                           */
  #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_No (0x0UL) /*!< Not all of the currently selected harts unavailable.                 */
  #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Yes (0x1UL) /*!< All of the currently selected harts unavailable.                    */

/* ANYNONEXISTENT @Bit 14 : Any currently selected harts nonexistent status. */
  #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos (14UL) /*!< Position of ANYNONEXISTENT field.                                */
  #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos) /*!< Bit mask of
                                                                            ANYNONEXISTENT field.*/
  #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ANYNONEXISTENT field.                   */
  #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ANYNONEXISTENT field.                   */
  #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_No (0x0UL) /*!< None of the currently selected harts nonexistent.                */
  #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Yes (0x1UL) /*!< Any of the currently selected harts nonexistent.                */

/* ALLNONEXISTENT @Bit 15 : All currently selected harts nonexistent status. */
  #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos (15UL) /*!< Position of ALLNONEXISTENT field.                                */
  #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos) /*!< Bit mask of
                                                                            ALLNONEXISTENT field.*/
  #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ALLNONEXISTENT field.                   */
  #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ALLNONEXISTENT field.                   */
  #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_No (0x0UL) /*!< Not all of the currently selected harts nonexistent.             */
  #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Yes (0x1UL) /*!< All of the currently selected harts nonexistent.                */

/* ANYRESUMEACK @Bit 16 : Any currently selected harts acknowledged last resume request. */
  #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos (16UL) /*!< Position of ANYRESUMEACK field.                                    */
  #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos) /*!< Bit mask of ANYRESUMEACK
                                                                            field.*/
  #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ANYRESUMEACK field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ANYRESUMEACK field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_No (0x0UL) /*!< None of the currently selected harts acknowledged last resume
                                                            request.*/
  #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Yes (0x1UL) /*!< Any of the currently selected harts acknowledged last resume
                                                             request.*/

/* ALLRESUMEACK @Bit 17 : All currently selected harts acknowledged last resume */
  #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos (17UL) /*!< Position of ALLRESUMEACK field.                                    */
  #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos) /*!< Bit mask of ALLRESUMEACK
                                                                            field.*/
  #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ALLRESUMEACK field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ALLRESUMEACK field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_No (0x0UL) /*!< Not all of the currently selected harts acknowledged last resume
                                                            request.*/
  #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Yes (0x1UL) /*!< All of the currently selected harts acknowledged last resume
                                                             request.*/

/* ANYHAVERESET @Bit 18 : Any currently selected harts have been reset and reset is not acknowledged. */
  #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos (18UL) /*!< Position of ANYHAVERESET field.                                    */
  #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos) /*!< Bit mask of ANYHAVERESET
                                                                            field.*/
  #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Min (0x0UL) /*!< Min enumerator value of ANYHAVERESET field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Max (0x1UL) /*!< Max enumerator value of ANYHAVERESET field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_No (0x0UL) /*!< None of the currently selected harts have been reset and reset is
                                                            not acknowledget.*/
  #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Yes (0x1UL) /*!< Any of the currently selected harts have been reset and reset is
                                                             not acknowledge.*/

/* ALLHAVERESET @Bit 19 : All currently selected harts have been reset and reset is not acknowledge */
  #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos (19UL) /*!< Position of ALLHAVERESET field.                                    */
  #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos) /*!< Bit mask of ALLHAVERESET
                                                                            field.*/
  #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Min (0x0UL) /*!< Min enumerator value of ALLHAVERESET field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Max (0x1UL) /*!< Max enumerator value of ALLHAVERESET field.                       */
  #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_No (0x0UL) /*!< Not all of the currently selected harts have been reset and reset is
                                                            not acknowledge.*/
  #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Yes (0x1UL) /*!< All of the currently selected harts have been reset and reset is
                                                             not acknowledge.*/

/* IMPEBREAK @Bit 22 : Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. */
  #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos (22UL)  /*!< Position of IMPEBREAK field.                                         */
  #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos) /*!< Bit mask of IMPEBREAK field.   */
  #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Min (0x0UL) /*!< Min enumerator value of IMPEBREAK field.                             */
  #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Max (0x1UL) /*!< Max enumerator value of IMPEBREAK field.                             */
  #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_No (0x0UL)  /*!< No implicit ebreak instruction.                                      */
  #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Yes (0x1UL) /*!< Implicit ebreak instruction.                                         */


/* VPR_DEBUGIF_HARTINFO: Hart Information */
  #define VPR_DEBUGIF_HARTINFO_ResetValue (0x00000000UL) /*!< Reset value of HARTINFO register.                                */

/* DATAADDR @Bits 0..11 : Data Address */
  #define VPR_DEBUGIF_HARTINFO_DATAADDR_Pos (0UL)    /*!< Position of DATAADDR field.                                          */
  #define VPR_DEBUGIF_HARTINFO_DATAADDR_Msk (0xFFFUL << VPR_DEBUGIF_HARTINFO_DATAADDR_Pos) /*!< Bit mask of DATAADDR field.    */
  #define VPR_DEBUGIF_HARTINFO_DATAADDR_Min (0x800UL) /*!< Min value of DATAADDR field.                                        */
  #define VPR_DEBUGIF_HARTINFO_DATAADDR_Max (0x7FFUL) /*!< Max size of DATAADDR field.                                         */

/* DATASIZE @Bits 12..15 : Data Size */
  #define VPR_DEBUGIF_HARTINFO_DATASIZE_Pos (12UL)   /*!< Position of DATASIZE field.                                          */
  #define VPR_DEBUGIF_HARTINFO_DATASIZE_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_DATASIZE_Pos) /*!< Bit mask of DATASIZE field.      */
  #define VPR_DEBUGIF_HARTINFO_DATASIZE_Min (0x0UL)  /*!< Min value of DATASIZE field.                                         */
  #define VPR_DEBUGIF_HARTINFO_DATASIZE_Max (0xCUL)  /*!< Max size of DATASIZE field.                                          */

/* DATAACCESS @Bit 16 : Data Access */
  #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos (16UL) /*!< Position of DATAACCESS field.                                        */
  #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Msk (0x1UL << VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos) /*!< Bit mask of DATAACCESS field.*/
  #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Min (0x0UL) /*!< Min enumerator value of DATAACCESS field.                           */
  #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Max (0x1UL) /*!< Max enumerator value of DATAACCESS field.                           */
  #define VPR_DEBUGIF_HARTINFO_DATAACCESS_No (0x0UL) /*!< The data registers are shadowed in the hart by CSRs. Each CSR is DXLEN
                                                          bits in size, and corresponds to a single argument.*/
  #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Yes (0x1UL) /*!< The data registers are shadowed in the hart's memory map. Each
                                                           register takes up 4 bytes in the memory map.*/

/* NSCRATCH @Bits 20..23 : Number of dscratch registers */
  #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos (20UL)   /*!< Position of NSCRATCH field.                                          */
  #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos) /*!< Bit mask of NSCRATCH field.      */


/* VPR_DEBUGIF_HALTSUM1: Halt Summary 1 */
  #define VPR_DEBUGIF_HALTSUM1_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM1 register.                                */

/* HALTSUM1 @Bits 0..31 : Halt Summary 1 */
  #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos (0UL)    /*!< Position of HALTSUM1 field.                                          */
  #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos) /*!< Bit mask of HALTSUM1
                                                                            field.*/


/* VPR_DEBUGIF_HAWINDOWSEL: Hart Array Window Select */
  #define VPR_DEBUGIF_HAWINDOWSEL_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOWSEL register.                          */

/* HAWINDOWSEL @Bits 0..14 : The high bits of this field may be tied to 0, depending on how large the array mask register is.
                             E.g. on a system with 48 harts only bit 0 of this field may actually be writable. */

  #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos (0UL) /*!< Position of HAWINDOWSEL field.                                    */
  #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Msk (0x7FFFUL << VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos) /*!< Bit mask of
                                                                            HAWINDOWSEL field.*/


/* VPR_DEBUGIF_HAWINDOW: Hart Array Window */
  #define VPR_DEBUGIF_HAWINDOW_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOW register.                                */

/* MASKDATA @Bits 0..31 : Mask data. */
  #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos (0UL)    /*!< Position of MASKDATA field.                                          */
  #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos) /*!< Bit mask of MASKDATA
                                                                            field.*/


/* VPR_DEBUGIF_ABSTRACTCS: Abstract Control and Status */
  #define VPR_DEBUGIF_ABSTRACTCS_ResetValue (0x01000002UL) /*!< Reset value of ABSTRACTCS register.                            */

/* DATACOUNT @Bits 0..3 : Number of data registers that are implemented as part of the abstract command interface. Valid sizes
                          are 1..12. */

  #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos (0UL) /*!< Position of DATACOUNT field.                                         */
  #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Msk (0xFUL << VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos) /*!< Bit mask of DATACOUNT
                                                                            field.*/

/* CMDERR @Bits 8..10 : Command error when the abstract command fails. */
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos (8UL)    /*!< Position of CMDERR field.                                            */
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Msk (0x7UL << VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos) /*!< Bit mask of CMDERR field.        */
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Min (0x0UL)  /*!< Min enumerator value of CMDERR field.                                */
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Max (0x7UL)  /*!< Max enumerator value of CMDERR field.                                */
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NoError (0x0UL) /*!< No error.                                                         */
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Busy (0x1UL) /*!< An abstract command was executing while command, abstractcs, or
                                                          abstractauto was written, or when one of the data or progbuf registers
                                                          was read or written. This status is only written if cmderr contains 0*/
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NotSupported (0x2UL) /*!< The requested command is notsupported, regardless of whether
                                                                  the hart is running or not.*/
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Exception (0x3UL) /*!< An exception occurred while executing the command (e.g. while
                                                               executing theProgram Buffer).*/
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_HaltResume (0x4UL) /*!< The abstract command couldn't execute because the hart wasn't in
                                                                the required state (running/halted). or unavailable.*/
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Bus (0x5UL)  /*!< The abstract command failed due to abus error (e.g. alignment, access
                                                          size, or timeout).*/
  #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Other (0x7UL) /*!< The command failed for another reason.                              */

/* BUSY @Bit 12 : Abstract command execution status. */
  #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos (12UL)     /*!< Position of BUSY field.                                              */
  #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Msk (0x1UL << VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos) /*!< Bit mask of BUSY field.              */
  #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Min (0x0UL)    /*!< Min enumerator value of BUSY field.                                  */
  #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Max (0x1UL)    /*!< Max enumerator value of BUSY field.                                  */
  #define VPR_DEBUGIF_ABSTRACTCS_BUSY_NotBusy (0x0UL) /*!< Not busy.                                                           */
  #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Busy (0x1UL)   /*!< An abstract command is currently being executed. This bit is set as
                                                          soon as command is written, and is not cleared until that command has
                                                          completed.*/

/* PROGBUFSIZE @Bits 24..28 : Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. */
  #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos (24UL) /*!< Position of PROGBUFSIZE field.                                    */
  #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Msk (0x1FUL << VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos) /*!< Bit mask of PROGBUFSIZE
                                                                            field.*/


/* VPR_DEBUGIF_ABSTRACTCMD: Abstract command */
  #define VPR_DEBUGIF_ABSTRACTCMD_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTCMD register.                          */

/* CONTROL @Bits 0..23 : This Field is interpreted in a command specific manner, described for each abstract command. */
  #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos (0UL)  /*!< Position of CONTROL field.                                           */
  #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Msk (0xFFFFFFUL << VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos) /*!< Bit mask of CONTROL
                                                                            field.*/

/* CMDTYPE @Bits 24..31 : The type determines the overall functionality of this abstract command. */
  #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos (24UL) /*!< Position of CMDTYPE field.                                           */
  #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Msk (0xFFUL << VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos) /*!< Bit mask of CMDTYPE field.  */
  #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Min (0x0UL) /*!< Min enumerator value of CMDTYPE field.                              */
  #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Max (0x2UL) /*!< Max enumerator value of CMDTYPE field.                              */
  #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_REGACCESS (0x00UL) /*!< Register Access Command                                      */
  #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_QUICKACCESS (0x01UL) /*!< Quick Access Command                                       */
  #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_MEMACCESS (0x02UL) /*!< Memory Access Command                                        */


/* VPR_DEBUGIF_ABSTRACTAUTO: Abstract Command Autoexec */
  #define VPR_DEBUGIF_ABSTRACTAUTO_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTAUTO register.                        */

/* AUTOEXECDATA @Bits 0..11 : When a bit in this field is 1, read or write accesses to the corresponding data word cause the
                              command in command to be executed again. */

  #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos (0UL) /*!< Position of AUTOEXECDATA field.                                 */
  #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Msk (0xFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos) /*!< Bit mask of
                                                                            AUTOEXECDATA field.*/

/* AUTOEXECPROGBUF @Bits 16..31 : When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause
                                  the command in command to be executed again. */

  #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos (16UL) /*!< Position of AUTOEXECPROGBUF field.                          */
  #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Msk (0xFFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos) /*!< Bit mask
                                                                            of AUTOEXECPROGBUF field.*/


/* VPR_DEBUGIF_CONFSTRPTR: Configuration String Pointer [n] */
  #define VPR_DEBUGIF_CONFSTRPTR_MaxCount (4UL)      /*!< Max size of CONFSTRPTR[4] array.                                     */
  #define VPR_DEBUGIF_CONFSTRPTR_MaxIndex (3UL)      /*!< Max index of CONFSTRPTR[4] array.                                    */
  #define VPR_DEBUGIF_CONFSTRPTR_MinIndex (0UL)      /*!< Min index of CONFSTRPTR[4] array.                                    */
  #define VPR_DEBUGIF_CONFSTRPTR_ResetValue (0x00000000UL) /*!< Reset value of CONFSTRPTR[4] register.                         */

/* ADDR @Bits 0..31 : Address */
  #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos (0UL)      /*!< Position of ADDR field.                                              */
  #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos) /*!< Bit mask of ADDR field.       */


/* VPR_DEBUGIF_NEXTDM: Next Debug Module */
  #define VPR_DEBUGIF_NEXTDM_ResetValue (0x00000000UL) /*!< Reset value of NEXTDM register.                                    */

/* ADDR @Bits 0..31 : Address */
  #define VPR_DEBUGIF_NEXTDM_ADDR_Pos (0UL)          /*!< Position of ADDR field.                                              */
  #define VPR_DEBUGIF_NEXTDM_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_NEXTDM_ADDR_Pos) /*!< Bit mask of ADDR field.               */


/* VPR_DEBUGIF_PROGBUF: Program Buffer [n] */
  #define VPR_DEBUGIF_PROGBUF_MaxCount (16UL)        /*!< Max size of PROGBUF[16] array.                                       */
  #define VPR_DEBUGIF_PROGBUF_MaxIndex (15UL)        /*!< Max index of PROGBUF[16] array.                                      */
  #define VPR_DEBUGIF_PROGBUF_MinIndex (0UL)         /*!< Min index of PROGBUF[16] array.                                      */
  #define VPR_DEBUGIF_PROGBUF_ResetValue (0x00000000UL) /*!< Reset value of PROGBUF[16] register.                              */

/* DATA @Bits 0..31 : Data */
  #define VPR_DEBUGIF_PROGBUF_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define VPR_DEBUGIF_PROGBUF_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_PROGBUF_DATA_Pos) /*!< Bit mask of DATA field.             */


/* VPR_DEBUGIF_AUTHDATA: Authentication Data */
  #define VPR_DEBUGIF_AUTHDATA_ResetValue (0x00000000UL) /*!< Reset value of AUTHDATA register.                                */

/* DATA @Bits 0..31 : Data */
  #define VPR_DEBUGIF_AUTHDATA_DATA_Pos (0UL)        /*!< Position of DATA field.                                              */
  #define VPR_DEBUGIF_AUTHDATA_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_AUTHDATA_DATA_Pos) /*!< Bit mask of DATA field.           */


/* VPR_DEBUGIF_HALTSUM2: Halt Summary 2 */
  #define VPR_DEBUGIF_HALTSUM2_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM2 register.                                */

/* HALTSUM2 @Bits 0..31 : Halt Summary 2 */
  #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos (0UL)    /*!< Position of HALTSUM2 field.                                          */
  #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos) /*!< Bit mask of HALTSUM2
                                                                            field.*/


/* VPR_DEBUGIF_HALTSUM3: Halt Summary 3 */
  #define VPR_DEBUGIF_HALTSUM3_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM3 register.                                */

/* HALTSUM3 @Bits 0..31 : Halt Summary 3 */
  #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos (0UL)    /*!< Position of HALTSUM3 field.                                          */
  #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos) /*!< Bit mask of HALTSUM3
                                                                            field.*/


/* VPR_DEBUGIF_SBADDRESS3: System Bus Addres 127:96 */
  #define VPR_DEBUGIF_SBADDRESS3_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS3 register.                            */

/* ADDRESS @Bits 0..31 : Accesses bits 127:96 of the physical address in sbaddress (if the system address bus is that wide). */
  #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
  #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos) /*!< Bit mask of ADDRESS
                                                                            field.*/


/* VPR_DEBUGIF_SBCS: System Bus Access Control and Status */
  #define VPR_DEBUGIF_SBCS_ResetValue (0x20000000UL) /*!< Reset value of SBCS register.                                        */

/* SBACCESS8 @Bit 0 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBACCESS8_Pos (0UL)       /*!< Position of SBACCESS8 field.                                         */
  #define VPR_DEBUGIF_SBCS_SBACCESS8_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS8_Pos) /*!< Bit mask of SBACCESS8 field.           */
  #define VPR_DEBUGIF_SBCS_SBACCESS8_Min (0x1UL)     /*!< Min enumerator value of SBACCESS8 field.                             */
  #define VPR_DEBUGIF_SBCS_SBACCESS8_Max (0x1UL)     /*!< Max enumerator value of SBACCESS8 field.                             */
  #define VPR_DEBUGIF_SBCS_SBACCESS8_sbaccess8 (0x1UL) /*!< 8-bit system bus accesses are supported.                           */

/* SBACCESS16 @Bit 1 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBACCESS16_Pos (1UL)      /*!< Position of SBACCESS16 field.                                        */
  #define VPR_DEBUGIF_SBCS_SBACCESS16_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS16_Pos) /*!< Bit mask of SBACCESS16 field.        */
  #define VPR_DEBUGIF_SBCS_SBACCESS16_Min (0x1UL)    /*!< Min enumerator value of SBACCESS16 field.                            */
  #define VPR_DEBUGIF_SBCS_SBACCESS16_Max (0x1UL)    /*!< Max enumerator value of SBACCESS16 field.                            */
  #define VPR_DEBUGIF_SBCS_SBACCESS16_sbaccess16 (0x1UL) /*!< 16-bit system bus accesses are supported.                        */

/* SBACCESS32 @Bit 2 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBACCESS32_Pos (2UL)      /*!< Position of SBACCESS32 field.                                        */
  #define VPR_DEBUGIF_SBCS_SBACCESS32_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS32_Pos) /*!< Bit mask of SBACCESS32 field.        */
  #define VPR_DEBUGIF_SBCS_SBACCESS32_Min (0x1UL)    /*!< Min enumerator value of SBACCESS32 field.                            */
  #define VPR_DEBUGIF_SBCS_SBACCESS32_Max (0x1UL)    /*!< Max enumerator value of SBACCESS32 field.                            */
  #define VPR_DEBUGIF_SBCS_SBACCESS32_sbaccess32 (0x1UL) /*!< 32-bit system bus accesses are supported.                        */

/* SBACCESS64 @Bit 3 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBACCESS64_Pos (3UL)      /*!< Position of SBACCESS64 field.                                        */
  #define VPR_DEBUGIF_SBCS_SBACCESS64_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS64_Pos) /*!< Bit mask of SBACCESS64 field.        */
  #define VPR_DEBUGIF_SBCS_SBACCESS64_Min (0x1UL)    /*!< Min enumerator value of SBACCESS64 field.                            */
  #define VPR_DEBUGIF_SBCS_SBACCESS64_Max (0x1UL)    /*!< Max enumerator value of SBACCESS64 field.                            */
  #define VPR_DEBUGIF_SBCS_SBACCESS64_sbaccess64 (0x1UL) /*!< 64-bit system bus accesses are supported.                        */

/* SBACCESS128 @Bit 4 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBACCESS128_Pos (4UL)     /*!< Position of SBACCESS128 field.                                       */
  #define VPR_DEBUGIF_SBCS_SBACCESS128_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS128_Pos) /*!< Bit mask of SBACCESS128 field.     */
  #define VPR_DEBUGIF_SBCS_SBACCESS128_Min (0x1UL)   /*!< Min enumerator value of SBACCESS128 field.                           */
  #define VPR_DEBUGIF_SBCS_SBACCESS128_Max (0x1UL)   /*!< Max enumerator value of SBACCESS128 field.                           */
  #define VPR_DEBUGIF_SBCS_SBACCESS128_sbaccess128 (0x1UL) /*!< 128-bit system bus accesses are supported.                     */

/* SBASIZE @Bits 5..11 : Width of system bus addresses in bits. (0 indicates there is no bus access support.) */
  #define VPR_DEBUGIF_SBCS_SBASIZE_Pos (5UL)         /*!< Position of SBASIZE field.                                           */
  #define VPR_DEBUGIF_SBCS_SBASIZE_Msk (0x7FUL << VPR_DEBUGIF_SBCS_SBASIZE_Pos) /*!< Bit mask of SBASIZE field.                */

/* SBERROR @Bits 12..14 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBERROR_Pos (12UL)        /*!< Position of SBERROR field.                                           */
  #define VPR_DEBUGIF_SBCS_SBERROR_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBERROR_Pos) /*!< Bit mask of SBERROR field.                 */
  #define VPR_DEBUGIF_SBCS_SBERROR_Min (0x0UL)       /*!< Min enumerator value of SBERROR field.                               */
  #define VPR_DEBUGIF_SBCS_SBERROR_Max (0x7UL)       /*!< Max enumerator value of SBERROR field.                               */
  #define VPR_DEBUGIF_SBCS_SBERROR_Normal (0x0UL)    /*!< There was no bus error.                                              */
  #define VPR_DEBUGIF_SBCS_SBERROR_Timeout (0x1UL)   /*!< There was a timeout.                                                 */
  #define VPR_DEBUGIF_SBCS_SBERROR_Address (0x2UL)   /*!< A bad address was accessed.                                          */
  #define VPR_DEBUGIF_SBCS_SBERROR_Alignment (0x3UL) /*!< There was an alignment error.                                        */
  #define VPR_DEBUGIF_SBCS_SBERROR_Size (0x4UL)      /*!< An access of unsupported size was requested.                         */
  #define VPR_DEBUGIF_SBCS_SBERROR_Other (0x7UL)     /*!< Other.                                                               */

/* SBREADONDATA @Bit 15 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBREADONDATA_Pos (15UL)   /*!< Position of SBREADONDATA field.                                      */
  #define VPR_DEBUGIF_SBCS_SBREADONDATA_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONDATA_Pos) /*!< Bit mask of SBREADONDATA field.  */
  #define VPR_DEBUGIF_SBCS_SBREADONDATA_Min (0x1UL)  /*!< Min enumerator value of SBREADONDATA field.                          */
  #define VPR_DEBUGIF_SBCS_SBREADONDATA_Max (0x1UL)  /*!< Max enumerator value of SBREADONDATA field.                          */
  #define VPR_DEBUGIF_SBCS_SBREADONDATA_sbreadondata (0x1UL) /*!< Every read from sbdata0 automatically triggers a system bus
                                                                  read at the (possibly autoincremented) address.*/

/* SBAUTOINCREMENT @Bit 16 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos (16UL) /*!< Position of SBAUTOINCREMENT field.                                  */
  #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos) /*!< Bit mask of SBAUTOINCREMENT
                                                                            field.*/
  #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Min (0x1UL) /*!< Min enumerator value of SBAUTOINCREMENT field.                     */
  #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Max (0x1UL) /*!< Max enumerator value of SBAUTOINCREMENT field.                     */
  #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_sbautoincrement (0x1UL) /*!< sbaddress is incremented by the access size (in bytes)
                                                                        selected in sbaccess after every system bus access.*/

/* SBACCESS @Bits 17..19 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBACCESS_Pos (17UL)       /*!< Position of SBACCESS field.                                          */
  #define VPR_DEBUGIF_SBCS_SBACCESS_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBACCESS_Pos) /*!< Bit mask of SBACCESS field.              */
  #define VPR_DEBUGIF_SBCS_SBACCESS_Min (0x0UL)      /*!< Min enumerator value of SBACCESS field.                              */
  #define VPR_DEBUGIF_SBCS_SBACCESS_Max (0x4UL)      /*!< Max enumerator value of SBACCESS field.                              */
  #define VPR_DEBUGIF_SBCS_SBACCESS_size8 (0x0UL)    /*!< 8-bit.                                                               */
  #define VPR_DEBUGIF_SBCS_SBACCESS_size16 (0x1UL)   /*!< 16-bit.                                                              */
  #define VPR_DEBUGIF_SBCS_SBACCESS_size32 (0x2UL)   /*!< 32-bit.                                                              */
  #define VPR_DEBUGIF_SBCS_SBACCESS_size64 (0x3UL)   /*!< 64-bit.                                                              */
  #define VPR_DEBUGIF_SBCS_SBACCESS_size128 (0x4UL)  /*!< 128-bit.                                                             */

/* SBREADONADDR @Bit 20 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBREADONADDR_Pos (20UL)   /*!< Position of SBREADONADDR field.                                      */
  #define VPR_DEBUGIF_SBCS_SBREADONADDR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONADDR_Pos) /*!< Bit mask of SBREADONADDR field.  */
  #define VPR_DEBUGIF_SBCS_SBREADONADDR_Min (0x1UL)  /*!< Min enumerator value of SBREADONADDR field.                          */
  #define VPR_DEBUGIF_SBCS_SBREADONADDR_Max (0x1UL)  /*!< Max enumerator value of SBREADONADDR field.                          */
  #define VPR_DEBUGIF_SBCS_SBREADONADDR_sbreadonaddr (0x1UL) /*!< Every write to sbaddress0 automatically triggers a system bus
                                                                  read at the new address.*/

/* SBBUSY @Bit 21 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBBUSY_Pos (21UL)         /*!< Position of SBBUSY field.                                            */
  #define VPR_DEBUGIF_SBCS_SBBUSY_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSY_Pos) /*!< Bit mask of SBBUSY field.                    */
  #define VPR_DEBUGIF_SBCS_SBBUSY_Min (0x0UL)        /*!< Min enumerator value of SBBUSY field.                                */
  #define VPR_DEBUGIF_SBCS_SBBUSY_Max (0x1UL)        /*!< Max enumerator value of SBBUSY field.                                */
  #define VPR_DEBUGIF_SBCS_SBBUSY_notbusy (0x0UL)    /*!< System bus master is not busy.                                       */
  #define VPR_DEBUGIF_SBCS_SBBUSY_busy (0x1UL)       /*!< System bus master is busy.                                           */

/* SBBUSYERROR @Bit 22 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos (22UL)    /*!< Position of SBBUSYERROR field.                                       */
  #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos) /*!< Bit mask of SBBUSYERROR field.     */
  #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Min (0x0UL)   /*!< Min enumerator value of SBBUSYERROR field.                           */
  #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Max (0x1UL)   /*!< Max enumerator value of SBBUSYERROR field.                           */
  #define VPR_DEBUGIF_SBCS_SBBUSYERROR_noerror (0x0UL) /*!< No error.                                                          */
  #define VPR_DEBUGIF_SBCS_SBBUSYERROR_error (0x1UL) /*!< Debugger access attempted while one in progress.                     */

/* SBVERSION @Bits 29..31 : (unspecified) */
  #define VPR_DEBUGIF_SBCS_SBVERSION_Pos (29UL)      /*!< Position of SBVERSION field.                                         */
  #define VPR_DEBUGIF_SBCS_SBVERSION_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBVERSION_Pos) /*!< Bit mask of SBVERSION field.           */
  #define VPR_DEBUGIF_SBCS_SBVERSION_Min (0x0UL)     /*!< Min enumerator value of SBVERSION field.                             */
  #define VPR_DEBUGIF_SBCS_SBVERSION_Max (0x1UL)     /*!< Max enumerator value of SBVERSION field.                             */
  #define VPR_DEBUGIF_SBCS_SBVERSION_version0 (0x0UL) /*!< The System Bus interface conforms to mainline drafts of thia RISC-V
                                                           External Debug Support spec older than 1 January, 2018.*/
  #define VPR_DEBUGIF_SBCS_SBVERSION_version1 (0x1UL) /*!< The System Bus interface conforms to RISC-V External Debug Support
                                                           version 0.14.0-DRAFT. Other values are reserved for future versions.*/


/* VPR_DEBUGIF_SBADDRESS0: System Bus Addres 31:0 */
  #define VPR_DEBUGIF_SBADDRESS0_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS0 register.                            */

/* ADDRESS @Bits 0..31 : Accesses bits 31:0 of the physical address in sbaddress. */
  #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
  #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos) /*!< Bit mask of ADDRESS
                                                                            field.*/


/* VPR_DEBUGIF_SBADDRESS1: System Bus Addres 63:32 */
  #define VPR_DEBUGIF_SBADDRESS1_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS1 register.                            */

/* ADDRESS @Bits 0..31 : Accesses bits 63:32 of the physical address in sbaddress (if the system address bus is that wide). */
  #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
  #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos) /*!< Bit mask of ADDRESS
                                                                            field.*/


/* VPR_DEBUGIF_SBADDRESS2: System Bus Addres 95:64 */
  #define VPR_DEBUGIF_SBADDRESS2_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS2 register.                            */

/* ADDRESS @Bits 0..31 : Accesses bits 95:64 of the physical address in sbaddress (if the system address bus is that wide). */
  #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
  #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos) /*!< Bit mask of ADDRESS
                                                                            field.*/


/* VPR_DEBUGIF_SBDATA0: System Bus Data 31:0 */
  #define VPR_DEBUGIF_SBDATA0_ResetValue (0x00000000UL) /*!< Reset value of SBDATA0 register.                                  */

/* DATA @Bits 0..31 : Accesses bits 31:0 of sbdata */
  #define VPR_DEBUGIF_SBDATA0_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define VPR_DEBUGIF_SBDATA0_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA0_DATA_Pos) /*!< Bit mask of DATA field.             */


/* VPR_DEBUGIF_SBDATA1: System Bus Data 63:32 */
  #define VPR_DEBUGIF_SBDATA1_ResetValue (0x00000000UL) /*!< Reset value of SBDATA1 register.                                  */

/* DATA @Bits 0..31 : Accesses bits 63:32 of sbdata (if the system bus is that wide). */
  #define VPR_DEBUGIF_SBDATA1_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define VPR_DEBUGIF_SBDATA1_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA1_DATA_Pos) /*!< Bit mask of DATA field.             */


/* VPR_DEBUGIF_SBDATA2: System Bus Data 95:64 */
  #define VPR_DEBUGIF_SBDATA2_ResetValue (0x00000000UL) /*!< Reset value of SBDATA2 register.                                  */

/* DATA @Bits 0..31 : Accesses bits 95:64 of sbdata (if the system bus is that wide). */
  #define VPR_DEBUGIF_SBDATA2_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define VPR_DEBUGIF_SBDATA2_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA2_DATA_Pos) /*!< Bit mask of DATA field.             */


/* VPR_DEBUGIF_SBDATA3: System Bus Data 127:96 */
  #define VPR_DEBUGIF_SBDATA3_ResetValue (0x00000000UL) /*!< Reset value of SBDATA3 register.                                  */

/* DATA @Bits 0..31 : Accesses bits 127:96 of sbdata (if the system bus is that wide). */
  #define VPR_DEBUGIF_SBDATA3_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define VPR_DEBUGIF_SBDATA3_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA3_DATA_Pos) /*!< Bit mask of DATA field.             */


/* VPR_DEBUGIF_HALTSUM0: Halt summary 0 */
  #define VPR_DEBUGIF_HALTSUM0_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM0 register.                                */

/* HALTSUM0 @Bits 0..31 : Halt summary 0 */
  #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos (0UL)    /*!< Position of HALTSUM0 field.                                          */
  #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos) /*!< Bit mask of HALTSUM0
                                                                            field.*/


/* ======================================================= Struct VPR ======================================================== */
/**
  * @brief VPR peripheral registers
  */
  typedef struct {                                   /*!< VPR Structure                                                        */
    __OM uint32_t TASKS_TRIGGER[23];                 /*!< (@ 0x00000000) VPR task [n] register                                 */
    __IM uint32_t RESERVED[9];
    __IOM uint32_t SUBSCRIBE_TRIGGER[4];             /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n]     */
    __IM uint32_t RESERVED1[28];
    __IOM uint32_t EVENTS_TRIGGERED[23];             /*!< (@ 0x00000100) VPR event [n] register                                */
    __IM uint32_t RESERVED2[9];
    __IOM uint32_t PUBLISH_TRIGGERED[4];             /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n]   */
    __IM uint32_t RESERVED3[92];
    __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
    __IM uint32_t RESERVED4[60];
    __IOM NRF_VPR_DEBUGIF_Type DEBUGIF;              /*!< (@ 0x00000400) (unspecified)                                         */
    __IM uint32_t RESERVED5[191];
    __IOM uint32_t CPURUN;                           /*!< (@ 0x00000800) State of the CPU after a core reset                   */
    __IM uint32_t RESERVED6;
    __IOM uint32_t INITPC;                           /*!< (@ 0x00000808) Initial value of the PC at CPU start.                 */
  } NRF_VPR_Type;                                    /*!< Size = 2060 (0x80C)                                                  */

/* VPR_TASKS_TRIGGER: VPR task [n] register */
  #define VPR_TASKS_TRIGGER_MaxCount (7UL)           /*!< Max size of TASKS_TRIGGER[23] array.                                 */
  #define VPR_TASKS_TRIGGER_MaxIndex (22UL)          /*!< Max index of TASKS_TRIGGER[23] array.                                */
  #define VPR_TASKS_TRIGGER_MinIndex (16UL)          /*!< Min index of TASKS_TRIGGER[23] array.                                */
  #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[23] register.                          */

/* TASKS_TRIGGER @Bit 0 : VPR task [n] register */
  #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL)  /*!< Position of TASKS_TRIGGER field.                                     */
  #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER
                                                                            field.*/
  #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field.                        */
  #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field.                        */
  #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task                                                    */


/* VPR_SUBSCRIBE_TRIGGER: Subscribe configuration for task TASKS_TRIGGER[n] */
  #define VPR_SUBSCRIBE_TRIGGER_MaxCount (4UL)       /*!< Max size of SUBSCRIBE_TRIGGER[4] array.                              */
  #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (3UL)       /*!< Max index of SUBSCRIBE_TRIGGER[4] array.                             */
  #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL)       /*!< Min index of SUBSCRIBE_TRIGGER[4] array.                             */
  #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[4] register.                   */

/* EN @Bit 31 : Subscription enable bit */
  #define VPR_SUBSCRIBE_TRIGGER_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define VPR_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << VPR_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field.                      */
  #define VPR_SUBSCRIBE_TRIGGER_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define VPR_SUBSCRIBE_TRIGGER_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define VPR_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
  #define VPR_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */


/* VPR_EVENTS_TRIGGERED: VPR event [n] register */
  #define VPR_EVENTS_TRIGGERED_MaxCount (7UL)        /*!< Max size of EVENTS_TRIGGERED[23] array.                              */
  #define VPR_EVENTS_TRIGGERED_MaxIndex (22UL)       /*!< Max index of EVENTS_TRIGGERED[23] array.                             */
  #define VPR_EVENTS_TRIGGERED_MinIndex (16UL)       /*!< Min index of EVENTS_TRIGGERED[23] array.                             */
  #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[23] register.                    */

/* EVENTS_TRIGGERED @Bit 0 : VPR event [n] register */
  #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field.                             */
  #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of
                                                                            EVENTS_TRIGGERED field.*/
  #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field.               */
  #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field.               */
  #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated                                  */
  #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated                                         */


/* VPR_PUBLISH_TRIGGERED: Publish configuration for event EVENTS_TRIGGERED[n] */
  #define VPR_PUBLISH_TRIGGERED_MaxCount (4UL)       /*!< Max size of PUBLISH_TRIGGERED[4] array.                              */
  #define VPR_PUBLISH_TRIGGERED_MaxIndex (3UL)       /*!< Max index of PUBLISH_TRIGGERED[4] array.                             */
  #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL)       /*!< Min index of PUBLISH_TRIGGERED[4] array.                             */
  #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[4] register.                   */

/* EN @Bit 31 : Publication enable bit */
  #define VPR_PUBLISH_TRIGGERED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
  #define VPR_PUBLISH_TRIGGERED_EN_Msk (0x1UL << VPR_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field.                      */
  #define VPR_PUBLISH_TRIGGERED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
  #define VPR_PUBLISH_TRIGGERED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
  #define VPR_PUBLISH_TRIGGERED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
  #define VPR_PUBLISH_TRIGGERED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */


/* VPR_INTEN: Enable or disable interrupt */
  #define VPR_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */

/* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
  #define VPR_INTEN_TRIGGERED16_Pos (16UL)           /*!< Position of TRIGGERED16 field.                                       */
  #define VPR_INTEN_TRIGGERED16_Msk (0x1UL << VPR_INTEN_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.                   */
  #define VPR_INTEN_TRIGGERED16_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTEN_TRIGGERED16_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTEN_TRIGGERED16_Disabled (0x0UL)     /*!< Disable                                                              */
  #define VPR_INTEN_TRIGGERED16_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
  #define VPR_INTEN_TRIGGERED17_Pos (17UL)           /*!< Position of TRIGGERED17 field.                                       */
  #define VPR_INTEN_TRIGGERED17_Msk (0x1UL << VPR_INTEN_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.                   */
  #define VPR_INTEN_TRIGGERED17_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTEN_TRIGGERED17_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTEN_TRIGGERED17_Disabled (0x0UL)     /*!< Disable                                                              */
  #define VPR_INTEN_TRIGGERED17_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
  #define VPR_INTEN_TRIGGERED18_Pos (18UL)           /*!< Position of TRIGGERED18 field.                                       */
  #define VPR_INTEN_TRIGGERED18_Msk (0x1UL << VPR_INTEN_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.                   */
  #define VPR_INTEN_TRIGGERED18_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTEN_TRIGGERED18_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTEN_TRIGGERED18_Disabled (0x0UL)     /*!< Disable                                                              */
  #define VPR_INTEN_TRIGGERED18_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
  #define VPR_INTEN_TRIGGERED19_Pos (19UL)           /*!< Position of TRIGGERED19 field.                                       */
  #define VPR_INTEN_TRIGGERED19_Msk (0x1UL << VPR_INTEN_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.                   */
  #define VPR_INTEN_TRIGGERED19_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTEN_TRIGGERED19_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTEN_TRIGGERED19_Disabled (0x0UL)     /*!< Disable                                                              */
  #define VPR_INTEN_TRIGGERED19_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
  #define VPR_INTEN_TRIGGERED20_Pos (20UL)           /*!< Position of TRIGGERED20 field.                                       */
  #define VPR_INTEN_TRIGGERED20_Msk (0x1UL << VPR_INTEN_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.                   */
  #define VPR_INTEN_TRIGGERED20_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTEN_TRIGGERED20_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTEN_TRIGGERED20_Disabled (0x0UL)     /*!< Disable                                                              */
  #define VPR_INTEN_TRIGGERED20_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
  #define VPR_INTEN_TRIGGERED21_Pos (21UL)           /*!< Position of TRIGGERED21 field.                                       */
  #define VPR_INTEN_TRIGGERED21_Msk (0x1UL << VPR_INTEN_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.                   */
  #define VPR_INTEN_TRIGGERED21_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTEN_TRIGGERED21_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTEN_TRIGGERED21_Disabled (0x0UL)     /*!< Disable                                                              */
  #define VPR_INTEN_TRIGGERED21_Enabled (0x1UL)      /*!< Enable                                                               */

/* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
  #define VPR_INTEN_TRIGGERED22_Pos (22UL)           /*!< Position of TRIGGERED22 field.                                       */
  #define VPR_INTEN_TRIGGERED22_Msk (0x1UL << VPR_INTEN_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.                   */
  #define VPR_INTEN_TRIGGERED22_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTEN_TRIGGERED22_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTEN_TRIGGERED22_Disabled (0x0UL)     /*!< Disable                                                              */
  #define VPR_INTEN_TRIGGERED22_Enabled (0x1UL)      /*!< Enable                                                               */


/* VPR_INTENSET: Enable interrupt */
  #define VPR_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
  #define VPR_INTENSET_TRIGGERED16_Pos (16UL)        /*!< Position of TRIGGERED16 field.                                       */
  #define VPR_INTENSET_TRIGGERED16_Msk (0x1UL << VPR_INTENSET_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.             */
  #define VPR_INTENSET_TRIGGERED16_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTENSET_TRIGGERED16_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTENSET_TRIGGERED16_Set (0x1UL)       /*!< Enable                                                               */
  #define VPR_INTENSET_TRIGGERED16_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENSET_TRIGGERED16_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
  #define VPR_INTENSET_TRIGGERED17_Pos (17UL)        /*!< Position of TRIGGERED17 field.                                       */
  #define VPR_INTENSET_TRIGGERED17_Msk (0x1UL << VPR_INTENSET_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.             */
  #define VPR_INTENSET_TRIGGERED17_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTENSET_TRIGGERED17_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTENSET_TRIGGERED17_Set (0x1UL)       /*!< Enable                                                               */
  #define VPR_INTENSET_TRIGGERED17_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENSET_TRIGGERED17_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
  #define VPR_INTENSET_TRIGGERED18_Pos (18UL)        /*!< Position of TRIGGERED18 field.                                       */
  #define VPR_INTENSET_TRIGGERED18_Msk (0x1UL << VPR_INTENSET_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.             */
  #define VPR_INTENSET_TRIGGERED18_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTENSET_TRIGGERED18_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTENSET_TRIGGERED18_Set (0x1UL)       /*!< Enable                                                               */
  #define VPR_INTENSET_TRIGGERED18_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENSET_TRIGGERED18_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
  #define VPR_INTENSET_TRIGGERED19_Pos (19UL)        /*!< Position of TRIGGERED19 field.                                       */
  #define VPR_INTENSET_TRIGGERED19_Msk (0x1UL << VPR_INTENSET_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.             */
  #define VPR_INTENSET_TRIGGERED19_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTENSET_TRIGGERED19_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTENSET_TRIGGERED19_Set (0x1UL)       /*!< Enable                                                               */
  #define VPR_INTENSET_TRIGGERED19_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENSET_TRIGGERED19_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
  #define VPR_INTENSET_TRIGGERED20_Pos (20UL)        /*!< Position of TRIGGERED20 field.                                       */
  #define VPR_INTENSET_TRIGGERED20_Msk (0x1UL << VPR_INTENSET_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.             */
  #define VPR_INTENSET_TRIGGERED20_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTENSET_TRIGGERED20_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTENSET_TRIGGERED20_Set (0x1UL)       /*!< Enable                                                               */
  #define VPR_INTENSET_TRIGGERED20_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENSET_TRIGGERED20_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
  #define VPR_INTENSET_TRIGGERED21_Pos (21UL)        /*!< Position of TRIGGERED21 field.                                       */
  #define VPR_INTENSET_TRIGGERED21_Msk (0x1UL << VPR_INTENSET_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.             */
  #define VPR_INTENSET_TRIGGERED21_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTENSET_TRIGGERED21_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTENSET_TRIGGERED21_Set (0x1UL)       /*!< Enable                                                               */
  #define VPR_INTENSET_TRIGGERED21_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENSET_TRIGGERED21_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
  #define VPR_INTENSET_TRIGGERED22_Pos (22UL)        /*!< Position of TRIGGERED22 field.                                       */
  #define VPR_INTENSET_TRIGGERED22_Msk (0x1UL << VPR_INTENSET_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.             */
  #define VPR_INTENSET_TRIGGERED22_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTENSET_TRIGGERED22_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTENSET_TRIGGERED22_Set (0x1UL)       /*!< Enable                                                               */
  #define VPR_INTENSET_TRIGGERED22_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENSET_TRIGGERED22_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* VPR_INTENCLR: Disable interrupt */
  #define VPR_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
  #define VPR_INTENCLR_TRIGGERED16_Pos (16UL)        /*!< Position of TRIGGERED16 field.                                       */
  #define VPR_INTENCLR_TRIGGERED16_Msk (0x1UL << VPR_INTENCLR_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.             */
  #define VPR_INTENCLR_TRIGGERED16_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTENCLR_TRIGGERED16_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTENCLR_TRIGGERED16_Clear (0x1UL)     /*!< Disable                                                              */
  #define VPR_INTENCLR_TRIGGERED16_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENCLR_TRIGGERED16_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
  #define VPR_INTENCLR_TRIGGERED17_Pos (17UL)        /*!< Position of TRIGGERED17 field.                                       */
  #define VPR_INTENCLR_TRIGGERED17_Msk (0x1UL << VPR_INTENCLR_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.             */
  #define VPR_INTENCLR_TRIGGERED17_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTENCLR_TRIGGERED17_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTENCLR_TRIGGERED17_Clear (0x1UL)     /*!< Disable                                                              */
  #define VPR_INTENCLR_TRIGGERED17_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENCLR_TRIGGERED17_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
  #define VPR_INTENCLR_TRIGGERED18_Pos (18UL)        /*!< Position of TRIGGERED18 field.                                       */
  #define VPR_INTENCLR_TRIGGERED18_Msk (0x1UL << VPR_INTENCLR_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.             */
  #define VPR_INTENCLR_TRIGGERED18_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTENCLR_TRIGGERED18_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTENCLR_TRIGGERED18_Clear (0x1UL)     /*!< Disable                                                              */
  #define VPR_INTENCLR_TRIGGERED18_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENCLR_TRIGGERED18_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
  #define VPR_INTENCLR_TRIGGERED19_Pos (19UL)        /*!< Position of TRIGGERED19 field.                                       */
  #define VPR_INTENCLR_TRIGGERED19_Msk (0x1UL << VPR_INTENCLR_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.             */
  #define VPR_INTENCLR_TRIGGERED19_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTENCLR_TRIGGERED19_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTENCLR_TRIGGERED19_Clear (0x1UL)     /*!< Disable                                                              */
  #define VPR_INTENCLR_TRIGGERED19_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENCLR_TRIGGERED19_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
  #define VPR_INTENCLR_TRIGGERED20_Pos (20UL)        /*!< Position of TRIGGERED20 field.                                       */
  #define VPR_INTENCLR_TRIGGERED20_Msk (0x1UL << VPR_INTENCLR_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.             */
  #define VPR_INTENCLR_TRIGGERED20_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTENCLR_TRIGGERED20_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTENCLR_TRIGGERED20_Clear (0x1UL)     /*!< Disable                                                              */
  #define VPR_INTENCLR_TRIGGERED20_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENCLR_TRIGGERED20_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
  #define VPR_INTENCLR_TRIGGERED21_Pos (21UL)        /*!< Position of TRIGGERED21 field.                                       */
  #define VPR_INTENCLR_TRIGGERED21_Msk (0x1UL << VPR_INTENCLR_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.             */
  #define VPR_INTENCLR_TRIGGERED21_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTENCLR_TRIGGERED21_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTENCLR_TRIGGERED21_Clear (0x1UL)     /*!< Disable                                                              */
  #define VPR_INTENCLR_TRIGGERED21_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENCLR_TRIGGERED21_Enabled (0x1UL)   /*!< Read: Enabled                                                        */

/* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
  #define VPR_INTENCLR_TRIGGERED22_Pos (22UL)        /*!< Position of TRIGGERED22 field.                                       */
  #define VPR_INTENCLR_TRIGGERED22_Msk (0x1UL << VPR_INTENCLR_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.             */
  #define VPR_INTENCLR_TRIGGERED22_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTENCLR_TRIGGERED22_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTENCLR_TRIGGERED22_Clear (0x1UL)     /*!< Disable                                                              */
  #define VPR_INTENCLR_TRIGGERED22_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
  #define VPR_INTENCLR_TRIGGERED22_Enabled (0x1UL)   /*!< Read: Enabled                                                        */


/* VPR_INTPEND: Pending interrupts */
  #define VPR_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */

/* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
  #define VPR_INTPEND_TRIGGERED16_Pos (16UL)         /*!< Position of TRIGGERED16 field.                                       */
  #define VPR_INTPEND_TRIGGERED16_Msk (0x1UL << VPR_INTPEND_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.               */
  #define VPR_INTPEND_TRIGGERED16_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTPEND_TRIGGERED16_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED16 field.                           */
  #define VPR_INTPEND_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define VPR_INTPEND_TRIGGERED16_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
  #define VPR_INTPEND_TRIGGERED17_Pos (17UL)         /*!< Position of TRIGGERED17 field.                                       */
  #define VPR_INTPEND_TRIGGERED17_Msk (0x1UL << VPR_INTPEND_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.               */
  #define VPR_INTPEND_TRIGGERED17_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTPEND_TRIGGERED17_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED17 field.                           */
  #define VPR_INTPEND_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define VPR_INTPEND_TRIGGERED17_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
  #define VPR_INTPEND_TRIGGERED18_Pos (18UL)         /*!< Position of TRIGGERED18 field.                                       */
  #define VPR_INTPEND_TRIGGERED18_Msk (0x1UL << VPR_INTPEND_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.               */
  #define VPR_INTPEND_TRIGGERED18_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTPEND_TRIGGERED18_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED18 field.                           */
  #define VPR_INTPEND_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define VPR_INTPEND_TRIGGERED18_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
  #define VPR_INTPEND_TRIGGERED19_Pos (19UL)         /*!< Position of TRIGGERED19 field.                                       */
  #define VPR_INTPEND_TRIGGERED19_Msk (0x1UL << VPR_INTPEND_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.               */
  #define VPR_INTPEND_TRIGGERED19_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTPEND_TRIGGERED19_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED19 field.                           */
  #define VPR_INTPEND_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define VPR_INTPEND_TRIGGERED19_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
  #define VPR_INTPEND_TRIGGERED20_Pos (20UL)         /*!< Position of TRIGGERED20 field.                                       */
  #define VPR_INTPEND_TRIGGERED20_Msk (0x1UL << VPR_INTPEND_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.               */
  #define VPR_INTPEND_TRIGGERED20_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTPEND_TRIGGERED20_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED20 field.                           */
  #define VPR_INTPEND_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define VPR_INTPEND_TRIGGERED20_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
  #define VPR_INTPEND_TRIGGERED21_Pos (21UL)         /*!< Position of TRIGGERED21 field.                                       */
  #define VPR_INTPEND_TRIGGERED21_Msk (0x1UL << VPR_INTPEND_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.               */
  #define VPR_INTPEND_TRIGGERED21_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTPEND_TRIGGERED21_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED21 field.                           */
  #define VPR_INTPEND_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define VPR_INTPEND_TRIGGERED21_Pending (0x1UL)    /*!< Read: Pending                                                        */

/* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
  #define VPR_INTPEND_TRIGGERED22_Pos (22UL)         /*!< Position of TRIGGERED22 field.                                       */
  #define VPR_INTPEND_TRIGGERED22_Msk (0x1UL << VPR_INTPEND_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.               */
  #define VPR_INTPEND_TRIGGERED22_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTPEND_TRIGGERED22_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED22 field.                           */
  #define VPR_INTPEND_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                                    */
  #define VPR_INTPEND_TRIGGERED22_Pending (0x1UL)    /*!< Read: Pending                                                        */


/* VPR_CPURUN: State of the CPU after a core reset */
  #define VPR_CPURUN_ResetValue (0x00000000UL)       /*!< Reset value of CPURUN register.                                      */

/* EN @Bit 0 : Controls CPU running state after a core reset. */
  #define VPR_CPURUN_EN_Pos (0UL)                    /*!< Position of EN field.                                                */
  #define VPR_CPURUN_EN_Msk (0x1UL << VPR_CPURUN_EN_Pos) /*!< Bit mask of EN field.                                            */
  #define VPR_CPURUN_EN_Min (0x0UL)                  /*!< Min enumerator value of EN field.                                    */
  #define VPR_CPURUN_EN_Max (0x1UL)                  /*!< Max enumerator value of EN field.                                    */
  #define VPR_CPURUN_EN_Stopped (0x0UL)              /*!< CPU stopped. If this is the CPU state after a core reset, setting this
                                                          bit will change the CPU state to CPU running.*/
  #define VPR_CPURUN_EN_Running (0x1UL)              /*!< CPU running. If this is the CPU state after a core reset, clearing
                                                          this bit will change the CPU state to CPU stopped after a core reset.*/


/* VPR_INITPC: Initial value of the PC at CPU start. */
  #define VPR_INITPC_ResetValue (0x00000000UL)       /*!< Reset value of INITPC register.                                      */

/* INITPC @Bits 0..31 : Initial value of the PC at CPU start. */
  #define VPR_INITPC_INITPC_Pos (0UL)                /*!< Position of INITPC field.                                            */
  #define VPR_INITPC_INITPC_Msk (0xFFFFFFFFUL << VPR_INITPC_INITPC_Pos) /*!< Bit mask of INITPC field.                         */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* =========================================================================================================================== */
/* ================                                          VPRCSR                                          ================ */
/* =========================================================================================================================== */

/**
  * @brief VPR CSR registers
  */
/**
  * @brief  [VPRCSR] (unspecified)
  */

/**
  * @brief  [VPRCSR] (unspecified)
  */

/**
  * @brief MSTATUS [VPRCSR_MSTATUS] Machine Status
  */
  #define VPRCSR_MSTATUS (0x00000300ul)
  #define VPRCSR_MSTATUS_ResetValue (0x00001800UL)   /*!< Reset value of MSTATUS register.                                     */

/* MIE @Bit 3 : global interrupt enable for machine privilege mode */
  #define VPRCSR_MSTATUS_MIE_Pos (3UL)               /*!< Position of MIE field.                                               */
  #define VPRCSR_MSTATUS_MIE_Msk (0x1UL << VPRCSR_MSTATUS_MIE_Pos) /*!< Bit mask of MIE field.                                 */
  #define VPRCSR_MSTATUS_MIE_Min (0x0UL)             /*!< Min enumerator value of MIE field.                                   */
  #define VPRCSR_MSTATUS_MIE_Max (0x1UL)             /*!< Max enumerator value of MIE field.                                   */
  #define VPRCSR_MSTATUS_MIE_Disabled (0x0UL)        /*!< (unspecified)                                                        */
  #define VPRCSR_MSTATUS_MIE_Enabled (0x1UL)         /*!< (unspecified)                                                        */

/* MPIE @Bit 7 : Exists to support nested traps. Value of the interrupt-enable bit active prior to the trap for machine
                 privilege mode */

  #define VPRCSR_MSTATUS_MPIE_Pos (7UL)              /*!< Position of MPIE field.                                              */
  #define VPRCSR_MSTATUS_MPIE_Msk (0x1UL << VPRCSR_MSTATUS_MPIE_Pos) /*!< Bit mask of MPIE field.                              */
  #define VPRCSR_MSTATUS_MPIE_Min (0x0UL)            /*!< Min enumerator value of MPIE field.                                  */
  #define VPRCSR_MSTATUS_MPIE_Max (0x1UL)            /*!< Max enumerator value of MPIE field.                                  */
  #define VPRCSR_MSTATUS_MPIE_Disabled (0x0UL)       /*!< (unspecified)                                                        */
  #define VPRCSR_MSTATUS_MPIE_Enabled (0x1UL)        /*!< (unspecified)                                                        */

/* MPP @Bits 11..12 : Exists to support nested traps. Value of the privlege mode prior to the trap for machine privilege mode */
  #define VPRCSR_MSTATUS_MPP_Pos (11UL)              /*!< Position of MPP field.                                               */
  #define VPRCSR_MSTATUS_MPP_Msk (0x3UL << VPRCSR_MSTATUS_MPP_Pos) /*!< Bit mask of MPP field.                                 */


/**
  * @brief MISA [VPRCSR_MISA] Machine ISA
  */
  #define VPRCSR_MISA (0x00000301ul)
  #define VPRCSR_MISA_ResetValue (0x40001016UL)      /*!< Reset value of MISA register.                                        */

/* A @Bit 0 : Atomic extension */
  #define VPRCSR_MISA_A_Pos (0UL)                    /*!< Position of A field.                                                 */
  #define VPRCSR_MISA_A_Msk (0x1UL << VPRCSR_MISA_A_Pos) /*!< Bit mask of A field.                                             */
  #define VPRCSR_MISA_A_Min (0x0UL)                  /*!< Min enumerator value of A field.                                     */
  #define VPRCSR_MISA_A_Max (0x1UL)                  /*!< Max enumerator value of A field.                                     */
  #define VPRCSR_MISA_A_Disabled (0x0UL)             /*!< (unspecified)                                                        */
  #define VPRCSR_MISA_A_Enabled (0x1UL)              /*!< (unspecified)                                                        */

/* B @Bit 1 : Bit-Manipulation extension */
  #define VPRCSR_MISA_B_Pos (1UL)                    /*!< Position of B field.                                                 */
  #define VPRCSR_MISA_B_Msk (0x1UL << VPRCSR_MISA_B_Pos) /*!< Bit mask of B field.                                             */
  #define VPRCSR_MISA_B_Min (0x0UL)                  /*!< Min enumerator value of B field.                                     */
  #define VPRCSR_MISA_B_Max (0x1UL)                  /*!< Max enumerator value of B field.                                     */
  #define VPRCSR_MISA_B_Disabled (0x0UL)             /*!< (unspecified)                                                        */
  #define VPRCSR_MISA_B_Enabled (0x1UL)              /*!< (unspecified)                                                        */

/* C @Bit 2 : Compressed extension */
  #define VPRCSR_MISA_C_Pos (2UL)                    /*!< Position of C field.                                                 */
  #define VPRCSR_MISA_C_Msk (0x1UL << VPRCSR_MISA_C_Pos) /*!< Bit mask of C field.                                             */
  #define VPRCSR_MISA_C_Min (0x0UL)                  /*!< Min enumerator value of C field.                                     */
  #define VPRCSR_MISA_C_Max (0x1UL)                  /*!< Max enumerator value of C field.                                     */
  #define VPRCSR_MISA_C_Disabled (0x0UL)             /*!< (unspecified)                                                        */
  #define VPRCSR_MISA_C_Enabled (0x1UL)              /*!< (unspecified)                                                        */

/* E @Bit 4 : RV32E base ISA */
  #define VPRCSR_MISA_E_Pos (4UL)                    /*!< Position of E field.                                                 */
  #define VPRCSR_MISA_E_Msk (0x1UL << VPRCSR_MISA_E_Pos) /*!< Bit mask of E field.                                             */
  #define VPRCSR_MISA_E_Min (0x0UL)                  /*!< Min enumerator value of E field.                                     */
  #define VPRCSR_MISA_E_Max (0x1UL)                  /*!< Max enumerator value of E field.                                     */
  #define VPRCSR_MISA_E_Disabled (0x0UL)             /*!< (unspecified)                                                        */
  #define VPRCSR_MISA_E_Enabled (0x1UL)              /*!< (unspecified)                                                        */

/* I @Bit 8 : RV32I/64I/128I base ISA */
  #define VPRCSR_MISA_I_Pos (8UL)                    /*!< Position of I field.                                                 */
  #define VPRCSR_MISA_I_Msk (0x1UL << VPRCSR_MISA_I_Pos) /*!< Bit mask of I field.                                             */
  #define VPRCSR_MISA_I_Min (0x0UL)                  /*!< Min enumerator value of I field.                                     */
  #define VPRCSR_MISA_I_Max (0x1UL)                  /*!< Max enumerator value of I field.                                     */
  #define VPRCSR_MISA_I_Disabled (0x0UL)             /*!< (unspecified)                                                        */
  #define VPRCSR_MISA_I_Enabled (0x1UL)              /*!< (unspecified)                                                        */

/* M @Bit 12 : Integer Multiply/Divide extension */
  #define VPRCSR_MISA_M_Pos (12UL)                   /*!< Position of M field.                                                 */
  #define VPRCSR_MISA_M_Msk (0x1UL << VPRCSR_MISA_M_Pos) /*!< Bit mask of M field.                                             */
  #define VPRCSR_MISA_M_Min (0x0UL)                  /*!< Min enumerator value of M field.                                     */
  #define VPRCSR_MISA_M_Max (0x1UL)                  /*!< Max enumerator value of M field.                                     */
  #define VPRCSR_MISA_M_Disabled (0x0UL)             /*!< (unspecified)                                                        */
  #define VPRCSR_MISA_M_Enabled (0x1UL)              /*!< (unspecified)                                                        */

/* N @Bit 13 : User-level interrupts supported */
  #define VPRCSR_MISA_N_Pos (13UL)                   /*!< Position of N field.                                                 */
  #define VPRCSR_MISA_N_Msk (0x1UL << VPRCSR_MISA_N_Pos) /*!< Bit mask of N field.                                             */
  #define VPRCSR_MISA_N_Min (0x0UL)                  /*!< Min enumerator value of N field.                                     */
  #define VPRCSR_MISA_N_Max (0x1UL)                  /*!< Max enumerator value of N field.                                     */
  #define VPRCSR_MISA_N_Disabled (0x0UL)             /*!< (unspecified)                                                        */
  #define VPRCSR_MISA_N_Enabled (0x1UL)              /*!< (unspecified)                                                        */

/* MXL @Bits 30..31 : Machine XLEN */
  #define VPRCSR_MISA_MXL_Pos (30UL)                 /*!< Position of MXL field.                                               */
  #define VPRCSR_MISA_MXL_Msk (0x3UL << VPRCSR_MISA_MXL_Pos) /*!< Bit mask of MXL field.                                       */
  #define VPRCSR_MISA_MXL_Min (0x1UL)                /*!< Min enumerator value of MXL field.                                   */
  #define VPRCSR_MISA_MXL_Max (0x3UL)                /*!< Max enumerator value of MXL field.                                   */
  #define VPRCSR_MISA_MXL_XLEN32 (0x1UL)             /*!< XLEN is 32 bits                                                      */
  #define VPRCSR_MISA_MXL_XLEN64 (0x2UL)             /*!< XLEN is 64 bits                                                      */
  #define VPRCSR_MISA_MXL_XLEN128 (0x3UL)            /*!< XLEN is 128 bits                                                     */


/**
  * @brief MTVEC [VPRCSR_MTVEC] Machine Trap-Vector
  */
  #define VPRCSR_MTVEC (0x00000305ul)
  #define VPRCSR_MTVEC_ResetValue (0x00000003UL)     /*!< Reset value of MTVEC register.                                       */

/* MODE @Bits 0..1 : Mode */
  #define VPRCSR_MTVEC_MODE_Pos (0UL)                /*!< Position of MODE field.                                              */
  #define VPRCSR_MTVEC_MODE_Msk (0x3UL << VPRCSR_MTVEC_MODE_Pos) /*!< Bit mask of MODE field.                                  */
  #define VPRCSR_MTVEC_MODE_Min (0x3UL)              /*!< Min enumerator value of MODE field.                                  */
  #define VPRCSR_MTVEC_MODE_Max (0x3UL)              /*!< Max enumerator value of MODE field.                                  */
  #define VPRCSR_MTVEC_MODE_CLIC (0x3UL)             /*!< Core Local Interrupt Controller (CLIC) interrupt handling mode       */

/* BASE @Bits 2..31 : Vector base address */
  #define VPRCSR_MTVEC_BASE_Pos (2UL)                /*!< Position of BASE field.                                              */
  #define VPRCSR_MTVEC_BASE_Msk (0x3FFFFFFFUL << VPRCSR_MTVEC_BASE_Pos) /*!< Bit mask of BASE field.                           */


/**
  * @brief MTVT [VPRCSR_MTVT] Machine Trap Vector Table
  */
  #define VPRCSR_MTVT (0x00000307ul)
  #define VPRCSR_MTVT_ResetValue (0x00000000UL)      /*!< Reset value of MTVT register.                                        */

/* VAL @Bits 6..31 : Machine Trap Vector Table base address value for CLIC vectored interrupts */
  #define VPRCSR_MTVT_VAL_Pos (6UL)                  /*!< Position of VAL field.                                               */
  #define VPRCSR_MTVT_VAL_Msk (0x3FFFFFFUL << VPRCSR_MTVT_VAL_Pos) /*!< Bit mask of VAL field.                                 */


/**
  * @brief MCOUNTINHIBIT [VPRCSR_MCOUNTINHIBIT] Machine Counter-Inhibit
  */
  #define VPRCSR_MCOUNTINHIBIT (0x00000320ul)
  #define VPRCSR_MCOUNTINHIBIT_ResetValue (0x00000005UL) /*!< Reset value of MCOUNTINHIBIT register.                           */

/* CY @Bit 0 : (unspecified) */
  #define VPRCSR_MCOUNTINHIBIT_CY_Pos (0UL)          /*!< Position of CY field.                                                */
  #define VPRCSR_MCOUNTINHIBIT_CY_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_CY_Pos) /*!< Bit mask of CY field.                        */
  #define VPRCSR_MCOUNTINHIBIT_CY_Min (0x0UL)        /*!< Min enumerator value of CY field.                                    */
  #define VPRCSR_MCOUNTINHIBIT_CY_Max (0x1UL)        /*!< Max enumerator value of CY field.                                    */
  #define VPRCSR_MCOUNTINHIBIT_CY_INCREMENT (0x0UL)  /*!< MCYCLE increments as usual                                           */
  #define VPRCSR_MCOUNTINHIBIT_CY_INHIBIT (0x1UL)    /*!< MCYCLE doesn't increment                                             */

/* IR @Bit 2 : (unspecified) */
  #define VPRCSR_MCOUNTINHIBIT_IR_Pos (2UL)          /*!< Position of IR field.                                                */
  #define VPRCSR_MCOUNTINHIBIT_IR_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_IR_Pos) /*!< Bit mask of IR field.                        */
  #define VPRCSR_MCOUNTINHIBIT_IR_Min (0x0UL)        /*!< Min enumerator value of IR field.                                    */
  #define VPRCSR_MCOUNTINHIBIT_IR_Max (0x1UL)        /*!< Max enumerator value of IR field.                                    */
  #define VPRCSR_MCOUNTINHIBIT_IR_INCREMENT (0x0UL)  /*!< MINSTRET increments as usual                                         */
  #define VPRCSR_MCOUNTINHIBIT_IR_INHIBIT (0x1UL)    /*!< MINSTRET doesn't increment                                           */


/**
  * @brief MSCRATCH [VPRCSR_MSCRATCH] Machine Scratch
  */
  #define VPRCSR_MSCRATCH (0x00000340ul)
  #define VPRCSR_MSCRATCH_ResetValue (0x00000000UL)  /*!< Reset value of MSCRATCH register.                                    */

/* VAL @Bits 0..31 : Machine Scratch value */
  #define VPRCSR_MSCRATCH_VAL_Pos (0UL)              /*!< Position of VAL field.                                               */
  #define VPRCSR_MSCRATCH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MSCRATCH_VAL_Pos) /*!< Bit mask of VAL field.                        */


/**
  * @brief MEPC [VPRCSR_MEPC] Machine Exception Program Counter
  */
  #define VPRCSR_MEPC (0x00000341ul)
  #define VPRCSR_MEPC_ResetValue (0x00000000UL)      /*!< Reset value of MEPC register.                                        */

/* VAL @Bits 0..31 : Machine Exception Program Counter value */
  #define VPRCSR_MEPC_VAL_Pos (0UL)                  /*!< Position of VAL field.                                               */
  #define VPRCSR_MEPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MEPC_VAL_Pos) /*!< Bit mask of VAL field.                                */


/**
  * @brief MCAUSE [VPRCSR_MCAUSE] Machine Cause
  */
  #define VPRCSR_MCAUSE (0x00000342ul)
  #define VPRCSR_MCAUSE_ResetValue (0x30000000UL)    /*!< Reset value of MCAUSE register.                                      */

/* EXCEPTIONCODE @Bits 0..11 : Exception code */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_Pos (0UL)      /*!< Position of EXCEPTIONCODE field.                                     */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_Msk (0xFFFUL << VPRCSR_MCAUSE_EXCEPTIONCODE_Pos) /*!< Bit mask of EXCEPTIONCODE field.   */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_Min (0x0UL)    /*!< Min enumerator value of EXCEPTIONCODE field.                         */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_Max (0x1FUL)   /*!< Max enumerator value of EXCEPTIONCODE field.                         */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTADDRMISALIGN (0x000UL) /*!< Instruction Address Misaligned                           */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTACCESSFAULT (0x001UL) /*!< Instruction Access Fault                                  */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_ILLEGALINST (0x002UL) /*!< Illegal Instruction                                           */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_BKPT (0x003UL) /*!< Breakpoint                                                           */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADADDRMISALIGN (0x004UL) /*!< Load Address Misaligned                                  */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADACCESSFAULT (0x005UL) /*!< Load Access Fault                                         */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREADDRMISALIGN (0x006UL) /*!< Store/AMO Address Misaligned                            */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREACCESSFAULT (0x007UL) /*!< Store/AMO Access Fault                                   */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_ECALLMMODE (0x00BUL) /*!< Environment Call M-Mode                                        */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNSTACKING (0x018UL) /*!< Misaligned Stacking                                      */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTSTACKING (0x019UL) /*!< Bus Fault on Stacking                                    */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_INTVECTORFAULT (0x01AUL) /*!< Interrupt Vector Fault                                     */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNUNSTACKING (0x01BUL) /*!< Misaligned Unstacking                                  */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTUNSTACKING (0x01CUL) /*!< Bus Fault on Unstacking                                */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_STORETIMEOUTFAULT (0x01DUL) /*!< Store Timeout Fault                                     */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADTIMEOUTFAULT (0x01EUL) /*!< Load Timeout Fault                                       */
  #define VPRCSR_MCAUSE_EXCEPTIONCODE_STACKINGEXCFAULT (0x01FUL) /*!< Fault on Exception Stacking                              */

/* MPIL @Bits 16..23 : Previous interrupt level */
  #define VPRCSR_MCAUSE_MPIL_Pos (16UL)              /*!< Position of MPIL field.                                              */
  #define VPRCSR_MCAUSE_MPIL_Msk (0xFFUL << VPRCSR_MCAUSE_MPIL_Pos) /*!< Bit mask of MPIL field.                               */

/* MPIE @Bit 27 : Previous interrupt enable, same as MSTATUS.MPIE */
  #define VPRCSR_MCAUSE_MPIE_Pos (27UL)              /*!< Position of MPIE field.                                              */
  #define VPRCSR_MCAUSE_MPIE_Msk (0x1UL << VPRCSR_MCAUSE_MPIE_Pos) /*!< Bit mask of MPIE field.                                */

/* MPP @Bits 28..29 : Previous privilege mode, same as MSTATUS.MPP */
  #define VPRCSR_MCAUSE_MPP_Pos (28UL)               /*!< Position of MPP field.                                               */
  #define VPRCSR_MCAUSE_MPP_Msk (0x3UL << VPRCSR_MCAUSE_MPP_Pos) /*!< Bit mask of MPP field.                                   */

/* MINHV @Bit 30 : In hardware vectoring */
  #define VPRCSR_MCAUSE_MINHV_Pos (30UL)             /*!< Position of MINHV field.                                             */
  #define VPRCSR_MCAUSE_MINHV_Msk (0x1UL << VPRCSR_MCAUSE_MINHV_Pos) /*!< Bit mask of MINHV field.                             */

/* INTERRUPT @Bit 31 : Interrupt bit */
  #define VPRCSR_MCAUSE_INTERRUPT_Pos (31UL)         /*!< Position of INTERRUPT field.                                         */
  #define VPRCSR_MCAUSE_INTERRUPT_Msk (0x1UL << VPRCSR_MCAUSE_INTERRUPT_Pos) /*!< Bit mask of INTERRUPT field.                 */
  #define VPRCSR_MCAUSE_INTERRUPT_Min (0x0UL)        /*!< Min enumerator value of INTERRUPT field.                             */
  #define VPRCSR_MCAUSE_INTERRUPT_Max (0x1UL)        /*!< Max enumerator value of INTERRUPT field.                             */
  #define VPRCSR_MCAUSE_INTERRUPT_EXCEPTION (0x0UL)  /*!< (unspecified)                                                        */
  #define VPRCSR_MCAUSE_INTERRUPT_INTERRUPT (0x1UL)  /*!< (unspecified)                                                        */


/**
  * @brief MTVAL [VPRCSR_MTVAL] Machine Trap Value
  */
  #define VPRCSR_MTVAL (0x00000343ul)
  #define VPRCSR_MTVAL_ResetValue (0x00000000UL)     /*!< Reset value of MTVAL register.                                       */

/* VAL @Bits 0..31 : Machine Trap Value */
  #define VPRCSR_MTVAL_VAL_Pos (0UL)                 /*!< Position of VAL field.                                               */
  #define VPRCSR_MTVAL_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MTVAL_VAL_Pos) /*!< Bit mask of VAL field.                              */


/**
  * @brief MINTSTATUS [VPRCSR_MINTSTATUS] M-mode Interrupt Status
  */
  #define VPRCSR_MINTSTATUS (0x00000346ul)
  #define VPRCSR_MINTSTATUS_ResetValue (0x00000000UL) /*!< Reset value of MINTSTATUS register.                                 */

/* MIL @Bits 24..31 : M-Mode interrupt level */
  #define VPRCSR_MINTSTATUS_MIL_Pos (24UL)           /*!< Position of MIL field.                                               */
  #define VPRCSR_MINTSTATUS_MIL_Msk (0xFFUL << VPRCSR_MINTSTATUS_MIL_Pos) /*!< Bit mask of MIL field.                          */


/**
  * @brief MINTTHRESH [VPRCSR_MINTTHRESH] M-mode Interrupt-level Threshold
  */
  #define VPRCSR_MINTTHRESH (0x00000347ul)
  #define VPRCSR_MINTTHRESH_ResetValue (0x00000000UL) /*!< Reset value of MINTTHRESH register.                                 */

/* TH @Bits 0..7 : M-Mode Interrupt-level Threshold */
  #define VPRCSR_MINTTHRESH_TH_Pos (0UL)             /*!< Position of TH field.                                                */
  #define VPRCSR_MINTTHRESH_TH_Msk (0xFFUL << VPRCSR_MINTTHRESH_TH_Pos) /*!< Bit mask of TH field.                             */
  #define VPRCSR_MINTTHRESH_TH_Min (0x0UL)           /*!< Min enumerator value of TH field.                                    */
  #define VPRCSR_MINTTHRESH_TH_Max (0xFFUL)          /*!< Max enumerator value of TH field.                                    */
  #define VPRCSR_MINTTHRESH_TH_DISABLED (0x00UL)     /*!< Threshold disabled                                                   */
  #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL0 (0x3FUL) /*!< Threshold level 0                                                    */
  #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL1 (0x7FUL) /*!< Threshold level 1                                                    */
  #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL2 (0xBFUL) /*!< Threshold level 2                                                    */
  #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL3 (0xFFUL) /*!< Threshold level 3                                                    */


/**
  * @brief MCLICBASE [VPRCSR_MCLICBASE] Machine CLIC Base
  */
  #define VPRCSR_MCLICBASE (0x00000350ul)
  #define VPRCSR_MCLICBASE_ResetValue (0xF0000000UL) /*!< Reset value of MCLICBASE register.                                   */

/* VAL @Bits 0..31 : CLIC base address value */
  #define VPRCSR_MCLICBASE_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
  #define VPRCSR_MCLICBASE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCLICBASE_VAL_Pos) /*!< Bit mask of VAL field.                      */


/**
  * @brief TSELECT [VPRCSR_TSELECT] Trigger Select
  */
  #define VPRCSR_TSELECT (0x000007A0ul)
  #define VPRCSR_TSELECT_ResetValue (0x00000000UL)   /*!< Reset value of TSELECT register.                                     */

/* VAL @Bits 0..31 : Trigger Select value */
  #define VPRCSR_TSELECT_VAL_Pos (0UL)               /*!< Position of VAL field.                                               */
  #define VPRCSR_TSELECT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_TSELECT_VAL_Pos) /*!< Bit mask of VAL field.                          */


/**
  * @brief TDATA1 [VPRCSR_TDATA1] Trigger Data 1
  */
  #define VPRCSR_TDATA1 (0x000007A1ul)
  #define VPRCSR_TDATA1_ResetValue (0x00000000UL)    /*!< Reset value of TDATA1 register.                                      */

/* DATA @Bits 0..26 : Trigger Specific Data */
  #define VPRCSR_TDATA1_DATA_Pos (0UL)               /*!< Position of DATA field.                                              */
  #define VPRCSR_TDATA1_DATA_Msk (0x7FFFFFFUL << VPRCSR_TDATA1_DATA_Pos) /*!< Bit mask of DATA field.                          */

/* DMODE @Bit 27 : Debug Mode */
  #define VPRCSR_TDATA1_DMODE_Pos (27UL)             /*!< Position of DMODE field.                                             */
  #define VPRCSR_TDATA1_DMODE_Msk (0x1UL << VPRCSR_TDATA1_DMODE_Pos) /*!< Bit mask of DMODE field.                             */
  #define VPRCSR_TDATA1_DMODE_Min (0x0UL)            /*!< Min enumerator value of DMODE field.                                 */
  #define VPRCSR_TDATA1_DMODE_Max (0x1UL)            /*!< Max enumerator value of DMODE field.                                 */
  #define VPRCSR_TDATA1_DMODE_BOTH (0x0UL)           /*!< Both Debug and M-mode can write the tdata registers at the selected
                                                          tselect.*/
  #define VPRCSR_TDATA1_DMODE_ONLYDEBUG (0x1UL)      /*!< Only Debug Mode can write the tdata registers at the selected tselect.
                                                          Writes from other modes are ignored.*/

/* TYPE @Bits 28..31 : Type */
  #define VPRCSR_TDATA1_TYPE_Pos (28UL)              /*!< Position of TYPE field.                                              */
  #define VPRCSR_TDATA1_TYPE_Msk (0xFUL << VPRCSR_TDATA1_TYPE_Pos) /*!< Bit mask of TYPE field.                                */
  #define VPRCSR_TDATA1_TYPE_Min (0x0UL)             /*!< Min enumerator value of TYPE field.                                  */
  #define VPRCSR_TDATA1_TYPE_Max (0xFUL)             /*!< Max enumerator value of TYPE field.                                  */
  #define VPRCSR_TDATA1_TYPE_NOTRIGGER (0x0UL)       /*!< There is no trigger at this tselect                                  */
  #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL)           /*!< The trigger is an address match trigger. The remaining bits in this
                                                          register act as described in mcontrol*/
  #define VPRCSR_TDATA1_TYPE_REMAP (0xFUL)           /*!< This trigger is a remapping trigger. The remaining bits in this
                                                          register behave as described in remapping functionality*/


/**
  * @brief TDATA2 [VPRCSR_TDATA2] Trigger Data 2
  */
  #define VPRCSR_TDATA2 (0x000007A2ul)
  #define VPRCSR_TDATA2_ResetValue (0x00000000UL)    /*!< Reset value of TDATA2 register.                                      */

/* DATA @Bits 0..31 : Trigger Specific Data */
  #define VPRCSR_TDATA2_DATA_Pos (0UL)               /*!< Position of DATA field.                                              */
  #define VPRCSR_TDATA2_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA2_DATA_Pos) /*!< Bit mask of DATA field.                         */


/**
  * @brief TDATA3 [VPRCSR_TDATA3] Trigger Data 3
  */
  #define VPRCSR_TDATA3 (0x000007A3ul)
  #define VPRCSR_TDATA3_ResetValue (0x00000000UL)    /*!< Reset value of TDATA3 register.                                      */

/* DATA @Bits 0..31 : Trigger Specific Data */
  #define VPRCSR_TDATA3_DATA_Pos (0UL)               /*!< Position of DATA field.                                              */
  #define VPRCSR_TDATA3_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA3_DATA_Pos) /*!< Bit mask of DATA field.                         */


/**
  * @brief TINFO [VPRCSR_TINFO] Trigger Info
  */
  #define VPRCSR_TINFO (0x000007A4ul)
  #define VPRCSR_TINFO_ResetValue (0x00000000UL)     /*!< Reset value of TINFO register.                                       */

/* INFO @Bits 0..15 : Trigger Info value */
  #define VPRCSR_TINFO_INFO_Pos (0UL)                /*!< Position of INFO field.                                              */
  #define VPRCSR_TINFO_INFO_Msk (0xFFFFUL << VPRCSR_TINFO_INFO_Pos) /*!< Bit mask of INFO field.                               */


/**
  * @brief TCONTROL [VPRCSR_TCONTROL] Trigger Control
  */
  #define VPRCSR_TCONTROL (0x000007A5ul)
  #define VPRCSR_TCONTROL_ResetValue (0x00000000UL)  /*!< Reset value of TCONTROL register.                                    */

/* MTE @Bit 3 : Mode Trigger Enable */
  #define VPRCSR_TCONTROL_MTE_Pos (3UL)              /*!< Position of MTE field.                                               */
  #define VPRCSR_TCONTROL_MTE_Msk (0x1UL << VPRCSR_TCONTROL_MTE_Pos) /*!< Bit mask of MTE field.                               */
  #define VPRCSR_TCONTROL_MTE_Min (0x0UL)            /*!< Min enumerator value of MTE field.                                   */
  #define VPRCSR_TCONTROL_MTE_Max (0x1UL)            /*!< Max enumerator value of MTE field.                                   */
  #define VPRCSR_TCONTROL_MTE_DONTMATCH (0x0UL)      /*!< Triggers with action=0 do not match/fire while the hart is in M-mode */
  #define VPRCSR_TCONTROL_MTE_MATCH (0x1UL)          /*!< Triggers do match/fire while the hart is in M-mode. When a trap into
                                                          M-mode is taken, mte is set to 0. When mret is executed, mte is set to
                                                          the value of mpte*/

/* MPTE @Bit 7 : Mode Previous Trigger Enable */
  #define VPRCSR_TCONTROL_MPTE_Pos (7UL)             /*!< Position of MPTE field.                                              */
  #define VPRCSR_TCONTROL_MPTE_Msk (0x1UL << VPRCSR_TCONTROL_MPTE_Pos) /*!< Bit mask of MPTE field.                            */


/**
  * @brief DCSR [VPRCSR_DCSR] Debug Control and Status
  */
  #define VPRCSR_DCSR (0x000007B0ul)
  #define VPRCSR_DCSR_ResetValue (0x40000003UL)      /*!< Reset value of DCSR register.                                        */

/* PRV @Bits 0..1 : Privilege level */
  #define VPRCSR_DCSR_PRV_Pos (0UL)                  /*!< Position of PRV field.                                               */
  #define VPRCSR_DCSR_PRV_Msk (0x3UL << VPRCSR_DCSR_PRV_Pos) /*!< Bit mask of PRV field.                                       */
  #define VPRCSR_DCSR_PRV_Min (0x3UL)                /*!< Min enumerator value of PRV field.                                   */
  #define VPRCSR_DCSR_PRV_Max (0x3UL)                /*!< Max enumerator value of PRV field.                                   */
  #define VPRCSR_DCSR_PRV_MACHINE (0x3UL)            /*!< (unspecified)                                                        */

/* STEP @Bit 2 : Step */
  #define VPRCSR_DCSR_STEP_Pos (2UL)                 /*!< Position of STEP field.                                              */
  #define VPRCSR_DCSR_STEP_Msk (0x1UL << VPRCSR_DCSR_STEP_Pos) /*!< Bit mask of STEP field.                                    */

/* CAUSE @Bits 6..8 : Debug Mode enter cause */
  #define VPRCSR_DCSR_CAUSE_Pos (6UL)                /*!< Position of CAUSE field.                                             */
  #define VPRCSR_DCSR_CAUSE_Msk (0x7UL << VPRCSR_DCSR_CAUSE_Pos) /*!< Bit mask of CAUSE field.                                 */
  #define VPRCSR_DCSR_CAUSE_Min (0x1UL)              /*!< Min enumerator value of CAUSE field.                                 */
  #define VPRCSR_DCSR_CAUSE_Max (0x5UL)              /*!< Max enumerator value of CAUSE field.                                 */
  #define VPRCSR_DCSR_CAUSE_EBREAK (0x1UL)           /*!< An ebreak instruction was executed. (priority 3)                     */
  #define VPRCSR_DCSR_CAUSE_TRIGGER (0x2UL)          /*!< The Trigger Module caused a breakpoint exception. (priority 4,
                                                          highest)*/
  #define VPRCSR_DCSR_CAUSE_HALTREQ (0x3UL)          /*!< The debugger requested entry to Debug Mode using haltreq. (priority
                                                          1)*/
  #define VPRCSR_DCSR_CAUSE_STEP (0x4UL)             /*!< The hart single stepped because step was set. (priority 0, lowest)   */
  #define VPRCSR_DCSR_CAUSE_RESETHALTREQ (0x5UL)     /*!< The hart halted directly out of reset due to resethaltreq. It is also
                                                          acceptable to report 3 when this happens. (priority 2)*/

/* STEPIE @Bit 11 : Step Interrupt Enable */
  #define VPRCSR_DCSR_STEPIE_Pos (11UL)              /*!< Position of STEPIE field.                                            */
  #define VPRCSR_DCSR_STEPIE_Msk (0x1UL << VPRCSR_DCSR_STEPIE_Pos) /*!< Bit mask of STEPIE field.                              */
  #define VPRCSR_DCSR_STEPIE_Min (0x0UL)             /*!< Min enumerator value of STEPIE field.                                */
  #define VPRCSR_DCSR_STEPIE_Max (0x1UL)             /*!< Max enumerator value of STEPIE field.                                */
  #define VPRCSR_DCSR_STEPIE_Disabled (0x0UL)        /*!< Interrupts are disabled during single stepping                       */
  #define VPRCSR_DCSR_STEPIE_Enabled (0x1UL)         /*!< Interrupts are enabled during single stepping. Implementations may
                                                          hard wire this bit to 0. In that case interrupt behavior can be
                                                          emulated by the debugger.*/

/* EBREAKM @Bit 15 : M-mode ebreak */
  #define VPRCSR_DCSR_EBREAKM_Pos (15UL)             /*!< Position of EBREAKM field.                                           */
  #define VPRCSR_DCSR_EBREAKM_Msk (0x1UL << VPRCSR_DCSR_EBREAKM_Pos) /*!< Bit mask of EBREAKM field.                           */
  #define VPRCSR_DCSR_EBREAKM_Min (0x0UL)            /*!< Min enumerator value of EBREAKM field.                               */
  #define VPRCSR_DCSR_EBREAKM_Max (0x1UL)            /*!< Max enumerator value of EBREAKM field.                               */
  #define VPRCSR_DCSR_EBREAKM_SPEC (0x0UL)           /*!< ebreak instructions in M-mode behave as described in the Privileged
                                                          Spe*/
  #define VPRCSR_DCSR_EBREAKM_ENTERDBG (0x1UL)       /*!< ebreak instructions in M-mode enter Debug Mode                       */

/* XDEBUGVER @Bits 28..31 : External Debug version */
  #define VPRCSR_DCSR_XDEBUGVER_Pos (28UL)           /*!< Position of XDEBUGVER field.                                         */
  #define VPRCSR_DCSR_XDEBUGVER_Msk (0xFUL << VPRCSR_DCSR_XDEBUGVER_Pos) /*!< Bit mask of XDEBUGVER field.                     */
  #define VPRCSR_DCSR_XDEBUGVER_Min (0x4UL)          /*!< Min enumerator value of XDEBUGVER field.                             */
  #define VPRCSR_DCSR_XDEBUGVER_Max (0x4UL)          /*!< Max enumerator value of XDEBUGVER field.                             */
  #define VPRCSR_DCSR_XDEBUGVER_STDDBG (0x4UL)       /*!< External debug support exists as it is described in this document    */


/**
  * @brief DPC [VPRCSR_DPC] Debug PC
  */
  #define VPRCSR_DPC (0x000007B1ul)
  #define VPRCSR_DPC_ResetValue (0x00000000UL)       /*!< Reset value of DPC register.                                         */

/* VAL @Bits 0..31 : Debug PC value */
  #define VPRCSR_DPC_VAL_Pos (0UL)                   /*!< Position of VAL field.                                               */
  #define VPRCSR_DPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_DPC_VAL_Pos) /*!< Bit mask of VAL field.                                  */


/**
  * @brief MCYCLE [VPRCSR_MCYCLE] Machine Cycle Counter
  */
  #define VPRCSR_MCYCLE (0x00000B00ul)
  #define VPRCSR_MCYCLE_ResetValue (0x00000000UL)    /*!< Reset value of MCYCLE register.                                      */

/* VAL @Bits 0..31 : Machine Cycle Counter value */
  #define VPRCSR_MCYCLE_VAL_Pos (0UL)                /*!< Position of VAL field.                                               */
  #define VPRCSR_MCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLE_VAL_Pos) /*!< Bit mask of VAL field.                            */


/**
  * @brief MINSTRET [VPRCSR_MINSTRET] Machine Instruction Counter
  */
  #define VPRCSR_MINSTRET (0x00000B02ul)
  #define VPRCSR_MINSTRET_ResetValue (0x00000000UL)  /*!< Reset value of MINSTRET register.                                    */

/* VAL @Bits 0..31 : Machine Instruction Counter value */
  #define VPRCSR_MINSTRET_VAL_Pos (0UL)              /*!< Position of VAL field.                                               */
  #define VPRCSR_MINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRET_VAL_Pos) /*!< Bit mask of VAL field.                        */


/**
  * @brief MCYCLEH [VPRCSR_MCYCLEH] Machine Cycle Counter (Upper part)
  */
  #define VPRCSR_MCYCLEH (0x00000B80ul)
  #define VPRCSR_MCYCLEH_ResetValue (0x00000000UL)   /*!< Reset value of MCYCLEH register.                                     */

/* VAL @Bits 0..31 : Machine Cycle Counter value */
  #define VPRCSR_MCYCLEH_VAL_Pos (0UL)               /*!< Position of VAL field.                                               */
  #define VPRCSR_MCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLEH_VAL_Pos) /*!< Bit mask of VAL field.                          */


/**
  * @brief MINSTRETH [VPRCSR_MINSTRETH] Machine Instruction Counter (Upper part)
  */
  #define VPRCSR_MINSTRETH (0x00000B82ul)
  #define VPRCSR_MINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of MINSTRETH register.                                   */

/* VAL @Bits 0..31 : Machine Instruction Counter (Upper part) value */
  #define VPRCSR_MINSTRETH_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
  #define VPRCSR_MINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRETH_VAL_Pos) /*!< Bit mask of VAL field.                      */


/**
  * @brief UCYCLE [VPRCSR_UCYCLE] User Cycle Counter
  */
  #define VPRCSR_UCYCLE (0x00000C00ul)
  #define VPRCSR_UCYCLE_ResetValue (0x00000000UL)    /*!< Reset value of UCYCLE register.                                      */

/* VAL @Bits 0..31 : User Cycle Counter value */
  #define VPRCSR_UCYCLE_VAL_Pos (0UL)                /*!< Position of VAL field.                                               */
  #define VPRCSR_UCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLE_VAL_Pos) /*!< Bit mask of VAL field.                            */


/**
  * @brief UINSTRET [VPRCSR_UINSTRET] User Instruction Counter
  */
  #define VPRCSR_UINSTRET (0x00000C02ul)
  #define VPRCSR_UINSTRET_ResetValue (0x00000000UL)  /*!< Reset value of UINSTRET register.                                    */

/* VAL @Bits 0..31 : User Instruction Counter value */
  #define VPRCSR_UINSTRET_VAL_Pos (0UL)              /*!< Position of VAL field.                                               */
  #define VPRCSR_UINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRET_VAL_Pos) /*!< Bit mask of VAL field.                        */


/**
  * @brief UCYCLEH [VPRCSR_UCYCLEH] User Cycle Counter (Upper part)
  */
  #define VPRCSR_UCYCLEH (0x00000C80ul)
  #define VPRCSR_UCYCLEH_ResetValue (0x00000000UL)   /*!< Reset value of UCYCLEH register.                                     */

/* VAL @Bits 0..31 : User Cycle Counter value */
  #define VPRCSR_UCYCLEH_VAL_Pos (0UL)               /*!< Position of VAL field.                                               */
  #define VPRCSR_UCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLEH_VAL_Pos) /*!< Bit mask of VAL field.                          */


/**
  * @brief UINSTRETH [VPRCSR_UINSTRETH] User Instruction Counter (Upper part)
  */
  #define VPRCSR_UINSTRETH (0x00000C82ul)
  #define VPRCSR_UINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of UINSTRETH register.                                   */

/* VAL @Bits 0..31 : User Instruction Counter (Upper part) value */
  #define VPRCSR_UINSTRETH_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
  #define VPRCSR_UINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRETH_VAL_Pos) /*!< Bit mask of VAL field.                      */


/**
  * @brief MVENDORID [VPRCSR_MVENDORID] Machine Vendor ID
  */
  #define VPRCSR_MVENDORID (0x00000F11ul)
  #define VPRCSR_MVENDORID_ResetValue (0x00000144UL) /*!< Reset value of MVENDORID register.                                   */

/* OFFSET @Bits 0..6 : MVENDORID encodes the final byte in the Offset field, discarding the parity bit */
  #define VPRCSR_MVENDORID_OFFSET_Pos (0UL)          /*!< Position of OFFSET field.                                            */
  #define VPRCSR_MVENDORID_OFFSET_Msk (0x7FUL << VPRCSR_MVENDORID_OFFSET_Pos) /*!< Bit mask of OFFSET field.                   */

/* BANK @Bits 7..31 : MVENDORID encodes the number of one-byte continuation codes in the Bank field */
  #define VPRCSR_MVENDORID_BANK_Pos (7UL)            /*!< Position of BANK field.                                              */
  #define VPRCSR_MVENDORID_BANK_Msk (0x1FFFFFFUL << VPRCSR_MVENDORID_BANK_Pos) /*!< Bit mask of BANK field.                    */


/**
  * @brief MARCHID [VPRCSR_MARCHID] Machine Architecture ID
  */
  #define VPRCSR_MARCHID (0x00000F12ul)
  #define VPRCSR_MARCHID_ResetValue (0x8000006EUL)   /*!< Reset value of MARCHID register.                                     */

/* MULDIV @Bits 0..1 : Indicates the MULDIV parameter option */
  #define VPRCSR_MARCHID_MULDIV_Pos (0UL)            /*!< Position of MULDIV field.                                            */
  #define VPRCSR_MARCHID_MULDIV_Msk (0x3UL << VPRCSR_MARCHID_MULDIV_Pos) /*!< Bit mask of MULDIV field.                        */

/* HIBERNATE @Bit 2 : Indicates the POWEROFFSLEEP parameter option */
  #define VPRCSR_MARCHID_HIBERNATE_Pos (2UL)         /*!< Position of HIBERNATE field.                                         */
  #define VPRCSR_MARCHID_HIBERNATE_Msk (0x1UL << VPRCSR_MARCHID_HIBERNATE_Pos) /*!< Bit mask of HIBERNATE field.               */

/* DBG @Bit 3 : Indicates the DBG parameter option */
  #define VPRCSR_MARCHID_DBG_Pos (3UL)               /*!< Position of DBG field.                                               */
  #define VPRCSR_MARCHID_DBG_Msk (0x1UL << VPRCSR_MARCHID_DBG_Pos) /*!< Bit mask of DBG field.                                 */

/* REMAP @Bit 4 : Indicates the REMAP parameter option */
  #define VPRCSR_MARCHID_REMAP_Pos (4UL)             /*!< Position of REMAP field.                                             */
  #define VPRCSR_MARCHID_REMAP_Msk (0x1UL << VPRCSR_MARCHID_REMAP_Pos) /*!< Bit mask of REMAP field.                           */

/* BUSWIDTH @Bit 5 : Indicates the BUS_WIDTH parameter option */
  #define VPRCSR_MARCHID_BUSWIDTH_Pos (5UL)          /*!< Position of BUSWIDTH field.                                          */
  #define VPRCSR_MARCHID_BUSWIDTH_Msk (0x1UL << VPRCSR_MARCHID_BUSWIDTH_Pos) /*!< Bit mask of BUSWIDTH field.                  */

/* BKPT @Bits 6..9 : Indicates the BKPT parameter option */
  #define VPRCSR_MARCHID_BKPT_Pos (6UL)              /*!< Position of BKPT field.                                              */
  #define VPRCSR_MARCHID_BKPT_Msk (0xFUL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field.                              */

/* CACHE @Bit 10 : Indicates that the CACHE is present */
  #define VPRCSR_MARCHID_CACHE_Pos (10UL)            /*!< Position of CACHE field.                                             */
  #define VPRCSR_MARCHID_CACHE_Msk (0x1UL << VPRCSR_MARCHID_CACHE_Pos) /*!< Bit mask of CACHE field.                           */

/* CACHEEXTRATAGBUF @Bits 11..13 : Indicates the number of extra TAG buffers in CACHE */
  #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos (11UL) /*!< Position of CACHEEXTRATAGBUF field.                                  */
  #define VPRCSR_MARCHID_CACHEEXTRATAGBUF_Msk (0x7UL << VPRCSR_MARCHID_CACHEEXTRATAGBUF_Pos) /*!< Bit mask of CACHEEXTRATAGBUF
                                                                            field.*/

/* RETAINED @Bit 16 : Indicates the RETAINED parameter option */
  #define VPRCSR_MARCHID_RETAINED_Pos (16UL)         /*!< Position of RETAINED field.                                          */
  #define VPRCSR_MARCHID_RETAINED_Msk (0x1UL << VPRCSR_MARCHID_RETAINED_Pos) /*!< Bit mask of RETAINED field.                  */

/* IMPLEM @Bit 31 : Indicates a non-open implementation */
  #define VPRCSR_MARCHID_IMPLEM_Pos (31UL)           /*!< Position of IMPLEM field.                                            */
  #define VPRCSR_MARCHID_IMPLEM_Msk (0x1UL << VPRCSR_MARCHID_IMPLEM_Pos) /*!< Bit mask of IMPLEM field.                        */


/**
  * @brief MIMPID [VPRCSR_MIMPID] Machine Implementation ID
  */
  #define VPRCSR_MIMPID (0x00000F13ul)
  #define VPRCSR_MIMPID_ResetValue (0x00010300UL)    /*!< Reset value of MIMPID register.                                      */

/* PATCHREV @Bits 0..7 : Indicates the number of the patch revision */
  #define VPRCSR_MIMPID_PATCHREV_Pos (0UL)           /*!< Position of PATCHREV field.                                          */
  #define VPRCSR_MIMPID_PATCHREV_Msk (0xFFUL << VPRCSR_MIMPID_PATCHREV_Pos) /*!< Bit mask of PATCHREV field.                   */

/* MINORREV @Bits 8..15 : Indicates the number of the minor revision */
  #define VPRCSR_MIMPID_MINORREV_Pos (8UL)           /*!< Position of MINORREV field.                                          */
  #define VPRCSR_MIMPID_MINORREV_Msk (0xFFUL << VPRCSR_MIMPID_MINORREV_Pos) /*!< Bit mask of MINORREV field.                   */

/* MAJORREV @Bits 16..23 : Indicates the number of the major revison */
  #define VPRCSR_MIMPID_MAJORREV_Pos (16UL)          /*!< Position of MAJORREV field.                                          */
  #define VPRCSR_MIMPID_MAJORREV_Msk (0xFFUL << VPRCSR_MIMPID_MAJORREV_Pos) /*!< Bit mask of MAJORREV field.                   */


/**
  * @brief MHARTID [VPRCSR_MHARTID] Machine Hart ID
  */
  #define VPRCSR_MHARTID (0x00000F14ul)
  #define VPRCSR_MHARTID_ResetValue (0x0000000EUL)   /*!< Reset value of MHARTID register.                                     */

/* HARTNUM @Bits 0..31 : Machine Hart ID value */
  #define VPRCSR_MHARTID_HARTNUM_Pos (0UL)           /*!< Position of HARTNUM field.                                           */
  #define VPRCSR_MHARTID_HARTNUM_Msk (0xFFFFFFFFUL << VPRCSR_MHARTID_HARTNUM_Pos) /*!< Bit mask of HARTNUM field.              */


/**
  * @brief NORDIC [VPRCSR_NORDIC] (unspecified)
  */

/**
  * @brief VPRNORDICCTRL [VPRCSR_NORDIC_VPRNORDICCTRL] Nordic Core Control
  */
  #define VPRCSR_NORDIC_VPRNORDICCTRL (0x000007C0ul)
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ResetValue (0x00000000UL) /*!< Reset value of VPRNORDICCTRL register.                    */

/* ENABLERTPERIPH @Bit 0 : Control bit to enable Real-Time Peripherals */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos (0UL) /*!< Position of ENABLERTPERIPH field.                          */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos) /*!< Bit mask
                                                                            of ENABLERTPERIPH field.*/
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Min (0x0UL) /*!< Min enumerator value of ENABLERTPERIPH field.            */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Max (0x1UL) /*!< Max enumerator value of ENABLERTPERIPH field.            */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Disabled (0x0UL) /*!< (unspecified)                                       */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Enabled (0x1UL) /*!< (unspecified)                                        */

/* ENABLEREMAP @Bit 3 : Enable remap feature */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos (3UL) /*!< Position of ENABLEREMAP field.                                */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos) /*!< Bit mask of
                                                                            ENABLEREMAP field.*/
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Min (0x0UL) /*!< Min enumerator value of ENABLEREMAP field.                  */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Max (0x1UL) /*!< Max enumerator value of ENABLEREMAP field.                  */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Disabled (0x0UL) /*!< (unspecified)                                          */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Enabled (0x1UL) /*!< (unspecified)                                           */

/* CNTIRQENABLE @Bit 6 : Enables the generation of IRQ number COUNTER_IRQ_NUM */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos (6UL) /*!< Position of CNTIRQENABLE field.                              */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos) /*!< Bit mask of
                                                                            CNTIRQENABLE field.*/
  #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Min (0x0UL) /*!< Min enumerator value of CNTIRQENABLE field.                */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Max (0x1UL) /*!< Max enumerator value of CNTIRQENABLE field.                */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Disabled (0x0UL) /*!< (unspecified)                                         */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Enabled (0x1UL) /*!< (unspecified)                                          */

/* VPRBUSPRI @Bit 7 : Arbitration priority on bus */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Pos (7UL) /*!< Position of VPRBUSPRI field.                                    */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Pos) /*!< Bit mask of
                                                                            VPRBUSPRI field.*/
  #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Min (0x0UL) /*!< Min enumerator value of VPRBUSPRI field.                      */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_Max (0x1UL) /*!< Max enumerator value of VPRBUSPRI field.                      */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_LowPriority (0x0UL) /*!< Low priority for VPR RAM transactions on bus          */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_VPRBUSPRI_HighPriority (0x1UL) /*!< High priority for VPR RAM transactions on bus        */

/* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field.                                   */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos) /*!< Bit mask of
                                                                            NORDICKEY field.*/
  #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field.                   */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field.                   */
  #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled                                          */


/**
  * @brief VPRNORDICSLEEPCTRL [VPRCSR_NORDIC_VPRNORDICSLEEPCTRL] Nordic Sleep Control
  */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL (0x000007C1ul)
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICSLEEPCTRL register.          */

/* SLEEPSTATE @Bits 0..3 : Sleep State */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field.                             */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Msk (0xFUL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos) /*!< Bit
                                                                            mask of SLEEPSTATE field.*/
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Min (0x0UL) /*!< Min enumerator value of SLEEPSTATE field.               */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Max (0xFUL) /*!< Max enumerator value of SLEEPSTATE field.               */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_WAIT (0x0UL) /*!< Sleep is not turning off the clock                     */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_RESET (0x2UL) /*!< Sleep state default reset value. Going to sleep with
                                                                         sleep state = RESET has the same effect as going to
                                                                         sleep with sleep state = WAIT*/
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_SLEEP (0x5UL) /*!< Sleep is turning the clock off                        */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_DEEPSLEEP (0x7UL) /*!< Sleep is turning the clock off and power is turned
                                                                            off*/
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_HIBERNATE (0xFUL) /*!< sleep is turning the clock off and all the
                                                                            registers are saved automatically, restart by a
                                                                            reset*/

/* RETURNTOSLEEP @Bit 16 : Return to Sleep */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos (16UL) /*!< Position of RETURNTOSLEEP field.                      */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos) /*!<
                                                                            Bit mask of RETURNTOSLEEP field.*/
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Min (0x0UL) /*!< Min enumerator value of RETURNTOSLEEP field.         */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Max (0x1UL) /*!< Max enumerator value of RETURNTOSLEEP field.         */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Disabled (0x0UL) /*!< (unspecified)                                   */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Enabled (0x1UL) /*!< (unspecified)                                    */

/* STACKONSLEEP @Bit 17 : Stack on Sleep */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos (17UL) /*!< Position of STACKONSLEEP field.                        */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos) /*!<
                                                                            Bit mask of STACKONSLEEP field.*/
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Min (0x0UL) /*!< Min enumerator value of STACKONSLEEP field.           */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Max (0x1UL) /*!< Max enumerator value of STACKONSLEEP field.           */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Disabled (0x0UL) /*!< (unspecified)                                    */
  #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Enabled (0x1UL) /*!< (unspecified)                                     */


/**
  * @brief VPRNORDICFEATURESDISABLE [VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE] (unspecified)
  */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE (0x000007C2ul)
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICFEATURESDISABLE
                                                                            register.*/

/* DISABLECLICROUNDROBIN @Bit 3 : Disable CLIC Round Robin */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos (3UL) /*!< Position of DISABLECLICROUNDROBIN field. */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos)
                                                                            /*!< Bit mask of DISABLECLICROUNDROBIN field.*/
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Min (0x0UL) /*!< Min enumerator value of
                                                                            DISABLECLICROUNDROBIN field.*/
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Max (0x1UL) /*!< Max enumerator value of
                                                                            DISABLECLICROUNDROBIN field.*/
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Enabled (0x0UL) /*!< (unspecified)                      */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Disabled (0x1UL) /*!< (unspecified)                     */

/* UNRECOVRETURN @Bit 4 : Unrecoverable Return */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos (4UL) /*!< Position of UNRECOVRETURN field.                 */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos)
                                                                            /*!< Bit mask of UNRECOVRETURN field.*/
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Min (0x0UL) /*!< Min enumerator value of UNRECOVRETURN field.   */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Max (0x1UL) /*!< Max enumerator value of UNRECOVRETURN field.   */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Disabled (0x0UL) /*!< (unspecified)                             */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Enabled (0x1UL) /*!< (unspecified)                              */

/* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field.                        */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos)
                                                                            /*!< Bit mask of NORDICKEY field.*/
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field.        */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field.        */
  #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled                               */


/**
  * @brief VIOPINS [VPRCSR_NORDIC_VIOPINS] VPR pins used for Real Time Peripherals VIO
  */
  #define VPRCSR_NORDIC_VIOPINS (0x000007C3ul)
  #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x0000FFFFUL) /*!< Reset value of VIOPINS register.                                */

/* VAL @Bits 0..31 : VPR pins used for Real Time Peripherals VIO */
  #define VPRCSR_NORDIC_VIOPINS_VAL_Pos (0UL)        /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_VIOPINS_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_VIOPINS_VAL_Pos) /*!< Bit mask of VAL field.            */


/**
  * @brief EXTPARAMS [VPRCSR_NORDIC_EXTPARAMS] Reads values of external configuration parameters
  */
  #define VPRCSR_NORDIC_EXTPARAMS (0x000007C4ul)
  #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x0000000EUL) /*!< Reset value of EXTPARAMS register.                            */

/* MULDIV @Bits 0..1 : value of MULDIV */
  #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos (0UL)   /*!< Position of MULDIV field.                                            */
  #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Msk (0x3UL << VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos) /*!< Bit mask of MULDIV field.      */

/* DBG @Bit 2 : value of DBG */
  #define VPRCSR_NORDIC_EXTPARAMS_DBG_Pos (2UL)      /*!< Position of DBG field.                                               */
  #define VPRCSR_NORDIC_EXTPARAMS_DBG_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_DBG_Pos) /*!< Bit mask of DBG field.               */

/* BKPT @Bits 3..6 : value of BKPT */
  #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos (3UL)     /*!< Position of BKPT field.                                              */
  #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Msk (0xFUL << VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos) /*!< Bit mask of BKPT field.            */

/* REMAP @Bit 7 : value of REMAP */
  #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos (7UL)    /*!< Position of REMAP field.                                             */
  #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos) /*!< Bit mask of REMAP field.         */


/**
  * @brief CACHE [VPRCSR_NORDIC_CACHE] (unspecified)
  */

/**
  * @brief AXCACHE [VPRCSR_NORDIC_CACHE_AXCACHE] Memory type encoding
  */
  #define VPRCSR_NORDIC_CACHE_AXCACHE (0x000007C5ul)
  #define VPRCSR_NORDIC_CACHE_AXCACHE_ResetValue (0x00000EEEUL) /*!< Reset value of AXCACHE register.                          */

/* AWCACHE @Bits 0..3 : Memory type for data stores */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Pos (0UL) /*!< Position of AWCACHE field.                                        */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Pos) /*!< Bit mask of AWCACHE
                                                                            field.*/
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Min (0x0UL) /*!< Min enumerator value of AWCACHE field.                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_Max (0xFUL) /*!< Max enumerator value of AWCACHE field.                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_DEVNONBUFF (0x0UL) /*!< Device Non-Bufferable                                    */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_DEVBUFF (0x1UL) /*!< Device Bufferable                                           */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_NNONCACHENONBUFF (0x2UL) /*!< Normal Non-cacheable Non-bufferable                */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_NNONCACHEBUFF (0x3UL) /*!< Normal Non-cacheable Bufferable                       */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHNALLOC (0x6UL) /*!< Write-through No-allocate                             */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHRALLOC (0x6UL) /*!< Write-through Read-allocate                           */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHWALLOC (0xEUL) /*!< Write-through Write-allocate                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITETHRWALLOC (0xEUL) /*!< Write-through Read and Write-allocate                */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKNALLOC (0x7UL) /*!< Write-back No-allocate                              */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKRALLOC (0x7UL) /*!< Write-back Read-allocate                            */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKWALLOC (0xFUL) /*!< Write-back Write-allocate                           */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_AWCACHE_WRITEBACKRWALLOC (0xFUL) /*!< Write-back Read and Write-allocate                 */

/* IARCACHE @Bits 4..7 : Memory type for instruction loads */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Pos (4UL) /*!< Position of IARCACHE field.                                      */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Pos) /*!< Bit mask of IARCACHE
                                                                            field.*/
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Min (0x0UL) /*!< Min enumerator value of IARCACHE field.                        */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_Max (0xFUL) /*!< Max enumerator value of IARCACHE field.                        */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_DEVNONBUFF (0x0UL) /*!< Device Non-Bufferable                                   */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_DEVBUFF (0x1UL) /*!< Device Bufferable                                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_NNONCACHENONBUFF (0x2UL) /*!< Normal Non-cacheable Non-bufferable               */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_NNONCACHEBUFF (0x3UL) /*!< Normal Non-cacheable Bufferable                      */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHNALLOC (0xAUL) /*!< Write-through No-allocate                            */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHRALLOC (0xEUL) /*!< Write-through Read-allocate                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHWALLOC (0xAUL) /*!< Write-through Write-allocate                         */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITETHRWALLOC (0xEUL) /*!< Write-through Read and Write-allocate               */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKNALLOC (0xBUL) /*!< Write-back No-allocate                             */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKRALLOC (0xFUL) /*!< Write-back Read-allocate                           */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKWALLOC (0xBUL) /*!< Write-back Write-allocate                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_IARCACHE_WRITEBACKRWALLOC (0xFUL) /*!< Write-back Read and Write-allocate                */

/* DARCACHE @Bits 8..11 : Memory type for data loads */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Pos (8UL) /*!< Position of DARCACHE field.                                      */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Pos) /*!< Bit mask of DARCACHE
                                                                            field.*/
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Min (0x0UL) /*!< Min enumerator value of DARCACHE field.                        */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_Max (0xFUL) /*!< Max enumerator value of DARCACHE field.                        */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_DEVNONBUFF (0x0UL) /*!< Device Non-Bufferable                                   */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_DEVBUFF (0x1UL) /*!< Device Bufferable                                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_NNONCACHENONBUFF (0x2UL) /*!< Normal Non-cacheable Non-bufferable               */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_NNONCACHEBUFF (0x3UL) /*!< Normal Non-cacheable Bufferable                      */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHNALLOC (0xAUL) /*!< Write-through No-allocate                            */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHRALLOC (0xEUL) /*!< Write-through Read-allocate                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHWALLOC (0xAUL) /*!< Write-through Write-allocate                         */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITETHRWALLOC (0xEUL) /*!< Write-through Read and Write-allocate               */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKNALLOC (0xBUL) /*!< Write-back No-allocate                             */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKRALLOC (0xFUL) /*!< Write-back Read-allocate                           */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKWALLOC (0xBUL) /*!< Write-back Write-allocate                          */
  #define VPRCSR_NORDIC_CACHE_AXCACHE_DARCACHE_WRITEBACKRWALLOC (0xFUL) /*!< Write-back Read and Write-allocate                */


/**
  * @brief CTRL [VPRCSR_NORDIC_CACHE_CTRL] Cache control
  */
  #define VPRCSR_NORDIC_CACHE_CTRL (0x000007C8ul)
  #define VPRCSR_NORDIC_CACHE_CTRL_ResetValue (0x00000000UL) /*!< Reset value of CTRL register.                                */

/* ENABLE @Bit 0 : Enable cache */
  #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Pos (0UL)  /*!< Position of ENABLE field.                                            */
  #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Msk (0x1UL << VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Pos) /*!< Bit mask of ENABLE field.    */
  #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                               */
  #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                               */
  #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Disabled (0x0UL) /*!< Cache disabled                                                 */
  #define VPRCSR_NORDIC_CACHE_CTRL_ENABLE_Enabled (0x1UL) /*!< Cache enabled                                                   */

/* CACHECLR @Bit 16 : Cache clear */
  #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Pos (16UL) /*!< Position of CACHECLR field.                                        */
  #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Msk (0x1UL << VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Pos) /*!< Bit mask of CACHECLR
                                                                            field.*/
  #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Min (0x0UL) /*!< Min enumerator value of CACHECLR field.                           */
  #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Max (0x1UL) /*!< Max enumerator value of CACHECLR field.                           */
  #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_NoOperation (0x0UL) /*!< No Operation                                              */
  #define VPRCSR_NORDIC_CACHE_CTRL_CACHECLR_Clear (0x1UL) /*!< Cache clear                                                     */


/**
  * @brief CFG [VPRCSR_NORDIC_CACHE_CFG] Cache configuration
  */
  #define VPRCSR_NORDIC_CACHE_CFG (0x000007C9ul)
  #define VPRCSR_NORDIC_CACHE_CFG_ResetValue (0x00000000UL) /*!< Reset value of CFG register.                                  */

/* CACHESIZE @Bits 0..3 : Cache size is 2^CACHESIZE or (1 << CACHESIZE) KB, with a maximum size of 32KB (CACHESIZE = 5) */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Pos (0UL) /*!< Position of CACHESIZE field.                                        */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Msk (0xFUL << VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Pos) /*!< Bit mask of CACHESIZE
                                                                            field.*/
  #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Min (0x0UL) /*!< Min value of CACHESIZE field.                                     */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHESIZE_Max (0xFUL) /*!< Max size of CACHESIZE field.                                      */

/* CACHELINESIZE @Bit 8 : Cache line size */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Pos (8UL) /*!< Position of CACHELINESIZE field.                                */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Msk (0x1UL << VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Pos) /*!< Bit mask of
                                                                            CACHELINESIZE field.*/
  #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Min (0x0UL) /*!< Min enumerator value of CACHELINESIZE field.                  */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_Max (0x1UL) /*!< Max enumerator value of CACHELINESIZE field.                  */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_CachelineSize32B (0x0UL) /*!< Cache line size is 32 bytes (4 data units)       */
  #define VPRCSR_NORDIC_CACHE_CFG_CACHELINESIZE_CachelineSize64B (0x1UL) /*!< Cache line size is 64 bytes (8 data units)       */


/**
  * @brief DATATAGADDR [VPRCSR_NORDIC_CACHE_DATATAGADDR] Cache tag base address
  */
  #define VPRCSR_NORDIC_CACHE_DATATAGADDR (0x000007CAul)
  #define VPRCSR_NORDIC_CACHE_DATATAGADDR_ResetValue (0x00000000UL) /*!< Reset value of DATATAGADDR register.                  */

/* VAL @Bits 0..31 : Cache tag base address value */
  #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Pos (0UL) /*!< Position of VAL field.                                            */
  #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Pos) /*!< Bit mask of VAL
                                                                            field.*/
  #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Min (0x00000000UL) /*!< Min value of VAL field.                                  */
  #define VPRCSR_NORDIC_CACHE_DATATAGADDR_VAL_Max (0xFFFFFFFCUL) /*!< Max size of VAL field.                                   */


/**
  * @brief DATABASEADDR [VPRCSR_NORDIC_CACHE_DATABASEADDR] Cache data base address
  */
  #define VPRCSR_NORDIC_CACHE_DATABASEADDR (0x000007CBul)
  #define VPRCSR_NORDIC_CACHE_DATABASEADDR_ResetValue (0x00000000UL) /*!< Reset value of DATABASEADDR register.                */

/* VAL @Bits 0..31 : Cache data base address value */
  #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Pos (0UL) /*!< Position of VAL field.                                           */
  #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Pos) /*!< Bit mask of
                                                                            VAL field.*/
  #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Min (0x00000000UL) /*!< Min value of VAL field.                                 */
  #define VPRCSR_NORDIC_CACHE_DATABASEADDR_VAL_Max (0xFFFFFFFCUL) /*!< Max size of VAL field.                                  */


/**
  * @brief RTPERIPHCTRL [VPRCSR_NORDIC_RTPERIPHCTRL] RT peripheral control
  */
  #define VPRCSR_NORDIC_RTPERIPHCTRL (0x000007CCul)
  #define VPRCSR_NORDIC_RTPERIPHCTRL_ResetValue (0x00000000UL) /*!< Reset value of RTPERIPHCTRL register.                      */

/* CLOCKPOLARITY @Bit 0 : Clock polarity */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Pos (0UL) /*!< Position of CLOCKPOLARITY field.                             */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Pos) /*!< Bit mask of
                                                                            CLOCKPOLARITY field.*/
  #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Min (0x0UL) /*!< Min enumerator value of CLOCKPOLARITY field.               */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Max (0x1UL) /*!< Max enumerator value of CLOCKPOLARITY field.               */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_Low (0x0UL) /*!< Clock polarity is low                                      */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_CLOCKPOLARITY_High (0x1UL) /*!< Clock polarity is High                                    */

/* STOPCOUNTERS @Bit 4 : Stop counters CNT0 and CNT1 on OUTB under-run, or on INB Overflow if OUTMODE2 and INMODE2 */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Pos (4UL) /*!< Position of STOPCOUNTERS field.                               */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Pos) /*!< Bit mask of
                                                                            STOPCOUNTERS field.*/
  #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Min (0x0UL) /*!< Min enumerator value of STOPCOUNTERS field.                 */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Max (0x1UL) /*!< Max enumerator value of STOPCOUNTERS field.                 */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_NoStop (0x0UL) /*!< Counters do not stop on OUTB under-run                   */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_STOPCOUNTERS_Stop (0x1UL) /*!< Counters stop on OUTB under-run                            */

/* INSEL @Bit 8 : Input pin selection */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Pos (8UL) /*!< Position of INSEL field.                                             */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Msk (0x1UL << VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Pos) /*!< Bit mask of INSEL field.   */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Min (0x0UL) /*!< Min enumerator value of INSEL field.                               */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_Max (0x1UL) /*!< Max enumerator value of INSEL field.                               */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_SamePin (0x0UL) /*!< Sample on same OUT pin                                         */
  #define VPRCSR_NORDIC_RTPERIPHCTRL_INSEL_SeparatePin (0x1UL) /*!< Sample on separate pin                                     */


/**
  * @brief CNTMODE0 [VPRCSR_NORDIC_CNTMODE0] CNT0 Mode
  */
  #define VPRCSR_NORDIC_CNTMODE0 (0x000007D0ul)
  #define VPRCSR_NORDIC_CNTMODE0_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE0 register.                              */

/* CNTMODE0 @Bits 0..2 : CNT0 Mode */
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos (0UL)  /*!< Position of CNTMODE0 field.                                          */
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Msk (0x7UL << VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos) /*!< Bit mask of CNTMODE0 field.  */
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Min (0x0UL) /*!< Min enumerator value of CNTMODE0 field.                             */
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Max (0x3UL) /*!< Max enumerator value of CNTMODE0 field.                             */
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_STOP (0x0UL) /*!< CNT0 stops at 0                                                    */
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_WRAP (0x1UL) /*!< When CNT0 reaches 0 it will continue counting from 0xFFFF          */
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_RELOAD (0x2UL) /*!< When CNT0 reaches 0 it will continue counting from the value in
                                                              CNTTOP*/
  #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_TRIGCOMB (0x3UL) /*!< When CNT0 reaches 0 it is reloaded from CNTTOP and stops.
                                                                Counting will restart when a VIO event happens*/


/**
  * @brief CNTMODE1 [VPRCSR_NORDIC_CNTMODE1] CNT1 Mode
  */
  #define VPRCSR_NORDIC_CNTMODE1 (0x000007D1ul)
  #define VPRCSR_NORDIC_CNTMODE1_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE1 register.                              */

/* CNTMODE1 @Bits 0..2 : CNT1 Mode */
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos (0UL)  /*!< Position of CNTMODE1 field.                                          */
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Msk (0x7UL << VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos) /*!< Bit mask of CNTMODE1 field.  */
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Min (0x0UL) /*!< Min enumerator value of CNTMODE1 field.                             */
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Max (0x3UL) /*!< Max enumerator value of CNTMODE1 field.                             */
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_STOP (0x0UL) /*!< CNT1 stops at 0                                                    */
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_WRAP (0x1UL) /*!< When CNT1 reaches 0 it will continue counting from 0xFFFF          */
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_RELOAD (0x2UL) /*!< When CNT1 reches 0 it will continue counting from the value in
                                                              CNTTOP*/
  #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_TRIGCOMB (0x3UL) /*!< In combine mode mode CNT1 acts as an extension of CNT0 (16 most
                                                                significant bits of the 32-bit CNT)*/


/**
  * @brief CNT [VPRCSR_NORDIC_CNT] 32-bit Counter
  */
  #define VPRCSR_NORDIC_CNT (0x000007D2ul)
  #define VPRCSR_NORDIC_CNT_ResetValue (0x00000000UL) /*!< Reset value of CNT register.                                        */

/* CNT0 @Bits 0..15 : 16-bit Counter 0 */
  #define VPRCSR_NORDIC_CNT_CNT0_Pos (0UL)           /*!< Position of CNT0 field.                                              */
  #define VPRCSR_NORDIC_CNT_CNT0_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT0_Pos) /*!< Bit mask of CNT0 field.                     */

/* CNT1 @Bits 16..31 : 16-bit Counter 1 */
  #define VPRCSR_NORDIC_CNT_CNT1_Pos (16UL)          /*!< Position of CNT1 field.                                              */
  #define VPRCSR_NORDIC_CNT_CNT1_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT1_Pos) /*!< Bit mask of CNT1 field.                     */


/**
  * @brief CNTTOP [VPRCSR_NORDIC_CNTTOP] Counter Top
  */
  #define VPRCSR_NORDIC_CNTTOP (0x000007D3ul)
  #define VPRCSR_NORDIC_CNTTOP_ResetValue (0x00000000UL) /*!< Reset value of CNTTOP register.                                  */

/* CNT0RELOAD @Bits 0..15 : Reload value for CNT0 */
  #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos (0UL)  /*!< Position of CNT0RELOAD field.                                        */
  #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos) /*!< Bit mask of CNT0RELOAD
                                                                            field.*/

/* CNT1RELOAD @Bits 16..31 : Reload value for CNT1 */
  #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos (16UL) /*!< Position of CNT1RELOAD field.                                        */
  #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos) /*!< Bit mask of CNT1RELOAD
                                                                            field.*/


/**
  * @brief CNTADD [VPRCSR_NORDIC_CNTADD] CNT Add
  */
  #define VPRCSR_NORDIC_CNTADD (0x000007D4ul)
  #define VPRCSR_NORDIC_CNTADD_ResetValue (0x00000000UL) /*!< Reset value of CNTADD register.                                  */

/* VAL @Bits 0..31 : Value added to CNT */
  #define VPRCSR_NORDIC_CNTADD_VAL_Pos (0UL)         /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_CNTADD_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD_VAL_Pos) /*!< Bit mask of VAL field.              */


/**
  * @brief CNT0 [VPRCSR_NORDIC_CNT0] 16 bit Counter 0
  */
  #define VPRCSR_NORDIC_CNT0 (0x000007D5ul)
  #define VPRCSR_NORDIC_CNT0_ResetValue (0x00000000UL) /*!< Reset value of CNT0 register.                                      */

/* VAL @Bits 0..15 : CNT0 value */
  #define VPRCSR_NORDIC_CNT0_VAL_Pos (0UL)           /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_CNT0_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT0_VAL_Pos) /*!< Bit mask of VAL field.                      */


/**
  * @brief CNTADD0 [VPRCSR_NORDIC_CNTADD0] CNT0 Add
  */
  #define VPRCSR_NORDIC_CNTADD0 (0x000007D6ul)
  #define VPRCSR_NORDIC_CNTADD0_ResetValue (0x00000000UL) /*!< Reset value of CNTADD0 register.                                */

/* VAL @Bits 0..31 : Value added to CNT0 */
  #define VPRCSR_NORDIC_CNTADD0_VAL_Pos (0UL)        /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_CNTADD0_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD0_VAL_Pos) /*!< Bit mask of VAL field.            */


/**
  * @brief CNT1 [VPRCSR_NORDIC_CNT1] 16-bit Counter 1
  */
  #define VPRCSR_NORDIC_CNT1 (0x000007D7ul)
  #define VPRCSR_NORDIC_CNT1_ResetValue (0x00000000UL) /*!< Reset value of CNT1 register.                                      */

/* VAL @Bits 0..15 : CNT1 value */
  #define VPRCSR_NORDIC_CNT1_VAL_Pos (0UL)           /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_CNT1_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT1_VAL_Pos) /*!< Bit mask of VAL field.                      */


/**
  * @brief CNTADD1 [VPRCSR_NORDIC_CNTADD1] CNT1 Add
  */
  #define VPRCSR_NORDIC_CNTADD1 (0x000007D8ul)
  #define VPRCSR_NORDIC_CNTADD1_ResetValue (0x00000000UL) /*!< Reset value of CNTADD1 register.                                */

/* VAL @Bits 0..31 : Value added to CNT1 */
  #define VPRCSR_NORDIC_CNTADD1_VAL_Pos (0UL)        /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_CNTADD1_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD1_VAL_Pos) /*!< Bit mask of VAL field.            */


/**
  * @brief WAIT0 [VPRCSR_NORDIC_WAIT0] Wait 0
  */
  #define VPRCSR_NORDIC_WAIT0 (0x000007DAul)
  #define VPRCSR_NORDIC_WAIT0_ResetValue (0x00000000UL) /*!< Reset value of WAIT0 register.                                    */

/* DATA @Bits 0..15 : Value to write to CNT0 */
  #define VPRCSR_NORDIC_WAIT0_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define VPRCSR_NORDIC_WAIT0_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT0_DATA_Pos) /*!< Bit mask of DATA field.                 */

/* WRITEDATA @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos (16UL)   /*!< Position of WRITEDATA field.                                         */
  #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field.     */
  #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Min (0x0UL)  /*!< Min enumerator value of WRITEDATA field.                             */
  #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Max (0x1UL)  /*!< Max enumerator value of WRITEDATA field.                             */
  #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT0 reaches 0                                            */
  #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT0 and then wait until CNT0 reaches 0               */


/**
  * @brief WAIT1 [VPRCSR_NORDIC_WAIT1] Wait 1
  */
  #define VPRCSR_NORDIC_WAIT1 (0x000007DBul)
  #define VPRCSR_NORDIC_WAIT1_ResetValue (0x00000000UL) /*!< Reset value of WAIT1 register.                                    */

/* DATA @Bits 0..15 : Value to write to CNT1 */
  #define VPRCSR_NORDIC_WAIT1_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
  #define VPRCSR_NORDIC_WAIT1_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT1_DATA_Pos) /*!< Bit mask of DATA field.                 */

/* WRITEDATA @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos (16UL)   /*!< Position of WRITEDATA field.                                         */
  #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field.     */
  #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Min (0x0UL)  /*!< Min enumerator value of WRITEDATA field.                             */
  #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Max (0x1UL)  /*!< Max enumerator value of WRITEDATA field.                             */
  #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT1 reaches 0                                            */
  #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT1 and then wait until CNT1 reaches 0               */


/**
  * @brief WAIT [VPRCSR_NORDIC_WAIT] Wait
  */
  #define VPRCSR_NORDIC_WAIT (0x000007DCul)
  #define VPRCSR_NORDIC_WAIT_ResetValue (0x00000000UL) /*!< Reset value of WAIT register.                                      */

/* VAL @Bits 0..31 : (unspecified) */
  #define VPRCSR_NORDIC_WAIT_VAL_Pos (0UL)           /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_WAIT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_WAIT_VAL_Pos) /*!< Bit mask of VAL field.                  */


/**
  * @brief TASKS [VPRCSR_NORDIC_TASKS] DPPI Tasks
  */
  #define VPRCSR_NORDIC_TASKS (0x000007E0ul)
  #define VPRCSR_NORDIC_TASKS_ResetValue (0x00000000UL) /*!< Reset value of TASKS register.                                    */

/* TASKS0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS0_Pos (0UL)       /*!< Position of TASKS0 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS0_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS0_Pos) /*!< Bit mask of TASKS0 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS0_Min (0x0UL)     /*!< Min enumerator value of TASKS0 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS0_Max (0x1UL)     /*!< Max enumerator value of TASKS0 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS0_Disabled (0x0UL) /*!< TASKS[0] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS0_Enabled (0x1UL) /*!< TASKS[0] enabled                                                     */

/* TASKS1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS1_Pos (1UL)       /*!< Position of TASKS1 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS1_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS1_Pos) /*!< Bit mask of TASKS1 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS1_Min (0x0UL)     /*!< Min enumerator value of TASKS1 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS1_Max (0x1UL)     /*!< Max enumerator value of TASKS1 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS1_Disabled (0x0UL) /*!< TASKS[1] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS1_Enabled (0x1UL) /*!< TASKS[1] enabled                                                     */

/* TASKS2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS2_Pos (2UL)       /*!< Position of TASKS2 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS2_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS2_Pos) /*!< Bit mask of TASKS2 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS2_Min (0x0UL)     /*!< Min enumerator value of TASKS2 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS2_Max (0x1UL)     /*!< Max enumerator value of TASKS2 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS2_Disabled (0x0UL) /*!< TASKS[2] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS2_Enabled (0x1UL) /*!< TASKS[2] enabled                                                     */

/* TASKS3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS3_Pos (3UL)       /*!< Position of TASKS3 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS3_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS3_Pos) /*!< Bit mask of TASKS3 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS3_Min (0x0UL)     /*!< Min enumerator value of TASKS3 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS3_Max (0x1UL)     /*!< Max enumerator value of TASKS3 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS3_Disabled (0x0UL) /*!< TASKS[3] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS3_Enabled (0x1UL) /*!< TASKS[3] enabled                                                     */

/* TASKS4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS4_Pos (4UL)       /*!< Position of TASKS4 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS4_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS4_Pos) /*!< Bit mask of TASKS4 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS4_Min (0x0UL)     /*!< Min enumerator value of TASKS4 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS4_Max (0x1UL)     /*!< Max enumerator value of TASKS4 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS4_Disabled (0x0UL) /*!< TASKS[4] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS4_Enabled (0x1UL) /*!< TASKS[4] enabled                                                     */

/* TASKS5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS5_Pos (5UL)       /*!< Position of TASKS5 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS5_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS5_Pos) /*!< Bit mask of TASKS5 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS5_Min (0x0UL)     /*!< Min enumerator value of TASKS5 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS5_Max (0x1UL)     /*!< Max enumerator value of TASKS5 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS5_Disabled (0x0UL) /*!< TASKS[5] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS5_Enabled (0x1UL) /*!< TASKS[5] enabled                                                     */

/* TASKS6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS6_Pos (6UL)       /*!< Position of TASKS6 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS6_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS6_Pos) /*!< Bit mask of TASKS6 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS6_Min (0x0UL)     /*!< Min enumerator value of TASKS6 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS6_Max (0x1UL)     /*!< Max enumerator value of TASKS6 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS6_Disabled (0x0UL) /*!< TASKS[6] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS6_Enabled (0x1UL) /*!< TASKS[6] enabled                                                     */

/* TASKS7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS7_Pos (7UL)       /*!< Position of TASKS7 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS7_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS7_Pos) /*!< Bit mask of TASKS7 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS7_Min (0x0UL)     /*!< Min enumerator value of TASKS7 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS7_Max (0x1UL)     /*!< Max enumerator value of TASKS7 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS7_Disabled (0x0UL) /*!< TASKS[7] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS7_Enabled (0x1UL) /*!< TASKS[7] enabled                                                     */

/* TASKS8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS8_Pos (8UL)       /*!< Position of TASKS8 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS8_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS8_Pos) /*!< Bit mask of TASKS8 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS8_Min (0x0UL)     /*!< Min enumerator value of TASKS8 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS8_Max (0x1UL)     /*!< Max enumerator value of TASKS8 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS8_Disabled (0x0UL) /*!< TASKS[8] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS8_Enabled (0x1UL) /*!< TASKS[8] enabled                                                     */

/* TASKS9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS9_Pos (9UL)       /*!< Position of TASKS9 field.                                            */
  #define VPRCSR_NORDIC_TASKS_TASKS9_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS9_Pos) /*!< Bit mask of TASKS9 field.              */
  #define VPRCSR_NORDIC_TASKS_TASKS9_Min (0x0UL)     /*!< Min enumerator value of TASKS9 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS9_Max (0x1UL)     /*!< Max enumerator value of TASKS9 field.                                */
  #define VPRCSR_NORDIC_TASKS_TASKS9_Disabled (0x0UL) /*!< TASKS[9] diabled                                                    */
  #define VPRCSR_NORDIC_TASKS_TASKS9_Enabled (0x1UL) /*!< TASKS[9] enabled                                                     */

/* TASKS10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS10_Pos (10UL)     /*!< Position of TASKS10 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS10_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS10_Pos) /*!< Bit mask of TASKS10 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS10_Min (0x0UL)    /*!< Min enumerator value of TASKS10 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS10_Max (0x1UL)    /*!< Max enumerator value of TASKS10 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS10_Disabled (0x0UL) /*!< TASKS[10] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS10_Enabled (0x1UL) /*!< TASKS[10] enabled                                                   */

/* TASKS11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS11_Pos (11UL)     /*!< Position of TASKS11 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS11_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS11_Pos) /*!< Bit mask of TASKS11 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS11_Min (0x0UL)    /*!< Min enumerator value of TASKS11 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS11_Max (0x1UL)    /*!< Max enumerator value of TASKS11 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS11_Disabled (0x0UL) /*!< TASKS[11] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS11_Enabled (0x1UL) /*!< TASKS[11] enabled                                                   */

/* TASKS12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS12_Pos (12UL)     /*!< Position of TASKS12 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS12_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS12_Pos) /*!< Bit mask of TASKS12 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS12_Min (0x0UL)    /*!< Min enumerator value of TASKS12 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS12_Max (0x1UL)    /*!< Max enumerator value of TASKS12 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS12_Disabled (0x0UL) /*!< TASKS[12] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS12_Enabled (0x1UL) /*!< TASKS[12] enabled                                                   */

/* TASKS13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS13_Pos (13UL)     /*!< Position of TASKS13 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS13_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS13_Pos) /*!< Bit mask of TASKS13 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS13_Min (0x0UL)    /*!< Min enumerator value of TASKS13 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS13_Max (0x1UL)    /*!< Max enumerator value of TASKS13 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS13_Disabled (0x0UL) /*!< TASKS[13] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS13_Enabled (0x1UL) /*!< TASKS[13] enabled                                                   */

/* TASKS14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS14_Pos (14UL)     /*!< Position of TASKS14 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS14_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS14_Pos) /*!< Bit mask of TASKS14 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS14_Min (0x0UL)    /*!< Min enumerator value of TASKS14 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS14_Max (0x1UL)    /*!< Max enumerator value of TASKS14 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS14_Disabled (0x0UL) /*!< TASKS[14] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS14_Enabled (0x1UL) /*!< TASKS[14] enabled                                                   */

/* TASKS15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS15_Pos (15UL)     /*!< Position of TASKS15 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS15_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS15_Pos) /*!< Bit mask of TASKS15 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS15_Min (0x0UL)    /*!< Min enumerator value of TASKS15 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS15_Max (0x1UL)    /*!< Max enumerator value of TASKS15 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS15_Disabled (0x0UL) /*!< TASKS[15] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS15_Enabled (0x1UL) /*!< TASKS[15] enabled                                                   */

/* TASKS16 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS16_Pos (16UL)     /*!< Position of TASKS16 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS16_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS16_Pos) /*!< Bit mask of TASKS16 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS16_Min (0x0UL)    /*!< Min enumerator value of TASKS16 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS16_Max (0x1UL)    /*!< Max enumerator value of TASKS16 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS16_Disabled (0x0UL) /*!< TASKS[16] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS16_Enabled (0x1UL) /*!< TASKS[16] enabled                                                   */

/* TASKS17 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS17_Pos (17UL)     /*!< Position of TASKS17 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS17_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS17_Pos) /*!< Bit mask of TASKS17 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS17_Min (0x0UL)    /*!< Min enumerator value of TASKS17 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS17_Max (0x1UL)    /*!< Max enumerator value of TASKS17 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS17_Disabled (0x0UL) /*!< TASKS[17] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS17_Enabled (0x1UL) /*!< TASKS[17] enabled                                                   */

/* TASKS18 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS18_Pos (18UL)     /*!< Position of TASKS18 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS18_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS18_Pos) /*!< Bit mask of TASKS18 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS18_Min (0x0UL)    /*!< Min enumerator value of TASKS18 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS18_Max (0x1UL)    /*!< Max enumerator value of TASKS18 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS18_Disabled (0x0UL) /*!< TASKS[18] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS18_Enabled (0x1UL) /*!< TASKS[18] enabled                                                   */

/* TASKS19 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS19_Pos (19UL)     /*!< Position of TASKS19 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS19_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS19_Pos) /*!< Bit mask of TASKS19 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS19_Min (0x0UL)    /*!< Min enumerator value of TASKS19 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS19_Max (0x1UL)    /*!< Max enumerator value of TASKS19 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS19_Disabled (0x0UL) /*!< TASKS[19] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS19_Enabled (0x1UL) /*!< TASKS[19] enabled                                                   */

/* TASKS20 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS20_Pos (20UL)     /*!< Position of TASKS20 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS20_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS20_Pos) /*!< Bit mask of TASKS20 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS20_Min (0x0UL)    /*!< Min enumerator value of TASKS20 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS20_Max (0x1UL)    /*!< Max enumerator value of TASKS20 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS20_Disabled (0x0UL) /*!< TASKS[20] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS20_Enabled (0x1UL) /*!< TASKS[20] enabled                                                   */

/* TASKS21 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS21_Pos (21UL)     /*!< Position of TASKS21 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS21_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS21_Pos) /*!< Bit mask of TASKS21 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS21_Min (0x0UL)    /*!< Min enumerator value of TASKS21 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS21_Max (0x1UL)    /*!< Max enumerator value of TASKS21 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS21_Disabled (0x0UL) /*!< TASKS[21] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS21_Enabled (0x1UL) /*!< TASKS[21] enabled                                                   */

/* TASKS22 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS22_Pos (22UL)     /*!< Position of TASKS22 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS22_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS22_Pos) /*!< Bit mask of TASKS22 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS22_Min (0x0UL)    /*!< Min enumerator value of TASKS22 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS22_Max (0x1UL)    /*!< Max enumerator value of TASKS22 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS22_Disabled (0x0UL) /*!< TASKS[22] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS22_Enabled (0x1UL) /*!< TASKS[22] enabled                                                   */

/* TASKS23 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS23_Pos (23UL)     /*!< Position of TASKS23 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS23_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS23_Pos) /*!< Bit mask of TASKS23 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS23_Min (0x0UL)    /*!< Min enumerator value of TASKS23 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS23_Max (0x1UL)    /*!< Max enumerator value of TASKS23 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS23_Disabled (0x0UL) /*!< TASKS[23] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS23_Enabled (0x1UL) /*!< TASKS[23] enabled                                                   */

/* TASKS24 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS24_Pos (24UL)     /*!< Position of TASKS24 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS24_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS24_Pos) /*!< Bit mask of TASKS24 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS24_Min (0x0UL)    /*!< Min enumerator value of TASKS24 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS24_Max (0x1UL)    /*!< Max enumerator value of TASKS24 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS24_Disabled (0x0UL) /*!< TASKS[24] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS24_Enabled (0x1UL) /*!< TASKS[24] enabled                                                   */

/* TASKS25 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS25_Pos (25UL)     /*!< Position of TASKS25 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS25_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS25_Pos) /*!< Bit mask of TASKS25 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS25_Min (0x0UL)    /*!< Min enumerator value of TASKS25 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS25_Max (0x1UL)    /*!< Max enumerator value of TASKS25 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS25_Disabled (0x0UL) /*!< TASKS[25] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS25_Enabled (0x1UL) /*!< TASKS[25] enabled                                                   */

/* TASKS26 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS26_Pos (26UL)     /*!< Position of TASKS26 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS26_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS26_Pos) /*!< Bit mask of TASKS26 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS26_Min (0x0UL)    /*!< Min enumerator value of TASKS26 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS26_Max (0x1UL)    /*!< Max enumerator value of TASKS26 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS26_Disabled (0x0UL) /*!< TASKS[26] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS26_Enabled (0x1UL) /*!< TASKS[26] enabled                                                   */

/* TASKS27 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS27_Pos (27UL)     /*!< Position of TASKS27 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS27_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS27_Pos) /*!< Bit mask of TASKS27 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS27_Min (0x0UL)    /*!< Min enumerator value of TASKS27 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS27_Max (0x1UL)    /*!< Max enumerator value of TASKS27 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS27_Disabled (0x0UL) /*!< TASKS[27] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS27_Enabled (0x1UL) /*!< TASKS[27] enabled                                                   */

/* TASKS28 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS28_Pos (28UL)     /*!< Position of TASKS28 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS28_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS28_Pos) /*!< Bit mask of TASKS28 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS28_Min (0x0UL)    /*!< Min enumerator value of TASKS28 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS28_Max (0x1UL)    /*!< Max enumerator value of TASKS28 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS28_Disabled (0x0UL) /*!< TASKS[28] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS28_Enabled (0x1UL) /*!< TASKS[28] enabled                                                   */

/* TASKS29 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS29_Pos (29UL)     /*!< Position of TASKS29 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS29_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS29_Pos) /*!< Bit mask of TASKS29 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS29_Min (0x0UL)    /*!< Min enumerator value of TASKS29 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS29_Max (0x1UL)    /*!< Max enumerator value of TASKS29 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS29_Disabled (0x0UL) /*!< TASKS[29] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS29_Enabled (0x1UL) /*!< TASKS[29] enabled                                                   */

/* TASKS30 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS30_Pos (30UL)     /*!< Position of TASKS30 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS30_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS30_Pos) /*!< Bit mask of TASKS30 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS30_Min (0x0UL)    /*!< Min enumerator value of TASKS30 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS30_Max (0x1UL)    /*!< Max enumerator value of TASKS30 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS30_Disabled (0x0UL) /*!< TASKS[30] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS30_Enabled (0x1UL) /*!< TASKS[30] enabled                                                   */

/* TASKS31 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_TASKS_TASKS31_Pos (31UL)     /*!< Position of TASKS31 field.                                           */
  #define VPRCSR_NORDIC_TASKS_TASKS31_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS31_Pos) /*!< Bit mask of TASKS31 field.           */
  #define VPRCSR_NORDIC_TASKS_TASKS31_Min (0x0UL)    /*!< Min enumerator value of TASKS31 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS31_Max (0x1UL)    /*!< Max enumerator value of TASKS31 field.                               */
  #define VPRCSR_NORDIC_TASKS_TASKS31_Disabled (0x0UL) /*!< TASKS[31] diabled                                                  */
  #define VPRCSR_NORDIC_TASKS_TASKS31_Enabled (0x1UL) /*!< TASKS[31] enabled                                                   */


/**
  * @brief SUBSCRIBE [VPRCSR_NORDIC_SUBSCRIBE] Enable Task Subscription
  */
  #define VPRCSR_NORDIC_SUBSCRIBE (0x000007E1ul)
  #define VPRCSR_NORDIC_SUBSCRIBE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE register.                            */

/* SUBSCRIBE0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos (0UL) /*!< Position of SUBSCRIBE0 field.                                      */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos) /*!< Bit mask of SUBSCRIBE0
                                                                            field.*/
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE0 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE0 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Disabled (0x0UL) /*!< Subscribe disabled for TASK[0]                              */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Enabled (0x1UL) /*!< Subscribe enabled for TASK[0]                                */

/* SUBSCRIBE1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos (1UL) /*!< Position of SUBSCRIBE1 field.                                      */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos) /*!< Bit mask of SUBSCRIBE1
                                                                            field.*/
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE1 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE1 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Disabled (0x0UL) /*!< Subscribe disabled for TASK[1]                              */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Enabled (0x1UL) /*!< Subscribe enabled for TASK[1]                                */

/* SUBSCRIBE2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos (2UL) /*!< Position of SUBSCRIBE2 field.                                      */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos) /*!< Bit mask of SUBSCRIBE2
                                                                            field.*/
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE2 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE2 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Disabled (0x0UL) /*!< Subscribe disabled for TASK[2]                              */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Enabled (0x1UL) /*!< Subscribe enabled for TASK[2]                                */

/* SUBSCRIBE3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos (3UL) /*!< Position of SUBSCRIBE3 field.                                      */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos) /*!< Bit mask of SUBSCRIBE3
                                                                            field.*/
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE3 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE3 field.                        */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Disabled (0x0UL) /*!< Subscribe disabled for TASK[3]                              */
  #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Enabled (0x1UL) /*!< Subscribe enabled for TASK[3]                                */


/**
  * @brief EVENTS [VPRCSR_NORDIC_EVENTS] DPPI Events
  */
  #define VPRCSR_NORDIC_EVENTS (0x000007E2ul)
  #define VPRCSR_NORDIC_EVENTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS register.                                  */

/* EVENTS0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS0_Pos (0UL)     /*!< Position of EVENTS0 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS0_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS0_Pos) /*!< Bit mask of EVENTS0 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS0_Min (0x0UL)   /*!< Min enumerator value of EVENTS0 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS0_Max (0x1UL)   /*!< Max enumerator value of EVENTS0 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS0_Disabled (0x0UL) /*!< EVENTS[0] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS0_Enabled (0x1UL) /*!< EVENTS[0] enabled                                                  */

/* EVENTS1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS1_Pos (1UL)     /*!< Position of EVENTS1 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS1_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS1_Pos) /*!< Bit mask of EVENTS1 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS1_Min (0x0UL)   /*!< Min enumerator value of EVENTS1 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS1_Max (0x1UL)   /*!< Max enumerator value of EVENTS1 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS1_Disabled (0x0UL) /*!< EVENTS[1] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS1_Enabled (0x1UL) /*!< EVENTS[1] enabled                                                  */

/* EVENTS2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS2_Pos (2UL)     /*!< Position of EVENTS2 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS2_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS2_Pos) /*!< Bit mask of EVENTS2 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS2_Min (0x0UL)   /*!< Min enumerator value of EVENTS2 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS2_Max (0x1UL)   /*!< Max enumerator value of EVENTS2 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS2_Disabled (0x0UL) /*!< EVENTS[2] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS2_Enabled (0x1UL) /*!< EVENTS[2] enabled                                                  */

/* EVENTS3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS3_Pos (3UL)     /*!< Position of EVENTS3 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS3_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS3_Pos) /*!< Bit mask of EVENTS3 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS3_Min (0x0UL)   /*!< Min enumerator value of EVENTS3 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS3_Max (0x1UL)   /*!< Max enumerator value of EVENTS3 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS3_Disabled (0x0UL) /*!< EVENTS[3] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS3_Enabled (0x1UL) /*!< EVENTS[3] enabled                                                  */

/* EVENTS4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS4_Pos (4UL)     /*!< Position of EVENTS4 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS4_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS4_Pos) /*!< Bit mask of EVENTS4 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS4_Min (0x0UL)   /*!< Min enumerator value of EVENTS4 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS4_Max (0x1UL)   /*!< Max enumerator value of EVENTS4 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS4_Disabled (0x0UL) /*!< EVENTS[4] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS4_Enabled (0x1UL) /*!< EVENTS[4] enabled                                                  */

/* EVENTS5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS5_Pos (5UL)     /*!< Position of EVENTS5 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS5_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS5_Pos) /*!< Bit mask of EVENTS5 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS5_Min (0x0UL)   /*!< Min enumerator value of EVENTS5 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS5_Max (0x1UL)   /*!< Max enumerator value of EVENTS5 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS5_Disabled (0x0UL) /*!< EVENTS[5] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS5_Enabled (0x1UL) /*!< EVENTS[5] enabled                                                  */

/* EVENTS6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS6_Pos (6UL)     /*!< Position of EVENTS6 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS6_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS6_Pos) /*!< Bit mask of EVENTS6 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS6_Min (0x0UL)   /*!< Min enumerator value of EVENTS6 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS6_Max (0x1UL)   /*!< Max enumerator value of EVENTS6 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS6_Disabled (0x0UL) /*!< EVENTS[6] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS6_Enabled (0x1UL) /*!< EVENTS[6] enabled                                                  */

/* EVENTS7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS7_Pos (7UL)     /*!< Position of EVENTS7 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS7_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS7_Pos) /*!< Bit mask of EVENTS7 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS7_Min (0x0UL)   /*!< Min enumerator value of EVENTS7 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS7_Max (0x1UL)   /*!< Max enumerator value of EVENTS7 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS7_Disabled (0x0UL) /*!< EVENTS[7] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS7_Enabled (0x1UL) /*!< EVENTS[7] enabled                                                  */

/* EVENTS8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS8_Pos (8UL)     /*!< Position of EVENTS8 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS8_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS8_Pos) /*!< Bit mask of EVENTS8 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS8_Min (0x0UL)   /*!< Min enumerator value of EVENTS8 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS8_Max (0x1UL)   /*!< Max enumerator value of EVENTS8 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS8_Disabled (0x0UL) /*!< EVENTS[8] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS8_Enabled (0x1UL) /*!< EVENTS[8] enabled                                                  */

/* EVENTS9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS9_Pos (9UL)     /*!< Position of EVENTS9 field.                                           */
  #define VPRCSR_NORDIC_EVENTS_EVENTS9_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS9_Pos) /*!< Bit mask of EVENTS9 field.         */
  #define VPRCSR_NORDIC_EVENTS_EVENTS9_Min (0x0UL)   /*!< Min enumerator value of EVENTS9 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS9_Max (0x1UL)   /*!< Max enumerator value of EVENTS9 field.                               */
  #define VPRCSR_NORDIC_EVENTS_EVENTS9_Disabled (0x0UL) /*!< EVENTS[9] disabled                                                */
  #define VPRCSR_NORDIC_EVENTS_EVENTS9_Enabled (0x1UL) /*!< EVENTS[9] enabled                                                  */

/* EVENTS10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS10_Pos (10UL)   /*!< Position of EVENTS10 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS10_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS10_Pos) /*!< Bit mask of EVENTS10 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS10_Min (0x0UL)  /*!< Min enumerator value of EVENTS10 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS10_Max (0x1UL)  /*!< Max enumerator value of EVENTS10 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS10_Disabled (0x0UL) /*!< EVENTS[10] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS10_Enabled (0x1UL) /*!< EVENTS[10] enabled                                                */

/* EVENTS11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS11_Pos (11UL)   /*!< Position of EVENTS11 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS11_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS11_Pos) /*!< Bit mask of EVENTS11 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS11_Min (0x0UL)  /*!< Min enumerator value of EVENTS11 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS11_Max (0x1UL)  /*!< Max enumerator value of EVENTS11 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS11_Disabled (0x0UL) /*!< EVENTS[11] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS11_Enabled (0x1UL) /*!< EVENTS[11] enabled                                                */

/* EVENTS12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS12_Pos (12UL)   /*!< Position of EVENTS12 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS12_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS12_Pos) /*!< Bit mask of EVENTS12 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS12_Min (0x0UL)  /*!< Min enumerator value of EVENTS12 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS12_Max (0x1UL)  /*!< Max enumerator value of EVENTS12 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS12_Disabled (0x0UL) /*!< EVENTS[12] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS12_Enabled (0x1UL) /*!< EVENTS[12] enabled                                                */

/* EVENTS13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS13_Pos (13UL)   /*!< Position of EVENTS13 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS13_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS13_Pos) /*!< Bit mask of EVENTS13 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS13_Min (0x0UL)  /*!< Min enumerator value of EVENTS13 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS13_Max (0x1UL)  /*!< Max enumerator value of EVENTS13 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS13_Disabled (0x0UL) /*!< EVENTS[13] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS13_Enabled (0x1UL) /*!< EVENTS[13] enabled                                                */

/* EVENTS14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS14_Pos (14UL)   /*!< Position of EVENTS14 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS14_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS14_Pos) /*!< Bit mask of EVENTS14 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS14_Min (0x0UL)  /*!< Min enumerator value of EVENTS14 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS14_Max (0x1UL)  /*!< Max enumerator value of EVENTS14 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS14_Disabled (0x0UL) /*!< EVENTS[14] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS14_Enabled (0x1UL) /*!< EVENTS[14] enabled                                                */

/* EVENTS15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS15_Pos (15UL)   /*!< Position of EVENTS15 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS15_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS15_Pos) /*!< Bit mask of EVENTS15 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS15_Min (0x0UL)  /*!< Min enumerator value of EVENTS15 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS15_Max (0x1UL)  /*!< Max enumerator value of EVENTS15 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS15_Disabled (0x0UL) /*!< EVENTS[15] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS15_Enabled (0x1UL) /*!< EVENTS[15] enabled                                                */

/* EVENTS16 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS16_Pos (16UL)   /*!< Position of EVENTS16 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS16_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS16_Pos) /*!< Bit mask of EVENTS16 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS16_Min (0x0UL)  /*!< Min enumerator value of EVENTS16 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS16_Max (0x1UL)  /*!< Max enumerator value of EVENTS16 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS16_Disabled (0x0UL) /*!< EVENTS[16] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS16_Enabled (0x1UL) /*!< EVENTS[16] enabled                                                */

/* EVENTS17 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS17_Pos (17UL)   /*!< Position of EVENTS17 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS17_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS17_Pos) /*!< Bit mask of EVENTS17 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS17_Min (0x0UL)  /*!< Min enumerator value of EVENTS17 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS17_Max (0x1UL)  /*!< Max enumerator value of EVENTS17 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS17_Disabled (0x0UL) /*!< EVENTS[17] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS17_Enabled (0x1UL) /*!< EVENTS[17] enabled                                                */

/* EVENTS18 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS18_Pos (18UL)   /*!< Position of EVENTS18 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS18_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS18_Pos) /*!< Bit mask of EVENTS18 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS18_Min (0x0UL)  /*!< Min enumerator value of EVENTS18 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS18_Max (0x1UL)  /*!< Max enumerator value of EVENTS18 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS18_Disabled (0x0UL) /*!< EVENTS[18] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS18_Enabled (0x1UL) /*!< EVENTS[18] enabled                                                */

/* EVENTS19 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS19_Pos (19UL)   /*!< Position of EVENTS19 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS19_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS19_Pos) /*!< Bit mask of EVENTS19 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS19_Min (0x0UL)  /*!< Min enumerator value of EVENTS19 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS19_Max (0x1UL)  /*!< Max enumerator value of EVENTS19 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS19_Disabled (0x0UL) /*!< EVENTS[19] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS19_Enabled (0x1UL) /*!< EVENTS[19] enabled                                                */

/* EVENTS20 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS20_Pos (20UL)   /*!< Position of EVENTS20 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS20_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS20_Pos) /*!< Bit mask of EVENTS20 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS20_Min (0x0UL)  /*!< Min enumerator value of EVENTS20 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS20_Max (0x1UL)  /*!< Max enumerator value of EVENTS20 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS20_Disabled (0x0UL) /*!< EVENTS[20] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS20_Enabled (0x1UL) /*!< EVENTS[20] enabled                                                */

/* EVENTS21 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS21_Pos (21UL)   /*!< Position of EVENTS21 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS21_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS21_Pos) /*!< Bit mask of EVENTS21 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS21_Min (0x0UL)  /*!< Min enumerator value of EVENTS21 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS21_Max (0x1UL)  /*!< Max enumerator value of EVENTS21 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS21_Disabled (0x0UL) /*!< EVENTS[21] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS21_Enabled (0x1UL) /*!< EVENTS[21] enabled                                                */

/* EVENTS22 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS22_Pos (22UL)   /*!< Position of EVENTS22 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS22_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS22_Pos) /*!< Bit mask of EVENTS22 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS22_Min (0x0UL)  /*!< Min enumerator value of EVENTS22 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS22_Max (0x1UL)  /*!< Max enumerator value of EVENTS22 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS22_Disabled (0x0UL) /*!< EVENTS[22] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS22_Enabled (0x1UL) /*!< EVENTS[22] enabled                                                */

/* EVENTS23 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS23_Pos (23UL)   /*!< Position of EVENTS23 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS23_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS23_Pos) /*!< Bit mask of EVENTS23 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS23_Min (0x0UL)  /*!< Min enumerator value of EVENTS23 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS23_Max (0x1UL)  /*!< Max enumerator value of EVENTS23 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS23_Disabled (0x0UL) /*!< EVENTS[23] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS23_Enabled (0x1UL) /*!< EVENTS[23] enabled                                                */

/* EVENTS24 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS24_Pos (24UL)   /*!< Position of EVENTS24 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS24_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS24_Pos) /*!< Bit mask of EVENTS24 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS24_Min (0x0UL)  /*!< Min enumerator value of EVENTS24 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS24_Max (0x1UL)  /*!< Max enumerator value of EVENTS24 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS24_Disabled (0x0UL) /*!< EVENTS[24] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS24_Enabled (0x1UL) /*!< EVENTS[24] enabled                                                */

/* EVENTS25 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS25_Pos (25UL)   /*!< Position of EVENTS25 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS25_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS25_Pos) /*!< Bit mask of EVENTS25 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS25_Min (0x0UL)  /*!< Min enumerator value of EVENTS25 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS25_Max (0x1UL)  /*!< Max enumerator value of EVENTS25 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS25_Disabled (0x0UL) /*!< EVENTS[25] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS25_Enabled (0x1UL) /*!< EVENTS[25] enabled                                                */

/* EVENTS26 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS26_Pos (26UL)   /*!< Position of EVENTS26 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS26_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS26_Pos) /*!< Bit mask of EVENTS26 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS26_Min (0x0UL)  /*!< Min enumerator value of EVENTS26 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS26_Max (0x1UL)  /*!< Max enumerator value of EVENTS26 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS26_Disabled (0x0UL) /*!< EVENTS[26] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS26_Enabled (0x1UL) /*!< EVENTS[26] enabled                                                */

/* EVENTS27 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS27_Pos (27UL)   /*!< Position of EVENTS27 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS27_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS27_Pos) /*!< Bit mask of EVENTS27 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS27_Min (0x0UL)  /*!< Min enumerator value of EVENTS27 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS27_Max (0x1UL)  /*!< Max enumerator value of EVENTS27 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS27_Disabled (0x0UL) /*!< EVENTS[27] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS27_Enabled (0x1UL) /*!< EVENTS[27] enabled                                                */

/* EVENTS28 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS28_Pos (28UL)   /*!< Position of EVENTS28 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS28_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS28_Pos) /*!< Bit mask of EVENTS28 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS28_Min (0x0UL)  /*!< Min enumerator value of EVENTS28 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS28_Max (0x1UL)  /*!< Max enumerator value of EVENTS28 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS28_Disabled (0x0UL) /*!< EVENTS[28] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS28_Enabled (0x1UL) /*!< EVENTS[28] enabled                                                */

/* EVENTS29 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS29_Pos (29UL)   /*!< Position of EVENTS29 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS29_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS29_Pos) /*!< Bit mask of EVENTS29 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS29_Min (0x0UL)  /*!< Min enumerator value of EVENTS29 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS29_Max (0x1UL)  /*!< Max enumerator value of EVENTS29 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS29_Disabled (0x0UL) /*!< EVENTS[29] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS29_Enabled (0x1UL) /*!< EVENTS[29] enabled                                                */

/* EVENTS30 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS30_Pos (30UL)   /*!< Position of EVENTS30 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS30_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS30_Pos) /*!< Bit mask of EVENTS30 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS30_Min (0x0UL)  /*!< Min enumerator value of EVENTS30 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS30_Max (0x1UL)  /*!< Max enumerator value of EVENTS30 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS30_Disabled (0x0UL) /*!< EVENTS[30] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS30_Enabled (0x1UL) /*!< EVENTS[30] enabled                                                */

/* EVENTS31 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTS_EVENTS31_Pos (31UL)   /*!< Position of EVENTS31 field.                                          */
  #define VPRCSR_NORDIC_EVENTS_EVENTS31_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS31_Pos) /*!< Bit mask of EVENTS31 field.      */
  #define VPRCSR_NORDIC_EVENTS_EVENTS31_Min (0x0UL)  /*!< Min enumerator value of EVENTS31 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS31_Max (0x1UL)  /*!< Max enumerator value of EVENTS31 field.                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS31_Disabled (0x0UL) /*!< EVENTS[31] disabled                                              */
  #define VPRCSR_NORDIC_EVENTS_EVENTS31_Enabled (0x1UL) /*!< EVENTS[31] enabled                                                */


/**
  * @brief PUBLISH [VPRCSR_NORDIC_PUBLISH] Enable Event Publication
  */
  #define VPRCSR_NORDIC_PUBLISH (0x000007E3ul)
  #define VPRCSR_NORDIC_PUBLISH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH register.                                */

/* PUBLISH0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos (0UL)   /*!< Position of PUBLISH0 field.                                          */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos) /*!< Bit mask of PUBLISH0 field.    */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Min (0x0UL) /*!< Min enumerator value of PUBLISH0 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Max (0x1UL) /*!< Max enumerator value of PUBLISH0 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Disabled (0x0UL) /*!< Publish disabled for EVENTS[0]                                  */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Enabled (0x1UL) /*!< Publish enabled for EVENTS[0]                                    */

/* PUBLISH1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos (1UL)   /*!< Position of PUBLISH1 field.                                          */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos) /*!< Bit mask of PUBLISH1 field.    */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Min (0x0UL) /*!< Min enumerator value of PUBLISH1 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Max (0x1UL) /*!< Max enumerator value of PUBLISH1 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Disabled (0x0UL) /*!< Publish disabled for EVENTS[1]                                  */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Enabled (0x1UL) /*!< Publish enabled for EVENTS[1]                                    */

/* PUBLISH2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos (2UL)   /*!< Position of PUBLISH2 field.                                          */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos) /*!< Bit mask of PUBLISH2 field.    */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Min (0x0UL) /*!< Min enumerator value of PUBLISH2 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Max (0x1UL) /*!< Max enumerator value of PUBLISH2 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Disabled (0x0UL) /*!< Publish disabled for EVENTS[2]                                  */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Enabled (0x1UL) /*!< Publish enabled for EVENTS[2]                                    */

/* PUBLISH3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos (3UL)   /*!< Position of PUBLISH3 field.                                          */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos) /*!< Bit mask of PUBLISH3 field.    */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Min (0x0UL) /*!< Min enumerator value of PUBLISH3 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Max (0x1UL) /*!< Max enumerator value of PUBLISH3 field.                              */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Disabled (0x0UL) /*!< Publish disabled for EVENTS[3]                                  */
  #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Enabled (0x1UL) /*!< Publish enabled for EVENTS[3]                                    */


/**
  * @brief INTEN [VPRCSR_NORDIC_INTEN] DPPI Event Interrupt Enable
  */
  #define VPRCSR_NORDIC_INTEN (0x000007E4ul)
  #define VPRCSR_NORDIC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register.                                    */

/* INTEN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN0_Pos (0UL)       /*!< Position of INTEN0 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN0_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN0_Pos) /*!< Bit mask of INTEN0 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN0_Min (0x0UL)     /*!< Min enumerator value of INTEN0 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN0_Max (0x1UL)     /*!< Max enumerator value of INTEN0 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN0_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[0]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN0_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[0]                                      */

/* INTEN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN1_Pos (1UL)       /*!< Position of INTEN1 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN1_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN1_Pos) /*!< Bit mask of INTEN1 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN1_Min (0x0UL)     /*!< Min enumerator value of INTEN1 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN1_Max (0x1UL)     /*!< Max enumerator value of INTEN1 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN1_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[1]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN1_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[1]                                      */

/* INTEN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN2_Pos (2UL)       /*!< Position of INTEN2 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN2_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN2_Pos) /*!< Bit mask of INTEN2 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN2_Min (0x0UL)     /*!< Min enumerator value of INTEN2 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN2_Max (0x1UL)     /*!< Max enumerator value of INTEN2 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN2_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[2]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN2_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[2]                                      */

/* INTEN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN3_Pos (3UL)       /*!< Position of INTEN3 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN3_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN3_Pos) /*!< Bit mask of INTEN3 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN3_Min (0x0UL)     /*!< Min enumerator value of INTEN3 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN3_Max (0x1UL)     /*!< Max enumerator value of INTEN3 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN3_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[3]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN3_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[3]                                      */

/* INTEN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN4_Pos (4UL)       /*!< Position of INTEN4 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN4_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN4_Pos) /*!< Bit mask of INTEN4 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN4_Min (0x0UL)     /*!< Min enumerator value of INTEN4 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN4_Max (0x1UL)     /*!< Max enumerator value of INTEN4 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN4_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[4]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN4_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[4]                                      */

/* INTEN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN5_Pos (5UL)       /*!< Position of INTEN5 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN5_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN5_Pos) /*!< Bit mask of INTEN5 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN5_Min (0x0UL)     /*!< Min enumerator value of INTEN5 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN5_Max (0x1UL)     /*!< Max enumerator value of INTEN5 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN5_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[5]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN5_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[5]                                      */

/* INTEN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN6_Pos (6UL)       /*!< Position of INTEN6 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN6_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN6_Pos) /*!< Bit mask of INTEN6 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN6_Min (0x0UL)     /*!< Min enumerator value of INTEN6 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN6_Max (0x1UL)     /*!< Max enumerator value of INTEN6 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN6_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[6]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN6_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[6]                                      */

/* INTEN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN7_Pos (7UL)       /*!< Position of INTEN7 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN7_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN7_Pos) /*!< Bit mask of INTEN7 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN7_Min (0x0UL)     /*!< Min enumerator value of INTEN7 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN7_Max (0x1UL)     /*!< Max enumerator value of INTEN7 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN7_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[7]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN7_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[7]                                      */

/* INTEN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN8_Pos (8UL)       /*!< Position of INTEN8 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN8_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN8_Pos) /*!< Bit mask of INTEN8 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN8_Min (0x0UL)     /*!< Min enumerator value of INTEN8 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN8_Max (0x1UL)     /*!< Max enumerator value of INTEN8 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN8_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[8]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN8_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[8]                                      */

/* INTEN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN9_Pos (9UL)       /*!< Position of INTEN9 field.                                            */
  #define VPRCSR_NORDIC_INTEN_INTEN9_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN9_Pos) /*!< Bit mask of INTEN9 field.              */
  #define VPRCSR_NORDIC_INTEN_INTEN9_Min (0x0UL)     /*!< Min enumerator value of INTEN9 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN9_Max (0x1UL)     /*!< Max enumerator value of INTEN9 field.                                */
  #define VPRCSR_NORDIC_INTEN_INTEN9_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[9]                                    */
  #define VPRCSR_NORDIC_INTEN_INTEN9_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[9]                                      */

/* INTEN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN10_Pos (10UL)     /*!< Position of INTEN10 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN10_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN10_Pos) /*!< Bit mask of INTEN10 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN10_Min (0x0UL)    /*!< Min enumerator value of INTEN10 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN10_Max (0x1UL)    /*!< Max enumerator value of INTEN10 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN10_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[10]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN10_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[10]                                    */

/* INTEN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN11_Pos (11UL)     /*!< Position of INTEN11 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN11_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN11_Pos) /*!< Bit mask of INTEN11 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN11_Min (0x0UL)    /*!< Min enumerator value of INTEN11 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN11_Max (0x1UL)    /*!< Max enumerator value of INTEN11 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN11_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[11]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN11_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[11]                                    */

/* INTEN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN12_Pos (12UL)     /*!< Position of INTEN12 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN12_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN12_Pos) /*!< Bit mask of INTEN12 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN12_Min (0x0UL)    /*!< Min enumerator value of INTEN12 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN12_Max (0x1UL)    /*!< Max enumerator value of INTEN12 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN12_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[12]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN12_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[12]                                    */

/* INTEN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN13_Pos (13UL)     /*!< Position of INTEN13 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN13_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN13_Pos) /*!< Bit mask of INTEN13 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN13_Min (0x0UL)    /*!< Min enumerator value of INTEN13 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN13_Max (0x1UL)    /*!< Max enumerator value of INTEN13 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN13_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[13]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN13_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[13]                                    */

/* INTEN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN14_Pos (14UL)     /*!< Position of INTEN14 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN14_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN14_Pos) /*!< Bit mask of INTEN14 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN14_Min (0x0UL)    /*!< Min enumerator value of INTEN14 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN14_Max (0x1UL)    /*!< Max enumerator value of INTEN14 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN14_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[14]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN14_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[14]                                    */

/* INTEN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN15_Pos (15UL)     /*!< Position of INTEN15 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN15_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN15_Pos) /*!< Bit mask of INTEN15 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN15_Min (0x0UL)    /*!< Min enumerator value of INTEN15 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN15_Max (0x1UL)    /*!< Max enumerator value of INTEN15 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN15_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[15]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN15_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[15]                                    */

/* INTEN16 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN16_Pos (16UL)     /*!< Position of INTEN16 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN16_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN16_Pos) /*!< Bit mask of INTEN16 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN16_Min (0x0UL)    /*!< Min enumerator value of INTEN16 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN16_Max (0x1UL)    /*!< Max enumerator value of INTEN16 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN16_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[16]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN16_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[16]                                    */

/* INTEN17 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN17_Pos (17UL)     /*!< Position of INTEN17 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN17_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN17_Pos) /*!< Bit mask of INTEN17 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN17_Min (0x0UL)    /*!< Min enumerator value of INTEN17 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN17_Max (0x1UL)    /*!< Max enumerator value of INTEN17 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN17_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[17]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN17_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[17]                                    */

/* INTEN18 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN18_Pos (18UL)     /*!< Position of INTEN18 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN18_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN18_Pos) /*!< Bit mask of INTEN18 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN18_Min (0x0UL)    /*!< Min enumerator value of INTEN18 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN18_Max (0x1UL)    /*!< Max enumerator value of INTEN18 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN18_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[18]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN18_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[18]                                    */

/* INTEN19 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN19_Pos (19UL)     /*!< Position of INTEN19 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN19_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN19_Pos) /*!< Bit mask of INTEN19 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN19_Min (0x0UL)    /*!< Min enumerator value of INTEN19 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN19_Max (0x1UL)    /*!< Max enumerator value of INTEN19 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN19_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[19]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN19_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[19]                                    */

/* INTEN20 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN20_Pos (20UL)     /*!< Position of INTEN20 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN20_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN20_Pos) /*!< Bit mask of INTEN20 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN20_Min (0x0UL)    /*!< Min enumerator value of INTEN20 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN20_Max (0x1UL)    /*!< Max enumerator value of INTEN20 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN20_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[20]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN20_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[20]                                    */

/* INTEN21 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN21_Pos (21UL)     /*!< Position of INTEN21 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN21_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN21_Pos) /*!< Bit mask of INTEN21 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN21_Min (0x0UL)    /*!< Min enumerator value of INTEN21 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN21_Max (0x1UL)    /*!< Max enumerator value of INTEN21 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN21_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[21]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN21_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[21]                                    */

/* INTEN22 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN22_Pos (22UL)     /*!< Position of INTEN22 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN22_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN22_Pos) /*!< Bit mask of INTEN22 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN22_Min (0x0UL)    /*!< Min enumerator value of INTEN22 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN22_Max (0x1UL)    /*!< Max enumerator value of INTEN22 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN22_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[22]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN22_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[22]                                    */

/* INTEN23 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN23_Pos (23UL)     /*!< Position of INTEN23 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN23_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN23_Pos) /*!< Bit mask of INTEN23 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN23_Min (0x0UL)    /*!< Min enumerator value of INTEN23 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN23_Max (0x1UL)    /*!< Max enumerator value of INTEN23 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN23_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[23]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN23_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[23]                                    */

/* INTEN24 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN24_Pos (24UL)     /*!< Position of INTEN24 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN24_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN24_Pos) /*!< Bit mask of INTEN24 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN24_Min (0x0UL)    /*!< Min enumerator value of INTEN24 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN24_Max (0x1UL)    /*!< Max enumerator value of INTEN24 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN24_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[24]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN24_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[24]                                    */

/* INTEN25 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN25_Pos (25UL)     /*!< Position of INTEN25 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN25_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN25_Pos) /*!< Bit mask of INTEN25 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN25_Min (0x0UL)    /*!< Min enumerator value of INTEN25 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN25_Max (0x1UL)    /*!< Max enumerator value of INTEN25 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN25_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[25]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN25_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[25]                                    */

/* INTEN26 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN26_Pos (26UL)     /*!< Position of INTEN26 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN26_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN26_Pos) /*!< Bit mask of INTEN26 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN26_Min (0x0UL)    /*!< Min enumerator value of INTEN26 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN26_Max (0x1UL)    /*!< Max enumerator value of INTEN26 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN26_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[26]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN26_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[26]                                    */

/* INTEN27 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN27_Pos (27UL)     /*!< Position of INTEN27 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN27_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN27_Pos) /*!< Bit mask of INTEN27 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN27_Min (0x0UL)    /*!< Min enumerator value of INTEN27 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN27_Max (0x1UL)    /*!< Max enumerator value of INTEN27 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN27_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[27]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN27_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[27]                                    */

/* INTEN28 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN28_Pos (28UL)     /*!< Position of INTEN28 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN28_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN28_Pos) /*!< Bit mask of INTEN28 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN28_Min (0x0UL)    /*!< Min enumerator value of INTEN28 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN28_Max (0x1UL)    /*!< Max enumerator value of INTEN28 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN28_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[28]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN28_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[28]                                    */

/* INTEN29 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN29_Pos (29UL)     /*!< Position of INTEN29 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN29_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN29_Pos) /*!< Bit mask of INTEN29 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN29_Min (0x0UL)    /*!< Min enumerator value of INTEN29 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN29_Max (0x1UL)    /*!< Max enumerator value of INTEN29 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN29_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[29]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN29_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[29]                                    */

/* INTEN30 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN30_Pos (30UL)     /*!< Position of INTEN30 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN30_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN30_Pos) /*!< Bit mask of INTEN30 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN30_Min (0x0UL)    /*!< Min enumerator value of INTEN30 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN30_Max (0x1UL)    /*!< Max enumerator value of INTEN30 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN30_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[30]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN30_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[30]                                    */

/* INTEN31 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_INTEN_INTEN31_Pos (31UL)     /*!< Position of INTEN31 field.                                           */
  #define VPRCSR_NORDIC_INTEN_INTEN31_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN31_Pos) /*!< Bit mask of INTEN31 field.           */
  #define VPRCSR_NORDIC_INTEN_INTEN31_Min (0x0UL)    /*!< Min enumerator value of INTEN31 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN31_Max (0x1UL)    /*!< Max enumerator value of INTEN31 field.                               */
  #define VPRCSR_NORDIC_INTEN_INTEN31_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[31]                                  */
  #define VPRCSR_NORDIC_INTEN_INTEN31_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[31]                                    */


/**
  * @brief EVENTSB [VPRCSR_NORDIC_EVENTSB] Buffered DPPI Events
  */
  #define VPRCSR_NORDIC_EVENTSB (0x000007E5ul)
  #define VPRCSR_NORDIC_EVENTSB_ResetValue (0x00000000UL) /*!< Reset value of EVENTSB register.                                */

/* EVENTSB0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos (0UL)   /*!< Position of EVENTSB0 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos) /*!< Bit mask of EVENTSB0 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Min (0x0UL) /*!< Min enumerator value of EVENTSB0 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Max (0x1UL) /*!< Max enumerator value of EVENTSB0 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Disabled (0x0UL) /*!< EVENTSB[0] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Enabled (0x1UL) /*!< EVENTSB[0] enabled                                               */

/* EVENTSB1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos (1UL)   /*!< Position of EVENTSB1 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos) /*!< Bit mask of EVENTSB1 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Min (0x0UL) /*!< Min enumerator value of EVENTSB1 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Max (0x1UL) /*!< Max enumerator value of EVENTSB1 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Disabled (0x0UL) /*!< EVENTSB[1] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Enabled (0x1UL) /*!< EVENTSB[1] enabled                                               */

/* EVENTSB2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos (2UL)   /*!< Position of EVENTSB2 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos) /*!< Bit mask of EVENTSB2 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Min (0x0UL) /*!< Min enumerator value of EVENTSB2 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Max (0x1UL) /*!< Max enumerator value of EVENTSB2 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Disabled (0x0UL) /*!< EVENTSB[2] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Enabled (0x1UL) /*!< EVENTSB[2] enabled                                               */

/* EVENTSB3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos (3UL)   /*!< Position of EVENTSB3 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos) /*!< Bit mask of EVENTSB3 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Min (0x0UL) /*!< Min enumerator value of EVENTSB3 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Max (0x1UL) /*!< Max enumerator value of EVENTSB3 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Disabled (0x0UL) /*!< EVENTSB[3] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Enabled (0x1UL) /*!< EVENTSB[3] enabled                                               */

/* EVENTSB4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos (4UL)   /*!< Position of EVENTSB4 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos) /*!< Bit mask of EVENTSB4 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Min (0x0UL) /*!< Min enumerator value of EVENTSB4 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Max (0x1UL) /*!< Max enumerator value of EVENTSB4 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Disabled (0x0UL) /*!< EVENTSB[4] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Enabled (0x1UL) /*!< EVENTSB[4] enabled                                               */

/* EVENTSB5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos (5UL)   /*!< Position of EVENTSB5 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos) /*!< Bit mask of EVENTSB5 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Min (0x0UL) /*!< Min enumerator value of EVENTSB5 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Max (0x1UL) /*!< Max enumerator value of EVENTSB5 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Disabled (0x0UL) /*!< EVENTSB[5] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Enabled (0x1UL) /*!< EVENTSB[5] enabled                                               */

/* EVENTSB6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos (6UL)   /*!< Position of EVENTSB6 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos) /*!< Bit mask of EVENTSB6 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Min (0x0UL) /*!< Min enumerator value of EVENTSB6 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Max (0x1UL) /*!< Max enumerator value of EVENTSB6 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Disabled (0x0UL) /*!< EVENTSB[6] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Enabled (0x1UL) /*!< EVENTSB[6] enabled                                               */

/* EVENTSB7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos (7UL)   /*!< Position of EVENTSB7 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos) /*!< Bit mask of EVENTSB7 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Min (0x0UL) /*!< Min enumerator value of EVENTSB7 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Max (0x1UL) /*!< Max enumerator value of EVENTSB7 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Disabled (0x0UL) /*!< EVENTSB[7] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Enabled (0x1UL) /*!< EVENTSB[7] enabled                                               */

/* EVENTSB8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos (8UL)   /*!< Position of EVENTSB8 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos) /*!< Bit mask of EVENTSB8 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Min (0x0UL) /*!< Min enumerator value of EVENTSB8 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Max (0x1UL) /*!< Max enumerator value of EVENTSB8 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Disabled (0x0UL) /*!< EVENTSB[8] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Enabled (0x1UL) /*!< EVENTSB[8] enabled                                               */

/* EVENTSB9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos (9UL)   /*!< Position of EVENTSB9 field.                                          */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos) /*!< Bit mask of EVENTSB9 field.    */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Min (0x0UL) /*!< Min enumerator value of EVENTSB9 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Max (0x1UL) /*!< Max enumerator value of EVENTSB9 field.                              */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Disabled (0x0UL) /*!< EVENTSB[9] disabled                                             */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Enabled (0x1UL) /*!< EVENTSB[9] enabled                                               */

/* EVENTSB10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos (10UL) /*!< Position of EVENTSB10 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos) /*!< Bit mask of EVENTSB10 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Min (0x0UL) /*!< Min enumerator value of EVENTSB10 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Max (0x1UL) /*!< Max enumerator value of EVENTSB10 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Disabled (0x0UL) /*!< EVENTSB[10] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Enabled (0x1UL) /*!< EVENTSB[10] enabled                                             */

/* EVENTSB11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos (11UL) /*!< Position of EVENTSB11 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos) /*!< Bit mask of EVENTSB11 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Min (0x0UL) /*!< Min enumerator value of EVENTSB11 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Max (0x1UL) /*!< Max enumerator value of EVENTSB11 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Disabled (0x0UL) /*!< EVENTSB[11] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Enabled (0x1UL) /*!< EVENTSB[11] enabled                                             */

/* EVENTSB12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos (12UL) /*!< Position of EVENTSB12 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos) /*!< Bit mask of EVENTSB12 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Min (0x0UL) /*!< Min enumerator value of EVENTSB12 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Max (0x1UL) /*!< Max enumerator value of EVENTSB12 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Disabled (0x0UL) /*!< EVENTSB[12] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Enabled (0x1UL) /*!< EVENTSB[12] enabled                                             */

/* EVENTSB13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos (13UL) /*!< Position of EVENTSB13 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos) /*!< Bit mask of EVENTSB13 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Min (0x0UL) /*!< Min enumerator value of EVENTSB13 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Max (0x1UL) /*!< Max enumerator value of EVENTSB13 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Disabled (0x0UL) /*!< EVENTSB[13] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Enabled (0x1UL) /*!< EVENTSB[13] enabled                                             */

/* EVENTSB14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos (14UL) /*!< Position of EVENTSB14 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos) /*!< Bit mask of EVENTSB14 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Min (0x0UL) /*!< Min enumerator value of EVENTSB14 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Max (0x1UL) /*!< Max enumerator value of EVENTSB14 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Disabled (0x0UL) /*!< EVENTSB[14] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Enabled (0x1UL) /*!< EVENTSB[14] enabled                                             */

/* EVENTSB15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos (15UL) /*!< Position of EVENTSB15 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos) /*!< Bit mask of EVENTSB15 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Min (0x0UL) /*!< Min enumerator value of EVENTSB15 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Max (0x1UL) /*!< Max enumerator value of EVENTSB15 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Disabled (0x0UL) /*!< EVENTSB[15] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Enabled (0x1UL) /*!< EVENTSB[15] enabled                                             */

/* EVENTSB16 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos (16UL) /*!< Position of EVENTSB16 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos) /*!< Bit mask of EVENTSB16 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Min (0x0UL) /*!< Min enumerator value of EVENTSB16 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Max (0x1UL) /*!< Max enumerator value of EVENTSB16 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Disabled (0x0UL) /*!< EVENTSB[16] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Enabled (0x1UL) /*!< EVENTSB[16] enabled                                             */

/* EVENTSB17 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos (17UL) /*!< Position of EVENTSB17 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos) /*!< Bit mask of EVENTSB17 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Min (0x0UL) /*!< Min enumerator value of EVENTSB17 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Max (0x1UL) /*!< Max enumerator value of EVENTSB17 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Disabled (0x0UL) /*!< EVENTSB[17] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Enabled (0x1UL) /*!< EVENTSB[17] enabled                                             */

/* EVENTSB18 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos (18UL) /*!< Position of EVENTSB18 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos) /*!< Bit mask of EVENTSB18 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Min (0x0UL) /*!< Min enumerator value of EVENTSB18 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Max (0x1UL) /*!< Max enumerator value of EVENTSB18 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Disabled (0x0UL) /*!< EVENTSB[18] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Enabled (0x1UL) /*!< EVENTSB[18] enabled                                             */

/* EVENTSB19 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos (19UL) /*!< Position of EVENTSB19 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos) /*!< Bit mask of EVENTSB19 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Min (0x0UL) /*!< Min enumerator value of EVENTSB19 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Max (0x1UL) /*!< Max enumerator value of EVENTSB19 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Disabled (0x0UL) /*!< EVENTSB[19] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Enabled (0x1UL) /*!< EVENTSB[19] enabled                                             */

/* EVENTSB20 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos (20UL) /*!< Position of EVENTSB20 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos) /*!< Bit mask of EVENTSB20 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Min (0x0UL) /*!< Min enumerator value of EVENTSB20 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Max (0x1UL) /*!< Max enumerator value of EVENTSB20 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Disabled (0x0UL) /*!< EVENTSB[20] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Enabled (0x1UL) /*!< EVENTSB[20] enabled                                             */

/* EVENTSB21 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos (21UL) /*!< Position of EVENTSB21 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos) /*!< Bit mask of EVENTSB21 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Min (0x0UL) /*!< Min enumerator value of EVENTSB21 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Max (0x1UL) /*!< Max enumerator value of EVENTSB21 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Disabled (0x0UL) /*!< EVENTSB[21] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Enabled (0x1UL) /*!< EVENTSB[21] enabled                                             */

/* EVENTSB22 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos (22UL) /*!< Position of EVENTSB22 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos) /*!< Bit mask of EVENTSB22 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Min (0x0UL) /*!< Min enumerator value of EVENTSB22 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Max (0x1UL) /*!< Max enumerator value of EVENTSB22 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Disabled (0x0UL) /*!< EVENTSB[22] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Enabled (0x1UL) /*!< EVENTSB[22] enabled                                             */

/* EVENTSB23 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos (23UL) /*!< Position of EVENTSB23 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos) /*!< Bit mask of EVENTSB23 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Min (0x0UL) /*!< Min enumerator value of EVENTSB23 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Max (0x1UL) /*!< Max enumerator value of EVENTSB23 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Disabled (0x0UL) /*!< EVENTSB[23] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Enabled (0x1UL) /*!< EVENTSB[23] enabled                                             */

/* EVENTSB24 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos (24UL) /*!< Position of EVENTSB24 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos) /*!< Bit mask of EVENTSB24 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Min (0x0UL) /*!< Min enumerator value of EVENTSB24 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Max (0x1UL) /*!< Max enumerator value of EVENTSB24 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Disabled (0x0UL) /*!< EVENTSB[24] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Enabled (0x1UL) /*!< EVENTSB[24] enabled                                             */

/* EVENTSB25 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos (25UL) /*!< Position of EVENTSB25 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos) /*!< Bit mask of EVENTSB25 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Min (0x0UL) /*!< Min enumerator value of EVENTSB25 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Max (0x1UL) /*!< Max enumerator value of EVENTSB25 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Disabled (0x0UL) /*!< EVENTSB[25] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Enabled (0x1UL) /*!< EVENTSB[25] enabled                                             */

/* EVENTSB26 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos (26UL) /*!< Position of EVENTSB26 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos) /*!< Bit mask of EVENTSB26 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Min (0x0UL) /*!< Min enumerator value of EVENTSB26 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Max (0x1UL) /*!< Max enumerator value of EVENTSB26 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Disabled (0x0UL) /*!< EVENTSB[26] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Enabled (0x1UL) /*!< EVENTSB[26] enabled                                             */

/* EVENTSB27 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos (27UL) /*!< Position of EVENTSB27 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos) /*!< Bit mask of EVENTSB27 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Min (0x0UL) /*!< Min enumerator value of EVENTSB27 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Max (0x1UL) /*!< Max enumerator value of EVENTSB27 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Disabled (0x0UL) /*!< EVENTSB[27] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Enabled (0x1UL) /*!< EVENTSB[27] enabled                                             */

/* EVENTSB28 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos (28UL) /*!< Position of EVENTSB28 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos) /*!< Bit mask of EVENTSB28 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Min (0x0UL) /*!< Min enumerator value of EVENTSB28 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Max (0x1UL) /*!< Max enumerator value of EVENTSB28 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Disabled (0x0UL) /*!< EVENTSB[28] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Enabled (0x1UL) /*!< EVENTSB[28] enabled                                             */

/* EVENTSB29 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos (29UL) /*!< Position of EVENTSB29 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos) /*!< Bit mask of EVENTSB29 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Min (0x0UL) /*!< Min enumerator value of EVENTSB29 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Max (0x1UL) /*!< Max enumerator value of EVENTSB29 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Disabled (0x0UL) /*!< EVENTSB[29] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Enabled (0x1UL) /*!< EVENTSB[29] enabled                                             */

/* EVENTSB30 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos (30UL) /*!< Position of EVENTSB30 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos) /*!< Bit mask of EVENTSB30 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Min (0x0UL) /*!< Min enumerator value of EVENTSB30 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Max (0x1UL) /*!< Max enumerator value of EVENTSB30 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Disabled (0x0UL) /*!< EVENTSB[30] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Enabled (0x1UL) /*!< EVENTSB[30] enabled                                             */

/* EVENTSB31 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos (31UL) /*!< Position of EVENTSB31 field.                                         */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos) /*!< Bit mask of EVENTSB31 field. */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Min (0x0UL) /*!< Min enumerator value of EVENTSB31 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Max (0x1UL) /*!< Max enumerator value of EVENTSB31 field.                            */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Disabled (0x0UL) /*!< EVENTSB[31] disabled                                           */
  #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Enabled (0x1UL) /*!< EVENTSB[31] enabled                                             */


/**
  * @brief EVENTSBS [VPRCSR_NORDIC_EVENTSBS] EVENTSB Dirty Status
  */
  #define VPRCSR_NORDIC_EVENTSBS (0x000007E6ul)
  #define VPRCSR_NORDIC_EVENTSBS_ResetValue (0x00000000UL) /*!< Reset value of EVENTSBS register.                              */

/* EVENTSB @Bits 0..31 : Write to EVENTSB (if not dirty) */
  #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos (0UL)   /*!< Position of EVENTSB field.                                           */
  #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos) /*!< Bit mask of EVENTSB
                                                                            field.*/

/* DIRTYBIT @Bit 0 : Read EVENTSB Dirty status */
  #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos (0UL)  /*!< Position of DIRTYBIT field.                                          */
  #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.  */
  #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field.                             */
  #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field.                             */
  #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                   */
  #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                   */


/**
  * @brief OUT [VPRCSR_NORDIC_OUT] GPIO Output value. Real Time Peripherals VIO.
  */
  #define VPRCSR_NORDIC_OUT (0x00000BC0ul)
  #define VPRCSR_NORDIC_OUT_ResetValue (0x00000000UL) /*!< Reset value of OUT register.                                        */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN0_Pos (0UL)           /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN0_Min (0x0UL)         /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN0_Max (0x1UL)         /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN0_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN0_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN1_Pos (1UL)           /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN1_Min (0x0UL)         /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN1_Max (0x1UL)         /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN1_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN1_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN2_Pos (2UL)           /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN2_Min (0x0UL)         /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN2_Max (0x1UL)         /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN2_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN2_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN3_Pos (3UL)           /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN3_Min (0x0UL)         /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN3_Max (0x1UL)         /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN3_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN3_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN4_Pos (4UL)           /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN4_Min (0x0UL)         /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN4_Max (0x1UL)         /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN4_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN4_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN5_Pos (5UL)           /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN5_Min (0x0UL)         /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN5_Max (0x1UL)         /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN5_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN5_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN6_Pos (6UL)           /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN6_Min (0x0UL)         /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN6_Max (0x1UL)         /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN6_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN6_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN7_Pos (7UL)           /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN7_Min (0x0UL)         /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN7_Max (0x1UL)         /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN7_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN7_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN8_Pos (8UL)           /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN8_Min (0x0UL)         /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN8_Max (0x1UL)         /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN8_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN8_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN9_Pos (9UL)           /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_OUT_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field.                        */
  #define VPRCSR_NORDIC_OUT_PIN9_Min (0x0UL)         /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN9_Max (0x1UL)         /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUT_PIN9_LOW (0x0UL)         /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN9_HIGH (0x1UL)        /*!< Pin driver is high                                                   */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN10_Pos (10UL)         /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_OUT_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field.                     */
  #define VPRCSR_NORDIC_OUT_PIN10_Min (0x0UL)        /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN10_Max (0x1UL)        /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN10_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN10_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN11_Pos (11UL)         /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_OUT_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field.                     */
  #define VPRCSR_NORDIC_OUT_PIN11_Min (0x0UL)        /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN11_Max (0x1UL)        /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN11_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN11_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN12_Pos (12UL)         /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_OUT_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field.                     */
  #define VPRCSR_NORDIC_OUT_PIN12_Min (0x0UL)        /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN12_Max (0x1UL)        /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN12_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN12_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN13_Pos (13UL)         /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_OUT_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field.                     */
  #define VPRCSR_NORDIC_OUT_PIN13_Min (0x0UL)        /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN13_Max (0x1UL)        /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN13_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN13_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN14_Pos (14UL)         /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_OUT_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field.                     */
  #define VPRCSR_NORDIC_OUT_PIN14_Min (0x0UL)        /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN14_Max (0x1UL)        /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN14_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN14_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_OUT_PIN15_Pos (15UL)         /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_OUT_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field.                     */
  #define VPRCSR_NORDIC_OUT_PIN15_Min (0x0UL)        /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN15_Max (0x1UL)        /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUT_PIN15_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUT_PIN15_HIGH (0x1UL)       /*!< Pin driver is high                                                   */


/**
  * @brief DIR [VPRCSR_NORDIC_DIR] GPIO pin Direction. Real Time Peripherals VIO.
  */
  #define VPRCSR_NORDIC_DIR (0x00000BC1ul)
  #define VPRCSR_NORDIC_DIR_ResetValue (0x00000000UL) /*!< Reset value of DIR register.                                        */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN0_Pos (0UL)           /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN0_Min (0x0UL)         /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN0_Max (0x1UL)         /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN0_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN0_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN1_Pos (1UL)           /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN1_Min (0x0UL)         /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN1_Max (0x1UL)         /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN1_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN1_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN2_Pos (2UL)           /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN2_Min (0x0UL)         /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN2_Max (0x1UL)         /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN2_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN2_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN3_Pos (3UL)           /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN3_Min (0x0UL)         /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN3_Max (0x1UL)         /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN3_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN3_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN4_Pos (4UL)           /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN4_Min (0x0UL)         /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN4_Max (0x1UL)         /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN4_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN4_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN5_Pos (5UL)           /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN5_Min (0x0UL)         /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN5_Max (0x1UL)         /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN5_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN5_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN6_Pos (6UL)           /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN6_Min (0x0UL)         /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN6_Max (0x1UL)         /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN6_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN6_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN7_Pos (7UL)           /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN7_Min (0x0UL)         /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN7_Max (0x1UL)         /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN7_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN7_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN8_Pos (8UL)           /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN8_Min (0x0UL)         /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN8_Max (0x1UL)         /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN8_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN8_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN9_Pos (9UL)           /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_DIR_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field.                        */
  #define VPRCSR_NORDIC_DIR_PIN9_Min (0x0UL)         /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN9_Max (0x1UL)         /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIR_PIN9_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN9_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN10_Pos (10UL)         /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_DIR_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field.                     */
  #define VPRCSR_NORDIC_DIR_PIN10_Min (0x0UL)        /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN10_Max (0x1UL)        /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN10_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN10_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN11_Pos (11UL)         /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_DIR_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field.                     */
  #define VPRCSR_NORDIC_DIR_PIN11_Min (0x0UL)        /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN11_Max (0x1UL)        /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN11_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN11_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN12_Pos (12UL)         /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_DIR_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field.                     */
  #define VPRCSR_NORDIC_DIR_PIN12_Min (0x0UL)        /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN12_Max (0x1UL)        /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN12_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN12_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN13_Pos (13UL)         /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_DIR_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field.                     */
  #define VPRCSR_NORDIC_DIR_PIN13_Min (0x0UL)        /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN13_Max (0x1UL)        /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN13_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN13_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN14_Pos (14UL)         /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_DIR_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field.                     */
  #define VPRCSR_NORDIC_DIR_PIN14_Min (0x0UL)        /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN14_Max (0x1UL)        /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN14_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN14_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_DIR_PIN15_Pos (15UL)         /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_DIR_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field.                     */
  #define VPRCSR_NORDIC_DIR_PIN15_Min (0x0UL)        /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN15_Max (0x1UL)        /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIR_PIN15_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIR_PIN15_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */


/**
  * @brief IN [VPRCSR_NORDIC_IN] GPIO Input. Real Time Peripherals VIO.
  */
  #define VPRCSR_NORDIC_IN (0x00000BC2ul)
  #define VPRCSR_NORDIC_IN_ResetValue (0x00000000UL) /*!< Reset value of IN register.                                          */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN0_Pos (0UL)            /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN0_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN0_Pos) /*!< Bit mask of PIN0 field.                          */
  #define VPRCSR_NORDIC_IN_PIN0_Min (0x0UL)          /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN0_Max (0x1UL)          /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN0_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN0_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN1_Pos (1UL)            /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN1_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN1_Pos) /*!< Bit mask of PIN1 field.                          */
  #define VPRCSR_NORDIC_IN_PIN1_Min (0x0UL)          /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN1_Max (0x1UL)          /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN1_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN1_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN2_Pos (2UL)            /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN2_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN2_Pos) /*!< Bit mask of PIN2 field.                          */
  #define VPRCSR_NORDIC_IN_PIN2_Min (0x0UL)          /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN2_Max (0x1UL)          /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN2_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN2_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN3_Pos (3UL)            /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN3_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN3_Pos) /*!< Bit mask of PIN3 field.                          */
  #define VPRCSR_NORDIC_IN_PIN3_Min (0x0UL)          /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN3_Max (0x1UL)          /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN3_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN3_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN4_Pos (4UL)            /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN4_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN4_Pos) /*!< Bit mask of PIN4 field.                          */
  #define VPRCSR_NORDIC_IN_PIN4_Min (0x0UL)          /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN4_Max (0x1UL)          /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN4_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN4_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN5_Pos (5UL)            /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN5_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN5_Pos) /*!< Bit mask of PIN5 field.                          */
  #define VPRCSR_NORDIC_IN_PIN5_Min (0x0UL)          /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN5_Max (0x1UL)          /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN5_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN5_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN6_Pos (6UL)            /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN6_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN6_Pos) /*!< Bit mask of PIN6 field.                          */
  #define VPRCSR_NORDIC_IN_PIN6_Min (0x0UL)          /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN6_Max (0x1UL)          /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN6_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN6_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN7_Pos (7UL)            /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN7_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN7_Pos) /*!< Bit mask of PIN7 field.                          */
  #define VPRCSR_NORDIC_IN_PIN7_Min (0x0UL)          /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN7_Max (0x1UL)          /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN7_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN7_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN8_Pos (8UL)            /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN8_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN8_Pos) /*!< Bit mask of PIN8 field.                          */
  #define VPRCSR_NORDIC_IN_PIN8_Min (0x0UL)          /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN8_Max (0x1UL)          /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN8_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN8_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN9_Pos (9UL)            /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_IN_PIN9_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN9_Pos) /*!< Bit mask of PIN9 field.                          */
  #define VPRCSR_NORDIC_IN_PIN9_Min (0x0UL)          /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN9_Max (0x1UL)          /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_IN_PIN9_LOW (0x0UL)          /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN9_HIGH (0x1UL)         /*!< Pin is High                                                          */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN10_Pos (10UL)          /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_IN_PIN10_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN10_Pos) /*!< Bit mask of PIN10 field.                       */
  #define VPRCSR_NORDIC_IN_PIN10_Min (0x0UL)         /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN10_Max (0x1UL)         /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN10_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN10_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN11_Pos (11UL)          /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_IN_PIN11_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN11_Pos) /*!< Bit mask of PIN11 field.                       */
  #define VPRCSR_NORDIC_IN_PIN11_Min (0x0UL)         /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN11_Max (0x1UL)         /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN11_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN11_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN12_Pos (12UL)          /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_IN_PIN12_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN12_Pos) /*!< Bit mask of PIN12 field.                       */
  #define VPRCSR_NORDIC_IN_PIN12_Min (0x0UL)         /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN12_Max (0x1UL)         /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN12_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN12_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN13_Pos (13UL)          /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_IN_PIN13_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN13_Pos) /*!< Bit mask of PIN13 field.                       */
  #define VPRCSR_NORDIC_IN_PIN13_Min (0x0UL)         /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN13_Max (0x1UL)         /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN13_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN13_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN14_Pos (14UL)          /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_IN_PIN14_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN14_Pos) /*!< Bit mask of PIN14 field.                       */
  #define VPRCSR_NORDIC_IN_PIN14_Min (0x0UL)         /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN14_Max (0x1UL)         /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN14_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN14_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_IN_PIN15_Pos (15UL)          /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_IN_PIN15_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN15_Pos) /*!< Bit mask of PIN15 field.                       */
  #define VPRCSR_NORDIC_IN_PIN15_Min (0x0UL)         /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN15_Max (0x1UL)         /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_IN_PIN15_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_IN_PIN15_HIGH (0x1UL)        /*!< Pin is High                                                          */


/**
  * @brief INMODE [VPRCSR_NORDIC_INMODE] Input Mode
  */
  #define VPRCSR_NORDIC_INMODE (0x00000BC3ul)
  #define VPRCSR_NORDIC_INMODE_ResetValue (0x00000000UL) /*!< Reset value of INMODE register.                                  */

/* MODE @Bits 0..1 : Input Mode */
  #define VPRCSR_NORDIC_INMODE_MODE_Pos (0UL)        /*!< Position of MODE field.                                              */
  #define VPRCSR_NORDIC_INMODE_MODE_Msk (0x3UL << VPRCSR_NORDIC_INMODE_MODE_Pos) /*!< Bit mask of MODE field.                  */
  #define VPRCSR_NORDIC_INMODE_MODE_Min (0x0UL)      /*!< Min enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_INMODE_MODE_Max (0x2UL)      /*!< Max enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_INMODE_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                       */
  #define VPRCSR_NORDIC_INMODE_MODE_EVENT (0x1UL)    /*!< Sampling on Counter1 event                                           */
  #define VPRCSR_NORDIC_INMODE_MODE_SHIFT (0x2UL)    /*!< Sampling and shifting on Counter1 event synchronized with OUT        */


/**
  * @brief OUTB [VPRCSR_NORDIC_OUTB] Buffered GPIO Output
  */
  #define VPRCSR_NORDIC_OUTB (0x00000BC4ul)
  #define VPRCSR_NORDIC_OUTB_ResetValue (0x00000000UL) /*!< Reset value of OUTB register.                                      */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN0_Pos (0UL)          /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN0_Pos) /*!< Bit mask of PIN0 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN0_Min (0x0UL)        /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN0_Max (0x1UL)        /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN0_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN0_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN1_Pos (1UL)          /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN1_Pos) /*!< Bit mask of PIN1 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN1_Min (0x0UL)        /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN1_Max (0x1UL)        /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN1_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN1_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN2_Pos (2UL)          /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN2_Pos) /*!< Bit mask of PIN2 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN2_Min (0x0UL)        /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN2_Max (0x1UL)        /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN2_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN2_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN3_Pos (3UL)          /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN3_Pos) /*!< Bit mask of PIN3 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN3_Min (0x0UL)        /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN3_Max (0x1UL)        /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN3_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN3_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN4_Pos (4UL)          /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN4_Pos) /*!< Bit mask of PIN4 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN4_Min (0x0UL)        /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN4_Max (0x1UL)        /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN4_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN4_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN5_Pos (5UL)          /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN5_Pos) /*!< Bit mask of PIN5 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN5_Min (0x0UL)        /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN5_Max (0x1UL)        /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN5_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN5_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN6_Pos (6UL)          /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN6_Pos) /*!< Bit mask of PIN6 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN6_Min (0x0UL)        /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN6_Max (0x1UL)        /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN6_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN6_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN7_Pos (7UL)          /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN7_Pos) /*!< Bit mask of PIN7 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN7_Min (0x0UL)        /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN7_Max (0x1UL)        /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN7_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN7_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN8_Pos (8UL)          /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN8_Pos) /*!< Bit mask of PIN8 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN8_Min (0x0UL)        /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN8_Max (0x1UL)        /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN8_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN8_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN9_Pos (9UL)          /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_OUTB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN9_Pos) /*!< Bit mask of PIN9 field.                      */
  #define VPRCSR_NORDIC_OUTB_PIN9_Min (0x0UL)        /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN9_Max (0x1UL)        /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUTB_PIN9_LOW (0x0UL)        /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN9_HIGH (0x1UL)       /*!< Pin driver is high                                                   */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN10_Pos (10UL)        /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN10_Pos) /*!< Bit mask of PIN10 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN10_Min (0x0UL)       /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN10_Max (0x1UL)       /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN10_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN10_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN11_Pos (11UL)        /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN11_Pos) /*!< Bit mask of PIN11 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN11_Min (0x0UL)       /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN11_Max (0x1UL)       /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN11_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN11_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN12_Pos (12UL)        /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN12_Pos) /*!< Bit mask of PIN12 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN12_Min (0x0UL)       /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN12_Max (0x1UL)       /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN12_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN12_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN13_Pos (13UL)        /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN13_Pos) /*!< Bit mask of PIN13 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN13_Min (0x0UL)       /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN13_Max (0x1UL)       /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN13_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN13_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN14_Pos (14UL)        /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN14_Pos) /*!< Bit mask of PIN14 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN14_Min (0x0UL)       /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN14_Max (0x1UL)       /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN14_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN14_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN15_Pos (15UL)        /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN15_Pos) /*!< Bit mask of PIN15 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN15_Min (0x0UL)       /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN15_Max (0x1UL)       /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN15_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN15_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN16 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN16_Pos (16UL)        /*!< Position of PIN16 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN16_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN16_Pos) /*!< Bit mask of PIN16 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN16_Min (0x0UL)       /*!< Min enumerator value of PIN16 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN16_Max (0x1UL)       /*!< Max enumerator value of PIN16 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN16_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN16_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN17 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN17_Pos (17UL)        /*!< Position of PIN17 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN17_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN17_Pos) /*!< Bit mask of PIN17 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN17_Min (0x0UL)       /*!< Min enumerator value of PIN17 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN17_Max (0x1UL)       /*!< Max enumerator value of PIN17 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN17_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN17_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN18 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN18_Pos (18UL)        /*!< Position of PIN18 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN18_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN18_Pos) /*!< Bit mask of PIN18 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN18_Min (0x0UL)       /*!< Min enumerator value of PIN18 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN18_Max (0x1UL)       /*!< Max enumerator value of PIN18 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN18_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN18_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN19 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN19_Pos (19UL)        /*!< Position of PIN19 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN19_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN19_Pos) /*!< Bit mask of PIN19 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN19_Min (0x0UL)       /*!< Min enumerator value of PIN19 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN19_Max (0x1UL)       /*!< Max enumerator value of PIN19 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN19_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN19_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN20 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN20_Pos (20UL)        /*!< Position of PIN20 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN20_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN20_Pos) /*!< Bit mask of PIN20 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN20_Min (0x0UL)       /*!< Min enumerator value of PIN20 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN20_Max (0x1UL)       /*!< Max enumerator value of PIN20 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN20_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN20_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN21 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN21_Pos (21UL)        /*!< Position of PIN21 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN21_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN21_Pos) /*!< Bit mask of PIN21 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN21_Min (0x0UL)       /*!< Min enumerator value of PIN21 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN21_Max (0x1UL)       /*!< Max enumerator value of PIN21 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN21_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN21_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN22 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN22_Pos (22UL)        /*!< Position of PIN22 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN22_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN22_Pos) /*!< Bit mask of PIN22 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN22_Min (0x0UL)       /*!< Min enumerator value of PIN22 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN22_Max (0x1UL)       /*!< Max enumerator value of PIN22 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN22_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN22_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN23 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN23_Pos (23UL)        /*!< Position of PIN23 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN23_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN23_Pos) /*!< Bit mask of PIN23 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN23_Min (0x0UL)       /*!< Min enumerator value of PIN23 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN23_Max (0x1UL)       /*!< Max enumerator value of PIN23 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN23_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN23_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN24 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN24_Pos (24UL)        /*!< Position of PIN24 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN24_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN24_Pos) /*!< Bit mask of PIN24 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN24_Min (0x0UL)       /*!< Min enumerator value of PIN24 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN24_Max (0x1UL)       /*!< Max enumerator value of PIN24 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN24_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN24_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN25 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN25_Pos (25UL)        /*!< Position of PIN25 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN25_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN25_Pos) /*!< Bit mask of PIN25 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN25_Min (0x0UL)       /*!< Min enumerator value of PIN25 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN25_Max (0x1UL)       /*!< Max enumerator value of PIN25 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN25_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN25_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN26 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN26_Pos (26UL)        /*!< Position of PIN26 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN26_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN26_Pos) /*!< Bit mask of PIN26 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN26_Min (0x0UL)       /*!< Min enumerator value of PIN26 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN26_Max (0x1UL)       /*!< Max enumerator value of PIN26 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN26_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN26_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN27 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN27_Pos (27UL)        /*!< Position of PIN27 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN27_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN27_Pos) /*!< Bit mask of PIN27 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN27_Min (0x0UL)       /*!< Min enumerator value of PIN27 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN27_Max (0x1UL)       /*!< Max enumerator value of PIN27 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN27_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN27_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN28 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN28_Pos (28UL)        /*!< Position of PIN28 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN28_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN28_Pos) /*!< Bit mask of PIN28 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN28_Min (0x0UL)       /*!< Min enumerator value of PIN28 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN28_Max (0x1UL)       /*!< Max enumerator value of PIN28 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN28_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN28_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN29 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN29_Pos (29UL)        /*!< Position of PIN29 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN29_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN29_Pos) /*!< Bit mask of PIN29 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN29_Min (0x0UL)       /*!< Min enumerator value of PIN29 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN29_Max (0x1UL)       /*!< Max enumerator value of PIN29 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN29_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN29_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN30 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN30_Pos (30UL)        /*!< Position of PIN30 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN30_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN30_Pos) /*!< Bit mask of PIN30 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN30_Min (0x0UL)       /*!< Min enumerator value of PIN30 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN30_Max (0x1UL)       /*!< Max enumerator value of PIN30 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN30_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN30_HIGH (0x1UL)      /*!< Pin driver is high                                                   */

/* PIN31 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_OUTB_PIN31_Pos (31UL)        /*!< Position of PIN31 field.                                             */
  #define VPRCSR_NORDIC_OUTB_PIN31_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN31_Pos) /*!< Bit mask of PIN31 field.                   */
  #define VPRCSR_NORDIC_OUTB_PIN31_Min (0x0UL)       /*!< Min enumerator value of PIN31 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN31_Max (0x1UL)       /*!< Max enumerator value of PIN31 field.                                 */
  #define VPRCSR_NORDIC_OUTB_PIN31_LOW (0x0UL)       /*!< Pin driver is low                                                    */
  #define VPRCSR_NORDIC_OUTB_PIN31_HIGH (0x1UL)      /*!< Pin driver is high                                                   */


/**
  * @brief DIRB [VPRCSR_NORDIC_DIRB] Buffered GPIO pin Direction
  */
  #define VPRCSR_NORDIC_DIRB (0x00000BC5ul)
  #define VPRCSR_NORDIC_DIRB_ResetValue (0x00000000UL) /*!< Reset value of DIRB register.                                      */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN0_Pos (0UL)          /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN0_Pos) /*!< Bit mask of PIN0 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN0_Min (0x0UL)        /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN0_Max (0x1UL)        /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN0_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN0_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN1_Pos (1UL)          /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN1_Pos) /*!< Bit mask of PIN1 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN1_Min (0x0UL)        /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN1_Max (0x1UL)        /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN1_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN1_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN2_Pos (2UL)          /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN2_Pos) /*!< Bit mask of PIN2 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN2_Min (0x0UL)        /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN2_Max (0x1UL)        /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN2_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN2_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN3_Pos (3UL)          /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN3_Pos) /*!< Bit mask of PIN3 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN3_Min (0x0UL)        /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN3_Max (0x1UL)        /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN3_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN3_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN4_Pos (4UL)          /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN4_Pos) /*!< Bit mask of PIN4 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN4_Min (0x0UL)        /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN4_Max (0x1UL)        /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN4_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN4_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN5_Pos (5UL)          /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN5_Pos) /*!< Bit mask of PIN5 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN5_Min (0x0UL)        /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN5_Max (0x1UL)        /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN5_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN5_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN6_Pos (6UL)          /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN6_Pos) /*!< Bit mask of PIN6 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN6_Min (0x0UL)        /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN6_Max (0x1UL)        /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN6_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN6_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN7_Pos (7UL)          /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN7_Pos) /*!< Bit mask of PIN7 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN7_Min (0x0UL)        /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN7_Max (0x1UL)        /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN7_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN7_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN8_Pos (8UL)          /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN8_Pos) /*!< Bit mask of PIN8 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN8_Min (0x0UL)        /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN8_Max (0x1UL)        /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN8_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN8_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN9_Pos (9UL)          /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_DIRB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN9_Pos) /*!< Bit mask of PIN9 field.                      */
  #define VPRCSR_NORDIC_DIRB_PIN9_Min (0x0UL)        /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN9_Max (0x1UL)        /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIRB_PIN9_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN9_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN10_Pos (10UL)        /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_DIRB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN10_Pos) /*!< Bit mask of PIN10 field.                   */
  #define VPRCSR_NORDIC_DIRB_PIN10_Min (0x0UL)       /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN10_Max (0x1UL)       /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN10_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN10_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN11_Pos (11UL)        /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_DIRB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN11_Pos) /*!< Bit mask of PIN11 field.                   */
  #define VPRCSR_NORDIC_DIRB_PIN11_Min (0x0UL)       /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN11_Max (0x1UL)       /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN11_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN11_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN12_Pos (12UL)        /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_DIRB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN12_Pos) /*!< Bit mask of PIN12 field.                   */
  #define VPRCSR_NORDIC_DIRB_PIN12_Min (0x0UL)       /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN12_Max (0x1UL)       /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN12_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN12_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN13_Pos (13UL)        /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_DIRB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN13_Pos) /*!< Bit mask of PIN13 field.                   */
  #define VPRCSR_NORDIC_DIRB_PIN13_Min (0x0UL)       /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN13_Max (0x1UL)       /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN13_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN13_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN14_Pos (14UL)        /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_DIRB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN14_Pos) /*!< Bit mask of PIN14 field.                   */
  #define VPRCSR_NORDIC_DIRB_PIN14_Min (0x0UL)       /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN14_Max (0x1UL)       /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN14_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN14_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_DIRB_PIN15_Pos (15UL)        /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_DIRB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN15_Pos) /*!< Bit mask of PIN15 field.                   */
  #define VPRCSR_NORDIC_DIRB_PIN15_Min (0x0UL)       /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN15_Max (0x1UL)       /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIRB_PIN15_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
  #define VPRCSR_NORDIC_DIRB_PIN15_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */


/**
  * @brief DIROUT [VPRCSR_NORDIC_DIROUT] DIR and OUT concatenation
  */
  #define VPRCSR_NORDIC_DIROUT (0x00000BC6ul)
  #define VPRCSR_NORDIC_DIROUT_ResetValue (0x00000000UL) /*!< Reset value of DIROUT register.                                  */

/* OUT @Bits 0..15 : GPIO Output */
  #define VPRCSR_NORDIC_DIROUT_OUT_Pos (0UL)         /*!< Position of OUT field.                                               */
  #define VPRCSR_NORDIC_DIROUT_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_OUT_Pos) /*!< Bit mask of OUT field.                  */

/* DIR @Bits 16..31 : GPIO pin Direction */
  #define VPRCSR_NORDIC_DIROUT_DIR_Pos (16UL)        /*!< Position of DIR field.                                               */
  #define VPRCSR_NORDIC_DIROUT_DIR_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_DIR_Pos) /*!< Bit mask of DIR field.                  */


/**
  * @brief DIROUTB [VPRCSR_NORDIC_DIROUTB] Concatenation of DIRB and OUTB
  */
  #define VPRCSR_NORDIC_DIROUTB (0x00000BC7ul)
  #define VPRCSR_NORDIC_DIROUTB_ResetValue (0x00000000UL) /*!< Reset value of DIROUTB register.                                */

/* OUTB @Bits 0..15 : Buffered GPIO Output */
  #define VPRCSR_NORDIC_DIROUTB_OUTB_Pos (0UL)       /*!< Position of OUTB field.                                              */
  #define VPRCSR_NORDIC_DIROUTB_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_OUTB_Pos) /*!< Bit mask of OUTB field.             */

/* DIRB @Bits 16..31 : Buffered GPIO pin Direction */
  #define VPRCSR_NORDIC_DIROUTB_DIRB_Pos (16UL)      /*!< Position of DIRB field.                                              */
  #define VPRCSR_NORDIC_DIROUTB_DIRB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_DIRB_Pos) /*!< Bit mask of DIRB field.             */


/**
  * @brief OUTBRB [VPRCSR_NORDIC_OUTBRB] Byte reversed register OUTB
  */
  #define VPRCSR_NORDIC_OUTBRB (0x00000BC8ul)
  #define VPRCSR_NORDIC_OUTBRB_ResetValue (0x00000000UL) /*!< Reset value of OUTBRB register.                                  */

/* VAL @Bits 0..31 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBRB_VAL_Pos (0UL)         /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_OUTBRB_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBRB_VAL_Pos) /*!< Bit mask of VAL field.              */
  #define VPRCSR_NORDIC_OUTBRB_VAL_Min (0x00000000UL) /*!< Min value of VAL field.                                             */
  #define VPRCSR_NORDIC_OUTBRB_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field.                                              */


/**
  * @brief OUTBRW [VPRCSR_NORDIC_OUTBRW] Word reversed register OUTB
  */
  #define VPRCSR_NORDIC_OUTBRW (0x00000BC9ul)
  #define VPRCSR_NORDIC_OUTBRW_ResetValue (0x00000000UL) /*!< Reset value of OUTBRW register.                                  */

/* VAL @Bits 0..31 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBRW_VAL_Pos (0UL)         /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_OUTBRW_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBRW_VAL_Pos) /*!< Bit mask of VAL field.              */
  #define VPRCSR_NORDIC_OUTBRW_VAL_Min (0x00000000UL) /*!< Min value of VAL field.                                             */
  #define VPRCSR_NORDIC_OUTBRW_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field.                                              */


/**
  * @brief INBRB [VPRCSR_NORDIC_INBRB] Byte reversed register INB
  */
  #define VPRCSR_NORDIC_INBRB (0x00000BCAul)
  #define VPRCSR_NORDIC_INBRB_ResetValue (0x00000000UL) /*!< Reset value of INBRB register.                                    */

/* VAL @Bits 0..31 : (unspecified) */
  #define VPRCSR_NORDIC_INBRB_VAL_Pos (0UL)          /*!< Position of VAL field.                                               */
  #define VPRCSR_NORDIC_INBRB_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_INBRB_VAL_Pos) /*!< Bit mask of VAL field.                */
  #define VPRCSR_NORDIC_INBRB_VAL_Min (0x00000000UL) /*!< Min value of VAL field.                                              */
  #define VPRCSR_NORDIC_INBRB_VAL_Max (0xFFFFFFFFUL) /*!< Max size of VAL field.                                               */


/**
  * @brief SHIFTCTRLB [VPRCSR_NORDIC_SHIFTCTRLB] Buffered IO shift control
  */
  #define VPRCSR_NORDIC_SHIFTCTRLB (0x00000BCBul)
  #define VPRCSR_NORDIC_SHIFTCTRLB_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCTRLB register.                          */

/* Field group SHIFTCNTB : (unspecified) */
/* VALUE @Bits 0..5 : Alias to SHIFTCNTB.VALUE register */
    #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Pos (0UL) /*!< Position of VALUE field.                                   */
    #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Pos) /*!< Bit mask
                                                                            of VALUE field.*/
    #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Min (0x00UL) /*!< Min value of VALUE field.                               */
    #define VPRCSR_NORDIC_SHIFTCTRLB_SHIFTCNTB_VALUE_Max (0x20UL) /*!< Max size of VALUE field.                                */

/* End field group SHIFTCNTB. */

/* Field group OUTMODEB : (unspecified) */
/* MODE @Bits 8..10 : Alias to OUTMODEB.MODE register */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Pos (8UL) /*!< Position of MODE field.                                      */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Msk (0x7UL << VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Pos) /*!< Bit mask of
                                                                            MODE field.*/
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field.                        */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_Max (0x4UL) /*!< Max enumerator value of MODE field.                        */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_NoShifting (0x0UL) /*!< No shifting                                         */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering                           */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock
                                                                            line*/

/* FRAMEWIDTH @Bits 12..16 : Alias to OUTMODEB.FRAMEWIDTH register */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Pos (12UL) /*!< Position of FRAMEWIDTH field.                         */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Pos) /*!<
                                                                            Bit mask of FRAMEWIDTH field.*/
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field.                      */
    #define VPRCSR_NORDIC_SHIFTCTRLB_OUTMODEB_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field.                       */

/* End field group OUTMODEB. */

/* Field group INMODEB : (unspecified) */
/* MODE @Bits 20..21 : Alias to INMODEB.MODE register */
    #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Pos (20UL) /*!< Position of MODE field.                                      */
    #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Msk (0x3UL << VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Pos) /*!< Bit mask of MODE
                                                                            field.*/
    #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field.                         */
    #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_Max (0x2UL) /*!< Max enumerator value of MODE field.                         */
    #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)         */
    #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_EVENT (0x1UL) /*!< Sampling on Counter1 event                                */
    #define VPRCSR_NORDIC_SHIFTCTRLB_INMODEB_MODE_SHIFT (0x2UL) /*!< Sampling and shifting on Counter1 event                   */

/* End field group INMODEB. */


/**
  * @brief SHIFTCNTIN [VPRCSR_NORDIC_SHIFTCNTIN] Number of frames to be shifted from INB before new data is required
  */
  #define VPRCSR_NORDIC_SHIFTCNTIN (0x00000BCDul)
  #define VPRCSR_NORDIC_SHIFTCNTIN_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTIN register.                          */

/* VALUE @Bits 0..5 : Value */
  #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Pos (0UL)   /*!< Position of VALUE field.                                             */
  #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Pos) /*!< Bit mask of VALUE field.      */
  #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Min (0x00UL) /*!< Min value of VALUE field.                                           */
  #define VPRCSR_NORDIC_SHIFTCNTIN_VALUE_Max (0x3FUL) /*!< Max size of VALUE field.                                            */


/**
  * @brief SHIFTCNTOUT [VPRCSR_NORDIC_SHIFTCNTOUT] Number of frames to be shifted to OUTB before new data is required
  */
  #define VPRCSR_NORDIC_SHIFTCNTOUT (0x00000BCEul)
  #define VPRCSR_NORDIC_SHIFTCNTOUT_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTOUT register.                        */

/* VALUE @Bits 0..5 : Value */
  #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Pos (0UL)  /*!< Position of VALUE field.                                             */
  #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Pos) /*!< Bit mask of VALUE field.    */
  #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Min (0x00UL) /*!< Min value of VALUE field.                                          */
  #define VPRCSR_NORDIC_SHIFTCNTOUT_VALUE_Max (0x3FUL) /*!< Max size of VALUE field.                                           */


/**
  * @brief SHIFTCNTB [VPRCSR_NORDIC_SHIFTCNTB] Buffered SHIFTCNTOUT and SHIFTCNTIN register
  */
  #define VPRCSR_NORDIC_SHIFTCNTB (0x00000BCFul)
  #define VPRCSR_NORDIC_SHIFTCNTB_ResetValue (0x00000000UL) /*!< Reset value of SHIFTCNTB register.                            */

/* VALUE @Bits 0..5 : Value */
  #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Pos (0UL)    /*!< Position of VALUE field.                                             */
  #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Msk (0x3FUL << VPRCSR_NORDIC_SHIFTCNTB_VALUE_Pos) /*!< Bit mask of VALUE field.        */
  #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Min (0x00UL) /*!< Min value of VALUE field.                                            */
  #define VPRCSR_NORDIC_SHIFTCNTB_VALUE_Max (0x3FUL) /*!< Max size of VALUE field.                                             */


/**
  * @brief OUTTGL [VPRCSR_NORDIC_OUTTGL] GPIO Output Toggle
  */
  #define VPRCSR_NORDIC_OUTTGL (0x00000BD0ul)
  #define VPRCSR_NORDIC_OUTTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTTGL register.                                  */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN0_Pos (0UL)        /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN0_Min (0x0UL)      /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN0_Max (0x1UL)      /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN0_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN1_Pos (1UL)        /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN1_Min (0x0UL)      /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN1_Max (0x1UL)      /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN1_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN2_Pos (2UL)        /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN2_Min (0x0UL)      /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN2_Max (0x1UL)      /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN2_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN3_Pos (3UL)        /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN3_Min (0x0UL)      /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN3_Max (0x1UL)      /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN3_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN4_Pos (4UL)        /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN4_Min (0x0UL)      /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN4_Max (0x1UL)      /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN4_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN5_Pos (5UL)        /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN5_Min (0x0UL)      /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN5_Max (0x1UL)      /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN5_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN6_Pos (6UL)        /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN6_Min (0x0UL)      /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN6_Max (0x1UL)      /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN6_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN7_Pos (7UL)        /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN7_Min (0x0UL)      /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN7_Max (0x1UL)      /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN7_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN8_Pos (8UL)        /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN8_Min (0x0UL)      /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN8_Max (0x1UL)      /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN8_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN9_Pos (9UL)        /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN9_Min (0x0UL)      /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN9_Max (0x1UL)      /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUTTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_OUTTGL_PIN9_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN10_Pos (10UL)      /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_OUTTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.               */
  #define VPRCSR_NORDIC_OUTTGL_PIN10_Min (0x0UL)     /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN10_Max (0x1UL)     /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN10_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN11_Pos (11UL)      /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_OUTTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.               */
  #define VPRCSR_NORDIC_OUTTGL_PIN11_Min (0x0UL)     /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN11_Max (0x1UL)     /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN11_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN12_Pos (12UL)      /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_OUTTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.               */
  #define VPRCSR_NORDIC_OUTTGL_PIN12_Min (0x0UL)     /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN12_Max (0x1UL)     /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN12_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN13_Pos (13UL)      /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_OUTTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.               */
  #define VPRCSR_NORDIC_OUTTGL_PIN13_Min (0x0UL)     /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN13_Max (0x1UL)     /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN13_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN14_Pos (14UL)      /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_OUTTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.               */
  #define VPRCSR_NORDIC_OUTTGL_PIN14_Min (0x0UL)     /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN14_Max (0x1UL)     /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN14_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_OUTTGL_PIN15_Pos (15UL)      /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_OUTTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.               */
  #define VPRCSR_NORDIC_OUTTGL_PIN15_Min (0x0UL)     /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN15_Max (0x1UL)     /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUTTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTTGL_PIN15_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */


/**
  * @brief DIRTGL [VPRCSR_NORDIC_DIRTGL] GPIO pin Direction Toggle
  */
  #define VPRCSR_NORDIC_DIRTGL (0x00000BD1ul)
  #define VPRCSR_NORDIC_DIRTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRTGL register.                                  */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN0_Pos (0UL)        /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN0_Min (0x0UL)      /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN0_Max (0x1UL)      /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN0_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN1_Pos (1UL)        /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN1_Min (0x0UL)      /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN1_Max (0x1UL)      /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN1_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN2_Pos (2UL)        /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN2_Min (0x0UL)      /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN2_Max (0x1UL)      /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN2_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN3_Pos (3UL)        /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN3_Min (0x0UL)      /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN3_Max (0x1UL)      /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN3_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN4_Pos (4UL)        /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN4_Min (0x0UL)      /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN4_Max (0x1UL)      /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN4_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN5_Pos (5UL)        /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN5_Min (0x0UL)      /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN5_Max (0x1UL)      /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN5_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN6_Pos (6UL)        /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN6_Min (0x0UL)      /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN6_Max (0x1UL)      /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN6_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN7_Pos (7UL)        /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN7_Min (0x0UL)      /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN7_Max (0x1UL)      /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN7_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN8_Pos (8UL)        /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN8_Min (0x0UL)      /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN8_Max (0x1UL)      /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN8_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN9_Pos (9UL)        /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN9_Min (0x0UL)      /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN9_Max (0x1UL)      /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIRTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
  #define VPRCSR_NORDIC_DIRTGL_PIN9_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN10_Pos (10UL)      /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_DIRTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.               */
  #define VPRCSR_NORDIC_DIRTGL_PIN10_Min (0x0UL)     /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN10_Max (0x1UL)     /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN10_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN11_Pos (11UL)      /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_DIRTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.               */
  #define VPRCSR_NORDIC_DIRTGL_PIN11_Min (0x0UL)     /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN11_Max (0x1UL)     /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN11_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN12_Pos (12UL)      /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_DIRTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.               */
  #define VPRCSR_NORDIC_DIRTGL_PIN12_Min (0x0UL)     /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN12_Max (0x1UL)     /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN12_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN13_Pos (13UL)      /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_DIRTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.               */
  #define VPRCSR_NORDIC_DIRTGL_PIN13_Min (0x0UL)     /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN13_Max (0x1UL)     /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN13_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN14_Pos (14UL)      /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_DIRTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.               */
  #define VPRCSR_NORDIC_DIRTGL_PIN14_Min (0x0UL)     /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN14_Max (0x1UL)     /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN14_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_DIRTGL_PIN15_Pos (15UL)      /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_DIRTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.               */
  #define VPRCSR_NORDIC_DIRTGL_PIN15_Min (0x0UL)     /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN15_Max (0x1UL)     /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIRTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRTGL_PIN15_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */


/**
  * @brief OUTBTGL [VPRCSR_NORDIC_OUTBTGL] Buffered GPIO Output Toggle
  */
  #define VPRCSR_NORDIC_OUTBTGL (0x00000BD2ul)
  #define VPRCSR_NORDIC_OUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBTGL register.                                */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN0_Pos (0UL)       /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN0_Min (0x0UL)     /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN0_Max (0x1UL)     /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN0_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN1_Pos (1UL)       /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN1_Min (0x0UL)     /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN1_Max (0x1UL)     /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN1_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN2_Pos (2UL)       /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN2_Min (0x0UL)     /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN2_Max (0x1UL)     /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN2_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN3_Pos (3UL)       /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN3_Min (0x0UL)     /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN3_Max (0x1UL)     /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN3_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN4_Pos (4UL)       /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN4_Min (0x0UL)     /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN4_Max (0x1UL)     /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN4_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN5_Pos (5UL)       /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN5_Min (0x0UL)     /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN5_Max (0x1UL)     /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN5_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN6_Pos (6UL)       /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN6_Min (0x0UL)     /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN6_Max (0x1UL)     /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN6_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN7_Pos (7UL)       /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN7_Min (0x0UL)     /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN7_Max (0x1UL)     /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN7_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN8_Pos (8UL)       /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN8_Min (0x0UL)     /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN8_Max (0x1UL)     /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN8_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN9_Pos (9UL)       /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                */
  #define VPRCSR_NORDIC_OUTBTGL_PIN9_Min (0x0UL)     /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN9_Max (0x1UL)     /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_OUTBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_OUTBTGL_PIN9_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN10_Pos (10UL)     /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN10_Min (0x0UL)    /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN10_Max (0x1UL)    /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN11_Pos (11UL)     /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN11_Min (0x0UL)    /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN11_Max (0x1UL)    /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN12_Pos (12UL)     /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN12_Min (0x0UL)    /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN12_Max (0x1UL)    /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN13_Pos (13UL)     /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN13_Min (0x0UL)    /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN13_Max (0x1UL)    /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN14_Pos (14UL)     /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN14_Min (0x0UL)    /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN14_Max (0x1UL)    /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBTGL_PIN15_Pos (15UL)     /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN15_Min (0x0UL)    /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN15_Max (0x1UL)    /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_OUTBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */


/**
  * @brief DIRBTGL [VPRCSR_NORDIC_DIRBTGL] Buffered GPIO pin Direction Toggle
  */
  #define VPRCSR_NORDIC_DIRBTGL (0x00000BD3ul)
  #define VPRCSR_NORDIC_DIRBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRBTGL register.                                */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN0_Pos (0UL)       /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN0_Min (0x0UL)     /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN0_Max (0x1UL)     /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN0_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN1_Pos (1UL)       /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN1_Min (0x0UL)     /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN1_Max (0x1UL)     /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN1_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN2_Pos (2UL)       /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN2_Min (0x0UL)     /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN2_Max (0x1UL)     /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN2_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN3_Pos (3UL)       /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN3_Min (0x0UL)     /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN3_Max (0x1UL)     /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN3_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN4_Pos (4UL)       /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN4_Min (0x0UL)     /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN4_Max (0x1UL)     /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN4_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN5_Pos (5UL)       /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN5_Min (0x0UL)     /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN5_Max (0x1UL)     /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN5_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN6_Pos (6UL)       /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN6_Min (0x0UL)     /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN6_Max (0x1UL)     /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN6_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN7_Pos (7UL)       /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN7_Min (0x0UL)     /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN7_Max (0x1UL)     /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN7_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN8_Pos (8UL)       /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN8_Min (0x0UL)     /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN8_Max (0x1UL)     /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN8_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN9_Pos (9UL)       /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                */
  #define VPRCSR_NORDIC_DIRBTGL_PIN9_Min (0x0UL)     /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN9_Max (0x1UL)     /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_DIRBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
  #define VPRCSR_NORDIC_DIRBTGL_PIN9_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN10_Pos (10UL)     /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN10_Min (0x0UL)    /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN10_Max (0x1UL)    /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN11_Pos (11UL)     /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN11_Min (0x0UL)    /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN11_Max (0x1UL)    /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN12_Pos (12UL)     /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN12_Min (0x0UL)    /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN12_Max (0x1UL)    /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN13_Pos (13UL)     /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN13_Min (0x0UL)    /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN13_Max (0x1UL)    /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN14_Pos (14UL)     /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN14_Min (0x0UL)    /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN14_Max (0x1UL)    /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_DIRBTGL_PIN15_Pos (15UL)     /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN15_Min (0x0UL)    /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN15_Max (0x1UL)    /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_DIRBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_DIRBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */


/**
  * @brief DIROUTTGL [VPRCSR_NORDIC_DIROUTTGL] DIROUT Toggle
  */
  #define VPRCSR_NORDIC_DIROUTTGL (0x00000BD4ul)
  #define VPRCSR_NORDIC_DIROUTTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTTGL register.                            */

/* OUT0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos (0UL)     /*!< Position of OUT0 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos) /*!< Bit mask of OUT0 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Min (0x0UL)   /*!< Min enumerator value of OUT0 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Max (0x1UL)   /*!< Max enumerator value of OUT0 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos (1UL)     /*!< Position of OUT1 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos) /*!< Bit mask of OUT1 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Min (0x0UL)   /*!< Min enumerator value of OUT1 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Max (0x1UL)   /*!< Max enumerator value of OUT1 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos (2UL)     /*!< Position of OUT2 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos) /*!< Bit mask of OUT2 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Min (0x0UL)   /*!< Min enumerator value of OUT2 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Max (0x1UL)   /*!< Max enumerator value of OUT2 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos (3UL)     /*!< Position of OUT3 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos) /*!< Bit mask of OUT3 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Min (0x0UL)   /*!< Min enumerator value of OUT3 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Max (0x1UL)   /*!< Max enumerator value of OUT3 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos (4UL)     /*!< Position of OUT4 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos) /*!< Bit mask of OUT4 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Min (0x0UL)   /*!< Min enumerator value of OUT4 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Max (0x1UL)   /*!< Max enumerator value of OUT4 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos (5UL)     /*!< Position of OUT5 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos) /*!< Bit mask of OUT5 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Min (0x0UL)   /*!< Min enumerator value of OUT5 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Max (0x1UL)   /*!< Max enumerator value of OUT5 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos (6UL)     /*!< Position of OUT6 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos) /*!< Bit mask of OUT6 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Min (0x0UL)   /*!< Min enumerator value of OUT6 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Max (0x1UL)   /*!< Max enumerator value of OUT6 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos (7UL)     /*!< Position of OUT7 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos) /*!< Bit mask of OUT7 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Min (0x0UL)   /*!< Min enumerator value of OUT7 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Max (0x1UL)   /*!< Max enumerator value of OUT7 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos (8UL)     /*!< Position of OUT8 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos) /*!< Bit mask of OUT8 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Min (0x0UL)   /*!< Min enumerator value of OUT8 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Max (0x1UL)   /*!< Max enumerator value of OUT8 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos (9UL)     /*!< Position of OUT9 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos) /*!< Bit mask of OUT9 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Min (0x0UL)   /*!< Min enumerator value of OUT9 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Max (0x1UL)   /*!< Max enumerator value of OUT9 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos (10UL)   /*!< Position of OUT10 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos) /*!< Bit mask of OUT10 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Min (0x0UL)  /*!< Min enumerator value of OUT10 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Max (0x1UL)  /*!< Max enumerator value of OUT10 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUT11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos (11UL)   /*!< Position of OUT11 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos) /*!< Bit mask of OUT11 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Min (0x0UL)  /*!< Min enumerator value of OUT11 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Max (0x1UL)  /*!< Max enumerator value of OUT11 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUT12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos (12UL)   /*!< Position of OUT12 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos) /*!< Bit mask of OUT12 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Min (0x0UL)  /*!< Min enumerator value of OUT12 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Max (0x1UL)  /*!< Max enumerator value of OUT12 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUT13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos (13UL)   /*!< Position of OUT13 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos) /*!< Bit mask of OUT13 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Min (0x0UL)  /*!< Min enumerator value of OUT13 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Max (0x1UL)  /*!< Max enumerator value of OUT13 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUT14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos (14UL)   /*!< Position of OUT14 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos) /*!< Bit mask of OUT14 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Min (0x0UL)  /*!< Min enumerator value of OUT14 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Max (0x1UL)  /*!< Max enumerator value of OUT14 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUT15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos (15UL)   /*!< Position of OUT15 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos) /*!< Bit mask of OUT15 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Min (0x0UL)  /*!< Min enumerator value of OUT15 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Max (0x1UL)  /*!< Max enumerator value of OUT15 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* DIR0 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos (16UL)    /*!< Position of DIR0 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos) /*!< Bit mask of DIR0 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Min (0x0UL)   /*!< Min enumerator value of DIR0 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Max (0x1UL)   /*!< Max enumerator value of DIR0 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR0_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR1 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos (17UL)    /*!< Position of DIR1 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos) /*!< Bit mask of DIR1 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Min (0x0UL)   /*!< Min enumerator value of DIR1 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Max (0x1UL)   /*!< Max enumerator value of DIR1 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR1_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR2 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos (18UL)    /*!< Position of DIR2 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos) /*!< Bit mask of DIR2 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Min (0x0UL)   /*!< Min enumerator value of DIR2 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Max (0x1UL)   /*!< Max enumerator value of DIR2 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR2_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR3 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos (19UL)    /*!< Position of DIR3 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos) /*!< Bit mask of DIR3 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Min (0x0UL)   /*!< Min enumerator value of DIR3 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Max (0x1UL)   /*!< Max enumerator value of DIR3 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR3_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR4 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos (20UL)    /*!< Position of DIR4 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos) /*!< Bit mask of DIR4 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Min (0x0UL)   /*!< Min enumerator value of DIR4 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Max (0x1UL)   /*!< Max enumerator value of DIR4 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR4_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR5 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos (21UL)    /*!< Position of DIR5 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos) /*!< Bit mask of DIR5 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Min (0x0UL)   /*!< Min enumerator value of DIR5 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Max (0x1UL)   /*!< Max enumerator value of DIR5 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR5_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR6 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos (22UL)    /*!< Position of DIR6 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos) /*!< Bit mask of DIR6 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Min (0x0UL)   /*!< Min enumerator value of DIR6 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Max (0x1UL)   /*!< Max enumerator value of DIR6 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR6_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR7 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos (23UL)    /*!< Position of DIR7 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos) /*!< Bit mask of DIR7 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Min (0x0UL)   /*!< Min enumerator value of DIR7 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Max (0x1UL)   /*!< Max enumerator value of DIR7 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR7_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR8 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos (24UL)    /*!< Position of DIR8 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos) /*!< Bit mask of DIR8 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Min (0x0UL)   /*!< Min enumerator value of DIR8 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Max (0x1UL)   /*!< Max enumerator value of DIR8 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR8_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR9 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos (25UL)    /*!< Position of DIR9 field.                                              */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos) /*!< Bit mask of DIR9 field.            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Min (0x0UL)   /*!< Min enumerator value of DIR9 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Max (0x1UL)   /*!< Max enumerator value of DIR9 field.                                  */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR9_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* DIR10 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos (26UL)   /*!< Position of DIR10 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos) /*!< Bit mask of DIR10 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Min (0x0UL)  /*!< Min enumerator value of DIR10 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Max (0x1UL)  /*!< Max enumerator value of DIR10 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR10_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* DIR11 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos (27UL)   /*!< Position of DIR11 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos) /*!< Bit mask of DIR11 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Min (0x0UL)  /*!< Min enumerator value of DIR11 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Max (0x1UL)  /*!< Max enumerator value of DIR11 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR11_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* DIR12 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos (28UL)   /*!< Position of DIR12 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos) /*!< Bit mask of DIR12 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Min (0x0UL)  /*!< Min enumerator value of DIR12 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Max (0x1UL)  /*!< Max enumerator value of DIR12 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR12_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* DIR13 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos (29UL)   /*!< Position of DIR13 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos) /*!< Bit mask of DIR13 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Min (0x0UL)  /*!< Min enumerator value of DIR13 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Max (0x1UL)  /*!< Max enumerator value of DIR13 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR13_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* DIR14 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos (30UL)   /*!< Position of DIR14 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos) /*!< Bit mask of DIR14 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Min (0x0UL)  /*!< Min enumerator value of DIR14 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Max (0x1UL)  /*!< Max enumerator value of DIR14 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR14_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* DIR15 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos (31UL)   /*!< Position of DIR15 field.                                             */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos) /*!< Bit mask of DIR15 field.         */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Min (0x0UL)  /*!< Min enumerator value of DIR15 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Max (0x1UL)  /*!< Max enumerator value of DIR15 field.                                 */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_DIROUTTGL_DIR15_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */


/**
  * @brief DIROUTBTGL [VPRCSR_NORDIC_DIROUTBTGL] DIROUTB Toggle
  */
  #define VPRCSR_NORDIC_DIROUTBTGL (0x00000BD5ul)
  #define VPRCSR_NORDIC_DIROUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBTGL register.                          */

/* OUTB0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos (0UL)   /*!< Position of OUTB0 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Min (0x0UL) /*!< Min enumerator value of OUTB0 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Max (0x1UL) /*!< Max enumerator value of OUTB0 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos (1UL)   /*!< Position of OUTB1 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Min (0x0UL) /*!< Min enumerator value of OUTB1 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Max (0x1UL) /*!< Max enumerator value of OUTB1 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos (2UL)   /*!< Position of OUTB2 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Min (0x0UL) /*!< Min enumerator value of OUTB2 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Max (0x1UL) /*!< Max enumerator value of OUTB2 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos (3UL)   /*!< Position of OUTB3 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Min (0x0UL) /*!< Min enumerator value of OUTB3 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Max (0x1UL) /*!< Max enumerator value of OUTB3 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos (4UL)   /*!< Position of OUTB4 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Min (0x0UL) /*!< Min enumerator value of OUTB4 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Max (0x1UL) /*!< Max enumerator value of OUTB4 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos (5UL)   /*!< Position of OUTB5 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Min (0x0UL) /*!< Min enumerator value of OUTB5 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Max (0x1UL) /*!< Max enumerator value of OUTB5 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos (6UL)   /*!< Position of OUTB6 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Min (0x0UL) /*!< Min enumerator value of OUTB6 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Max (0x1UL) /*!< Max enumerator value of OUTB6 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos (7UL)   /*!< Position of OUTB7 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Min (0x0UL) /*!< Min enumerator value of OUTB7 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Max (0x1UL) /*!< Max enumerator value of OUTB7 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos (8UL)   /*!< Position of OUTB8 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Min (0x0UL) /*!< Min enumerator value of OUTB8 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Max (0x1UL) /*!< Max enumerator value of OUTB8 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos (9UL)   /*!< Position of OUTB9 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Min (0x0UL) /*!< Min enumerator value of OUTB9 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Max (0x1UL) /*!< Max enumerator value of OUTB9 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* OUTB10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos (10UL) /*!< Position of OUTB10 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Min (0x0UL) /*!< Min enumerator value of OUTB10 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Max (0x1UL) /*!< Max enumerator value of OUTB10 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* OUTB11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos (11UL) /*!< Position of OUTB11 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Min (0x0UL) /*!< Min enumerator value of OUTB11 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Max (0x1UL) /*!< Max enumerator value of OUTB11 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* OUTB12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos (12UL) /*!< Position of OUTB12 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Min (0x0UL) /*!< Min enumerator value of OUTB12 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Max (0x1UL) /*!< Max enumerator value of OUTB12 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* OUTB13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos (13UL) /*!< Position of OUTB13 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Min (0x0UL) /*!< Min enumerator value of OUTB13 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Max (0x1UL) /*!< Max enumerator value of OUTB13 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* OUTB14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos (14UL) /*!< Position of OUTB14 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Min (0x0UL) /*!< Min enumerator value of OUTB14 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Max (0x1UL) /*!< Max enumerator value of OUTB14 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* OUTB15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos (15UL) /*!< Position of OUTB15 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Min (0x0UL) /*!< Min enumerator value of OUTB15 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Max (0x1UL) /*!< Max enumerator value of OUTB15 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* DIRB0 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos (16UL)  /*!< Position of DIRB0 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos) /*!< Bit mask of DIRB0 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Min (0x0UL) /*!< Min enumerator value of DIRB0 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Max (0x1UL) /*!< Max enumerator value of DIRB0 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB1 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos (17UL)  /*!< Position of DIRB1 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos) /*!< Bit mask of DIRB1 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Min (0x0UL) /*!< Min enumerator value of DIRB1 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Max (0x1UL) /*!< Max enumerator value of DIRB1 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB2 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos (18UL)  /*!< Position of DIRB2 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos) /*!< Bit mask of DIRB2 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Min (0x0UL) /*!< Min enumerator value of DIRB2 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Max (0x1UL) /*!< Max enumerator value of DIRB2 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB3 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos (19UL)  /*!< Position of DIRB3 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos) /*!< Bit mask of DIRB3 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Min (0x0UL) /*!< Min enumerator value of DIRB3 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Max (0x1UL) /*!< Max enumerator value of DIRB3 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB4 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos (20UL)  /*!< Position of DIRB4 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos) /*!< Bit mask of DIRB4 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Min (0x0UL) /*!< Min enumerator value of DIRB4 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Max (0x1UL) /*!< Max enumerator value of DIRB4 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB5 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos (21UL)  /*!< Position of DIRB5 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos) /*!< Bit mask of DIRB5 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Min (0x0UL) /*!< Min enumerator value of DIRB5 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Max (0x1UL) /*!< Max enumerator value of DIRB5 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB6 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos (22UL)  /*!< Position of DIRB6 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos) /*!< Bit mask of DIRB6 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Min (0x0UL) /*!< Min enumerator value of DIRB6 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Max (0x1UL) /*!< Max enumerator value of DIRB6 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB7 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos (23UL)  /*!< Position of DIRB7 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos) /*!< Bit mask of DIRB7 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Min (0x0UL) /*!< Min enumerator value of DIRB7 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Max (0x1UL) /*!< Max enumerator value of DIRB7 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB8 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos (24UL)  /*!< Position of DIRB8 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos) /*!< Bit mask of DIRB8 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Min (0x0UL) /*!< Min enumerator value of DIRB8 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Max (0x1UL) /*!< Max enumerator value of DIRB8 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB9 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos (25UL)  /*!< Position of DIRB9 field.                                             */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos) /*!< Bit mask of DIRB9 field.       */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Min (0x0UL) /*!< Min enumerator value of DIRB9 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Max (0x1UL) /*!< Max enumerator value of DIRB9 field.                                 */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */

/* DIRB10 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos (26UL) /*!< Position of DIRB10 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos) /*!< Bit mask of DIRB10 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Min (0x0UL) /*!< Min enumerator value of DIRB10 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Max (0x1UL) /*!< Max enumerator value of DIRB10 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* DIRB11 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos (27UL) /*!< Position of DIRB11 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos) /*!< Bit mask of DIRB11 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Min (0x0UL) /*!< Min enumerator value of DIRB11 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Max (0x1UL) /*!< Max enumerator value of DIRB11 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* DIRB12 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos (28UL) /*!< Position of DIRB12 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos) /*!< Bit mask of DIRB12 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Min (0x0UL) /*!< Min enumerator value of DIRB12 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Max (0x1UL) /*!< Max enumerator value of DIRB12 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* DIRB13 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos (29UL) /*!< Position of DIRB13 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos) /*!< Bit mask of DIRB13 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Min (0x0UL) /*!< Min enumerator value of DIRB13 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Max (0x1UL) /*!< Max enumerator value of DIRB13 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* DIRB14 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos (30UL) /*!< Position of DIRB14 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos) /*!< Bit mask of DIRB14 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Min (0x0UL) /*!< Min enumerator value of DIRB14 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Max (0x1UL) /*!< Max enumerator value of DIRB14 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */

/* DIRB15 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos (31UL) /*!< Position of DIRB15 field.                                            */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos) /*!< Bit mask of DIRB15 field.    */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Min (0x0UL) /*!< Min enumerator value of DIRB15 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Max (0x1UL) /*!< Max enumerator value of DIRB15 field.                               */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
  #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */


/**
  * @brief OUTBS [VPRCSR_NORDIC_OUTBS] Buffered GPIO Output Dirty Status
  */
  #define VPRCSR_NORDIC_OUTBS (0x00000BD8ul)
  #define VPRCSR_NORDIC_OUTBS_ResetValue (0x00000000UL) /*!< Reset value of OUTBS register.                                    */

/* OUTB @Bits 0..31 : Write to OUTB (if not dirty) */
  #define VPRCSR_NORDIC_OUTBS_OUTB_Pos (0UL)         /*!< Position of OUTB field.                                              */
  #define VPRCSR_NORDIC_OUTBS_OUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBS_OUTB_Pos) /*!< Bit mask of OUTB field.             */

/* DIRTYBIT @Bit 0 : Read Buffer Dirty status */
  #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos (0UL)     /*!< Position of DIRTYBIT field.                                          */
  #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.        */
  #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Min (0x0UL)   /*!< Min enumerator value of DIRTYBIT field.                              */
  #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Max (0x1UL)   /*!< Max enumerator value of DIRTYBIT field.                              */
  #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                      */
  #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                      */


/**
  * @brief DIRBS [VPRCSR_NORDIC_DIRBS] Buffered GPIO pin Direction Dirty Status
  */
  #define VPRCSR_NORDIC_DIRBS (0x00000BD9ul)
  #define VPRCSR_NORDIC_DIRBS_ResetValue (0x00000000UL) /*!< Reset value of DIRBS register.                                    */

/* DIRB @Bits 0..31 : Write to DIRB (if not dirty) */
  #define VPRCSR_NORDIC_DIRBS_DIRB_Pos (0UL)         /*!< Position of DIRB field.                                              */
  #define VPRCSR_NORDIC_DIRBS_DIRB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIRBS_DIRB_Pos) /*!< Bit mask of DIRB field.             */

/* DIRTYBIT @Bit 0 : Read Buffer Dirty status */
  #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos (0UL)     /*!< Position of DIRTYBIT field.                                          */
  #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.        */
  #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Min (0x0UL)   /*!< Min enumerator value of DIRTYBIT field.                              */
  #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Max (0x1UL)   /*!< Max enumerator value of DIRTYBIT field.                              */
  #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                      */
  #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                      */


/**
  * @brief DIROUTBS [VPRCSR_NORDIC_DIROUTBS] Combination of DIRB and OUTB Dirty Status
  */
  #define VPRCSR_NORDIC_DIROUTBS (0x00000BDAul)
  #define VPRCSR_NORDIC_DIROUTBS_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBS register.                              */

/* DIROUTB @Bits 0..31 : Write to DIROUTB (if not dirty) */
  #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos (0UL)   /*!< Position of DIROUTB field.                                           */
  #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos) /*!< Bit mask of DIROUTB
                                                                            field.*/

/* DIRTYBIT @Bit 0 : Read Combination (OR) of DIRB and OUTB Dirty status */
  #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos (0UL)  /*!< Position of DIRTYBIT field.                                          */
  #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.  */
  #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field.                             */
  #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field.                             */
  #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                   */
  #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                   */


/**
  * @brief OUTBD [VPRCSR_NORDIC_OUTBD] Concatenation of Buffered GPIO Output and GPIO Output
  */
  #define VPRCSR_NORDIC_OUTBD (0x00000BE0ul)
  #define VPRCSR_NORDIC_OUTBD_ResetValue (0x00000000UL) /*!< Reset value of OUTBD register.                                    */

/* OUT @Bits 0..15 : GPIO Output */
  #define VPRCSR_NORDIC_OUTBD_OUT_Pos (0UL)          /*!< Position of OUT field.                                               */
  #define VPRCSR_NORDIC_OUTBD_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUT_Pos) /*!< Bit mask of OUT field.                    */

/* OUTB @Bits 16..31 : Buffered GPIO Output */
  #define VPRCSR_NORDIC_OUTBD_OUTB_Pos (16UL)        /*!< Position of OUTB field.                                              */
  #define VPRCSR_NORDIC_OUTBD_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUTB_Pos) /*!< Bit mask of OUTB field.                 */


/**
  * @brief OUTBDTGL [VPRCSR_NORDIC_OUTBDTGL] OUTBD Toggle
  */
  #define VPRCSR_NORDIC_OUTBDTGL (0x00000BE1ul)
  #define VPRCSR_NORDIC_OUTBDTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBDTGL register.                              */

/* OUT0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos (0UL)      /*!< Position of OUT0 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos) /*!< Bit mask of OUT0 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Min (0x0UL)    /*!< Min enumerator value of OUT0 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Max (0x1UL)    /*!< Max enumerator value of OUT0 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos (1UL)      /*!< Position of OUT1 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos) /*!< Bit mask of OUT1 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Min (0x0UL)    /*!< Min enumerator value of OUT1 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Max (0x1UL)    /*!< Max enumerator value of OUT1 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos (2UL)      /*!< Position of OUT2 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos) /*!< Bit mask of OUT2 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Min (0x0UL)    /*!< Min enumerator value of OUT2 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Max (0x1UL)    /*!< Max enumerator value of OUT2 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos (3UL)      /*!< Position of OUT3 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos) /*!< Bit mask of OUT3 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Min (0x0UL)    /*!< Min enumerator value of OUT3 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Max (0x1UL)    /*!< Max enumerator value of OUT3 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos (4UL)      /*!< Position of OUT4 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos) /*!< Bit mask of OUT4 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Min (0x0UL)    /*!< Min enumerator value of OUT4 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Max (0x1UL)    /*!< Max enumerator value of OUT4 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos (5UL)      /*!< Position of OUT5 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos) /*!< Bit mask of OUT5 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Min (0x0UL)    /*!< Min enumerator value of OUT5 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Max (0x1UL)    /*!< Max enumerator value of OUT5 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos (6UL)      /*!< Position of OUT6 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos) /*!< Bit mask of OUT6 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Min (0x0UL)    /*!< Min enumerator value of OUT6 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Max (0x1UL)    /*!< Max enumerator value of OUT6 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos (7UL)      /*!< Position of OUT7 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos) /*!< Bit mask of OUT7 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Min (0x0UL)    /*!< Min enumerator value of OUT7 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Max (0x1UL)    /*!< Max enumerator value of OUT7 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos (8UL)      /*!< Position of OUT8 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos) /*!< Bit mask of OUT8 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Min (0x0UL)    /*!< Min enumerator value of OUT8 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Max (0x1UL)    /*!< Max enumerator value of OUT8 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos (9UL)      /*!< Position of OUT9 field.                                              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos) /*!< Bit mask of OUT9 field.              */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Min (0x0UL)    /*!< Min enumerator value of OUT9 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Max (0x1UL)    /*!< Max enumerator value of OUT9 field.                                  */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */

/* OUT10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos (10UL)    /*!< Position of OUT10 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos) /*!< Bit mask of OUT10 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Min (0x0UL)   /*!< Min enumerator value of OUT10 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Max (0x1UL)   /*!< Max enumerator value of OUT10 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos (11UL)    /*!< Position of OUT11 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos) /*!< Bit mask of OUT11 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Min (0x0UL)   /*!< Min enumerator value of OUT11 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Max (0x1UL)   /*!< Max enumerator value of OUT11 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos (12UL)    /*!< Position of OUT12 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos) /*!< Bit mask of OUT12 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Min (0x0UL)   /*!< Min enumerator value of OUT12 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Max (0x1UL)   /*!< Max enumerator value of OUT12 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos (13UL)    /*!< Position of OUT13 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos) /*!< Bit mask of OUT13 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Min (0x0UL)   /*!< Min enumerator value of OUT13 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Max (0x1UL)   /*!< Max enumerator value of OUT13 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos (14UL)    /*!< Position of OUT14 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos) /*!< Bit mask of OUT14 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Min (0x0UL)   /*!< Min enumerator value of OUT14 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Max (0x1UL)   /*!< Max enumerator value of OUT14 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUT15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos (15UL)    /*!< Position of OUT15 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos) /*!< Bit mask of OUT15 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Min (0x0UL)   /*!< Min enumerator value of OUT15 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Max (0x1UL)   /*!< Max enumerator value of OUT15 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB0 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos (16UL)    /*!< Position of OUTB0 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Min (0x0UL)   /*!< Min enumerator value of OUTB0 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Max (0x1UL)   /*!< Max enumerator value of OUTB0 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB1 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos (17UL)    /*!< Position of OUTB1 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Min (0x0UL)   /*!< Min enumerator value of OUTB1 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Max (0x1UL)   /*!< Max enumerator value of OUTB1 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB2 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos (18UL)    /*!< Position of OUTB2 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Min (0x0UL)   /*!< Min enumerator value of OUTB2 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Max (0x1UL)   /*!< Max enumerator value of OUTB2 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB3 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos (19UL)    /*!< Position of OUTB3 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Min (0x0UL)   /*!< Min enumerator value of OUTB3 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Max (0x1UL)   /*!< Max enumerator value of OUTB3 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB4 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos (20UL)    /*!< Position of OUTB4 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Min (0x0UL)   /*!< Min enumerator value of OUTB4 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Max (0x1UL)   /*!< Max enumerator value of OUTB4 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB5 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos (21UL)    /*!< Position of OUTB5 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Min (0x0UL)   /*!< Min enumerator value of OUTB5 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Max (0x1UL)   /*!< Max enumerator value of OUTB5 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB6 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos (22UL)    /*!< Position of OUTB6 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Min (0x0UL)   /*!< Min enumerator value of OUTB6 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Max (0x1UL)   /*!< Max enumerator value of OUTB6 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB7 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos (23UL)    /*!< Position of OUTB7 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Min (0x0UL)   /*!< Min enumerator value of OUTB7 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Max (0x1UL)   /*!< Max enumerator value of OUTB7 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB8 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos (24UL)    /*!< Position of OUTB8 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Min (0x0UL)   /*!< Min enumerator value of OUTB8 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Max (0x1UL)   /*!< Max enumerator value of OUTB8 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB9 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos (25UL)    /*!< Position of OUTB9 field.                                             */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field.           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Min (0x0UL)   /*!< Min enumerator value of OUTB9 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Max (0x1UL)   /*!< Max enumerator value of OUTB9 field.                                 */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */

/* OUTB10 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos (26UL)   /*!< Position of OUTB10 field.                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field.        */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Min (0x0UL)  /*!< Min enumerator value of OUTB10 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Max (0x1UL)  /*!< Max enumerator value of OUTB10 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUTB11 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos (27UL)   /*!< Position of OUTB11 field.                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field.        */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Min (0x0UL)  /*!< Min enumerator value of OUTB11 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Max (0x1UL)  /*!< Max enumerator value of OUTB11 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUTB12 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos (28UL)   /*!< Position of OUTB12 field.                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field.        */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Min (0x0UL)  /*!< Min enumerator value of OUTB12 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Max (0x1UL)  /*!< Max enumerator value of OUTB12 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUTB13 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos (29UL)   /*!< Position of OUTB13 field.                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field.        */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Min (0x0UL)  /*!< Min enumerator value of OUTB13 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Max (0x1UL)  /*!< Max enumerator value of OUTB13 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUTB14 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos (30UL)   /*!< Position of OUTB14 field.                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field.        */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Min (0x0UL)  /*!< Min enumerator value of OUTB14 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Max (0x1UL)  /*!< Max enumerator value of OUTB14 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */

/* OUTB15 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos (31UL)   /*!< Position of OUTB15 field.                                            */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field.        */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Min (0x0UL)  /*!< Min enumerator value of OUTB15 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Max (0x1UL)  /*!< Max enumerator value of OUTB15 field.                                */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
  #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */


/**
  * @brief OUTBDS [VPRCSR_NORDIC_OUTBDS] OUTBD Dirty Status
  */
  #define VPRCSR_NORDIC_OUTBDS (0x00000BE2ul)
  #define VPRCSR_NORDIC_OUTBDS_ResetValue (0x00000000UL) /*!< Reset value of OUTBDS register.                                  */

/* OUTBD @Bits 0..31 : Write to OUTBD register (if not dirty) */
  #define VPRCSR_NORDIC_OUTBDS_OUTBD_Pos (0UL)       /*!< Position of OUTBD field.                                             */
  #define VPRCSR_NORDIC_OUTBDS_OUTBD_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBDS_OUTBD_Pos) /*!< Bit mask of OUTBD field.        */

/* DIRTYBIT @Bit 0 : Read OUTB and OUT parallel write Dirty status */
  #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos (0UL)    /*!< Position of DIRTYBIT field.                                          */
  #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.      */
  #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Min (0x0UL)  /*!< Min enumerator value of DIRTYBIT field.                              */
  #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Max (0x1UL)  /*!< Max enumerator value of DIRTYBIT field.                              */
  #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                     */
  #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                     */


/**
  * @brief OUTMODE [VPRCSR_NORDIC_OUTMODE] Serial output mode
  */
  #define VPRCSR_NORDIC_OUTMODE (0x00000BE3ul)
  #define VPRCSR_NORDIC_OUTMODE_ResetValue (0x00000000UL) /*!< Reset value of OUTMODE register.                                */

/* MODE @Bits 0..2 : Mode */
  #define VPRCSR_NORDIC_OUTMODE_MODE_Pos (0UL)       /*!< Position of MODE field.                                              */
  #define VPRCSR_NORDIC_OUTMODE_MODE_Msk (0x7UL << VPRCSR_NORDIC_OUTMODE_MODE_Pos) /*!< Bit mask of MODE field.                */
  #define VPRCSR_NORDIC_OUTMODE_MODE_Min (0x0UL)     /*!< Min enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_OUTMODE_MODE_Max (0x4UL)     /*!< Max enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_OUTMODE_MODE_NoShifting (0x0UL) /*!< No shifting                                                       */
  #define VPRCSR_NORDIC_OUTMODE_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering                                         */
  #define VPRCSR_NORDIC_OUTMODE_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock line        */

/* SHIFTMODE @Bit 0 : Shift mode */
  #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos (0UL)  /*!< Position of SHIFTMODE field.                                         */
  #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Msk (0x1UL << VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos) /*!< Bit mask of SHIFTMODE field. */
  #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Min (0x0UL) /*!< Min enumerator value of SHIFTMODE field.                            */
  #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Max (0x1UL) /*!< Max enumerator value of SHIFTMODE field.                            */
  #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Disabled (0x0UL) /*!< Shift mode is disabled                                         */
  #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Enabled (0x1UL) /*!< Shift mode is enabled                                           */

/* FRAMEWIDTH @Bits 16..20 : Output frame width MODE=0x1: BITS=2^FRAMEWIDTH. Legal FRAMEWIDTH values: 0, 1, 2, 3, 4 MODE=0x2:
                             BITS=FRAMEWIDTH. Legal values: 1, 2, 3, 4, 5, 6, 7, 8, 16 (9-15 are not legal) MODE=0x4:
                             BITS=FRAMEWIDTH. Legal values: 1, 2, 3, 4, 5, 6, 7, 8 */

  #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Pos (16UL) /*!< Position of FRAMEWIDTH field.                                       */
  #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Pos) /*!< Bit mask of FRAMEWIDTH
                                                                            field.*/
  #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field.                                    */
  #define VPRCSR_NORDIC_OUTMODE_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field.                                     */

/* SHIFSIZE @Bits 16..19 : Shift size. Only applies if Shift mode is enabled */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos (16UL)  /*!< Position of SHIFSIZE field.                                          */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Msk (0xFUL << VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos) /*!< Bit mask of SHIFSIZE field.    */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Min (0x0UL) /*!< Min enumerator value of SHIFSIZE field.                              */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Max (0x4UL) /*!< Max enumerator value of SHIFSIZE field.                              */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT1 (0x0UL) /*!< Shift OUT by 1 bit                                                */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT2 (0x1UL) /*!< Shift OUT by 2 bits                                               */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT4 (0x2UL) /*!< Shift OUT by 4 bits                                               */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT8 (0x3UL) /*!< Shift OUT by 8 bits                                               */
  #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT16 (0x4UL) /*!< Shift OUT by 16 bits                                             */


/**
  * @brief OUTMODEB [VPRCSR_NORDIC_OUTMODEB] Buffered OUTMODE register
  */
  #define VPRCSR_NORDIC_OUTMODEB (0x00000BE4ul)
  #define VPRCSR_NORDIC_OUTMODEB_ResetValue (0x00000000UL) /*!< Reset value of OUTMODEB register.                              */

/* MODE @Bits 0..2 : Mode */
  #define VPRCSR_NORDIC_OUTMODEB_MODE_Pos (0UL)      /*!< Position of MODE field.                                              */
  #define VPRCSR_NORDIC_OUTMODEB_MODE_Msk (0x7UL << VPRCSR_NORDIC_OUTMODEB_MODE_Pos) /*!< Bit mask of MODE field.              */
  #define VPRCSR_NORDIC_OUTMODEB_MODE_Min (0x0UL)    /*!< Min enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_OUTMODEB_MODE_Max (0x4UL)    /*!< Max enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_OUTMODEB_MODE_NoShifting (0x0UL) /*!< No shifting                                                      */
  #define VPRCSR_NORDIC_OUTMODEB_MODE_OutBBuf (0x2UL) /*!< Only OUTB used for buffering                                        */
  #define VPRCSR_NORDIC_OUTMODEB_MODE_OutBBufToggleClk (0x4UL) /*!< Only OUTB used for buffering, auto-toggle clock line       */

/* FRAMEWIDTH @Bits 16..20 : Frame width in bits */
  #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Pos (16UL) /*!< Position of FRAMEWIDTH field.                                      */
  #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Msk (0x1FUL << VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Pos) /*!< Bit mask of FRAMEWIDTH
                                                                            field.*/
  #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Min (0x00UL) /*!< Min value of FRAMEWIDTH field.                                   */
  #define VPRCSR_NORDIC_OUTMODEB_FRAMEWIDTH_Max (0x10UL) /*!< Max size of FRAMEWIDTH field.                                    */


/**
  * @brief INMODEB [VPRCSR_NORDIC_INMODEB] Buffered INMODE register
  */
  #define VPRCSR_NORDIC_INMODEB (0x00000BE5ul)
  #define VPRCSR_NORDIC_INMODEB_ResetValue (0x00000000UL) /*!< Reset value of INMODEB register.                                */

/* MODE @Bits 0..1 : Input Mode */
  #define VPRCSR_NORDIC_INMODEB_MODE_Pos (0UL)       /*!< Position of MODE field.                                              */
  #define VPRCSR_NORDIC_INMODEB_MODE_Msk (0x3UL << VPRCSR_NORDIC_INMODEB_MODE_Pos) /*!< Bit mask of MODE field.                */
  #define VPRCSR_NORDIC_INMODEB_MODE_Min (0x0UL)     /*!< Min enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_INMODEB_MODE_Max (0x2UL)     /*!< Max enumerator value of MODE field.                                  */
  #define VPRCSR_NORDIC_INMODEB_MODE_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
  #define VPRCSR_NORDIC_INMODEB_MODE_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
  #define VPRCSR_NORDIC_INMODEB_MODE_SHIFT (0x2UL)   /*!< Sampling and shifting on Counter1 event                              */


/**
  * @brief INB [VPRCSR_NORDIC_INB] Buffered GPIO input
  */
  #define VPRCSR_NORDIC_INB (0x00000BE6ul)
  #define VPRCSR_NORDIC_INB_ResetValue (0x00000000UL) /*!< Reset value of INB register.                                        */

/* PIN0 @Bit 0 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN0_Pos (0UL)           /*!< Position of PIN0 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN0_Pos) /*!< Bit mask of PIN0 field.                        */
  #define VPRCSR_NORDIC_INB_PIN0_Min (0x0UL)         /*!< Min enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN0_Max (0x1UL)         /*!< Max enumerator value of PIN0 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN0_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN0_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN1 @Bit 1 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN1_Pos (1UL)           /*!< Position of PIN1 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN1_Pos) /*!< Bit mask of PIN1 field.                        */
  #define VPRCSR_NORDIC_INB_PIN1_Min (0x0UL)         /*!< Min enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN1_Max (0x1UL)         /*!< Max enumerator value of PIN1 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN1_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN1_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN2 @Bit 2 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN2_Pos (2UL)           /*!< Position of PIN2 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN2_Pos) /*!< Bit mask of PIN2 field.                        */
  #define VPRCSR_NORDIC_INB_PIN2_Min (0x0UL)         /*!< Min enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN2_Max (0x1UL)         /*!< Max enumerator value of PIN2 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN2_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN2_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN3 @Bit 3 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN3_Pos (3UL)           /*!< Position of PIN3 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN3_Pos) /*!< Bit mask of PIN3 field.                        */
  #define VPRCSR_NORDIC_INB_PIN3_Min (0x0UL)         /*!< Min enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN3_Max (0x1UL)         /*!< Max enumerator value of PIN3 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN3_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN3_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN4 @Bit 4 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN4_Pos (4UL)           /*!< Position of PIN4 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN4_Pos) /*!< Bit mask of PIN4 field.                        */
  #define VPRCSR_NORDIC_INB_PIN4_Min (0x0UL)         /*!< Min enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN4_Max (0x1UL)         /*!< Max enumerator value of PIN4 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN4_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN4_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN5 @Bit 5 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN5_Pos (5UL)           /*!< Position of PIN5 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN5_Pos) /*!< Bit mask of PIN5 field.                        */
  #define VPRCSR_NORDIC_INB_PIN5_Min (0x0UL)         /*!< Min enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN5_Max (0x1UL)         /*!< Max enumerator value of PIN5 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN5_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN5_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN6 @Bit 6 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN6_Pos (6UL)           /*!< Position of PIN6 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN6_Pos) /*!< Bit mask of PIN6 field.                        */
  #define VPRCSR_NORDIC_INB_PIN6_Min (0x0UL)         /*!< Min enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN6_Max (0x1UL)         /*!< Max enumerator value of PIN6 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN6_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN6_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN7 @Bit 7 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN7_Pos (7UL)           /*!< Position of PIN7 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN7_Pos) /*!< Bit mask of PIN7 field.                        */
  #define VPRCSR_NORDIC_INB_PIN7_Min (0x0UL)         /*!< Min enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN7_Max (0x1UL)         /*!< Max enumerator value of PIN7 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN7_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN7_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN8 @Bit 8 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN8_Pos (8UL)           /*!< Position of PIN8 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN8_Pos) /*!< Bit mask of PIN8 field.                        */
  #define VPRCSR_NORDIC_INB_PIN8_Min (0x0UL)         /*!< Min enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN8_Max (0x1UL)         /*!< Max enumerator value of PIN8 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN8_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN8_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN9 @Bit 9 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN9_Pos (9UL)           /*!< Position of PIN9 field.                                              */
  #define VPRCSR_NORDIC_INB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN9_Pos) /*!< Bit mask of PIN9 field.                        */
  #define VPRCSR_NORDIC_INB_PIN9_Min (0x0UL)         /*!< Min enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN9_Max (0x1UL)         /*!< Max enumerator value of PIN9 field.                                  */
  #define VPRCSR_NORDIC_INB_PIN9_LOW (0x0UL)         /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN9_HIGH (0x1UL)        /*!< Pin is High                                                          */

/* PIN10 @Bit 10 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN10_Pos (10UL)         /*!< Position of PIN10 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN10_Pos) /*!< Bit mask of PIN10 field.                     */
  #define VPRCSR_NORDIC_INB_PIN10_Min (0x0UL)        /*!< Min enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN10_Max (0x1UL)        /*!< Max enumerator value of PIN10 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN10_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN10_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN11 @Bit 11 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN11_Pos (11UL)         /*!< Position of PIN11 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN11_Pos) /*!< Bit mask of PIN11 field.                     */
  #define VPRCSR_NORDIC_INB_PIN11_Min (0x0UL)        /*!< Min enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN11_Max (0x1UL)        /*!< Max enumerator value of PIN11 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN11_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN11_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN12 @Bit 12 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN12_Pos (12UL)         /*!< Position of PIN12 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN12_Pos) /*!< Bit mask of PIN12 field.                     */
  #define VPRCSR_NORDIC_INB_PIN12_Min (0x0UL)        /*!< Min enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN12_Max (0x1UL)        /*!< Max enumerator value of PIN12 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN12_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN12_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN13 @Bit 13 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN13_Pos (13UL)         /*!< Position of PIN13 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN13_Pos) /*!< Bit mask of PIN13 field.                     */
  #define VPRCSR_NORDIC_INB_PIN13_Min (0x0UL)        /*!< Min enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN13_Max (0x1UL)        /*!< Max enumerator value of PIN13 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN13_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN13_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN14 @Bit 14 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN14_Pos (14UL)         /*!< Position of PIN14 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN14_Pos) /*!< Bit mask of PIN14 field.                     */
  #define VPRCSR_NORDIC_INB_PIN14_Min (0x0UL)        /*!< Min enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN14_Max (0x1UL)        /*!< Max enumerator value of PIN14 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN14_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN14_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN15 @Bit 15 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN15_Pos (15UL)         /*!< Position of PIN15 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN15_Pos) /*!< Bit mask of PIN15 field.                     */
  #define VPRCSR_NORDIC_INB_PIN15_Min (0x0UL)        /*!< Min enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN15_Max (0x1UL)        /*!< Max enumerator value of PIN15 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN15_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN15_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN16 @Bit 16 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN16_Pos (16UL)         /*!< Position of PIN16 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN16_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN16_Pos) /*!< Bit mask of PIN16 field.                     */
  #define VPRCSR_NORDIC_INB_PIN16_Min (0x0UL)        /*!< Min enumerator value of PIN16 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN16_Max (0x1UL)        /*!< Max enumerator value of PIN16 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN16_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN16_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN17 @Bit 17 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN17_Pos (17UL)         /*!< Position of PIN17 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN17_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN17_Pos) /*!< Bit mask of PIN17 field.                     */
  #define VPRCSR_NORDIC_INB_PIN17_Min (0x0UL)        /*!< Min enumerator value of PIN17 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN17_Max (0x1UL)        /*!< Max enumerator value of PIN17 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN17_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN17_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN18 @Bit 18 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN18_Pos (18UL)         /*!< Position of PIN18 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN18_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN18_Pos) /*!< Bit mask of PIN18 field.                     */
  #define VPRCSR_NORDIC_INB_PIN18_Min (0x0UL)        /*!< Min enumerator value of PIN18 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN18_Max (0x1UL)        /*!< Max enumerator value of PIN18 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN18_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN18_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN19 @Bit 19 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN19_Pos (19UL)         /*!< Position of PIN19 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN19_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN19_Pos) /*!< Bit mask of PIN19 field.                     */
  #define VPRCSR_NORDIC_INB_PIN19_Min (0x0UL)        /*!< Min enumerator value of PIN19 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN19_Max (0x1UL)        /*!< Max enumerator value of PIN19 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN19_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN19_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN20 @Bit 20 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN20_Pos (20UL)         /*!< Position of PIN20 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN20_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN20_Pos) /*!< Bit mask of PIN20 field.                     */
  #define VPRCSR_NORDIC_INB_PIN20_Min (0x0UL)        /*!< Min enumerator value of PIN20 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN20_Max (0x1UL)        /*!< Max enumerator value of PIN20 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN20_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN20_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN21 @Bit 21 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN21_Pos (21UL)         /*!< Position of PIN21 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN21_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN21_Pos) /*!< Bit mask of PIN21 field.                     */
  #define VPRCSR_NORDIC_INB_PIN21_Min (0x0UL)        /*!< Min enumerator value of PIN21 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN21_Max (0x1UL)        /*!< Max enumerator value of PIN21 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN21_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN21_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN22 @Bit 22 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN22_Pos (22UL)         /*!< Position of PIN22 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN22_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN22_Pos) /*!< Bit mask of PIN22 field.                     */
  #define VPRCSR_NORDIC_INB_PIN22_Min (0x0UL)        /*!< Min enumerator value of PIN22 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN22_Max (0x1UL)        /*!< Max enumerator value of PIN22 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN22_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN22_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN23 @Bit 23 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN23_Pos (23UL)         /*!< Position of PIN23 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN23_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN23_Pos) /*!< Bit mask of PIN23 field.                     */
  #define VPRCSR_NORDIC_INB_PIN23_Min (0x0UL)        /*!< Min enumerator value of PIN23 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN23_Max (0x1UL)        /*!< Max enumerator value of PIN23 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN23_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN23_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN24 @Bit 24 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN24_Pos (24UL)         /*!< Position of PIN24 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN24_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN24_Pos) /*!< Bit mask of PIN24 field.                     */
  #define VPRCSR_NORDIC_INB_PIN24_Min (0x0UL)        /*!< Min enumerator value of PIN24 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN24_Max (0x1UL)        /*!< Max enumerator value of PIN24 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN24_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN24_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN25 @Bit 25 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN25_Pos (25UL)         /*!< Position of PIN25 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN25_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN25_Pos) /*!< Bit mask of PIN25 field.                     */
  #define VPRCSR_NORDIC_INB_PIN25_Min (0x0UL)        /*!< Min enumerator value of PIN25 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN25_Max (0x1UL)        /*!< Max enumerator value of PIN25 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN25_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN25_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN26 @Bit 26 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN26_Pos (26UL)         /*!< Position of PIN26 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN26_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN26_Pos) /*!< Bit mask of PIN26 field.                     */
  #define VPRCSR_NORDIC_INB_PIN26_Min (0x0UL)        /*!< Min enumerator value of PIN26 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN26_Max (0x1UL)        /*!< Max enumerator value of PIN26 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN26_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN26_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN27 @Bit 27 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN27_Pos (27UL)         /*!< Position of PIN27 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN27_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN27_Pos) /*!< Bit mask of PIN27 field.                     */
  #define VPRCSR_NORDIC_INB_PIN27_Min (0x0UL)        /*!< Min enumerator value of PIN27 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN27_Max (0x1UL)        /*!< Max enumerator value of PIN27 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN27_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN27_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN28 @Bit 28 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN28_Pos (28UL)         /*!< Position of PIN28 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN28_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN28_Pos) /*!< Bit mask of PIN28 field.                     */
  #define VPRCSR_NORDIC_INB_PIN28_Min (0x0UL)        /*!< Min enumerator value of PIN28 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN28_Max (0x1UL)        /*!< Max enumerator value of PIN28 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN28_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN28_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN29 @Bit 29 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN29_Pos (29UL)         /*!< Position of PIN29 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN29_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN29_Pos) /*!< Bit mask of PIN29 field.                     */
  #define VPRCSR_NORDIC_INB_PIN29_Min (0x0UL)        /*!< Min enumerator value of PIN29 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN29_Max (0x1UL)        /*!< Max enumerator value of PIN29 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN29_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN29_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN30 @Bit 30 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN30_Pos (30UL)         /*!< Position of PIN30 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN30_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN30_Pos) /*!< Bit mask of PIN30 field.                     */
  #define VPRCSR_NORDIC_INB_PIN30_Min (0x0UL)        /*!< Min enumerator value of PIN30 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN30_Max (0x1UL)        /*!< Max enumerator value of PIN30 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN30_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN30_HIGH (0x1UL)       /*!< Pin is High                                                          */

/* PIN31 @Bit 31 : (unspecified) */
  #define VPRCSR_NORDIC_INB_PIN31_Pos (31UL)         /*!< Position of PIN31 field.                                             */
  #define VPRCSR_NORDIC_INB_PIN31_Msk (0x1UL << VPRCSR_NORDIC_INB_PIN31_Pos) /*!< Bit mask of PIN31 field.                     */
  #define VPRCSR_NORDIC_INB_PIN31_Min (0x0UL)        /*!< Min enumerator value of PIN31 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN31_Max (0x1UL)        /*!< Max enumerator value of PIN31 field.                                 */
  #define VPRCSR_NORDIC_INB_PIN31_LOW (0x0UL)        /*!< Pin is Low                                                           */
  #define VPRCSR_NORDIC_INB_PIN31_HIGH (0x1UL)       /*!< Pin is High                                                          */




/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */

#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
/* ======================================================= Struct WDT ======================================================== */
/**
  * @brief Watchdog Timer
  */
  typedef struct {                                   /*!< WDT Structure                                                        */
    __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start WDT                                             */
    __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop WDT                                              */
    __IM uint32_t RESERVED[30];
    __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
    __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
    __IM uint32_t RESERVED1[30];
    __IOM uint32_t EVENTS_TIMEOUT;                   /*!< (@ 0x00000100) Watchdog timeout                                      */
    __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) Watchdog stopped                                      */
    __IM uint32_t RESERVED2[30];
    __IOM uint32_t PUBLISH_TIMEOUT;                  /*!< (@ 0x00000180) Publish configuration for event TIMEOUT               */
    __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
    __IM uint32_t RESERVED3[95];
    __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
    __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
    __IM uint32_t RESERVED4[6];
    __IOM uint32_t NMIENSET;                         /*!< (@ 0x00000324) Enable interrupt                                      */
    __IOM uint32_t NMIENCLR;                         /*!< (@ 0x00000328) Disable interrupt                                     */
    __IM uint32_t RESERVED5[53];
    __IM uint32_t RUNSTATUS;                         /*!< (@ 0x00000400) Run status                                            */
    __IM uint32_t REQSTATUS;                         /*!< (@ 0x00000404) Request status                                        */
    __IM uint32_t RESERVED6[63];
    __IOM uint32_t CRV;                              /*!< (@ 0x00000504) Counter reload value                                  */
    __IOM uint32_t RREN;                             /*!< (@ 0x00000508) Enable register for reload request registers          */
    __IOM uint32_t CONFIG;                           /*!< (@ 0x0000050C) Configuration register                                */
    __IM uint32_t RESERVED7[4];
    __OM uint32_t TSEN;                              /*!< (@ 0x00000520) Task stop enable                                      */
    __IM uint32_t RESERVED8[55];
    __OM uint32_t RR[8];                             /*!< (@ 0x00000600) Reload request n                                      */
  } NRF_WDT_Type;                                    /*!< Size = 1568 (0x620)                                                  */

/* WDT_TASKS_START: Start WDT */
  #define WDT_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */

/* TASKS_START @Bit 0 : Start WDT */
  #define WDT_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
  #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
  #define WDT_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
  #define WDT_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
  #define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */


/* WDT_TASKS_STOP: Stop WDT */
  #define WDT_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */

/* TASKS_STOP @Bit 0 : Stop WDT */
  #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
  #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
  #define WDT_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
  #define WDT_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
  #define WDT_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */


/* WDT_SUBSCRIBE_START: Subscribe configuration for task START */
  #define WDT_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
  #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define WDT_SUBSCRIBE_START_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define WDT_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define WDT_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
  #define WDT_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define WDT_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
  #define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */


/* WDT_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
  #define WDT_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */

/* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
  #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
  #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
  #define WDT_SUBSCRIBE_STOP_CHIDX_Min (0x00UL)      /*!< Min value of CHIDX field.                                            */
  #define WDT_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
  #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
  #define WDT_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
  #define WDT_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
  #define WDT_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
  #define WDT_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */


/* WDT_EVENTS_TIMEOUT: Watchdog timeout */
  #define WDT_EVENTS_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TIMEOUT register.                            */

/* EVENTS_TIMEOUT @Bit 0 : Watchdog timeout */
  #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field.                                   */
  #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT
                                                                            field.*/
  #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of EVENTS_TIMEOUT field.                     */
  #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of EVENTS_TIMEOUT field.                     */
  #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated                                             */


/* WDT_EVENTS_STOPPED: Watchdog stopped */
  #define WDT_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */

/* EVENTS_STOPPED @Bit 0 : Watchdog stopped */
  #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
  #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
                                                                            field.*/
  #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
  #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
  #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
  #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */


/* WDT_PUBLISH_TIMEOUT: Publish configuration for event TIMEOUT */
  #define WDT_PUBLISH_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TIMEOUT register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event TIMEOUT will publish to */
  #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define WDT_PUBLISH_TIMEOUT_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define WDT_PUBLISH_TIMEOUT_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field.                          */
  #define WDT_PUBLISH_TIMEOUT_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define WDT_PUBLISH_TIMEOUT_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* WDT_PUBLISH_STOPPED: Publish configuration for event STOPPED */
  #define WDT_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */

/* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
  #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
  #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
  #define WDT_PUBLISH_STOPPED_CHIDX_Min (0x00UL)     /*!< Min value of CHIDX field.                                            */
  #define WDT_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */

/* EN @Bit 31 : (unspecified) */
  #define WDT_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
  #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
  #define WDT_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
  #define WDT_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
  #define WDT_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
  #define WDT_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */


/* WDT_INTENSET: Enable interrupt */
  #define WDT_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */

/* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
  #define WDT_INTENSET_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
  #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
  #define WDT_INTENSET_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
  #define WDT_INTENSET_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
  #define WDT_INTENSET_TIMEOUT_Set (0x1UL)           /*!< Enable                                                               */
  #define WDT_INTENSET_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_INTENSET_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
  #define WDT_INTENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define WDT_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define WDT_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define WDT_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
  #define WDT_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */


/* WDT_INTENCLR: Disable interrupt */
  #define WDT_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */

/* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
  #define WDT_INTENCLR_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
  #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
  #define WDT_INTENCLR_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
  #define WDT_INTENCLR_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
  #define WDT_INTENCLR_TIMEOUT_Clear (0x1UL)         /*!< Disable                                                              */
  #define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
  #define WDT_INTENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define WDT_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define WDT_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define WDT_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
  #define WDT_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */


/* WDT_NMIENSET: Enable interrupt */
  #define WDT_NMIENSET_ResetValue (0x00000000UL)     /*!< Reset value of NMIENSET register.                                    */

/* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
  #define WDT_NMIENSET_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
  #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
  #define WDT_NMIENSET_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
  #define WDT_NMIENSET_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
  #define WDT_NMIENSET_TIMEOUT_Set (0x1UL)           /*!< Enable                                                               */
  #define WDT_NMIENSET_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_NMIENSET_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
  #define WDT_NMIENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define WDT_NMIENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define WDT_NMIENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define WDT_NMIENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
  #define WDT_NMIENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_NMIENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */


/* WDT_NMIENCLR: Disable interrupt */
  #define WDT_NMIENCLR_ResetValue (0x00000000UL)     /*!< Reset value of NMIENCLR register.                                    */

/* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
  #define WDT_NMIENCLR_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
  #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
  #define WDT_NMIENCLR_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
  #define WDT_NMIENCLR_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
  #define WDT_NMIENCLR_TIMEOUT_Clear (0x1UL)         /*!< Disable                                                              */
  #define WDT_NMIENCLR_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_NMIENCLR_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */

/* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
  #define WDT_NMIENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
  #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
  #define WDT_NMIENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
  #define WDT_NMIENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
  #define WDT_NMIENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
  #define WDT_NMIENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
  #define WDT_NMIENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */


/* WDT_RUNSTATUS: Run status */
  #define WDT_RUNSTATUS_ResetValue (0x00000000UL)    /*!< Reset value of RUNSTATUS register.                                   */

/* RUNSTATUSWDT @Bit 0 : Indicates whether or not WDT is running */
  #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL)       /*!< Position of RUNSTATUSWDT field.                                      */
  #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field.        */
  #define WDT_RUNSTATUS_RUNSTATUSWDT_Min (0x0UL)     /*!< Min enumerator value of RUNSTATUSWDT field.                          */
  #define WDT_RUNSTATUS_RUNSTATUSWDT_Max (0x1UL)     /*!< Max enumerator value of RUNSTATUSWDT field.                          */
  #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog is not running                                           */
  #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running                                                  */


/* WDT_REQSTATUS: Request status */
  #define WDT_REQSTATUS_ResetValue (0x00000001UL)    /*!< Reset value of REQSTATUS register.                                   */

/* RR0 @Bit 0 : Request status for RR[0] register */
  #define WDT_REQSTATUS_RR0_Pos (0UL)                /*!< Position of RR0 field.                                               */
  #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field.                                   */
  #define WDT_REQSTATUS_RR0_Min (0x0UL)              /*!< Min enumerator value of RR0 field.                                   */
  #define WDT_REQSTATUS_RR0_Max (0x1UL)              /*!< Max enumerator value of RR0 field.                                   */
  #define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload    */

/* RR1 @Bit 1 : Request status for RR[1] register */
  #define WDT_REQSTATUS_RR1_Pos (1UL)                /*!< Position of RR1 field.                                               */
  #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field.                                   */
  #define WDT_REQSTATUS_RR1_Min (0x0UL)              /*!< Min enumerator value of RR1 field.                                   */
  #define WDT_REQSTATUS_RR1_Max (0x1UL)              /*!< Max enumerator value of RR1 field.                                   */
  #define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload    */

/* RR2 @Bit 2 : Request status for RR[2] register */
  #define WDT_REQSTATUS_RR2_Pos (2UL)                /*!< Position of RR2 field.                                               */
  #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field.                                   */
  #define WDT_REQSTATUS_RR2_Min (0x0UL)              /*!< Min enumerator value of RR2 field.                                   */
  #define WDT_REQSTATUS_RR2_Max (0x1UL)              /*!< Max enumerator value of RR2 field.                                   */
  #define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload    */

/* RR3 @Bit 3 : Request status for RR[3] register */
  #define WDT_REQSTATUS_RR3_Pos (3UL)                /*!< Position of RR3 field.                                               */
  #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field.                                   */
  #define WDT_REQSTATUS_RR3_Min (0x0UL)              /*!< Min enumerator value of RR3 field.                                   */
  #define WDT_REQSTATUS_RR3_Max (0x1UL)              /*!< Max enumerator value of RR3 field.                                   */
  #define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload    */

/* RR4 @Bit 4 : Request status for RR[4] register */
  #define WDT_REQSTATUS_RR4_Pos (4UL)                /*!< Position of RR4 field.                                               */
  #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field.                                   */
  #define WDT_REQSTATUS_RR4_Min (0x0UL)              /*!< Min enumerator value of RR4 field.                                   */
  #define WDT_REQSTATUS_RR4_Max (0x1UL)              /*!< Max enumerator value of RR4 field.                                   */
  #define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload    */

/* RR5 @Bit 5 : Request status for RR[5] register */
  #define WDT_REQSTATUS_RR5_Pos (5UL)                /*!< Position of RR5 field.                                               */
  #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field.                                   */
  #define WDT_REQSTATUS_RR5_Min (0x0UL)              /*!< Min enumerator value of RR5 field.                                   */
  #define WDT_REQSTATUS_RR5_Max (0x1UL)              /*!< Max enumerator value of RR5 field.                                   */
  #define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload    */

/* RR6 @Bit 6 : Request status for RR[6] register */
  #define WDT_REQSTATUS_RR6_Pos (6UL)                /*!< Position of RR6 field.                                               */
  #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field.                                   */
  #define WDT_REQSTATUS_RR6_Min (0x0UL)              /*!< Min enumerator value of RR6 field.                                   */
  #define WDT_REQSTATUS_RR6_Max (0x1UL)              /*!< Max enumerator value of RR6 field.                                   */
  #define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload    */

/* RR7 @Bit 7 : Request status for RR[7] register */
  #define WDT_REQSTATUS_RR7_Pos (7UL)                /*!< Position of RR7 field.                                               */
  #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field.                                   */
  #define WDT_REQSTATUS_RR7_Min (0x0UL)              /*!< Min enumerator value of RR7 field.                                   */
  #define WDT_REQSTATUS_RR7_Max (0x1UL)              /*!< Max enumerator value of RR7 field.                                   */
  #define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload   */
  #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload    */


/* WDT_CRV: Counter reload value */
  #define WDT_CRV_ResetValue (0xFFFFFFFFUL)          /*!< Reset value of CRV register.                                         */

/* CRV @Bits 0..31 : Counter reload value in number of cycles of the 32.768 kHz clock */
  #define WDT_CRV_CRV_Pos (0UL)                      /*!< Position of CRV field.                                               */
  #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field.                                        */
  #define WDT_CRV_CRV_Min (0x0000000FUL)             /*!< Min value of CRV field.                                              */
  #define WDT_CRV_CRV_Max (0xFFFFFFFFUL)             /*!< Max size of CRV field.                                               */


/* WDT_RREN: Enable register for reload request registers */
  #define WDT_RREN_ResetValue (0x00000001UL)         /*!< Reset value of RREN register.                                        */

/* RR0 @Bit 0 : Enable or disable RR[0] register */
  #define WDT_RREN_RR0_Pos (0UL)                     /*!< Position of RR0 field.                                               */
  #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field.                                             */
  #define WDT_RREN_RR0_Min (0x0UL)                   /*!< Min enumerator value of RR0 field.                                   */
  #define WDT_RREN_RR0_Max (0x1UL)                   /*!< Max enumerator value of RR0 field.                                   */
  #define WDT_RREN_RR0_Disabled (0x0UL)              /*!< Disable RR[0] register                                               */
  #define WDT_RREN_RR0_Enabled (0x1UL)               /*!< Enable RR[0] register                                                */

/* RR1 @Bit 1 : Enable or disable RR[1] register */
  #define WDT_RREN_RR1_Pos (1UL)                     /*!< Position of RR1 field.                                               */
  #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field.                                             */
  #define WDT_RREN_RR1_Min (0x0UL)                   /*!< Min enumerator value of RR1 field.                                   */
  #define WDT_RREN_RR1_Max (0x1UL)                   /*!< Max enumerator value of RR1 field.                                   */
  #define WDT_RREN_RR1_Disabled (0x0UL)              /*!< Disable RR[1] register                                               */
  #define WDT_RREN_RR1_Enabled (0x1UL)               /*!< Enable RR[1] register                                                */

/* RR2 @Bit 2 : Enable or disable RR[2] register */
  #define WDT_RREN_RR2_Pos (2UL)                     /*!< Position of RR2 field.                                               */
  #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field.                                             */
  #define WDT_RREN_RR2_Min (0x0UL)                   /*!< Min enumerator value of RR2 field.                                   */
  #define WDT_RREN_RR2_Max (0x1UL)                   /*!< Max enumerator value of RR2 field.                                   */
  #define WDT_RREN_RR2_Disabled (0x0UL)              /*!< Disable RR[2] register                                               */
  #define WDT_RREN_RR2_Enabled (0x1UL)               /*!< Enable RR[2] register                                                */

/* RR3 @Bit 3 : Enable or disable RR[3] register */
  #define WDT_RREN_RR3_Pos (3UL)                     /*!< Position of RR3 field.                                               */
  #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field.                                             */
  #define WDT_RREN_RR3_Min (0x0UL)                   /*!< Min enumerator value of RR3 field.                                   */
  #define WDT_RREN_RR3_Max (0x1UL)                   /*!< Max enumerator value of RR3 field.                                   */
  #define WDT_RREN_RR3_Disabled (0x0UL)              /*!< Disable RR[3] register                                               */
  #define WDT_RREN_RR3_Enabled (0x1UL)               /*!< Enable RR[3] register                                                */

/* RR4 @Bit 4 : Enable or disable RR[4] register */
  #define WDT_RREN_RR4_Pos (4UL)                     /*!< Position of RR4 field.                                               */
  #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field.                                             */
  #define WDT_RREN_RR4_Min (0x0UL)                   /*!< Min enumerator value of RR4 field.                                   */
  #define WDT_RREN_RR4_Max (0x1UL)                   /*!< Max enumerator value of RR4 field.                                   */
  #define WDT_RREN_RR4_Disabled (0x0UL)              /*!< Disable RR[4] register                                               */
  #define WDT_RREN_RR4_Enabled (0x1UL)               /*!< Enable RR[4] register                                                */

/* RR5 @Bit 5 : Enable or disable RR[5] register */
  #define WDT_RREN_RR5_Pos (5UL)                     /*!< Position of RR5 field.                                               */
  #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field.                                             */
  #define WDT_RREN_RR5_Min (0x0UL)                   /*!< Min enumerator value of RR5 field.                                   */
  #define WDT_RREN_RR5_Max (0x1UL)                   /*!< Max enumerator value of RR5 field.                                   */
  #define WDT_RREN_RR5_Disabled (0x0UL)              /*!< Disable RR[5] register                                               */
  #define WDT_RREN_RR5_Enabled (0x1UL)               /*!< Enable RR[5] register                                                */

/* RR6 @Bit 6 : Enable or disable RR[6] register */
  #define WDT_RREN_RR6_Pos (6UL)                     /*!< Position of RR6 field.                                               */
  #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field.                                             */
  #define WDT_RREN_RR6_Min (0x0UL)                   /*!< Min enumerator value of RR6 field.                                   */
  #define WDT_RREN_RR6_Max (0x1UL)                   /*!< Max enumerator value of RR6 field.                                   */
  #define WDT_RREN_RR6_Disabled (0x0UL)              /*!< Disable RR[6] register                                               */
  #define WDT_RREN_RR6_Enabled (0x1UL)               /*!< Enable RR[6] register                                                */

/* RR7 @Bit 7 : Enable or disable RR[7] register */
  #define WDT_RREN_RR7_Pos (7UL)                     /*!< Position of RR7 field.                                               */
  #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field.                                             */
  #define WDT_RREN_RR7_Min (0x0UL)                   /*!< Min enumerator value of RR7 field.                                   */
  #define WDT_RREN_RR7_Max (0x1UL)                   /*!< Max enumerator value of RR7 field.                                   */
  #define WDT_RREN_RR7_Disabled (0x0UL)              /*!< Disable RR[7] register                                               */
  #define WDT_RREN_RR7_Enabled (0x1UL)               /*!< Enable RR[7] register                                                */


/* WDT_CONFIG: Configuration register */
  #define WDT_CONFIG_ResetValue (0x00000001UL)       /*!< Reset value of CONFIG register.                                      */

/* SLEEP @Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */
  #define WDT_CONFIG_SLEEP_Pos (0UL)                 /*!< Position of SLEEP field.                                             */
  #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field.                                   */
  #define WDT_CONFIG_SLEEP_Min (0x0UL)               /*!< Min enumerator value of SLEEP field.                                 */
  #define WDT_CONFIG_SLEEP_Max (0x1UL)               /*!< Max enumerator value of SLEEP field.                                 */
  #define WDT_CONFIG_SLEEP_Pause (0x0UL)             /*!< Pause WDT while the CPU is sleeping                                  */
  #define WDT_CONFIG_SLEEP_Run (0x1UL)               /*!< Keep WDT running while the CPU is sleeping                           */

/* HALT @Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */
  #define WDT_CONFIG_HALT_Pos (3UL)                  /*!< Position of HALT field.                                              */
  #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field.                                      */
  #define WDT_CONFIG_HALT_Min (0x0UL)                /*!< Min enumerator value of HALT field.                                  */
  #define WDT_CONFIG_HALT_Max (0x1UL)                /*!< Max enumerator value of HALT field.                                  */
  #define WDT_CONFIG_HALT_Pause (0x0UL)              /*!< Pause WDT while the CPU is halted by the debugger                    */
  #define WDT_CONFIG_HALT_Run (0x1UL)                /*!< Keep WDT running while the CPU is halted by the debugger             */

/* STOPEN @Bit 6 : Allow stopping WDT */
  #define WDT_CONFIG_STOPEN_Pos (6UL)                /*!< Position of STOPEN field.                                            */
  #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field.                                */
  #define WDT_CONFIG_STOPEN_Min (0x0UL)              /*!< Min enumerator value of STOPEN field.                                */
  #define WDT_CONFIG_STOPEN_Max (0x1UL)              /*!< Max enumerator value of STOPEN field.                                */
  #define WDT_CONFIG_STOPEN_Disable (0x0UL)          /*!< Do not allow stopping WDT                                            */
  #define WDT_CONFIG_STOPEN_Enable (0x1UL)           /*!< Allow stopping WDT                                                   */


/* WDT_TSEN: Task stop enable */
  #define WDT_TSEN_ResetValue (0x00000000UL)         /*!< Reset value of TSEN register.                                        */

/* TSEN @Bits 0..31 : Allow stopping WDT */
  #define WDT_TSEN_TSEN_Pos (0UL)                    /*!< Position of TSEN field.                                              */
  #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field.                                   */
  #define WDT_TSEN_TSEN_Min (0x6E524635UL)           /*!< Min enumerator value of TSEN field.                                  */
  #define WDT_TSEN_TSEN_Max (0x6E524635UL)           /*!< Max enumerator value of TSEN field.                                  */
  #define WDT_TSEN_TSEN_Enable (0x6E524635UL)        /*!< Value to allow stopping WDT                                          */


/* WDT_RR: Reload request n */
  #define WDT_RR_MaxCount (8UL)                      /*!< Max size of RR[8] array.                                             */
  #define WDT_RR_MaxIndex (7UL)                      /*!< Max index of RR[8] array.                                            */
  #define WDT_RR_MinIndex (0UL)                      /*!< Min index of RR[8] array.                                            */
  #define WDT_RR_ResetValue (0x00000000UL)           /*!< Reset value of RR[8] register.                                       */

/* RR @Bits 0..31 : Reload request register */
  #define WDT_RR_RR_Pos (0UL)                        /*!< Position of RR field.                                                */
  #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field.                                             */
  #define WDT_RR_RR_Min (0x6E524635UL)               /*!< Min enumerator value of RR field.                                    */
  #define WDT_RR_RR_Max (0x6E524635UL)               /*!< Max enumerator value of RR field.                                    */
  #define WDT_RR_RR_Reload (0x6E524635UL)            /*!< Value to request a reload of the watchdog timer                      */


#endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */

/* ========================================== End of section using anonymous unions ========================================== */

#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


#ifdef __cplusplus
}
#endif
#endif /* NRF54L10_TYPES_H */

