PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
GFXSS_GPU_GCNANO_Type Struct Reference

## Description

Host Interface Registers (GFXSS_GPU_GCNANO)

## Data Fields
__IOM uint32_t | AQHICLOCKCONTROL
__IM uint32_t | AQHIIDLE
__IOM uint32_t | AQAXICONFIG
__IM uint32_t | AQAXISTATUS
__IM uint32_t | AQINTRACKNOWLEDGE
__IOM uint32_t | AQINTRENBL
__IM uint32_t | RESERVED [3]
__IM uint32_t | GCCHIPREV
__IM uint32_t | GCCHIPDATE
__IM uint32_t | RESERVED1 [27]
__IM uint32_t | GCREGHICHIPPATCHREV
__IM uint32_t | RESERVED2 [3]
__IM uint32_t | GCPRODUCTID
__IM uint32_t | RESERVED3 [21]
__IOM uint32_t | GCMODULEPOWERCONTROLS
__IOM uint32_t | GCMODULEPOWERMODULECONTROL
__IM uint32_t | GCMODULEPOWERMODULESTATUS
__IM uint32_t | RESERVED4 [194]
__IOM uint32_t | AQMEMORYDEBUG
__IM uint32_t | RESERVED5 [5]
__IOM uint32_t | AQREGISTERTIMINGCONTROL
__IM uint32_t | RESERVED6 [52]
__IOM uint32_t | GCREGFETCHADDRESS
__IOM uint32_t | GCREGFETCHCONTROL
__IM uint32_t | GCREGCURRENTFETCHADDRESS
__IM uint32_t | RESERVED7 [189]

## Field Documentation

## ◆ AQHICLOCKCONTROL

__IOM uint32_t GFXSS_GPU_GCNANO_Type::AQHICLOCKCONTROL

0x00000000 Clock Control Register.

## ◆ AQHIIDLE

__IM uint32_t GFXSS_GPU_GCNANO_Type::AQHIIDLE

0x00000004 Idle Status Register.

## ◆ AQAXICONFIG

__IOM uint32_t GFXSS_GPU_GCNANO_Type::AQAXICONFIG

0x00000008 AXI Configuration Register.

## ◆ AQAXISTATUS

__IM uint32_t GFXSS_GPU_GCNANO_Type::AQAXISTATUS

0x0000000C AXI Status Register. READ ONLY. Back-to-back read is forbidden to this register and can cause system hang. Please insert delay (nop operation) between two consecutive reads while accessing this register outside of VSI drivers.

## ◆ AQINTRACKNOWLEDGE

__IM uint32_t GFXSS_GPU_GCNANO_Type::AQINTRACKNOWLEDGE

0x00000010 Interrupt Acknowledge Register. Each bit represents a corresponding event being triggered. Reading from this register clears the outstanding interrupt. READ ONLY. When the access comes from a debugger (HMASTER[0] == 1), the clear by read function is disabled. Back-to-back read is forbidden to this register and can cause system hang. Please insert delay (nop operation) between two consecutive reads while accessing this register outside of VSI drivers.

## ◆ AQINTRENBL

__IOM uint32_t GFXSS_GPU_GCNANO_Type::AQINTRENBL

0x00000014 Interrupt Enable Register. Each bit enables a corresponding event.

## ◆ RESERVED

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED[3]

## ◆ GCCHIPREV

__IM uint32_t GFXSS_GPU_GCNANO_Type::GCCHIPREV

0x00000024 Chip Revsion Register. Shows the revision for the chip in BCD. This register has no set reset value. It varies with the implementation. READ ONLY.

## ◆ GCCHIPDATE

__IM uint32_t GFXSS_GPU_GCNANO_Type::GCCHIPDATE

0x00000028 Chip Date Register. Shows the release date for the IP in YYYYMMDD (year/month/day) format. This register has no set reset value. It varies with the implementation. READ ONLY.

## ◆ RESERVED1

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED1[27]

## ◆ GCREGHICHIPPATCHREV

__IM uint32_t GFXSS_GPU_GCNANO_Type::GCREGHICHIPPATCHREV

0x00000098 Chip Patch Revision Register. Patch revision level for the chip. It varies per release. READ ONLY

## ◆ RESERVED2

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED2[3]

## ◆ GCPRODUCTID

__IM uint32_t GFXSS_GPU_GCNANO_Type::GCPRODUCTID

0x000000A8 Product Identification Register. Shows Product ID. READ ONLY.

## ◆ RESERVED3

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED3[21]

## ◆ GCMODULEPOWERCONTROLS

__IOM uint32_t GFXSS_GPU_GCNANO_Type::GCMODULEPOWERCONTROLS

0x00000100 Module Power Control Register. Control register for module level power controls.

## ◆ GCMODULEPOWERMODULECONTROL

__IOM uint32_t GFXSS_GPU_GCNANO_Type::GCMODULEPOWERMODULECONTROL

0x00000104 Module Power Module Control Register. Module level control register.

## ◆ GCMODULEPOWERMODULESTATUS

__IM uint32_t GFXSS_GPU_GCNANO_Type::GCMODULEPOWERMODULESTATUS

0x00000108 Module Power Module Status Register. Module level control status.

## ◆ RESERVED4

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED4[194]

## ◆ AQMEMORYDEBUG

__IOM uint32_t GFXSS_GPU_GCNANO_Type::AQMEMORYDEBUG

0x00000414 Memory Debug Register.

## ◆ RESERVED5

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED5[5]

## ◆ AQREGISTERTIMINGCONTROL

__IOM uint32_t GFXSS_GPU_GCNANO_Type::AQREGISTERTIMINGCONTROL

0x0000042C Timing Control Register.

## ◆ RESERVED6

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED6[52]

## ◆ GCREGFETCHADDRESS

__IOM uint32_t GFXSS_GPU_GCNANO_Type::GCREGFETCHADDRESS

0x00000500 Fetch Command Buffer Base Address Register. Address of the command buffer. The address must be 64-byte aligned.

## ◆ GCREGFETCHCONTROL

__IOM uint32_t GFXSS_GPU_GCNANO_Type::GCREGFETCHCONTROL

0x00000504 Fetch Control Register. Writing a non-zero value to this register starts the fetch engine. The FE will start fetching 64-bit commands and data starting at the address specified by the gcregFetchAddress register. Make sure this count is large enough to fetch the END command, otherwise the FE will wait until more data is coming.

## ◆ GCREGCURRENTFETCHADDRESS

__IM uint32_t GFXSS_GPU_GCNANO_Type::GCREGCURRENTFETCHADDRESS

0x00000508 Current Fetch Command Address Register. Debugging register that defines the current address the FE is fetching data from. READ ONLY.

## ◆ RESERVED7

__IM uint32_t GFXSS_GPU_GCNANO_Type::RESERVED7[189]