/***************************************************************************//**
* LPPASS_MMIO IP definitions
*
********************************************************************************
* \copyright
* (c) (2016-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#ifndef _CYIP_LPPASS_MMIO_V1_1_H_
#define _CYIP_LPPASS_MMIO_V1_1_H_

#include "cyip_headers.h"

/*******************************************************************************
*                                 LPPASS_MMIO
*******************************************************************************/

#define LPPASS_MMIO_STA_SECTION_SIZE            0x00000100UL
#define LPPASS_MMIO_SECTION_SIZE                0x00010000UL

/**
  * \brief FIFO Static configuration (LPPASS_MMIO_STA)
  */
typedef struct {
  __IOM uint32_t CFG;                           /*!< 0x00000000 FIFO configuration register. */
  __IOM uint32_t MODE;                          /*!< 0x00000004 FIFO mode register. */
   __IM uint32_t MODE_STATUS;                   /*!< 0x00000008 FIFO mode status register. */
   __IM uint32_t RESERVED;
  __IOM uint32_t LEVEL[8];                      /*!< 0x00000010 FIFO level register. */
   __IM uint32_t RD_DATA[8];                    /*!< 0x00000030 FIFO 32-bit read data register */
   __IM uint32_t USED[8];                       /*!< 0x00000050 FIFO used register */
   __IM uint32_t STATUS[8];                     /*!< 0x00000070 FIFO status register */
   __IM uint32_t RESERVED1[28];
} LPPASS_MMIO_STA_Type;                         /*!< Size = 256 (0x100) */

/**
  * \brief LPPASS top-level MMIO (LPPASS_MMIO)
  */
typedef struct {
   __IM uint32_t INTR_CAUSE;                    /*!< 0x00000000 Interrupt cause register */
   __IM uint32_t FIFO_INTR_CAUSE;               /*!< 0x00000004 FIFO Interrupt cause register */
   __IM uint32_t RESERVED[2];
  __IOM uint32_t TR_OUT[8];                     /*!< 0x00000010 Trigger out select register */
   __IM uint32_t RESERVED1[4];
  __IOM uint32_t INTR;                          /*!< 0x00000040 Interrupt request register */
   __IM uint32_t RESERVED2;
  __IOM uint32_t INTR_SET;                      /*!< 0x00000048 Interrupt request set register */
   __IM uint32_t RESERVED3;
  __IOM uint32_t INTR_MASK;                     /*!< 0x00000050 Interrupt request mask */
   __IM uint32_t RESERVED4;
   __IM uint32_t INTR_MASKED;                   /*!< 0x00000058 Interrupt request masked */
   __IM uint32_t RESERVED5;
  __IOM uint32_t FIFO_INTR;                     /*!< 0x00000060 FIFO Interrupt request register */
   __IM uint32_t RESERVED6;
  __IOM uint32_t FIFO_INTR_SET;                 /*!< 0x00000068 FIFO Interrupt set request register */
   __IM uint32_t RESERVED7;
  __IOM uint32_t FIFO_INTR_MASK;                /*!< 0x00000070 FIFO Interrupt mask register */
   __IM uint32_t RESERVED8;
   __IM uint32_t FIFO_INTR_MASKED;              /*!< 0x00000078 FIFO Interrupt masked request register */
   __IM uint32_t RESERVED9[225];
        LPPASS_MMIO_STA_Type STA;               /*!< 0x00000400 FIFO Static configuration */
} LPPASS_MMIO_Type;                             /*!< Size = 1280 (0x500) */


/* LPPASS_MMIO_STA.CFG */
#define LPPASS_MMIO_STA_CFG_SEL_Pos             0UL
#define LPPASS_MMIO_STA_CFG_SEL_Msk             0x3UL
/* LPPASS_MMIO_STA.MODE */
#define LPPASS_MMIO_STA_MODE_RD_LOCKOUT_EN_Pos  0UL
#define LPPASS_MMIO_STA_MODE_RD_LOCKOUT_EN_Msk  0x1UL
/* LPPASS_MMIO_STA.MODE_STATUS */
#define LPPASS_MMIO_STA_MODE_STATUS_RD_LOCKOUT_Pos 0UL
#define LPPASS_MMIO_STA_MODE_STATUS_RD_LOCKOUT_Msk 0x1UL
/* LPPASS_MMIO_STA.LEVEL */
#define LPPASS_MMIO_STA_LEVEL_LEVEL_Pos         0UL
#define LPPASS_MMIO_STA_LEVEL_LEVEL_Msk         0x1FFUL
/* LPPASS_MMIO_STA.RD_DATA */
#define LPPASS_MMIO_STA_RD_DATA_RESULT_Pos      0UL
#define LPPASS_MMIO_STA_RD_DATA_RESULT_Msk      0xFFFFFFFFUL
/* LPPASS_MMIO_STA.USED */
#define LPPASS_MMIO_STA_USED_USED_Pos           0UL
#define LPPASS_MMIO_STA_USED_USED_Msk           0x3FFUL
/* LPPASS_MMIO_STA.STATUS */
#define LPPASS_MMIO_STA_STATUS_RD_PTR_Pos       0UL
#define LPPASS_MMIO_STA_STATUS_RD_PTR_Msk       0x1FFUL
#define LPPASS_MMIO_STA_STATUS_WR_PTR_Pos       16UL
#define LPPASS_MMIO_STA_STATUS_WR_PTR_Msk       0x1FF0000UL


/* LPPASS_MMIO.INTR_CAUSE */
#define LPPASS_MMIO_INTR_CAUSE_CTBL0_COMP0_INT_Pos 0UL
#define LPPASS_MMIO_INTR_CAUSE_CTBL0_COMP0_INT_Msk 0x1UL
#define LPPASS_MMIO_INTR_CAUSE_CTBL0_COMP1_INT_Pos 1UL
#define LPPASS_MMIO_INTR_CAUSE_CTBL0_COMP1_INT_Msk 0x2UL
#define LPPASS_MMIO_INTR_CAUSE_CTBL1_COMP0_INT_Pos 2UL
#define LPPASS_MMIO_INTR_CAUSE_CTBL1_COMP0_INT_Msk 0x4UL
#define LPPASS_MMIO_INTR_CAUSE_CTBL1_COMP1_INT_Pos 3UL
#define LPPASS_MMIO_INTR_CAUSE_CTBL1_COMP1_INT_Msk 0x8UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_COMP0_INT_Pos 4UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_COMP0_INT_Msk 0x10UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_COMP1_INT_Pos 5UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_COMP1_INT_Msk 0x20UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_RANGE0_INT_Pos 6UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_RANGE0_INT_Msk 0x40UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_RANGE1_INT_Pos 7UL
#define LPPASS_MMIO_INTR_CAUSE_PTC_RANGE1_INT_Msk 0x80UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_RANGE0_INT_Pos 8UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_RANGE0_INT_Msk 0x100UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_RANGE1_INT_Pos 9UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_RANGE1_INT_Msk 0x200UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_RANGE2_INT_Pos 10UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_RANGE2_INT_Msk 0x400UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_EPOCH_INT_Pos 11UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_EPOCH_INT_Msk 0x800UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_EMPTY_INT_Pos 12UL
#define LPPASS_MMIO_INTR_CAUSE_DAC0_EMPTY_INT_Msk 0x1000UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_RANGE0_INT_Pos 13UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_RANGE0_INT_Msk 0x2000UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_RANGE1_INT_Pos 14UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_RANGE1_INT_Msk 0x4000UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_RANGE2_INT_Pos 15UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_RANGE2_INT_Msk 0x8000UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_EPOCH_INT_Pos 16UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_EPOCH_INT_Msk 0x10000UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_EMPTY_INT_Pos 17UL
#define LPPASS_MMIO_INTR_CAUSE_DAC1_EMPTY_INT_Msk 0x20000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_DONE_INT_Pos 18UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_DONE_INT_Msk 0x40000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_EOS_INT_Pos  19UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_EOS_INT_Msk  0x80000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RESULT_INT_Pos 20UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RESULT_INT_Msk 0x100000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE0_INT_Pos 21UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE0_INT_Msk 0x200000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE1_INT_Pos 22UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE1_INT_Msk 0x400000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE2_INT_Pos 23UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE2_INT_Msk 0x800000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE3_INT_Pos 24UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_RANGE3_INT_Msk 0x1000000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_FIR0_RESULT_INT_Pos 25UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_FIR0_RESULT_INT_Msk 0x2000000UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_FIR1_RESULT_INT_Pos 26UL
#define LPPASS_MMIO_INTR_CAUSE_SAR_FIR1_RESULT_INT_Msk 0x4000000UL
#define LPPASS_MMIO_INTR_CAUSE_RESERVED_Pos     27UL
#define LPPASS_MMIO_INTR_CAUSE_RESERVED_Msk     0x78000000UL
#define LPPASS_MMIO_INTR_CAUSE_AC_INT_Pos       31UL
#define LPPASS_MMIO_INTR_CAUSE_AC_INT_Msk       0x80000000UL
/* LPPASS_MMIO.FIFO_INTR_CAUSE */
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW0_INT_Pos 0UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW0_INT_Msk 0x1UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW1_INT_Pos 1UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW1_INT_Msk 0x2UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW2_INT_Pos 2UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW2_INT_Msk 0x4UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW3_INT_Pos 3UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW3_INT_Msk 0x8UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW4_INT_Pos 4UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW4_INT_Msk 0x10UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW5_INT_Pos 5UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW5_INT_Msk 0x20UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW6_INT_Pos 6UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW6_INT_Msk 0x40UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW7_INT_Pos 7UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_OVERFLOW7_INT_Msk 0x80UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW0_INT_Pos 8UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW0_INT_Msk 0x100UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW1_INT_Pos 9UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW1_INT_Msk 0x200UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW2_INT_Pos 10UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW2_INT_Msk 0x400UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW3_INT_Pos 11UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW3_INT_Msk 0x800UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW4_INT_Pos 12UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW4_INT_Msk 0x1000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW5_INT_Pos 13UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW5_INT_Msk 0x2000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW6_INT_Pos 14UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW6_INT_Msk 0x4000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW7_INT_Pos 15UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_UNDERFLOW7_INT_Msk 0x8000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_0_Pos 16UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_0_Msk 0x10000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL0_INT_Pos 17UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL0_INT_Msk 0x20000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_1_Pos 18UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_1_Msk 0xC0000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL1_INT_Pos 20UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL1_INT_Msk 0x100000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_2_Pos 21UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_2_Msk 0x1E00000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL2_INT_Pos 25UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL2_INT_Msk 0x2000000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL3_INT_Pos 26UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL3_INT_Msk 0x4000000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL4_INT_Pos 27UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL4_INT_Msk 0x8000000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL5_INT_Pos 28UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL5_INT_Msk 0x10000000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL6_INT_Pos 29UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL6_INT_Msk 0x20000000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL7_INT_Pos 30UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_FIFO_LEVEL7_INT_Msk 0x40000000UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_3_Pos 31UL
#define LPPASS_MMIO_FIFO_INTR_CAUSE_RESERVED_3_Msk 0x80000000UL
/* LPPASS_MMIO.TR_OUT */
#define LPPASS_MMIO_TR_OUT_CTBL0_COMP0_Pos      0UL
#define LPPASS_MMIO_TR_OUT_CTBL0_COMP0_Msk      0x1UL
#define LPPASS_MMIO_TR_OUT_CTBL0_COMP1_Pos      1UL
#define LPPASS_MMIO_TR_OUT_CTBL0_COMP1_Msk      0x2UL
#define LPPASS_MMIO_TR_OUT_CTBL1_COMP0_Pos      2UL
#define LPPASS_MMIO_TR_OUT_CTBL1_COMP0_Msk      0x4UL
#define LPPASS_MMIO_TR_OUT_CTBL1_COMP1_Pos      3UL
#define LPPASS_MMIO_TR_OUT_CTBL1_COMP1_Msk      0x8UL
#define LPPASS_MMIO_TR_OUT_PTC_COMP0_Pos        4UL
#define LPPASS_MMIO_TR_OUT_PTC_COMP0_Msk        0x10UL
#define LPPASS_MMIO_TR_OUT_PTC_COMP1_Pos        5UL
#define LPPASS_MMIO_TR_OUT_PTC_COMP1_Msk        0x20UL
#define LPPASS_MMIO_TR_OUT_PTC_RANGE0_Pos       6UL
#define LPPASS_MMIO_TR_OUT_PTC_RANGE0_Msk       0x40UL
#define LPPASS_MMIO_TR_OUT_PTC_RANGE1_Pos       7UL
#define LPPASS_MMIO_TR_OUT_PTC_RANGE1_Msk       0x80UL
#define LPPASS_MMIO_TR_OUT_DAC0_RANGE0_Pos      8UL
#define LPPASS_MMIO_TR_OUT_DAC0_RANGE0_Msk      0x100UL
#define LPPASS_MMIO_TR_OUT_DAC0_RANGE1_Pos      9UL
#define LPPASS_MMIO_TR_OUT_DAC0_RANGE1_Msk      0x200UL
#define LPPASS_MMIO_TR_OUT_DAC0_RANGE2_Pos      10UL
#define LPPASS_MMIO_TR_OUT_DAC0_RANGE2_Msk      0x400UL
#define LPPASS_MMIO_TR_OUT_DAC0_EPOCH_Pos       11UL
#define LPPASS_MMIO_TR_OUT_DAC0_EPOCH_Msk       0x800UL
#define LPPASS_MMIO_TR_OUT_RESERVED_4_Pos       12UL
#define LPPASS_MMIO_TR_OUT_RESERVED_4_Msk       0x1000UL
#define LPPASS_MMIO_TR_OUT_DAC1_RANGE0_Pos      13UL
#define LPPASS_MMIO_TR_OUT_DAC1_RANGE0_Msk      0x2000UL
#define LPPASS_MMIO_TR_OUT_DAC1_RANGE1_Pos      14UL
#define LPPASS_MMIO_TR_OUT_DAC1_RANGE1_Msk      0x4000UL
#define LPPASS_MMIO_TR_OUT_DAC1_RANGE2_Pos      15UL
#define LPPASS_MMIO_TR_OUT_DAC1_RANGE2_Msk      0x8000UL
#define LPPASS_MMIO_TR_OUT_DAC1_EPOCH_Pos       16UL
#define LPPASS_MMIO_TR_OUT_DAC1_EPOCH_Msk       0x10000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL0_Pos      17UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL0_Msk      0x20000UL
#define LPPASS_MMIO_TR_OUT_SAR_DONE_Pos         18UL
#define LPPASS_MMIO_TR_OUT_SAR_DONE_Msk         0x40000UL
#define LPPASS_MMIO_TR_OUT_SAR_EOS_Pos          19UL
#define LPPASS_MMIO_TR_OUT_SAR_EOS_Msk          0x80000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL1_Pos      20UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL1_Msk      0x100000UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE0_Pos       21UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE0_Msk       0x200000UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE1_Pos       22UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE1_Msk       0x400000UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE2_Pos       23UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE2_Msk       0x800000UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE3_Pos       24UL
#define LPPASS_MMIO_TR_OUT_SAR_RANGE3_Msk       0x1000000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL2_Pos      25UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL2_Msk      0x2000000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL3_Pos      26UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL3_Msk      0x4000000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL4_Pos      27UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL4_Msk      0x8000000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL5_Pos      28UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL5_Msk      0x10000000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL6_Pos      29UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL6_Msk      0x20000000UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL7_Pos      30UL
#define LPPASS_MMIO_TR_OUT_FIFO_LEVEL7_Msk      0x40000000UL
#define LPPASS_MMIO_TR_OUT_AC_Pos               31UL
#define LPPASS_MMIO_TR_OUT_AC_Msk               0x80000000UL
/* LPPASS_MMIO.INTR */
#define LPPASS_MMIO_INTR_CTBL0_COMP0_Pos        0UL
#define LPPASS_MMIO_INTR_CTBL0_COMP0_Msk        0x1UL
#define LPPASS_MMIO_INTR_CTBL0_COMP1_Pos        1UL
#define LPPASS_MMIO_INTR_CTBL0_COMP1_Msk        0x2UL
#define LPPASS_MMIO_INTR_CTBL1_COMP0_Pos        2UL
#define LPPASS_MMIO_INTR_CTBL1_COMP0_Msk        0x4UL
#define LPPASS_MMIO_INTR_CTBL1_COMP1_Pos        3UL
#define LPPASS_MMIO_INTR_CTBL1_COMP1_Msk        0x8UL
#define LPPASS_MMIO_INTR_PTC_COMP0_Pos          4UL
#define LPPASS_MMIO_INTR_PTC_COMP0_Msk          0x10UL
#define LPPASS_MMIO_INTR_PTC_COMP1_Pos          5UL
#define LPPASS_MMIO_INTR_PTC_COMP1_Msk          0x20UL
#define LPPASS_MMIO_INTR_PTC_RANGE0_Pos         6UL
#define LPPASS_MMIO_INTR_PTC_RANGE0_Msk         0x40UL
#define LPPASS_MMIO_INTR_PTC_RANGE1_Pos         7UL
#define LPPASS_MMIO_INTR_PTC_RANGE1_Msk         0x80UL
#define LPPASS_MMIO_INTR_DAC0_RANGE0_Pos        8UL
#define LPPASS_MMIO_INTR_DAC0_RANGE0_Msk        0x100UL
#define LPPASS_MMIO_INTR_DAC0_RANGE1_Pos        9UL
#define LPPASS_MMIO_INTR_DAC0_RANGE1_Msk        0x200UL
#define LPPASS_MMIO_INTR_DAC0_RANGE2_Pos        10UL
#define LPPASS_MMIO_INTR_DAC0_RANGE2_Msk        0x400UL
#define LPPASS_MMIO_INTR_DAC0_EPOCH_Pos         11UL
#define LPPASS_MMIO_INTR_DAC0_EPOCH_Msk         0x800UL
#define LPPASS_MMIO_INTR_DAC0_EMPTY_Pos         12UL
#define LPPASS_MMIO_INTR_DAC0_EMPTY_Msk         0x1000UL
#define LPPASS_MMIO_INTR_DAC1_RANGE0_Pos        13UL
#define LPPASS_MMIO_INTR_DAC1_RANGE0_Msk        0x2000UL
#define LPPASS_MMIO_INTR_DAC1_RANGE1_Pos        14UL
#define LPPASS_MMIO_INTR_DAC1_RANGE1_Msk        0x4000UL
#define LPPASS_MMIO_INTR_DAC1_RANGE2_Pos        15UL
#define LPPASS_MMIO_INTR_DAC1_RANGE2_Msk        0x8000UL
#define LPPASS_MMIO_INTR_DAC1_EPOCH_Pos         16UL
#define LPPASS_MMIO_INTR_DAC1_EPOCH_Msk         0x10000UL
#define LPPASS_MMIO_INTR_DAC1_EMPTY_Pos         17UL
#define LPPASS_MMIO_INTR_DAC1_EMPTY_Msk         0x20000UL
#define LPPASS_MMIO_INTR_SAR_DONE_Pos           18UL
#define LPPASS_MMIO_INTR_SAR_DONE_Msk           0x40000UL
#define LPPASS_MMIO_INTR_SAR_EOS_Pos            19UL
#define LPPASS_MMIO_INTR_SAR_EOS_Msk            0x80000UL
#define LPPASS_MMIO_INTR_SAR_RESULT_Pos         20UL
#define LPPASS_MMIO_INTR_SAR_RESULT_Msk         0x100000UL
#define LPPASS_MMIO_INTR_SAR_RANGE0_Pos         21UL
#define LPPASS_MMIO_INTR_SAR_RANGE0_Msk         0x200000UL
#define LPPASS_MMIO_INTR_SAR_RANGE1_Pos         22UL
#define LPPASS_MMIO_INTR_SAR_RANGE1_Msk         0x400000UL
#define LPPASS_MMIO_INTR_SAR_RANGE2_Pos         23UL
#define LPPASS_MMIO_INTR_SAR_RANGE2_Msk         0x800000UL
#define LPPASS_MMIO_INTR_SAR_RANGE3_Pos         24UL
#define LPPASS_MMIO_INTR_SAR_RANGE3_Msk         0x1000000UL
#define LPPASS_MMIO_INTR_SAR_FIR0_RESULT_Pos    25UL
#define LPPASS_MMIO_INTR_SAR_FIR0_RESULT_Msk    0x2000000UL
#define LPPASS_MMIO_INTR_SAR_FIR1_RESULT_Pos    26UL
#define LPPASS_MMIO_INTR_SAR_FIR1_RESULT_Msk    0x4000000UL
#define LPPASS_MMIO_INTR_RESERVED_Pos           27UL
#define LPPASS_MMIO_INTR_RESERVED_Msk           0x78000000UL
#define LPPASS_MMIO_INTR_AC_Pos                 31UL
#define LPPASS_MMIO_INTR_AC_Msk                 0x80000000UL
/* LPPASS_MMIO.INTR_SET */
#define LPPASS_MMIO_INTR_SET_CTBL0_COMP0_SET_Pos 0UL
#define LPPASS_MMIO_INTR_SET_CTBL0_COMP0_SET_Msk 0x1UL
#define LPPASS_MMIO_INTR_SET_CTBL0_COMP1_SET_Pos 1UL
#define LPPASS_MMIO_INTR_SET_CTBL0_COMP1_SET_Msk 0x2UL
#define LPPASS_MMIO_INTR_SET_CTBL1_COMP0_SET_Pos 2UL
#define LPPASS_MMIO_INTR_SET_CTBL1_COMP0_SET_Msk 0x4UL
#define LPPASS_MMIO_INTR_SET_CTBL1_COMP1_SET_Pos 3UL
#define LPPASS_MMIO_INTR_SET_CTBL1_COMP1_SET_Msk 0x8UL
#define LPPASS_MMIO_INTR_SET_PTC_COMP0_SET_Pos  4UL
#define LPPASS_MMIO_INTR_SET_PTC_COMP0_SET_Msk  0x10UL
#define LPPASS_MMIO_INTR_SET_PTC_COMP1_SET_Pos  5UL
#define LPPASS_MMIO_INTR_SET_PTC_COMP1_SET_Msk  0x20UL
#define LPPASS_MMIO_INTR_SET_PTC_RANGE0_SET_Pos 6UL
#define LPPASS_MMIO_INTR_SET_PTC_RANGE0_SET_Msk 0x40UL
#define LPPASS_MMIO_INTR_SET_PTC_RANGE1_SET_Pos 7UL
#define LPPASS_MMIO_INTR_SET_PTC_RANGE1_SET_Msk 0x80UL
#define LPPASS_MMIO_INTR_SET_DAC0_RANGE0_SET_Pos 8UL
#define LPPASS_MMIO_INTR_SET_DAC0_RANGE0_SET_Msk 0x100UL
#define LPPASS_MMIO_INTR_SET_DAC0_RANGE1_SET_Pos 9UL
#define LPPASS_MMIO_INTR_SET_DAC0_RANGE1_SET_Msk 0x200UL
#define LPPASS_MMIO_INTR_SET_DAC0_RANGE2_SET_Pos 10UL
#define LPPASS_MMIO_INTR_SET_DAC0_RANGE2_SET_Msk 0x400UL
#define LPPASS_MMIO_INTR_SET_DAC0_EPOCH_SET_Pos 11UL
#define LPPASS_MMIO_INTR_SET_DAC0_EPOCH_SET_Msk 0x800UL
#define LPPASS_MMIO_INTR_SET_DAC0_EMPTY_SET_Pos 12UL
#define LPPASS_MMIO_INTR_SET_DAC0_EMPTY_SET_Msk 0x1000UL
#define LPPASS_MMIO_INTR_SET_DAC1_RANGE0_SET_Pos 13UL
#define LPPASS_MMIO_INTR_SET_DAC1_RANGE0_SET_Msk 0x2000UL
#define LPPASS_MMIO_INTR_SET_DAC1_RANGE1_SET_Pos 14UL
#define LPPASS_MMIO_INTR_SET_DAC1_RANGE1_SET_Msk 0x4000UL
#define LPPASS_MMIO_INTR_SET_DAC1_RANGE2_SET_Pos 15UL
#define LPPASS_MMIO_INTR_SET_DAC1_RANGE2_SET_Msk 0x8000UL
#define LPPASS_MMIO_INTR_SET_DAC1_EPOCH_SET_Pos 16UL
#define LPPASS_MMIO_INTR_SET_DAC1_EPOCH_SET_Msk 0x10000UL
#define LPPASS_MMIO_INTR_SET_DAC1_EMPTY_SET_Pos 17UL
#define LPPASS_MMIO_INTR_SET_DAC1_EMPTY_SET_Msk 0x20000UL
#define LPPASS_MMIO_INTR_SET_SAR_DONE_SET_Pos   18UL
#define LPPASS_MMIO_INTR_SET_SAR_DONE_SET_Msk   0x40000UL
#define LPPASS_MMIO_INTR_SET_SAR_EOS_SET_Pos    19UL
#define LPPASS_MMIO_INTR_SET_SAR_EOS_SET_Msk    0x80000UL
#define LPPASS_MMIO_INTR_SET_SAR_RESULT_SET_Pos 20UL
#define LPPASS_MMIO_INTR_SET_SAR_RESULT_SET_Msk 0x100000UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE0_SET_Pos 21UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE0_SET_Msk 0x200000UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE1_SET_Pos 22UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE1_SET_Msk 0x400000UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE2_SET_Pos 23UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE2_SET_Msk 0x800000UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE3_SET_Pos 24UL
#define LPPASS_MMIO_INTR_SET_SAR_RANGE3_SET_Msk 0x1000000UL
#define LPPASS_MMIO_INTR_SET_SAR_FIR0_RESULT_SET_Pos 25UL
#define LPPASS_MMIO_INTR_SET_SAR_FIR0_RESULT_SET_Msk 0x2000000UL
#define LPPASS_MMIO_INTR_SET_SAR_FIR1_RESULT_SET_Pos 26UL
#define LPPASS_MMIO_INTR_SET_SAR_FIR1_RESULT_SET_Msk 0x4000000UL
#define LPPASS_MMIO_INTR_SET_RESERVED_Pos       27UL
#define LPPASS_MMIO_INTR_SET_RESERVED_Msk       0x78000000UL
#define LPPASS_MMIO_INTR_SET_AC_SET_Pos         31UL
#define LPPASS_MMIO_INTR_SET_AC_SET_Msk         0x80000000UL
/* LPPASS_MMIO.INTR_MASK */
#define LPPASS_MMIO_INTR_MASK_CTBL0_COMP0_MASK_Pos 0UL
#define LPPASS_MMIO_INTR_MASK_CTBL0_COMP0_MASK_Msk 0x1UL
#define LPPASS_MMIO_INTR_MASK_CTBL0_COMP1_MASK_Pos 1UL
#define LPPASS_MMIO_INTR_MASK_CTBL0_COMP1_MASK_Msk 0x2UL
#define LPPASS_MMIO_INTR_MASK_CTBL1_COMP0_MASK_Pos 2UL
#define LPPASS_MMIO_INTR_MASK_CTBL1_COMP0_MASK_Msk 0x4UL
#define LPPASS_MMIO_INTR_MASK_CTBL1_COMP1_MASK_Pos 3UL
#define LPPASS_MMIO_INTR_MASK_CTBL1_COMP1_MASK_Msk 0x8UL
#define LPPASS_MMIO_INTR_MASK_PTC_COMP0_MASK_Pos 4UL
#define LPPASS_MMIO_INTR_MASK_PTC_COMP0_MASK_Msk 0x10UL
#define LPPASS_MMIO_INTR_MASK_PTC_COMP1_MASK_Pos 5UL
#define LPPASS_MMIO_INTR_MASK_PTC_COMP1_MASK_Msk 0x20UL
#define LPPASS_MMIO_INTR_MASK_PTC_RANGE0_MASK_Pos 6UL
#define LPPASS_MMIO_INTR_MASK_PTC_RANGE0_MASK_Msk 0x40UL
#define LPPASS_MMIO_INTR_MASK_PTC_RANGE1_MASK_Pos 7UL
#define LPPASS_MMIO_INTR_MASK_PTC_RANGE1_MASK_Msk 0x80UL
#define LPPASS_MMIO_INTR_MASK_DAC0_RANGE0_MASK_Pos 8UL
#define LPPASS_MMIO_INTR_MASK_DAC0_RANGE0_MASK_Msk 0x100UL
#define LPPASS_MMIO_INTR_MASK_DAC0_RANGE1_MASK_Pos 9UL
#define LPPASS_MMIO_INTR_MASK_DAC0_RANGE1_MASK_Msk 0x200UL
#define LPPASS_MMIO_INTR_MASK_DAC0_RANGE2_MASK_Pos 10UL
#define LPPASS_MMIO_INTR_MASK_DAC0_RANGE2_MASK_Msk 0x400UL
#define LPPASS_MMIO_INTR_MASK_DAC0_EPOCH_MASK_Pos 11UL
#define LPPASS_MMIO_INTR_MASK_DAC0_EPOCH_MASK_Msk 0x800UL
#define LPPASS_MMIO_INTR_MASK_DAC0_EMPTY_MASK_Pos 12UL
#define LPPASS_MMIO_INTR_MASK_DAC0_EMPTY_MASK_Msk 0x1000UL
#define LPPASS_MMIO_INTR_MASK_DAC1_RANGE0_MASK_Pos 13UL
#define LPPASS_MMIO_INTR_MASK_DAC1_RANGE0_MASK_Msk 0x2000UL
#define LPPASS_MMIO_INTR_MASK_DAC1_RANGE1_MASK_Pos 14UL
#define LPPASS_MMIO_INTR_MASK_DAC1_RANGE1_MASK_Msk 0x4000UL
#define LPPASS_MMIO_INTR_MASK_DAC1_RANGE2_MASK_Pos 15UL
#define LPPASS_MMIO_INTR_MASK_DAC1_RANGE2_MASK_Msk 0x8000UL
#define LPPASS_MMIO_INTR_MASK_DAC1_EPOCH_MASK_Pos 16UL
#define LPPASS_MMIO_INTR_MASK_DAC1_EPOCH_MASK_Msk 0x10000UL
#define LPPASS_MMIO_INTR_MASK_DAC1_EMPTY_MASK_Pos 17UL
#define LPPASS_MMIO_INTR_MASK_DAC1_EMPTY_MASK_Msk 0x20000UL
#define LPPASS_MMIO_INTR_MASK_SAR_DONE_MASK_Pos 18UL
#define LPPASS_MMIO_INTR_MASK_SAR_DONE_MASK_Msk 0x40000UL
#define LPPASS_MMIO_INTR_MASK_SAR_EOS_MASK_Pos  19UL
#define LPPASS_MMIO_INTR_MASK_SAR_EOS_MASK_Msk  0x80000UL
#define LPPASS_MMIO_INTR_MASK_SAR_RESULT_MASK_Pos 20UL
#define LPPASS_MMIO_INTR_MASK_SAR_RESULT_MASK_Msk 0x100000UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE0_MASK_Pos 21UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE0_MASK_Msk 0x200000UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE1_MASK_Pos 22UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE1_MASK_Msk 0x400000UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE2_MASK_Pos 23UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE2_MASK_Msk 0x800000UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE3_MASK_Pos 24UL
#define LPPASS_MMIO_INTR_MASK_SAR_RANGE3_MASK_Msk 0x1000000UL
#define LPPASS_MMIO_INTR_MASK_SAR_FIR0_RESULT_MASK_Pos 25UL
#define LPPASS_MMIO_INTR_MASK_SAR_FIR0_RESULT_MASK_Msk 0x2000000UL
#define LPPASS_MMIO_INTR_MASK_SAR_FIR1_RESULT_MASK_Pos 26UL
#define LPPASS_MMIO_INTR_MASK_SAR_FIR1_RESULT_MASK_Msk 0x4000000UL
#define LPPASS_MMIO_INTR_MASK_RESERVED_Pos      27UL
#define LPPASS_MMIO_INTR_MASK_RESERVED_Msk      0x78000000UL
#define LPPASS_MMIO_INTR_MASK_AC_MASK_Pos       31UL
#define LPPASS_MMIO_INTR_MASK_AC_MASK_Msk       0x80000000UL
/* LPPASS_MMIO.INTR_MASKED */
#define LPPASS_MMIO_INTR_MASKED_CTBL0_COMP0_MASKED_Pos 0UL
#define LPPASS_MMIO_INTR_MASKED_CTBL0_COMP0_MASKED_Msk 0x1UL
#define LPPASS_MMIO_INTR_MASKED_CTBL0_COMP1_MASKED_Pos 1UL
#define LPPASS_MMIO_INTR_MASKED_CTBL0_COMP1_MASKED_Msk 0x2UL
#define LPPASS_MMIO_INTR_MASKED_CTBL1_COMP0_MASKED_Pos 2UL
#define LPPASS_MMIO_INTR_MASKED_CTBL1_COMP0_MASKED_Msk 0x4UL
#define LPPASS_MMIO_INTR_MASKED_CTBL1_COMP1_MASKED_Pos 3UL
#define LPPASS_MMIO_INTR_MASKED_CTBL1_COMP1_MASKED_Msk 0x8UL
#define LPPASS_MMIO_INTR_MASKED_PTC_COMP0_MASKED_Pos 4UL
#define LPPASS_MMIO_INTR_MASKED_PTC_COMP0_MASKED_Msk 0x10UL
#define LPPASS_MMIO_INTR_MASKED_PTC_COMP1_MASKED_Pos 5UL
#define LPPASS_MMIO_INTR_MASKED_PTC_COMP1_MASKED_Msk 0x20UL
#define LPPASS_MMIO_INTR_MASKED_PTC_RANGE0_MASKED_Pos 6UL
#define LPPASS_MMIO_INTR_MASKED_PTC_RANGE0_MASKED_Msk 0x40UL
#define LPPASS_MMIO_INTR_MASKED_PTC_RANGE1_MASKED_Pos 7UL
#define LPPASS_MMIO_INTR_MASKED_PTC_RANGE1_MASKED_Msk 0x80UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_RANGE0_MASKED_Pos 8UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_RANGE0_MASKED_Msk 0x100UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_RANGE1_MASKED_Pos 9UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_RANGE1_MASKED_Msk 0x200UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_RANGE2_MASKED_Pos 10UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_RANGE2_MASKED_Msk 0x400UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_EPOCH_MASKED_Pos 11UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_EPOCH_MASKED_Msk 0x800UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_EMPTY_MASKED_Pos 12UL
#define LPPASS_MMIO_INTR_MASKED_DAC0_EMPTY_MASKED_Msk 0x1000UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_RANGE0_MASKED_Pos 13UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_RANGE0_MASKED_Msk 0x2000UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_RANGE1_MASKED_Pos 14UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_RANGE1_MASKED_Msk 0x4000UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_RANGE2_MASKED_Pos 15UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_RANGE2_MASKED_Msk 0x8000UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_EPOCH_MASKED_Pos 16UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_EPOCH_MASKED_Msk 0x10000UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_EMPTY_MASKED_Pos 17UL
#define LPPASS_MMIO_INTR_MASKED_DAC1_EMPTY_MASKED_Msk 0x20000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_DONE_MASKED_Pos 18UL
#define LPPASS_MMIO_INTR_MASKED_SAR_DONE_MASKED_Msk 0x40000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_EOS_MASKED_Pos 19UL
#define LPPASS_MMIO_INTR_MASKED_SAR_EOS_MASKED_Msk 0x80000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RESULT_MASKED_Pos 20UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RESULT_MASKED_Msk 0x100000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE0_MASKED_Pos 21UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE0_MASKED_Msk 0x200000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE1_MASKED_Pos 22UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE1_MASKED_Msk 0x400000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE2_MASKED_Pos 23UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE2_MASKED_Msk 0x800000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE3_MASKED_Pos 24UL
#define LPPASS_MMIO_INTR_MASKED_SAR_RANGE3_MASKED_Msk 0x1000000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_FIR0_RESULT_MASKED_Pos 25UL
#define LPPASS_MMIO_INTR_MASKED_SAR_FIR0_RESULT_MASKED_Msk 0x2000000UL
#define LPPASS_MMIO_INTR_MASKED_SAR_FIR1_RESULT_MASKED_Pos 26UL
#define LPPASS_MMIO_INTR_MASKED_SAR_FIR1_RESULT_MASKED_Msk 0x4000000UL
#define LPPASS_MMIO_INTR_MASKED_RESERVED_Pos    27UL
#define LPPASS_MMIO_INTR_MASKED_RESERVED_Msk    0x78000000UL
#define LPPASS_MMIO_INTR_MASKED_AC_MASKED_Pos   31UL
#define LPPASS_MMIO_INTR_MASKED_AC_MASKED_Msk   0x80000000UL
/* LPPASS_MMIO.FIFO_INTR */
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW0_Pos 0UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW0_Msk 0x1UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW1_Pos 1UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW1_Msk 0x2UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW2_Pos 2UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW2_Msk 0x4UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW3_Pos 3UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW3_Msk 0x8UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW4_Pos 4UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW4_Msk 0x10UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW5_Pos 5UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW5_Msk 0x20UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW6_Pos 6UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW6_Msk 0x40UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW7_Pos 7UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_OVERFLOW7_Msk 0x80UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW0_Pos 8UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW0_Msk 0x100UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW1_Pos 9UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW1_Msk 0x200UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW2_Pos 10UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW2_Msk 0x400UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW3_Pos 11UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW3_Msk 0x800UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW4_Pos 12UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW4_Msk 0x1000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW5_Pos 13UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW5_Msk 0x2000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW6_Pos 14UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW6_Msk 0x4000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW7_Pos 15UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_UNDERFLOW7_Msk 0x8000UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_0_Pos    16UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_0_Msk    0x10000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL0_Pos   17UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL0_Msk   0x20000UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_1_Pos    18UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_1_Msk    0xC0000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL1_Pos   20UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL1_Msk   0x100000UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_2_Pos    21UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_2_Msk    0x1E00000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL2_Pos   25UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL2_Msk   0x2000000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL3_Pos   26UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL3_Msk   0x4000000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL4_Pos   27UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL4_Msk   0x8000000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL5_Pos   28UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL5_Msk   0x10000000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL6_Pos   29UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL6_Msk   0x20000000UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL7_Pos   30UL
#define LPPASS_MMIO_FIFO_INTR_FIFO_LEVEL7_Msk   0x40000000UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_3_Pos    31UL
#define LPPASS_MMIO_FIFO_INTR_RESERVED_3_Msk    0x80000000UL
/* LPPASS_MMIO.FIFO_INTR_SET */
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW0_SET_Pos 0UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW0_SET_Msk 0x1UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW1_SET_Pos 1UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW1_SET_Msk 0x2UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW2_SET_Pos 2UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW2_SET_Msk 0x4UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW3_SET_Pos 3UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW3_SET_Msk 0x8UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW4_SET_Pos 4UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW4_SET_Msk 0x10UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW5_SET_Pos 5UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW5_SET_Msk 0x20UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW6_SET_Pos 6UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW6_SET_Msk 0x40UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW7_SET_Pos 7UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_OVERFLOW7_SET_Msk 0x80UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW0_SET_Pos 8UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW0_SET_Msk 0x100UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW1_SET_Pos 9UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW1_SET_Msk 0x200UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW2_SET_Pos 10UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW2_SET_Msk 0x400UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW3_SET_Pos 11UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW3_SET_Msk 0x800UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW4_SET_Pos 12UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW4_SET_Msk 0x1000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW5_SET_Pos 13UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW5_SET_Msk 0x2000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW6_SET_Pos 14UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW6_SET_Msk 0x4000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW7_SET_Pos 15UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_UNDERFLOW7_SET_Msk 0x8000UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_0_Pos 16UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_0_Msk 0x10000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL0_SET_Pos 17UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL0_SET_Msk 0x20000UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_1_Pos 18UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_1_Msk 0xC0000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL1_SET_Pos 20UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL1_SET_Msk 0x100000UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_2_Pos 21UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_2_Msk 0x1E00000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL2_SET_Pos 25UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL2_SET_Msk 0x2000000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL3_SET_Pos 26UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL3_SET_Msk 0x4000000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL4_SET_Pos 27UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL4_SET_Msk 0x8000000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL5_SET_Pos 28UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL5_SET_Msk 0x10000000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL6_SET_Pos 29UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL6_SET_Msk 0x20000000UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL7_SET_Pos 30UL
#define LPPASS_MMIO_FIFO_INTR_SET_FIFO_LEVEL7_SET_Msk 0x40000000UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_3_Pos 31UL
#define LPPASS_MMIO_FIFO_INTR_SET_RESERVED_3_Msk 0x80000000UL
/* LPPASS_MMIO.FIFO_INTR_MASK */
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW0_MASK_Pos 0UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW0_MASK_Msk 0x1UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW1_MASK_Pos 1UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW1_MASK_Msk 0x2UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW2_MASK_Pos 2UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW2_MASK_Msk 0x4UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW3_MASK_Pos 3UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW3_MASK_Msk 0x8UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW4_MASK_Pos 4UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW4_MASK_Msk 0x10UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW5_MASK_Pos 5UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW5_MASK_Msk 0x20UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW6_MASK_Pos 6UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW6_MASK_Msk 0x40UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW7_MASK_Pos 7UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_OVERFLOW7_MASK_Msk 0x80UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW0_MASK_Pos 8UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW0_MASK_Msk 0x100UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW1_MASK_Pos 9UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW1_MASK_Msk 0x200UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW2_MASK_Pos 10UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW2_MASK_Msk 0x400UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW3_MASK_Pos 11UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW3_MASK_Msk 0x800UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW4_MASK_Pos 12UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW4_MASK_Msk 0x1000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW5_MASK_Pos 13UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW5_MASK_Msk 0x2000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW6_MASK_Pos 14UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW6_MASK_Msk 0x4000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW7_MASK_Pos 15UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_UNDERFLOW7_MASK_Msk 0x8000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_0_Pos 16UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_0_Msk 0x10000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL0_MASK_Pos 17UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL0_MASK_Msk 0x20000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_1_Pos 18UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_1_Msk 0xC0000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL1_MASK_Pos 20UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL1_MASK_Msk 0x100000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_2_Pos 21UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_2_Msk 0x1E00000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL2_MASK_Pos 25UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL2_MASK_Msk 0x2000000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL3_MASK_Pos 26UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL3_MASK_Msk 0x4000000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL4_MASK_Pos 27UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL4_MASK_Msk 0x8000000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL5_MASK_Pos 28UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL5_MASK_Msk 0x10000000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL6_MASK_Pos 29UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL6_MASK_Msk 0x20000000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL7_MASK_Pos 30UL
#define LPPASS_MMIO_FIFO_INTR_MASK_FIFO_LEVEL7_MASK_Msk 0x40000000UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_3_Pos 31UL
#define LPPASS_MMIO_FIFO_INTR_MASK_RESERVED_3_Msk 0x80000000UL
/* LPPASS_MMIO.FIFO_INTR_MASKED */
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW0_MASKED_Pos 0UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW0_MASKED_Msk 0x1UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW1_MASKED_Pos 1UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW1_MASKED_Msk 0x2UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW2_MASKED_Pos 2UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW2_MASKED_Msk 0x4UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW3_MASKED_Pos 3UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW3_MASKED_Msk 0x8UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW4_MASKED_Pos 4UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW4_MASKED_Msk 0x10UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW5_MASKED_Pos 5UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW5_MASKED_Msk 0x20UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW6_MASKED_Pos 6UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW6_MASKED_Msk 0x40UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW7_MASKED_Pos 7UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_OVERFLOW7_MASKED_Msk 0x80UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW0_MASKED_Pos 8UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW0_MASKED_Msk 0x100UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW1_MASKED_Pos 9UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW1_MASKED_Msk 0x200UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW2_MASKED_Pos 10UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW2_MASKED_Msk 0x400UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW3_MASKED_Pos 11UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW3_MASKED_Msk 0x800UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW4_MASKED_Pos 12UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW4_MASKED_Msk 0x1000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW5_MASKED_Pos 13UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW5_MASKED_Msk 0x2000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW6_MASKED_Pos 14UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW6_MASKED_Msk 0x4000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW7_MASKED_Pos 15UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_UNDERFLOW7_MASKED_Msk 0x8000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_0_Pos 16UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_0_Msk 0x10000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL0_MASKED_Pos 17UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL0_MASKED_Msk 0x20000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_1_Pos 18UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_1_Msk 0xC0000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL1_MASKED_Pos 20UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL1_MASKED_Msk 0x100000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_2_Pos 21UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_2_Msk 0x1E00000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL2_MASKED_Pos 25UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL2_MASKED_Msk 0x2000000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL3_MASKED_Pos 26UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL3_MASKED_Msk 0x4000000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL4_MASKED_Pos 27UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL4_MASKED_Msk 0x8000000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL5_MASKED_Pos 28UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL5_MASKED_Msk 0x10000000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL6_MASKED_Pos 29UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL6_MASKED_Msk 0x20000000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL7_MASKED_Pos 30UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_FIFO_LEVEL7_MASKED_Msk 0x40000000UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_3_Pos 31UL
#define LPPASS_MMIO_FIFO_INTR_MASKED_RESERVED_3_Msk 0x80000000UL


#endif /* _CYIP_LPPASS_MMIO_V1_1_H_ */


/* [] END OF FILE */
