PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Structures
Data Structures
PDL API Reference » PDM_PCM_v2 (PDM-PCM Converter)

## General Description

## Data Structures
struct | cy_stc_test_config_t
| PDM-PCM Test Mode configuration. More...
struct | cy_stc_pdm_pcm_fir_coeff_t
| PDM-PCM fir coeff_data structure. More...
struct | cy_stc_pdm_pcm_channel_config_t
| PDM-PCM Channel initialization configuration. More...
struct | cy_stc_pdm_pcm_config_v2_t
| PDM-PCM initialization configuration. More...

## Data Structure Documentation

## ◆ cy_stc_test_config_t

struct cy_stc_test_config_t

Data Fields
uint8_t | drive_delay_hi | Interface drive delay on the high phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm
uint8_t | drive_delay_lo | Interface drive delay on the low phase of the PDM interface clock. This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm
uint8_t | mode_hi | Pattern generator mode on the high phase of the PDM interface clock. This field specifies the type of pattern driven by the generator: "0": constant 0's "1": constant 1's "2": alternating 0's and 1's (clock pattern) "3": sine wave
uint8_t | mode_lo | Pattern generator mode on the low phase of the PDM interface clock. This field specifies the type of pattern driven by the generator: "0": constant 0's "1": constant 1's "2": alternating 0's and 1's (clock pattern) "3": sine wave
uint8_t | audio_freq_div | Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency. This field determines the frequency of the sine wave generated by the pattern generator when MODE=3. The formula is below: Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV)
bool | enable | enable

## ◆ cy_stc_pdm_pcm_fir_coeff_t

struct cy_stc_pdm_pcm_fir_coeff_t

Data Fields
int16_t | coeff_data0 | filter taps coefficients data 0
int16_t | coeff_data1 | filter taps coefficients data 1

## ◆ cy_stc_pdm_pcm_channel_config_t

struct cy_stc_pdm_pcm_channel_config_t

Data Fields
uint8_t | sampledelay | Interface sample delay. This field specifies when a PDM value is captured. The value that user assigns here will be incremented by 1 and assigned internally
cy_en_pdm_pcm_word_size_t | wordSize | see cy_en_pdm_pcm_word_size_t
bool | signExtension | Word extension type: 0: extension by zero 1: extension by sign bits
uint8_t | rxFifoTriggerLevel | Fifo interrupt trigger level (in words), range: 0 - 63
bool | fir0_enable | FIR 0 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation): 0: Disabled 1: Enabled
cy_en_pdm_pcm_ch_cic_decimcode_t | cic_decim_code | CIC filter decimation. The CIC filter PCM frequency is a fraction of the PDM frequency. cy_en_pdm_pcm_ch_cic_decimcode_t
cy_en_pdm_pcm_ch_fir0_decimcode_t | fir0_decim_code | FIR filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency. cy_en_pdm_pcm_ch_fir0_decimcode_t
uint8_t | fir0_scale | FIR 0 filter PCM scaling. range 0-31
cy_en_pdm_pcm_ch_fir1_decimcode_t | fir1_decim_code | FIR filter decimation. The FIR filter PCM frequency is a fraction of the FIR0 filter PCM frequency. cy_en_pdm_pcm_ch_fir1_decimcode_t
uint8_t | fir1_scale | FIR 1 filter PCM scaling. range 0 to 31
bool | dc_block_disable | Disables DC BLOCK if set to true. This is for debug only. To be used for test modes 0,1 and 2 in test config ie. if the input is constant 0's or constant 1's or alternating 0's and 1's
cy_en_pdm_pcm_ch_dcblock_coef_t | dc_block_code | DC blocker coefficient. cy_en_pdm_pcm_ch_dcblock_coef_t

## ◆ cy_stc_pdm_pcm_config_v2_t

struct cy_stc_pdm_pcm_config_v2_t

Data Fields
uint8_t | clkDiv | PDM Clock Divider This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. The value that user assigns here will be incremented by 1 and assigned internally. For example, if the clkDiv value is 0, it is internally incremented by 1.
cy_en_pdm_pcm_clock_sel_t | clksel | Interface clock clk_if selection. cy_en_pdm_pcm_clock_sel_t
cy_en_pdm_pcm_halve_rate_sel_t | halverate | Halve rate sampling. cy_en_pdm_pcm_halve_rate_sel_t
uint8_t | route | Specifies what IOSS data input signal "pdm_data[]" is routed to a specific PDM receiver. Each PDM receiver j has a dedicated 1-bit control field: PDM receiver j uses DATA_SEL[j]. The 1-bit field DATA_SEL[j] specification is as follows: '0': PDM receiver j uses data input signal "pdm_data[j]". '1': PDM receiver j uses data input signal "pdm_data[j ^ 1]" (the lower bit of the index is inverted)
uint8_t | fir0_coeff_user_value | FIR 0 filter coefficient enable. User has to configure the coeff values. 0: Disabled. 1: Enabled
uint8_t | fir1_coeff_user_value | FIR 1 filter coefficient enable. User has to configure the coeff values. 0: Disabled. 1: Enabled
cy_stc_pdm_pcm_fir_coeff_t | fir0_coeff[8] | The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7. The FIR filter coefficients have no default values: the coefficients MUST be programmed BEFORE the filter is enabled. By Default FIR0 is disabled and is only used for 8Khz and 16 Khz sample frequencies
cy_stc_pdm_pcm_fir_coeff_t | fir1_coeff[14] | The (symmetric) 55-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR1_COEFF0, ..., FIR1_COEFF13. The (default) FIR filter has built in droop correction. The filter gain (sum of the coefficients) is 13921 and the default coefficients (as specified by FIR1_COEFFx.DATA0/1[13:0]) are: (-2, 21), (26, -17), (-41, 25), (68, -33), (-107, 41), (160, -48), (-230, 54), (325, -56), (-453, 51), (631, -31), (-894, -21), (1326, 172), (-2191, -770), (4859, 8191)