PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

API Reference
EPHY (Ethernet PHY)
PDL API Reference

## General Description

The PHY chip is outside of SoC.

It has 15 IEEE specified standard registers. The EPHY driver implements those standard registers. It provides an API for PHY management abstraction layer.

The functions and other declarations used in this driver are in cy_ephy.h. You can include cy_pdl.h (ModusToolbox only) to get access to all functions and declarations in the PDL.

Note
  Apart from IEEE standard registers, optionally it has some vendor specific extended registers. The EPHY driver does not implement extended registers. Any access to PHY registers can be done by using MAC driver APIs, i.e, Cy_ETHIF_PhyRegRead() and Cy_ETHIF_PhyRegWrite().

# Configuration Considerations

Code snippet for Initializing DP83867IR PHY chip

#define EMAC_MII 0
#define EMAC_RMII 1
#define EMAC_GMII 2
#define EMAC_RGMII 3
#define ETH_LINKSPEED_10 10
#define ETH_LINKSPEED_100 100
#define ETH_LINKSPEED_1000 1000
/********************************************************/
/* PHY Mode Selection */
#define EMAC_INTERFACE EMAC_RGMII
#define EMAC_LINKSPEED ETH_LINKSPEED_1000
/*******************************************************/
/* PHY related constants */
#define PHY_ADDR 0
cy_stc_ephy_t phyObj;
/*******************************************************/
/* MAC related constants */
#define ETH_REG_BASE ETH1
/*******************************************************************************
* Function Name: snippet_Cy_EPHY_Read
****************************************************************************/
void snippet_Cy_EPHY_Read(uint32_t phyId, uint32_t regAddress, uint32_t *value)
{
*value = Cy_ETHIF_PhyRegRead(ETH_REG_BASE, regAddress, phyId);
}
/*******************************************************************************
* Function Name: snippet_Cy_EPHY_Write
****************************************************************************/
void snippet_Cy_EPHY_Write(uint32_t phyId, uint32_t regAddress, uint32_t value)
{
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, regAddress, value, phyId);
}
/*******************************************************************************
* Function Name: snippet_Cy_EPHY_DP83867IR_Init_ExtendedReg
****************************************************************************/
static void snippet_Cy_EPHY_DP83867IR_Init_ExtendedReg(void)
{
#if EMAC_LINKSPEED == ETH_LINKSPEED_100
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x10, 0x5028, PHY_ADDR); /* Disable auto neg for MDI/MDI-X **/
#elif EMAC_LINKSPEED == ETH_LINKSPEED_1000
uint32_t u32ReadData;
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0D, 0x001F, PHY_ADDR); /* Begin write access to Extended register */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0E, 0x0170, PHY_ADDR);
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0D, 0x401F, PHY_ADDR);
u32ReadData = Cy_ETHIF_PhyRegRead(ETH_REG_BASE, (uint8_t)0x0E, PHY_ADDR);
u32ReadData = u32ReadData & 0x0000; /* changing IO impedance on the PHY */
u32ReadData = u32ReadData | 0x010C;
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0E, u32ReadData, PHY_ADDR); /* Enable clock from PHY -> Route it to MCU */
u32ReadData = Cy_ETHIF_PhyRegRead(ETH_REG_BASE, (uint8_t)0x0E, PHY_ADDR);
#else
#endif /* EMAC_LINKSPEED == ETH_LINKSPEED_100 */
/* Disable RGMII by accessing extended register set || Please read data sheet section 8.4.2.1 for procedure in detail */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0D, 0x001F, PHY_ADDR); /* REGCR */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0E, 0x0032, PHY_ADDR); /* ADDAR, 0x0032 RGMII config register */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0D, 0x401F, PHY_ADDR); /* REGCR, will force next write/read access non incremental */
#if EMAC_INTERFACE != EMAC_RGMII
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0E, 0x0000, PHY_ADDR); /* Disable RGMII */
Cy_ETHIF_PhyRegRead(ETH_REG_BASE, (uint8_t)0x0E, PHY_ADDR); /* Read the RGMII mode status */
#else
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0E, 0x00D3, PHY_ADDR); /* Enable Tx and RX Clock delay in RGMII configuration register */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0D, 0x001F, PHY_ADDR); /* REGCR */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0E, 0x0086, PHY_ADDR); /* ADDAR, 0x0086 Delay config register */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0D, 0x401F, PHY_ADDR); /* REGCR, will force next write/read access non incremental */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x0E, 0x0066, PHY_ADDR); /* Adjust Tx and Rn Clock delays in PHY */
#endif /* EMAC_INTERFACE != EMAC_RGMII */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x1F, 0x4000, PHY_ADDR); /* CTRL */
Cy_SysLib_Delay(30); /* Some more delay to get PHY adapted to new interface */
Cy_ETHIF_PhyRegRead(ETH_REG_BASE, (uint8_t)0x11, PHY_ADDR);
}
/*******************************************************************************
* Function Name: snippet_Cy_EPHY_DP83867IR_Init
****************************************************************************/
void snippet_Cy_EPHY_DP83867IR_Init(void)
{
cy_stc_ephy_config_t phyConfig;
/* 1. initialize phy: register phy read and write callback functions */
Cy_EPHY_Init(&phyObj, snippet_Cy_EPHY_Read, snippet_Cy_EPHY_Write);
/* 2. PHY reset before configuring registers */
Cy_EPHY_Reset(&phyObj); /* reset IEEE standard registers */
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, 0x1F, 0x8000, PHY_ADDR); /* Reset vendor specific (DP83867IR) Extended registers */
Cy_SysLib_Delay(30); /* Required some delay to get PHY back to Run state after Reset */
/* 3. Fill PHY configure structure */
phyConfig.duplex = CY_EPHY_DUPLEX_FULL;
phyConfig.speed = EMAC_LINKSPEED;
/* 4. Configure IEEE standard PHY registers */
Cy_EPHY_Configure(&phyObj, &phyConfig);
/* 5. Configure vendor specific (DP83867IR) extended registers */
snippet_Cy_EPHY_DP83867IR_Init_ExtendedReg();
}
cy_stc_ephy_config_t::duplex
uint32_t duplex
suplex mode
Definition: cy_ephy.h:286
cy_stc_ephy_config_t::speed
uint32_t speed
speed
Definition: cy_ephy.h:285
cy_stc_ephy_config_t
EPHY configuration.
Definition: cy_ephy.h:284
cy_stc_ephy_t
This is the private data structure of EPHY.
Definition: cy_ephy.h:273
CY_EPHY_DUPLEX_FULL
@ CY_EPHY_DUPLEX_FULL
full duplex
Definition: cy_ephy.h:241
Cy_EPHY_Reset
cy_en_ephy_status_t Cy_EPHY_Reset(cy_stc_ephy_t *phy)
Soft reset PHY by enabling 15th bit of BMCR register.
Definition: cy_ephy.c:124
Cy_EPHY_Configure
cy_en_ephy_status_t Cy_EPHY_Configure(cy_stc_ephy_t *phy, cy_stc_ephy_config_t *config)
Configures PHY with user provided speed and duplex mode.
Definition: cy_ephy.c:176
Cy_EPHY_Init
cy_en_ephy_status_t Cy_EPHY_Init(cy_stc_ephy_t *phy, cy_ephy_read_handle fnRead, cy_ephy_write_handle fnWrite)
This function initializes the private structure and assign a PHY-read, PHY-write function handle to i...
Definition: cy_ephy.c:54
Cy_ETHIF_PhyRegRead
uint32_t Cy_ETHIF_PhyRegRead(ETH_Type *base, uint8_t u8RegNo, uint8_t u8PHYAddr)
Local function used by other APIs to read the PHY register.
Definition: cy_ethif.c:780
Cy_ETHIF_PhyRegWrite
cy_en_ethif_status_t Cy_ETHIF_PhyRegWrite(ETH_Type *base, uint8_t u8RegNo, uint16_t u16Data, uint8_t u8PHYAddr)
Local function used by other APIs to write the PHY register.
Definition: cy_ethif.c:833
Cy_SysLib_Delay
void Cy_SysLib_Delay(uint32_t milliseconds)
The function delays by the specified number of milliseconds.
Definition: cy_syslib.c:104

# More Information

Refer to the technical reference manual (TRM) and the device datasheet.

# MISRA-C Compliance

The EPHY driver does not have any specific deviation

## API Reference
| Macros
| Functions
| Enumerated Types
| Data Structures