PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Macros
I3C Controller Status
PDL API Reference » I3C (I3C) » Macros

## General Description

Macros to check current I3C controller status returned by Cy_I3C_GetBusStatus function.

Each I3C controller status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status.

## Macros
#define | CY_I3C_CONTROLLER_BUSY (0x00010000UL)
| The controller is busy executing operation started by Cy_I3C_SendCCCCmd or Cy_I3C_ControllerRead or Cy_I3C_ControllerWrite or Cy_I3C_ControllerStartEntDaa Cy_I3C_ControllerSendHdrCmds.
#define | CY_I3C_CONTROLLER_BROADCAST_CCC_WR_XFER (0x00000001UL)
| The controller has currently performed a broadcast CCC write transfer.
#define | CY_I3C_CONTROLLER_DIRECTED_CCC_WR_XFER (0x00000002UL)
| The controller has currently performed a directed CCC write transfer.
#define | CY_I3C_CONTROLLER_DIRECTED_CCC_RD_XFER (0x00000004UL)
| The controller has currently performed a broadcast CCC read transfer.
#define | CY_I3C_CONTROLLER_ENTDAA_XFER (0x00000008UL)
| The controller has currently performed DAA.
#define | CY_I3C_CONTROLLER_I3C_SDR_WR_XFER (0x00000010UL)
| The controller has currently performed a private SDR write to an I3C Target.
#define | CY_I3C_CONTROLLER_I3C_SDR_RD_XFER (0x00000020UL)
| The controller has currently performed a private SDR read from an I3C Target.
#define | CY_I3C_CONTROLLER_I2C_SDR_WR_XFER (0x00000040UL)
| The controller has currently performed a private SDR read to an I2C Target.
#define | CY_I3C_CONTROLLER_I2C_SDR_RD_XFER (0x00000080UL)
| The controller has currently performed a private SDR read from an I2C Target.
#define | CY_I3C_CONTROLLER_HDR_DDR_WR_XFER (0x00000100UL)
| The controller has currently performed a private HDR write in DDR mode.
#define | CY_I3C_CONTROLLER_HDR_DDR_RD_XFER (0x00000200UL)
| The controller has currently performed a private HDR read in DDR mode.
#define | CY_I3C_CONTROLLER_IBI_XFER (0x00000400UL)
| The controller has currently responded to a IBI request.
#define | CY_I3C_CONTROLLER_HALT_STATE (0x00000800UL)
| The controller is in HALT state due to error in the transfer.
#define | CY_I3C_CONTROLLER_XFER_ABORTED (0X00001000UL)
| The transaction was aborted.