PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
CySCB_Type Struct Reference

## Description

Serial Communications Block (SPI/UART/I2C) (CySCB)

## Data Fields
__IOM uint32_t | CTRL
__IM uint32_t | STATUS
__IOM uint32_t | CMD_RESP_CTRL
__IM uint32_t | CMD_RESP_STATUS
__IM uint32_t | RESERVED [4]
__IOM uint32_t | SPI_CTRL
__IM uint32_t | SPI_STATUS
__IOM uint32_t | SPI_TX_CTRL
__IOM uint32_t | SPI_RX_CTRL
__IM uint32_t | RESERVED1 [4]
__IOM uint32_t | UART_CTRL
__IOM uint32_t | UART_TX_CTRL
__IOM uint32_t | UART_RX_CTRL
__IM uint32_t | UART_RX_STATUS
__IOM uint32_t | UART_FLOW_CTRL
__IM uint32_t | RESERVED2 [3]
__IOM uint32_t | I2C_CTRL
__IM uint32_t | I2C_STATUS
__IOM uint32_t | I2C_M_CMD
__IOM uint32_t | I2C_S_CMD
__IOM uint32_t | I2C_CFG
__IOM uint32_t | I2C_STRETCH_CTRL
__IM uint32_t | I2C_STRETCH_STATUS
__IM uint32_t | RESERVED3
__IOM uint32_t | I2C_CTRL_HS
__IM uint32_t | RESERVED4 [95]
__IOM uint32_t | TX_CTRL
__IOM uint32_t | TX_FIFO_CTRL
__IM uint32_t | TX_FIFO_STATUS
__IM uint32_t | RESERVED5 [13]
__OM uint32_t | TX_FIFO_WR
__IM uint32_t | RESERVED6 [47]
__IOM uint32_t | RX_CTRL
__IOM uint32_t | RX_FIFO_CTRL
__IM uint32_t | RX_FIFO_STATUS
__IM uint32_t | RESERVED7
__IOM uint32_t | RX_MATCH
__IM uint32_t | RESERVED8 [11]
__IM uint32_t | RX_FIFO_RD
__IM uint32_t | RX_FIFO_RD_SILENT
__IM uint32_t | RESERVED9 [46]
__IOM uint32_t | EZ_DATA [512]
__IM uint32_t | RESERVED10 [128]
__IM uint32_t | INTR_CAUSE
__IM uint32_t | RESERVED11 [31]
__IOM uint32_t | INTR_I2C_EC
__IM uint32_t | RESERVED12
__IOM uint32_t | INTR_I2C_EC_MASK
__IM uint32_t | INTR_I2C_EC_MASKED
__IM uint32_t | RESERVED13 [12]
__IOM uint32_t | INTR_SPI_EC
__IM uint32_t | RESERVED14
__IOM uint32_t | INTR_SPI_EC_MASK
__IM uint32_t | INTR_SPI_EC_MASKED
__IM uint32_t | RESERVED15 [12]
__IOM uint32_t | INTR_M
__IOM uint32_t | INTR_M_SET
__IOM uint32_t | INTR_M_MASK
__IM uint32_t | INTR_M_MASKED
__IM uint32_t | RESERVED16 [12]
__IOM uint32_t | INTR_S
__IOM uint32_t | INTR_S_SET
__IOM uint32_t | INTR_S_MASK
__IM uint32_t | INTR_S_MASKED
__IM uint32_t | RESERVED17 [12]
__IOM uint32_t | INTR_TX
__IOM uint32_t | INTR_TX_SET
__IOM uint32_t | INTR_TX_MASK
__IM uint32_t | INTR_TX_MASKED
__IM uint32_t | RESERVED18 [12]
__IOM uint32_t | INTR_RX
__IOM uint32_t | INTR_RX_SET
__IOM uint32_t | INTR_RX_MASK
__IM uint32_t | INTR_RX_MASKED

## Field Documentation

## ◆ CTRL

__IOM uint32_t CySCB_Type::CTRL

0x00000000 Generic control

## ◆ STATUS

__IM uint32_t CySCB_Type::STATUS

0x00000004 Generic status

## ◆ CMD_RESP_CTRL

__IOM uint32_t CySCB_Type::CMD_RESP_CTRL

0x00000008 Command/response control

## ◆ CMD_RESP_STATUS

__IM uint32_t CySCB_Type::CMD_RESP_STATUS

0x0000000C Command/response status

## ◆ RESERVED

__IM uint32_t CySCB_Type::RESERVED[4]

## ◆ SPI_CTRL

__IOM uint32_t CySCB_Type::SPI_CTRL

0x00000020 SPI control

## ◆ SPI_STATUS

__IM uint32_t CySCB_Type::SPI_STATUS

0x00000024 SPI status

## ◆ SPI_TX_CTRL

__IOM uint32_t CySCB_Type::SPI_TX_CTRL

0x00000028 SPI transmitter control

## ◆ SPI_RX_CTRL

__IOM uint32_t CySCB_Type::SPI_RX_CTRL

0x0000002C SPI receiver control

## ◆ RESERVED1

__IM uint32_t CySCB_Type::RESERVED1[4]

## ◆ UART_CTRL

__IOM uint32_t CySCB_Type::UART_CTRL

0x00000040 UART control

## ◆ UART_TX_CTRL

__IOM uint32_t CySCB_Type::UART_TX_CTRL

0x00000044 UART transmitter control

## ◆ UART_RX_CTRL

__IOM uint32_t CySCB_Type::UART_RX_CTRL

0x00000048 UART receiver control

## ◆ UART_RX_STATUS

__IM uint32_t CySCB_Type::UART_RX_STATUS

0x0000004C UART receiver status

## ◆ UART_FLOW_CTRL

__IOM uint32_t CySCB_Type::UART_FLOW_CTRL

0x00000050 UART flow control

## ◆ RESERVED2

__IM uint32_t CySCB_Type::RESERVED2[3]

## ◆ I2C_CTRL

__IOM uint32_t CySCB_Type::I2C_CTRL

0x00000060 I2C control

## ◆ I2C_STATUS

__IM uint32_t CySCB_Type::I2C_STATUS

0x00000064 I2C status

## ◆ I2C_M_CMD

__IOM uint32_t CySCB_Type::I2C_M_CMD

0x00000068 I2C master command

## ◆ I2C_S_CMD

__IOM uint32_t CySCB_Type::I2C_S_CMD

0x0000006C I2C slave command

## ◆ I2C_CFG

__IOM uint32_t CySCB_Type::I2C_CFG

0x00000070 I2C configuration

## ◆ I2C_STRETCH_CTRL

__IOM uint32_t CySCB_Type::I2C_STRETCH_CTRL

0x00000074 I2C stretch control

## ◆ I2C_STRETCH_STATUS

__IM uint32_t CySCB_Type::I2C_STRETCH_STATUS

0x00000078 I2C stretch status

## ◆ RESERVED3

__IM uint32_t CySCB_Type::RESERVED3

## ◆ I2C_CTRL_HS

__IOM uint32_t CySCB_Type::I2C_CTRL_HS

0x00000080 I2C control for High-Speed mode

## ◆ RESERVED4

__IM uint32_t CySCB_Type::RESERVED4[95]

## ◆ TX_CTRL

__IOM uint32_t CySCB_Type::TX_CTRL

0x00000200 Transmitter control

## ◆ TX_FIFO_CTRL

__IOM uint32_t CySCB_Type::TX_FIFO_CTRL

0x00000204 Transmitter FIFO control

## ◆ TX_FIFO_STATUS

__IM uint32_t CySCB_Type::TX_FIFO_STATUS

0x00000208 Transmitter FIFO status

## ◆ RESERVED5

__IM uint32_t CySCB_Type::RESERVED5[13]

## ◆ TX_FIFO_WR

__OM uint32_t CySCB_Type::TX_FIFO_WR

0x00000240 Transmitter FIFO write

## ◆ RESERVED6

__IM uint32_t CySCB_Type::RESERVED6[47]

## ◆ RX_CTRL

__IOM uint32_t CySCB_Type::RX_CTRL

0x00000300 Receiver control

## ◆ RX_FIFO_CTRL

__IOM uint32_t CySCB_Type::RX_FIFO_CTRL

0x00000304 Receiver FIFO control

## ◆ RX_FIFO_STATUS

__IM uint32_t CySCB_Type::RX_FIFO_STATUS

0x00000308 Receiver FIFO status

## ◆ RESERVED7

__IM uint32_t CySCB_Type::RESERVED7

## ◆ RX_MATCH

__IOM uint32_t CySCB_Type::RX_MATCH

0x00000310 Slave address and mask

## ◆ RESERVED8

__IM uint32_t CySCB_Type::RESERVED8[11]

## ◆ RX_FIFO_RD

__IM uint32_t CySCB_Type::RX_FIFO_RD

0x00000340 Receiver FIFO read

## ◆ RX_FIFO_RD_SILENT

__IM uint32_t CySCB_Type::RX_FIFO_RD_SILENT

0x00000344 Receiver FIFO read silent

## ◆ RESERVED9

__IM uint32_t CySCB_Type::RESERVED9[46]

## ◆ EZ_DATA

__IOM uint32_t CySCB_Type::EZ_DATA[512]

0x00000400 Memory buffer

## ◆ RESERVED10

__IM uint32_t CySCB_Type::RESERVED10[128]

## ◆ INTR_CAUSE

__IM uint32_t CySCB_Type::INTR_CAUSE

0x00000E00 Active clocked interrupt signal

## ◆ RESERVED11

__IM uint32_t CySCB_Type::RESERVED11[31]

## ◆ INTR_I2C_EC

__IOM uint32_t CySCB_Type::INTR_I2C_EC

0x00000E80 Externally clocked I2C interrupt request

## ◆ RESERVED12

__IM uint32_t CySCB_Type::RESERVED12

## ◆ INTR_I2C_EC_MASK

__IOM uint32_t CySCB_Type::INTR_I2C_EC_MASK

0x00000E88 Externally clocked I2C interrupt mask

## ◆ INTR_I2C_EC_MASKED

__IM uint32_t CySCB_Type::INTR_I2C_EC_MASKED

0x00000E8C Externally clocked I2C interrupt masked

## ◆ RESERVED13

__IM uint32_t CySCB_Type::RESERVED13[12]

## ◆ INTR_SPI_EC

__IOM uint32_t CySCB_Type::INTR_SPI_EC

0x00000EC0 Externally clocked SPI interrupt request

## ◆ RESERVED14

__IM uint32_t CySCB_Type::RESERVED14

## ◆ INTR_SPI_EC_MASK

__IOM uint32_t CySCB_Type::INTR_SPI_EC_MASK

0x00000EC8 Externally clocked SPI interrupt mask

## ◆ INTR_SPI_EC_MASKED

__IM uint32_t CySCB_Type::INTR_SPI_EC_MASKED

0x00000ECC Externally clocked SPI interrupt masked

## ◆ RESERVED15

__IM uint32_t CySCB_Type::RESERVED15[12]

## ◆ INTR_M

__IOM uint32_t CySCB_Type::INTR_M

0x00000F00 Master interrupt request

## ◆ INTR_M_SET

__IOM uint32_t CySCB_Type::INTR_M_SET

0x00000F04 Master interrupt set request

## ◆ INTR_M_MASK

__IOM uint32_t CySCB_Type::INTR_M_MASK

0x00000F08 Master interrupt mask

## ◆ INTR_M_MASKED

__IM uint32_t CySCB_Type::INTR_M_MASKED

0x00000F0C Master interrupt masked request

## ◆ RESERVED16

__IM uint32_t CySCB_Type::RESERVED16[12]

## ◆ INTR_S

__IOM uint32_t CySCB_Type::INTR_S

0x00000F40 Slave interrupt request

## ◆ INTR_S_SET

__IOM uint32_t CySCB_Type::INTR_S_SET

0x00000F44 Slave interrupt set request

## ◆ INTR_S_MASK

__IOM uint32_t CySCB_Type::INTR_S_MASK

0x00000F48 Slave interrupt mask

## ◆ INTR_S_MASKED

__IM uint32_t CySCB_Type::INTR_S_MASKED

0x00000F4C Slave interrupt masked request

## ◆ RESERVED17

__IM uint32_t CySCB_Type::RESERVED17[12]

## ◆ INTR_TX

__IOM uint32_t CySCB_Type::INTR_TX

0x00000F80 Transmitter interrupt request

## ◆ INTR_TX_SET

__IOM uint32_t CySCB_Type::INTR_TX_SET

0x00000F84 Transmitter interrupt set request

## ◆ INTR_TX_MASK

__IOM uint32_t CySCB_Type::INTR_TX_MASK

0x00000F88 Transmitter interrupt mask

## ◆ INTR_TX_MASKED

__IM uint32_t CySCB_Type::INTR_TX_MASKED

0x00000F8C Transmitter interrupt masked request

## ◆ RESERVED18

__IM uint32_t CySCB_Type::RESERVED18[12]

## ◆ INTR_RX

__IOM uint32_t CySCB_Type::INTR_RX

0x00000FC0 Receiver interrupt request

## ◆ INTR_RX_SET

__IOM uint32_t CySCB_Type::INTR_RX_SET

0x00000FC4 Receiver interrupt set request

## ◆ INTR_RX_MASK

__IOM uint32_t CySCB_Type::INTR_RX_MASK

0x00000FC8 Receiver interrupt mask

## ◆ INTR_RX_MASKED

__IM uint32_t CySCB_Type::INTR_RX_MASKED

0x00000FCC Receiver interrupt masked request