PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
I3C_CORE_Type Struct Reference

## Description

registers in I3C IP core (I3C_CORE)

## Data Fields
__IOM uint32_t | DEVICE_CTRL
__IOM uint32_t | DEVICE_ADDR
__IM uint32_t | RESERVED
__OM uint32_t | COMMAND_QUEUE_PORT
__IM uint32_t | RESPONSE_QUEUE_PORT
__IOM uint32_t | TX_RX_DATA_PORT
__IM uint32_t | IBI_QUEUE_DATA
__IOM uint32_t | QUEUE_THLD_CTRL
__IOM uint32_t | DATA_BUFFER_THLD_CTRL
__IOM uint32_t | IBI_QUEUE_CTRL
__IM uint32_t | RESERVED1 [3]
__IOM uint32_t | RESET_CTRL
__IOM uint32_t | TGT_EVENT_STATUS
__IOM uint32_t | INTR_STATUS
__IOM uint32_t | INTR_STATUS_EN
__IOM uint32_t | INTR_SIGNAL_EN
__OM uint32_t | INTR_FORCE
__IM uint32_t | QUEUE_STATUS_LEVEL
__IM uint32_t | DATA_BUFFER_STATUS_LEVEL
__IM uint32_t | PRESENT_STATE
__IM uint32_t | CCC_DEVICE_STATUS
__IM uint32_t | DEVICE_ADDR_TABLE_POINTER
__IOM uint32_t | DEV_CHAR_TABLE_POINTER
__IM uint32_t | RESERVED2 [2]
__IM uint32_t | VENDOR_SPECIFIC_REG_POINTER
__IOM uint32_t | TGT_MIPI_ID_VALUE
__IOM uint32_t | TGT_PID_VALUE
__IOM uint32_t | TGT_CHAR_CTRL
__IM uint32_t | TGT_MAX_LEN
__IM uint32_t | MAX_READ_TURNAROUND
__IOM uint32_t | MAX_DATA_SPEED
__IM uint32_t | RESERVED3
__IOM uint32_t | TGT_INTR_REQ
__IM uint32_t | RESERVED4
__IOM uint32_t | TGT_TIR_DATA
__IM uint32_t | TGT_IBI_RESP
__IM uint32_t | RESERVED5 [5]
__IOM uint32_t | DEVICE_CTRL_EXTENDED
__IOM uint32_t | SCL_I3C_OD_TIMING
__IOM uint32_t | SCL_I3C_PP_TIMING
__IOM uint32_t | SCL_I2C_FM_TIMING
__IOM uint32_t | SCL_I2C_FMP_TIMING
__IM uint32_t | RESERVED6
__IOM uint32_t | SCL_EXT_LCNT_TIMING
__IOM uint32_t | SCL_EXT_TERMN_LCNT_TIMING
__IOM uint32_t | SDA_HOLD_SWITCH_DLY_TIMING
__IOM uint32_t | BUS_FREE_AVAIL_TIMING
__IOM uint32_t | BUS_IDLE_TIMING
__IOM uint32_t | SCL_LOW_CTR_EXT_TIMEOUT
__IM uint32_t | RESERVED7 [3]
__IOM uint32_t | RELEASE_SDA_TIMING
__IM uint32_t | RESERVED8 [16]
__OM uint32_t | EXT_TX_DATA_PORT_0
__OM uint32_t | EXT_TX_DATA_PORT_1
__OM uint32_t | EXT_TX_DATA_PORT_2
__OM uint32_t | EXT_TX_DATA_PORT_3
__IM uint32_t | RESERVED9 [5]
__IM uint32_t | EXT_0_1_DATA_BUF_STS_LEVEL
__IM uint32_t | EXT_2_3_DATA_BUF_STS_LEVEL
__IM uint32_t | RESERVED10 [2]
__IOM uint32_t | EXT_CMD_REG_0
__IOM uint32_t | EXT_CMD_REG_1
__IOM uint32_t | EXT_CMD_REG_2
__IOM uint32_t | EXT_CMD_REG_3
__IM uint32_t | RESERVED11 [4]
__IOM uint32_t | EXT_TX_QUEUE_RESET_CTRL
__IM uint32_t | RESERVED12 [30]
__IM uint32_t | DEV_CHAR_TABLE1_LOC1
__IM uint32_t | DEV_CHAR_TABLE1_LOC2
__IM uint32_t | DEV_CHAR_TABLE1_LOC3
__IM uint32_t | DEV_CHAR_TABLE1_LOC4
__IM uint32_t | DEV_CHAR_TABLE2_LOC1
__IM uint32_t | DEV_CHAR_TABLE2_LOC2
__IM uint32_t | DEV_CHAR_TABLE2_LOC3
__IM uint32_t | DEV_CHAR_TABLE2_LOC4
__IM uint32_t | DEV_CHAR_TABLE3_LOC1
__IM uint32_t | DEV_CHAR_TABLE3_LOC2
__IM uint32_t | DEV_CHAR_TABLE3_LOC3
__IM uint32_t | DEV_CHAR_TABLE3_LOC4
__IM uint32_t | DEV_CHAR_TABLE4_LOC1
__IM uint32_t | DEV_CHAR_TABLE4_LOC2
__IM uint32_t | DEV_CHAR_TABLE4_LOC3
__IM uint32_t | DEV_CHAR_TABLE4_LOC4
__IM uint32_t | DEV_CHAR_TABLE5_LOC1
__IM uint32_t | DEV_CHAR_TABLE5_LOC2
__IM uint32_t | DEV_CHAR_TABLE5_LOC3
__IM uint32_t | DEV_CHAR_TABLE5_LOC4
__IM uint32_t | DEV_CHAR_TABLE6_LOC1
__IM uint32_t | DEV_CHAR_TABLE6_LOC2
__IM uint32_t | DEV_CHAR_TABLE6_LOC3
__IM uint32_t | DEV_CHAR_TABLE6_LOC4
__IM uint32_t | DEV_CHAR_TABLE7_LOC1
__IM uint32_t | DEV_CHAR_TABLE7_LOC2
__IM uint32_t | DEV_CHAR_TABLE7_LOC3
__IM uint32_t | DEV_CHAR_TABLE7_LOC4
__IM uint32_t | DEV_CHAR_TABLE8_LOC1
__IM uint32_t | DEV_CHAR_TABLE8_LOC2
__IM uint32_t | DEV_CHAR_TABLE8_LOC3
__IM uint32_t | DEV_CHAR_TABLE8_LOC4
__IM uint32_t | DEV_CHAR_TABLE9_LOC1
__IM uint32_t | DEV_CHAR_TABLE9_LOC2
__IM uint32_t | DEV_CHAR_TABLE9_LOC3
__IM uint32_t | DEV_CHAR_TABLE9_LOC4
__IM uint32_t | DEV_CHAR_TABLE10_LOC1
__IM uint32_t | DEV_CHAR_TABLE10_LOC2
__IM uint32_t | DEV_CHAR_TABLE10_LOC3
__IM uint32_t | DEV_CHAR_TABLE10_LOC4
__IM uint32_t | DEV_CHAR_TABLE11_LOC1
__IM uint32_t | DEV_CHAR_TABLE11_LOC2
__IM uint32_t | DEV_CHAR_TABLE11_LOC3
__IM uint32_t | DEV_CHAR_TABLE11_LOC4
__IM uint32_t | RESERVED13 [4]
__IOM uint32_t | DEV_ADDR_TABLE_LOC1
__IOM uint32_t | DEV_ADDR_TABLE_LOC2
__IOM uint32_t | DEV_ADDR_TABLE_LOC3
__IOM uint32_t | DEV_ADDR_TABLE_LOC4
__IOM uint32_t | DEV_ADDR_TABLE_LOC5
__IOM uint32_t | DEV_ADDR_TABLE_LOC6
__IOM uint32_t | DEV_ADDR_TABLE_LOC7
__IOM uint32_t | DEV_ADDR_TABLE_LOC8
__IOM uint32_t | DEV_ADDR_TABLE_LOC9
__IOM uint32_t | DEV_ADDR_TABLE_LOC10
__IOM uint32_t | DEV_ADDR_TABLE_LOC11
__IM uint32_t | RESERVED14 [5]

## Field Documentation

## ◆ DEVICE_CTRL

__IOM uint32_t I3C_CORE_Type::DEVICE_CTRL

0x00000000 Device Control Register

## ◆ DEVICE_ADDR

__IOM uint32_t I3C_CORE_Type::DEVICE_ADDR

0x00000004 Device Address Register

## ◆ RESERVED

__IM uint32_t I3C_CORE_Type::RESERVED

## ◆ COMMAND_QUEUE_PORT

__OM uint32_t I3C_CORE_Type::COMMAND_QUEUE_PORT

0x0000000C COMMAND_QUEUE_PORT

## ◆ RESPONSE_QUEUE_PORT

__IM uint32_t I3C_CORE_Type::RESPONSE_QUEUE_PORT

0x00000010 RESPONSE_QUEUE_PORT

## ◆ TX_RX_DATA_PORT

__IOM uint32_t I3C_CORE_Type::TX_RX_DATA_PORT

0x00000014 Transmit/Receive Data Port Register

## ◆ IBI_QUEUE_DATA

__IM uint32_t I3C_CORE_Type::IBI_QUEUE_DATA

0x00000018 In-Band Interrupt Queue Data Register

## ◆ QUEUE_THLD_CTRL

__IOM uint32_t I3C_CORE_Type::QUEUE_THLD_CTRL

0x0000001C Queue Threshold Control Register

## ◆ DATA_BUFFER_THLD_CTRL

__IOM uint32_t I3C_CORE_Type::DATA_BUFFER_THLD_CTRL

0x00000020 Data Buffer Threshold Control Register

## ◆ IBI_QUEUE_CTRL

__IOM uint32_t I3C_CORE_Type::IBI_QUEUE_CTRL

0x00000024 IBI Queue Control Register

## ◆ RESERVED1

__IM uint32_t I3C_CORE_Type::RESERVED1[3]

## ◆ RESET_CTRL

__IOM uint32_t I3C_CORE_Type::RESET_CTRL

0x00000034 Reset Control Register

## ◆ TGT_EVENT_STATUS

__IOM uint32_t I3C_CORE_Type::TGT_EVENT_STATUS

0x00000038 Target Event Status Register

## ◆ INTR_STATUS

__IOM uint32_t I3C_CORE_Type::INTR_STATUS

0x0000003C Reset Control Register

## ◆ INTR_STATUS_EN

__IOM uint32_t I3C_CORE_Type::INTR_STATUS_EN

0x00000040 Interrupt Status Enable Register.

## ◆ INTR_SIGNAL_EN

__IOM uint32_t I3C_CORE_Type::INTR_SIGNAL_EN

0x00000044 Interrupt Signal Enable Register

## ◆ INTR_FORCE

__OM uint32_t I3C_CORE_Type::INTR_FORCE

0x00000048 Interrupt Force Enable Register

## ◆ QUEUE_STATUS_LEVEL

__IM uint32_t I3C_CORE_Type::QUEUE_STATUS_LEVEL

0x0000004C Queue Status Level Register.

## ◆ DATA_BUFFER_STATUS_LEVEL

__IM uint32_t I3C_CORE_Type::DATA_BUFFER_STATUS_LEVEL

0x00000050 Data Buffer Status Level Register.

## ◆ PRESENT_STATE

__IM uint32_t I3C_CORE_Type::PRESENT_STATE

0x00000054 Present State Register

## ◆ CCC_DEVICE_STATUS

__IM uint32_t I3C_CORE_Type::CCC_DEVICE_STATUS

0x00000058 Device Operating Status Register.

## ◆ DEVICE_ADDR_TABLE_POINTER

__IM uint32_t I3C_CORE_Type::DEVICE_ADDR_TABLE_POINTER

0x0000005C Pointer for Device Address Table

## ◆ DEV_CHAR_TABLE_POINTER

__IOM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE_POINTER

0x00000060 Pointer for Device Characteristics Table

## ◆ RESERVED2

__IM uint32_t I3C_CORE_Type::RESERVED2[2]

## ◆ VENDOR_SPECIFIC_REG_POINTER

__IM uint32_t I3C_CORE_Type::VENDOR_SPECIFIC_REG_POINTER

0x0000006C Pointer for Vendor Specific Registers.

## ◆ TGT_MIPI_ID_VALUE

__IOM uint32_t I3C_CORE_Type::TGT_MIPI_ID_VALUE

0x00000070 I3C MIPI Manufacturer ID Register

## ◆ TGT_PID_VALUE

__IOM uint32_t I3C_CORE_Type::TGT_PID_VALUE

0x00000074 I3C Normal Provisional ID Register

## ◆ TGT_CHAR_CTRL

__IOM uint32_t I3C_CORE_Type::TGT_CHAR_CTRL

0x00000078 I3C Target Characteristic Register.

## ◆ TGT_MAX_LEN

__IM uint32_t I3C_CORE_Type::TGT_MAX_LEN

0x0000007C I3C Max Write/Read Length Register.

## ◆ MAX_READ_TURNAROUND

__IM uint32_t I3C_CORE_Type::MAX_READ_TURNAROUND

0x00000080 MXDS Maximum Read Turnaround Time.

## ◆ MAX_DATA_SPEED

__IOM uint32_t I3C_CORE_Type::MAX_DATA_SPEED

0x00000084 Maximum Data Speed Register

## ◆ RESERVED3

__IM uint32_t I3C_CORE_Type::RESERVED3

## ◆ TGT_INTR_REQ

__IOM uint32_t I3C_CORE_Type::TGT_INTR_REQ

0x0000008C Target Interrupt Request Register

## ◆ RESERVED4

__IM uint32_t I3C_CORE_Type::RESERVED4

## ◆ TGT_TIR_DATA

__IOM uint32_t I3C_CORE_Type::TGT_TIR_DATA

0x00000094 Target Interrupt Request Data Register

## ◆ TGT_IBI_RESP

__IM uint32_t I3C_CORE_Type::TGT_IBI_RESP

0x00000098 Target IBI Response Register

## ◆ RESERVED5

__IM uint32_t I3C_CORE_Type::RESERVED5[5]

## ◆ DEVICE_CTRL_EXTENDED

__IOM uint32_t I3C_CORE_Type::DEVICE_CTRL_EXTENDED

0x000000B0 Device Control Extended Register

## ◆ SCL_I3C_OD_TIMING

__IOM uint32_t I3C_CORE_Type::SCL_I3C_OD_TIMING

0x000000B4 SCL I3C Open Drain Timing Register

## ◆ SCL_I3C_PP_TIMING

__IOM uint32_t I3C_CORE_Type::SCL_I3C_PP_TIMING

0x000000B8 SCL I3C Push Pull Timing Register

## ◆ SCL_I2C_FM_TIMING

__IOM uint32_t I3C_CORE_Type::SCL_I2C_FM_TIMING

0x000000BC SCL I2C Fast Mode Timing Register

## ◆ SCL_I2C_FMP_TIMING

__IOM uint32_t I3C_CORE_Type::SCL_I2C_FMP_TIMING

0x000000C0 SCL I2C Fast Mode Plus Timing Register

## ◆ RESERVED6

__IM uint32_t I3C_CORE_Type::RESERVED6

## ◆ SCL_EXT_LCNT_TIMING

__IOM uint32_t I3C_CORE_Type::SCL_EXT_LCNT_TIMING

0x000000C8 SCL Extended Low Count Timing Register.

## ◆ SCL_EXT_TERMN_LCNT_TIMING

__IOM uint32_t I3C_CORE_Type::SCL_EXT_TERMN_LCNT_TIMING

0x000000CC SCL Termination Bit Low Count Timing Register

## ◆ SDA_HOLD_SWITCH_DLY_TIMING

__IOM uint32_t I3C_CORE_Type::SDA_HOLD_SWITCH_DLY_TIMING

0x000000D0 SDA Hold and Mode Switch Delay Timing Register

## ◆ BUS_FREE_AVAIL_TIMING

__IOM uint32_t I3C_CORE_Type::BUS_FREE_AVAIL_TIMING

0x000000D4 Bus Free and Available Timing Register

## ◆ BUS_IDLE_TIMING

__IOM uint32_t I3C_CORE_Type::BUS_IDLE_TIMING

0x000000D8 Bus Idle Timing Register

## ◆ SCL_LOW_CTR_EXT_TIMEOUT

__IOM uint32_t I3C_CORE_Type::SCL_LOW_CTR_EXT_TIMEOUT

0x000000DC SCL LOW Controller Timeout

## ◆ RESERVED7

__IM uint32_t I3C_CORE_Type::RESERVED7[3]

## ◆ RELEASE_SDA_TIMING

__IOM uint32_t I3C_CORE_Type::RELEASE_SDA_TIMING

0x000000EC Release SDA count value.

## ◆ RESERVED8

__IM uint32_t I3C_CORE_Type::RESERVED8[16]

## ◆ EXT_TX_DATA_PORT_0

__OM uint32_t I3C_CORE_Type::EXT_TX_DATA_PORT_0

0x00000130 DWC_mipi_i3c Directed read Vendor-specific CCC 0 TX Data Port Register

## ◆ EXT_TX_DATA_PORT_1

__OM uint32_t I3C_CORE_Type::EXT_TX_DATA_PORT_1

0x00000134 DWC_mipi_i3c Directed read Vendor-specific CCC 1 TX Data Port Register

## ◆ EXT_TX_DATA_PORT_2

__OM uint32_t I3C_CORE_Type::EXT_TX_DATA_PORT_2

0x00000138 DWC_mipi_i3c Directed read Vendor-specific CCC 2 TX Data Port Register

## ◆ EXT_TX_DATA_PORT_3

__OM uint32_t I3C_CORE_Type::EXT_TX_DATA_PORT_3

0x0000013C DWC_mipi_i3c Directed read Vendor-specific CCC 3 TX Data Port Register

## ◆ RESERVED9

__IM uint32_t I3C_CORE_Type::RESERVED9[5]

## ◆ EXT_0_1_DATA_BUF_STS_LEVEL

__IM uint32_t I3C_CORE_Type::EXT_0_1_DATA_BUF_STS_LEVEL

0x00000154 Vendor-specific CCC types 0 and 1 Data Buffer Status Level Register

## ◆ EXT_2_3_DATA_BUF_STS_LEVEL

__IM uint32_t I3C_CORE_Type::EXT_2_3_DATA_BUF_STS_LEVEL

0x00000158 Vendor-specific CCC types 2 and 3 Data Buffer Status Level Register

## ◆ RESERVED10

__IM uint32_t I3C_CORE_Type::RESERVED10[2]

## ◆ EXT_CMD_REG_0

__IOM uint32_t I3C_CORE_Type::EXT_CMD_REG_0

0x00000164 TID, CCC type value and Defining Byte of Vendor-specific CCC 0 Register

## ◆ EXT_CMD_REG_1

__IOM uint32_t I3C_CORE_Type::EXT_CMD_REG_1

0x00000168 TID, CCC type value and Defining Byte of Vendor-specific CCC 1 Register

## ◆ EXT_CMD_REG_2

__IOM uint32_t I3C_CORE_Type::EXT_CMD_REG_2

0x0000016C TID, CCC type value and Defining Byte of Vendor-specific CCC 2 Register

## ◆ EXT_CMD_REG_3

__IOM uint32_t I3C_CORE_Type::EXT_CMD_REG_3

0x00000170 TID, CCC type value and Defining Byte of Vendor-specific CCC 3 Register

## ◆ RESERVED11

__IM uint32_t I3C_CORE_Type::RESERVED11[4]

## ◆ EXT_TX_QUEUE_RESET_CTRL

__IOM uint32_t I3C_CORE_Type::EXT_TX_QUEUE_RESET_CTRL

0x00000184 Individual Vendor CCC buffer reset.

## ◆ RESERVED12

__IM uint32_t I3C_CORE_Type::RESERVED12[30]

## ◆ DEV_CHAR_TABLE1_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE1_LOC1

0x00000200 Device Characteristic Table Location-1 of Device1, MSB_PROVISIONAL_ID

## ◆ DEV_CHAR_TABLE1_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE1_LOC2

0x00000204 Device Characteristic Table Location-2 of Device1, LSB_PROVISIONAL_ID

## ◆ DEV_CHAR_TABLE1_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE1_LOC3

0x00000208 Device Characteristic Table Location-3 of Device1, BCR, DCR

## ◆ DEV_CHAR_TABLE1_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE1_LOC4

0x0000020C Device Characteristic Table Location-4 of Device1, DEV_DYNAMIC_ADDR

## ◆ DEV_CHAR_TABLE2_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE2_LOC1

0x00000210 Device Characteristic Table Location-1 of Device2

## ◆ DEV_CHAR_TABLE2_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE2_LOC2

0x00000214 Device Characteristic Table Location-2 of Device2

## ◆ DEV_CHAR_TABLE2_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE2_LOC3

0x00000218 Device Characteristic Table Location-3 of Device2

## ◆ DEV_CHAR_TABLE2_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE2_LOC4

0x0000021C Device Characteristic Table Location-4 of Device2

## ◆ DEV_CHAR_TABLE3_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE3_LOC1

0x00000220 Device Characteristic Table Location-1 of Device3

## ◆ DEV_CHAR_TABLE3_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE3_LOC2

0x00000224 Device Characteristic Table Location-2 of Device3

## ◆ DEV_CHAR_TABLE3_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE3_LOC3

0x00000228 Device Characteristic Table Location-3 of Device3

## ◆ DEV_CHAR_TABLE3_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE3_LOC4

0x0000022C Device Characteristic Table Location-4 of Device3

## ◆ DEV_CHAR_TABLE4_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE4_LOC1

0x00000230 Device Characteristic Table Location-1 of Device4

## ◆ DEV_CHAR_TABLE4_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE4_LOC2

0x00000234 Device Characteristic Table Location-2 of Device4

## ◆ DEV_CHAR_TABLE4_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE4_LOC3

0x00000238 Device Characteristic Table Location-3 of Device4

## ◆ DEV_CHAR_TABLE4_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE4_LOC4

0x0000023C Device Characteristic Table Location-4 of Device4

## ◆ DEV_CHAR_TABLE5_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE5_LOC1

0x00000240 Device Characteristic Table Location-1 of Device5

## ◆ DEV_CHAR_TABLE5_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE5_LOC2

0x00000244 Device Characteristic Table Location-4 of Device10

## ◆ DEV_CHAR_TABLE5_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE5_LOC3

0x00000248 Device Characteristic Table Location-3 of Device5

## ◆ DEV_CHAR_TABLE5_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE5_LOC4

0x0000024C Device Characteristic Table Location-4 of Device5

## ◆ DEV_CHAR_TABLE6_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE6_LOC1

0x00000250 Device Characteristic Table Location-1 of Device6

## ◆ DEV_CHAR_TABLE6_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE6_LOC2

0x00000254 Device Characteristic Table Location-2 of Device6

## ◆ DEV_CHAR_TABLE6_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE6_LOC3

0x00000258 Device Characteristic Table Location-3 of Device6

## ◆ DEV_CHAR_TABLE6_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE6_LOC4

0x0000025C Device Characteristic Table Location-4 of Device6

## ◆ DEV_CHAR_TABLE7_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE7_LOC1

0x00000260 Device Address Table of Device3

## ◆ DEV_CHAR_TABLE7_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE7_LOC2

0x00000264 Device Characteristic Table Location-2 of Device7

## ◆ DEV_CHAR_TABLE7_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE7_LOC3

0x00000268 Device Characteristic Table Location-3 of Device7

## ◆ DEV_CHAR_TABLE7_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE7_LOC4

0x0000026C Device Characteristic Table Location-4 of Device7

## ◆ DEV_CHAR_TABLE8_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE8_LOC1

0x00000270 Device Characteristic Table Location-1 of Device8

## ◆ DEV_CHAR_TABLE8_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE8_LOC2

0x00000274 Device Characteristic Table Location-2 of Device8

## ◆ DEV_CHAR_TABLE8_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE8_LOC3

0x00000278 Device Characteristic Table Location-3 of Device8

## ◆ DEV_CHAR_TABLE8_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE8_LOC4

0x0000027C Device Address Table of Device10

## ◆ DEV_CHAR_TABLE9_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE9_LOC1

0x00000280 Device Characteristic Table Location-1 of Device9

## ◆ DEV_CHAR_TABLE9_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE9_LOC2

0x00000284 Device Characteristic Table Location-2 of Device9

## ◆ DEV_CHAR_TABLE9_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE9_LOC3

0x00000288 Device Characteristic Table Location-3 of Device9

## ◆ DEV_CHAR_TABLE9_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE9_LOC4

0x0000028C Device Characteristic Table Location-4 of Device9

## ◆ DEV_CHAR_TABLE10_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE10_LOC1

0x00000290 Device Characteristic Table Location-1 of Device10

## ◆ DEV_CHAR_TABLE10_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE10_LOC2

0x00000294 Device Characteristic Table Location-2 of Device10

## ◆ DEV_CHAR_TABLE10_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE10_LOC3

0x00000298 Device Characteristic Table Location-3 of Device10

## ◆ DEV_CHAR_TABLE10_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE10_LOC4

0x0000029C Device Characteristic Table Location-4 of Device10

## ◆ DEV_CHAR_TABLE11_LOC1

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE11_LOC1

0x000002A0 Device Characteristic Table Location-1 of Device11

## ◆ DEV_CHAR_TABLE11_LOC2

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE11_LOC2

0x000002A4 0

## ◆ DEV_CHAR_TABLE11_LOC3

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE11_LOC3

0x000002A8 Device Characteristic Table Location-3 of Device11

## ◆ DEV_CHAR_TABLE11_LOC4

__IM uint32_t I3C_CORE_Type::DEV_CHAR_TABLE11_LOC4

0x000002AC Device Characteristic Table Location-4 of Device11

## ◆ RESERVED13

__IM uint32_t I3C_CORE_Type::RESERVED13[4]

## ◆ DEV_ADDR_TABLE_LOC1

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC1

0x000002C0 Device Address Table of Device1

## ◆ DEV_ADDR_TABLE_LOC2

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC2

0x000002C4 Device Address Table of Device2

## ◆ DEV_ADDR_TABLE_LOC3

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC3

0x000002C8 Device Address Table of Device3

## ◆ DEV_ADDR_TABLE_LOC4

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC4

0x000002CC Device Address Table of Device4

## ◆ DEV_ADDR_TABLE_LOC5

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC5

0x000002D0 Device Address Table of Device5

## ◆ DEV_ADDR_TABLE_LOC6

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC6

0x000002D4 Device Address Table of Device6

## ◆ DEV_ADDR_TABLE_LOC7

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC7

0x000002D8 Device Address Table of Device7

## ◆ DEV_ADDR_TABLE_LOC8

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC8

0x000002DC Device Address Table of Device8

## ◆ DEV_ADDR_TABLE_LOC9

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC9

0x000002E0 Device Address Table of Device9

## ◆ DEV_ADDR_TABLE_LOC10

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC10

0x000002E4 Device Address Table of Device10

## ◆ DEV_ADDR_TABLE_LOC11

__IOM uint32_t I3C_CORE_Type::DEV_ADDR_TABLE_LOC11

0x000002E8 Device Address Table of Device11

## ◆ RESERVED14

__IM uint32_t I3C_CORE_Type::RESERVED14[5]