PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

API Reference
CTB (Continuous Time Block)
PDL API Reference » AUTONOMOUS ANALOG (Autonomous Analog Block)

## General Description

This driver provides API functions to configure the CTB subsystem of the Autonomous Analog.

The CTB block provides operational amplifiers (Opamps) for use in continuous-time signal chains. Each CTB includes two identical Opamps marked OA0 and OA1, a switch matrix for input/output routing, and the resistor ladder for each Opamp gain setting.

For more information on the CTB, refer to the device Architecture Technical Reference Manual (TRM).
For the exact location of the pins, see the device datasheet.

# Static Configuration

The static configuration contains application-specific settings intended to remain static for any Opamp application. The Autonomous Controller (AC) will NOT change the static configuration during operation.

The static configuration of the Opamp includes:

- Power mode;
- Topology;
- Interrupt mode (Comparator only);
- Opamp compensation;
  For configuration settings, see cy_stc_autanalog_ctb_sta_t.

The Opamp topology in the CTB can be configured as follows:

- Comparator (with or without hysteresis);
  Note
    The comparator output is not connected to pin and can only be used as an interrupt or trigger source.
- Programmable Gain Amplifier (PGA, inverting and non-inverting, ground and Vref referenced);
- Trans-impedance Amplifier (TIA);
- Opamp with open loop (Potentiostat);
- Differential Amplifier (DiffAmp);
- Buffer (Voltage follower).

# Dynamic Configuration and State Transition Table

The dynamic configuration structure includes the Opamp settings, which can be modified by the Autonomous Controller (AC) during operation.

The Autonomous Controller is able to modify the following characteristics of the CTB in runtime per settings provided in the State Transition Table:

- Enable/Disable Opamp within the CTB;
- Re-configure the switch matrix:
  - change the connection of the non-inverting Opamp input to the pin or voltage reference;
  - change the connection of the inverting Opamp input to the pin;
  - change the connection of the bottom end of the resistor ladder to the pin or voltage reference;
- Adjust the Opamps gain;

For the configuration settings, see cy_stc_autanalog_ctb_dyn_t and cy_stc_autanalog_stt_ctb_t.

The gain settings for each topology are as follows:

Index | Gain | R-ladder, Ohm | Non-inv PGA | Inv PGA | DiffAmp | TIA
--- | --- | --- | --- | --- | --- | ---
0 | 1.00 | Rin = 192k, Rfb = 0 | 1.00 | 0 | 1.00 | 0k
1 | 1.42 | Rin = 135k, Rfb = 57k | 1.42 | 0.42 | 1.42 | Rfb = 57k
2 | 2.00 | Rin = 96k, Rfb = 96k | 2.00 | 1.00 | 2.00 | Rfb = 96k
3 | 2.78 | Rin = 69k, Rfb = 123k | 2.78 | 1.78 | 2.78 | Rfb = 123k
4 | 4.00 | Rin = 48k, Rfb = 144k | 4.00 | 3.00 | 4.00 | Rfb = 144k
5 | 5.82 | Rin = 33k, Rfb = 159k | 5.82 | 4.82 | 5.82 | Rfb = 159k
6 | 8.00 | Rin = 24k, Rfb = 168k | 8.00 | 7.00 | 8.00 | Rfb = 168k
7 | 10.67 | Rin = 18k, Rfb = 174k | 10.67 | 9.67 | 10.67 | Rfb = 174k
8 | 16.00 | Rin = 12k, Rfb = 180k | 16.00 | 15.00 | 16.00 | Rfb = 180k
9 | 21.33 | Rin = 9k, Rfb = 183k | 21.33 | 20.33 | 21.33 | Rfb = 183k
10 | 32.00 | Rin = 6k, Rfb = 186k | 32.00 | 31.00 | 32.00 | Rfb = 186k

Note
  For more information on the operating principles of the Autonomous Controller (static and dynamic configurations, State transition Table, etc.), refer to the corresponding chapter AC (Autonomous Controller).

# Opamp Input and Output Ranges

The input range of the Opamp can be rail-to-rail if the charge pump is enabled. Without the charge pump, the input range is 0 V to VDDA - 1.5 V. The output range of the Opamp is typically 0.2 V to VDDA - 1.0 V and will depend on the load. See the device datasheet for more details.

Charge Pump | Input Range | Output Range
--- | --- | ---
Enabled | 0 V to VDDA | 0.2 V to VDDA - 0.2 V
Disabled | 0 V to VDDA - 1.5 V | 0.2 V to VDDA - 1.0 V

Note
  The charge pump nominal clock is 4MHz

For the configuration settings, see cy_en_autanalog_ctb_oa_pwr_t.

# Opamp compensation

The Opamp stability is affected by the phase delay caused by the resistance in the Opmap feedback and parasitic capacitance at the Opamp input. Therefore, a 4-bit programmable compensation capacitor block is added in parallel with the resistor in the Opmap feedback to optimize the stability of the Opamp performance. For the configuration settings, see cy_en_autanalog_ctb_oa_fb_cap_t and cy_en_autanalog_ctb_oa_cc_cap_t.

Note
  Use the Autonomous Analog Configurator to define the actual capacitance value required for a particular configuration.

# Sample use case: inverting PGA and Comparator

/* Define the index for CTB0 instance within the Autonomous Analog */
#define CTB0IDX (0U)
/* Define the index for CTB1 instance within the Autonomous Analog */
#define CTB1IDX (1U)
/* Define the index for Opamp0 within the CTB */
#define OPAMP0IDX (0U)
/* Define the index for Opamp1 within the CTB */
#define OPAMP1IDX (1U)
/* Scenario 1:
* CTB0 configured to operate in Ultra-low power mode
* - Opamp0: Inverting the ground-referenced PGA with gain setting 15.00. The charge pump is enabled.
* - Opamp1: Comparator with hysteresis;
* Note: The values for the FB and CC capacitors are given only as examples.
*/
/* The static part of the configuration for the CTB0 */
static cy_stc_autanalog_ctb_sta_t ctb0StaticCfgPGA =
{
/* CTB0, Opamp0 */
.pwrOpamp0 = CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW_RAIL,
.topologyOpamp0 = CY_AUTANALOG_CTB_OA_TOPO_PGA,
.intComp0 = CY_AUTANALOG_CTB_COMP_INT_EDGE_DISABLED,
.capCcOpamp0 = CY_AUTANALOG_CTB_OA_CC_CAP_2_1_pF,
.capFbOpamp0 = CY_AUTANALOG_CTB_OA_FB_CAP_3_5_pF,
/* CTB0, Opamp1 */
.pwrOpamp1 = CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW_RAIL,
.topologyOpamp1 = CY_AUTANALOG_CTB_OA_TOPO_HYST_COMPARATOR,
.intComp1 = CY_AUTANALOG_CTB_COMP_INT_EDGE_BOTH,
.capCcOpamp1 = CY_AUTANALOG_CTB_OA_CC_CAP_0_1_pF,
.capFbOpamp1 = CY_AUTANALOG_CTB_OA_FB_CAP_0_pF,
};
/* The dynamic part of the configuration for the CTB0 */
static cy_stc_autanalog_ctb_dyn_t ctb0DynamicCfgPGA[] =
{
/* CTB0, Opamp0 */
{
.ninvInpPin = CY_AUTANALOG_CTB_OA_NINV_PIN_OA0_P0_OA1_P5,
.ninvInpRef = CY_AUTANALOG_CTB_OA_NINV_REF_DISCONNECT,
.invInpPin = CY_AUTANALOG_CTB_OA_INV_PIN_DISCONNECT,
.resInpPin = CY_AUTANALOG_CTB_OA_RES_PIN_OA0_P1_OA1_P4,
.resInpRef = CY_AUTANALOG_CTB_OA_RES_REF_DISCONNECT,
.sharedMuxIn = CY_AUTANALOG_CTB_OA_MUX_IN_DISCONNECT,
.sharedMuxOut = CY_AUTANALOG_CTB_OA_MUX_OUT_DISCONNECT,
.outToPin = true,
},
/* CTB0, Opamp1 */
{
.ninvInpPin = CY_AUTANALOG_CTB_OA_NINV_PIN_DISCONNECT,
.ninvInpRef = CY_AUTANALOG_CTB_OA_NINV_REF_PRB_OUT0,
.invInpPin = CY_AUTANALOG_CTB_OA_INV_PIN_OA0_P1_OA1_P4,
.resInpPin = CY_AUTANALOG_CTB_OA_RES_PIN_DISCONNECT,
.resInpRef = CY_AUTANALOG_CTB_OA_RES_REF_DISCONNECT,
.sharedMuxIn = CY_AUTANALOG_CTB_OA_MUX_IN_DISCONNECT,
.sharedMuxOut = CY_AUTANALOG_CTB_OA_MUX_OUT_DISCONNECT,
.outToPin = false,
},
};
/* Total configuration for the CTB0 */
cy_stc_autanalog_ctb_t ctb0CfgPGA =
{
.ctbStaCfg = &ctb0StaticCfgPGA,
.ctbDynCfgNum = sizeof(ctb0DynamicCfgPGA) / sizeof(ctb0DynamicCfgPGA[0U]),
.ctbDynCfgArr = ctb0DynamicCfgPGA,
};
/* The State Transition Table configuration for the CTB0 */
cy_stc_autanalog_stt_ctb_t ctb0TtPGA[] =
{
/* The single state configuration in the State Transition Table */
{
/* Enable the configuration for state #0 */
.unlock = true,
/* CTB0, Opamp0 */
.enableOpamp0 = true,
.cfgOpamp0 = OPAMP0IDX,
.gainOpamp0 = CY_AUTANALOG_STT_CTB_OA_GAIN_16_00,
/* CTB0, Opamp1 */
.enableOpamp1 = true,
.cfgOpamp1 = OPAMP1IDX,
.gainOpamp1 = CY_AUTANALOG_STT_CTB_OA_GAIN_1_00,
},
};
cy_stc_autanalog_ctb_t::ctbStaCfg
cy_stc_autanalog_ctb_sta_t * ctbStaCfg
The pointer to a static part of the CTB configuration.
Definition: cy_autanalog_ctb.h:683
cy_stc_autanalog_stt_ctb_t::unlock
bool unlock
CTB Unlock FALSE - Locked: Data from fields enableOpampX, cfgOpampX, gainOpampX will NOT be taken in...
Definition: cy_autanalog_ctb.h:698
cy_stc_autanalog_ctb_dyn_t::ninvInpPin
cy_en_autanalog_ctb_oa_ninv_pin_t ninvInpPin
Connection of the non-inverting input of the Opamp to pin.
Definition: cy_autanalog_ctb.h:663
cy_stc_autanalog_ctb_sta_t::pwrOpamp0
cy_en_autanalog_ctb_oa_pwr_t pwrOpamp0
The Power mode for the Opamp0.
Definition: cy_autanalog_ctb.h:642
cy_stc_autanalog_ctb_dyn_t
Defines the dynamic configuration structure, see Dynamic Configuration and State Transition Table.
Definition: cy_autanalog_ctb.h:662
cy_stc_autanalog_ctb_sta_t
Defines the static configuration structure, see Static Configuration.
Definition: cy_autanalog_ctb.h:641
cy_stc_autanalog_ctb_t
The configuration structure to set up the entire CTB based on static and dynamic configurations.
Definition: cy_autanalog_ctb.h:681
cy_stc_autanalog_stt_ctb_t
The CTB section in the State Transition Table state.
Definition: cy_autanalog_ctb.h:697
CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW_RAIL
@ CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW_RAIL
The Opamp power mode is ULTRA LOW, the charge pump is ON, the Opamp quiescent current is 35uA.
Definition: cy_autanalog_ctb.h:329
CY_AUTANALOG_CTB_OA_NINV_PIN_DISCONNECT
@ CY_AUTANALOG_CTB_OA_NINV_PIN_DISCONNECT
The non-inverting inputs of the Opamps are not connected to pin.
Definition: cy_autanalog_ctb.h:476
CY_AUTANALOG_CTB_OA_NINV_PIN_OA0_P0_OA1_P5
@ CY_AUTANALOG_CTB_OA_NINV_PIN_OA0_P0_OA1_P5
The non-inverting inputs of the Opamps OA0, OA1 are connected to P0 and P5 respectively.
Definition: cy_autanalog_ctb.h:477
CY_AUTANALOG_CTB_OA_RES_PIN_OA0_P1_OA1_P4
@ CY_AUTANALOG_CTB_OA_RES_PIN_OA0_P1_OA1_P4
The bottom ends of the resistor ladders of Opamps OA0, OA1 are connected to P1 and P4 respectively.
Definition: cy_autanalog_ctb.h:534
CY_AUTANALOG_CTB_OA_RES_PIN_DISCONNECT
@ CY_AUTANALOG_CTB_OA_RES_PIN_DISCONNECT
The bottom ends of the resistor ladders are not connected to the pin.
Definition: cy_autanalog_ctb.h:531
CY_AUTANALOG_CTB_OA_MUX_IN_DISCONNECT
@ CY_AUTANALOG_CTB_OA_MUX_IN_DISCONNECT
The input multiplexer is disconnected.
Definition: cy_autanalog_ctb.h:572
CY_AUTANALOG_CTB_COMP_INT_EDGE_DISABLED
@ CY_AUTANALOG_CTB_COMP_INT_EDGE_DISABLED
Disabled, no interrupts detected.
Definition: cy_autanalog_ctb.h:407
CY_AUTANALOG_CTB_COMP_INT_EDGE_BOTH
@ CY_AUTANALOG_CTB_COMP_INT_EDGE_BOTH
Both edges generate an interrupt.
Definition: cy_autanalog_ctb.h:410
CY_AUTANALOG_CTB_OA_FB_CAP_0_pF
@ CY_AUTANALOG_CTB_OA_FB_CAP_0_pF
The capacitor is NOT connected in the feedback loop.
Definition: cy_autanalog_ctb.h:426
CY_AUTANALOG_CTB_OA_FB_CAP_3_5_pF
@ CY_AUTANALOG_CTB_OA_FB_CAP_3_5_pF
The value of the feedback capacitor is 3.5 pF.
Definition: cy_autanalog_ctb.h:431
CY_AUTANALOG_CTB_OA_CC_CAP_2_1_pF
@ CY_AUTANALOG_CTB_OA_CC_CAP_2_1_pF
The value of the compensation capacitor is 2.1 pF.
Definition: cy_autanalog_ctb.h:457
CY_AUTANALOG_CTB_OA_CC_CAP_0_1_pF
@ CY_AUTANALOG_CTB_OA_CC_CAP_0_1_pF
The value of the compensation capacitor is 0.1 pF.
Definition: cy_autanalog_ctb.h:455
CY_AUTANALOG_CTB_OA_TOPO_PGA
@ CY_AUTANALOG_CTB_OA_TOPO_PGA
The Opamp operational topology is Programmable Gain Amplifier.
Definition: cy_autanalog_ctb.h:381
CY_AUTANALOG_CTB_OA_TOPO_HYST_COMPARATOR
@ CY_AUTANALOG_CTB_OA_TOPO_HYST_COMPARATOR
The Opamp operational topology is Comparator with hysteresis.
Definition: cy_autanalog_ctb.h:388
CY_AUTANALOG_CTB_OA_NINV_REF_DISCONNECT
@ CY_AUTANALOG_CTB_OA_NINV_REF_DISCONNECT
The non-inverting input of the Opamp is not connected to Vref.
Definition: cy_autanalog_ctb.h:492
CY_AUTANALOG_CTB_OA_NINV_REF_PRB_OUT0
@ CY_AUTANALOG_CTB_OA_NINV_REF_PRB_OUT0
The non-inverting input is connected to VREF2 (from PRB0)
Definition: cy_autanalog_ctb.h:495
CY_AUTANALOG_STT_CTB_OA_GAIN_1_00
@ CY_AUTANALOG_STT_CTB_OA_GAIN_1_00
The value of the gain is 1.00.
Definition: cy_autanalog_ctb.h:611
CY_AUTANALOG_STT_CTB_OA_GAIN_16_00
@ CY_AUTANALOG_STT_CTB_OA_GAIN_16_00
The value of the gain is 16.00.
Definition: cy_autanalog_ctb.h:619
CY_AUTANALOG_CTB_OA_INV_PIN_DISCONNECT
@ CY_AUTANALOG_CTB_OA_INV_PIN_DISCONNECT
The inverting inputs of the Opamps are not connected to pin.
Definition: cy_autanalog_ctb.h:513
CY_AUTANALOG_CTB_OA_INV_PIN_OA0_P1_OA1_P4
@ CY_AUTANALOG_CTB_OA_INV_PIN_OA0_P1_OA1_P4
The inverting inputs of the Opamps OA0, OA1 are connected to P1 and P4 respectively.
Definition: cy_autanalog_ctb.h:517
CY_AUTANALOG_CTB_OA_MUX_OUT_DISCONNECT
@ CY_AUTANALOG_CTB_OA_MUX_OUT_DISCONNECT
The output multiplexer is disconnected.
Definition: cy_autanalog_ctb.h:593
CY_AUTANALOG_CTB_OA_RES_REF_DISCONNECT
@ CY_AUTANALOG_CTB_OA_RES_REF_DISCONNECT
The bottom end of the resistor ladder is not connected to the voltage reference.
Definition: cy_autanalog_ctb.h:547
cy_en_autanalog_status_t status;
cy_en_autanalog_status_t
cy_en_autanalog_status_t
Return the status for functions of the Autonomous Analog driver.
Definition: cy_autanalog_common.h:109
status = Cy_AutAnalog_CTB_LoadConfig(CTB0IDX, &ctb0CfgPGA);
if (CY_AUTANALOG_SUCCESS != status)
{
/* Error handling */
}
Cy_AutAnalog_CTB_LoadConfig
cy_en_autanalog_status_t Cy_AutAnalog_CTB_LoadConfig(uint8_t ctbIdx, const cy_stc_autanalog_ctb_t *ctbCfg)
Configures the CTB per provided static and dynamic settings.
Definition: cy_autanalog_ctb.c:47
CY_AUTANALOG_SUCCESS
@ CY_AUTANALOG_SUCCESS
Initialization completed successfully.
Definition: cy_autanalog_common.h:110

# Sample use case: non-inverting PGA and Voltage follower

/* Define the index for CTB0 instance within the Autonomous Analog */
#define CTB0IDX (0U)
/* Define the index for CTB1 instance within the Autonomous Analog */
#define CTB1IDX (1U)
/* Define the index for Opamp0 within the CTB */
#define OPAMP0IDX (0U)
/* Define the index for Opamp1 within the CTB */
#define OPAMP1IDX (1U)
/* Scenario 2:
* CTB1 configured to operate in Ultra-low power mode
* - Opamp0: Non-inverting the ground-referenced PGA with gain setting 8.00. The charge pump is enabled.
* - Opamp1: Voltage follower;
* Note: The values for FB and CC capacitors are given only as examples.
*/
/* The static part of the configuration for CTB1 */
static cy_stc_autanalog_ctb_sta_t ctb1StaticCfgPGA =
{
/* CTB1, Opamp0 */
.pwrOpamp0 = CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW,
.topologyOpamp0 = CY_AUTANALOG_CTB_OA_TOPO_PGA,
.intComp0 = CY_AUTANALOG_CTB_COMP_INT_EDGE_DISABLED,
.capCcOpamp0 = CY_AUTANALOG_CTB_OA_CC_CAP_5_1_pF,
.capFbOpamp0 = CY_AUTANALOG_CTB_OA_FB_CAP_7_7_pF,
/* CTB1, Opamp1 */
.pwrOpamp1 = CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW,
.topologyOpamp1 = CY_AUTANALOG_CTB_OA_TOPO_BUFFER,
.intComp1 = CY_AUTANALOG_CTB_COMP_INT_EDGE_DISABLED,
.capCcOpamp1 = CY_AUTANALOG_CTB_OA_CC_CAP_1_1_pF,
.capFbOpamp1 = CY_AUTANALOG_CTB_OA_FB_CAP_0_pF,
};
/* The dynamic part of the configuration for CTB1 */
static cy_stc_autanalog_ctb_dyn_t ctb1DynamicCfgPGA[] =
{
/* CTB1, Opamp0 */
{
.ninvInpPin = CY_AUTANALOG_CTB_OA_NINV_PIN_OA0_P0_OA1_P5,
.ninvInpRef = CY_AUTANALOG_CTB_OA_NINV_REF_DISCONNECT,
.invInpPin = CY_AUTANALOG_CTB_OA_INV_PIN_DISCONNECT,
.resInpPin = CY_AUTANALOG_CTB_OA_RES_PIN_DISCONNECT,
.resInpRef = CY_AUTANALOG_CTB_OA_RES_REF_VSSA,
.sharedMuxIn = CY_AUTANALOG_CTB_OA_MUX_IN_DISCONNECT,
.sharedMuxOut = CY_AUTANALOG_CTB_OA_MUX_OUT_DISCONNECT,
.outToPin = true,
},
/* CTB1, Opamp1 */
{
.ninvInpPin = CY_AUTANALOG_CTB_OA_NINV_PIN_OA0_P0_OA1_P5,
.ninvInpRef = CY_AUTANALOG_CTB_OA_NINV_REF_DISCONNECT,
.invInpPin = CY_AUTANALOG_CTB_OA_INV_PIN_DISCONNECT,
.resInpPin = CY_AUTANALOG_CTB_OA_RES_PIN_DISCONNECT,
.resInpRef = CY_AUTANALOG_CTB_OA_RES_REF_DISCONNECT,
.sharedMuxIn = CY_AUTANALOG_CTB_OA_MUX_IN_DISCONNECT,
.sharedMuxOut = CY_AUTANALOG_CTB_OA_MUX_OUT_DISCONNECT,
.outToPin = true,
},
};
/* The total configuration for CTB1 */
cy_stc_autanalog_ctb_t ctb1CfgPGA =
{
.ctbStaCfg = &ctb1StaticCfgPGA,
.ctbDynCfgNum = sizeof(ctb1DynamicCfgPGA) / sizeof(ctb1DynamicCfgPGA[0U]),
.ctbDynCfgArr = ctb1DynamicCfgPGA,
};
/* The State Transition Table configuration for CTB1 */
cy_stc_autanalog_stt_ctb_t ctb1TtPGA[] =
{
/* The single state configuration in the State Transition Table */
{
/* Enable the configuration for state #0 */
.unlock = true,
/* CTB1, Opamp0 */
.enableOpamp0 = true,
.cfgOpamp0 = OPAMP0IDX,
.gainOpamp0 = CY_AUTANALOG_STT_CTB_OA_GAIN_8_00,
/* CTB1, Opamp1 */
.enableOpamp1 = true,
.cfgOpamp1 = OPAMP1IDX,
.gainOpamp1 = CY_AUTANALOG_STT_CTB_OA_GAIN_1_00,
},
};
CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW
@ CY_AUTANALOG_CTB_OA_PWR_ULTRA_LOW
The Opamp power mode is ULTRA LOW, the charge pump is OFF, the Opamp quiescent current is 15uA.
Definition: cy_autanalog_ctb.h:321
CY_AUTANALOG_CTB_OA_FB_CAP_7_7_pF
@ CY_AUTANALOG_CTB_OA_FB_CAP_7_7_pF
The value of the feedback capacitor is 7.7 pF.
Definition: cy_autanalog_ctb.h:437
CY_AUTANALOG_CTB_OA_CC_CAP_1_1_pF
@ CY_AUTANALOG_CTB_OA_CC_CAP_1_1_pF
The value of the compensation capacitor is 1.1 pF.
Definition: cy_autanalog_ctb.h:456
CY_AUTANALOG_CTB_OA_CC_CAP_5_1_pF
@ CY_AUTANALOG_CTB_OA_CC_CAP_5_1_pF
The value of the compensation capacitor is 5.1 pF.
Definition: cy_autanalog_ctb.h:460
CY_AUTANALOG_CTB_OA_TOPO_BUFFER
@ CY_AUTANALOG_CTB_OA_TOPO_BUFFER
The Opamp operational topology is Voltage follower.
Definition: cy_autanalog_ctb.h:396
CY_AUTANALOG_STT_CTB_OA_GAIN_8_00
@ CY_AUTANALOG_STT_CTB_OA_GAIN_8_00
The value of the gain is 8.00.
Definition: cy_autanalog_ctb.h:617
CY_AUTANALOG_CTB_OA_RES_REF_VSSA
@ CY_AUTANALOG_CTB_OA_RES_REF_VSSA
The bottom end of the resistor ladder is connected to VSSA.
Definition: cy_autanalog_ctb.h:559

Note
  The configuration must only be done while the AC is in High Speed mode, when cy_stc_autanalog_stt_ac_t::lpMode is equal to FALSE.

cy_en_autanalog_status_t status;
status = Cy_AutAnalog_CTB_LoadConfig(CTB1IDX, &ctb1CfgPGA);
if (CY_AUTANALOG_SUCCESS != status)
{
/* Error handling */
}

## API Reference
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