PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Functions
Functions
PDL API Reference » SysClk (System Clock) » Phase Locked Loop (PLL)

## General Description

## Functions
cy_en_sysclk_status_t | Cy_SysClk_PllConfigure (uint32_t clkPath, const cy_stc_pll_config_t *config)
| Configures a given PLL. More...
cy_en_sysclk_status_t | Cy_SysClk_PllManualConfigure (uint32_t clkPath, const cy_stc_pll_manual_config_t *config)
| Manually configures a PLL based on user inputs. More...
cy_en_sysclk_status_t | Cy_SysClk_PllGetConfiguration (uint32_t clkPath, cy_stc_pll_manual_config_t *config)
| Reports configuration settings for a PLL. More...
cy_en_sysclk_status_t | Cy_SysClk_PllEnable (uint32_t clkPath, uint32_t timeoutus)
| Enables the PLL. More...
bool | Cy_SysClk_PllIsEnabled (uint32_t clkPath)
| Reports whether or not the selected PLL is enabled. More...
bool | Cy_SysClk_PllLocked (uint32_t clkPath)
| Reports whether or not the selected PLL is locked. More...
bool | Cy_SysClk_PllLostLock (uint32_t clkPath)
| Reports whether or not the selected PLL lost its lock since the last time this function was called. More...
cy_en_sysclk_status_t | Cy_SysClk_PllDisable (uint32_t clkPath)
| Disables the selected PLL. More...
uint32_t | Cy_SysClk_PllGetFrequency (uint32_t clkPath)
| Returns the output frequency of the PLL. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllLpConfigure (uint32_t pllNum, const cy_stc_pll_config_t *config)
| Configures DPLL-LP. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllLpManualConfigure (uint32_t pllNum, const cy_stc_pll_manual_config_t *config)
| Manually configures a DPLL-LP based on user inputs. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllLpGetConfiguration (uint32_t pllNum, cy_stc_pll_manual_config_t *config)
| Reports configuration settings for DPLL-LP. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllLpEnable (uint32_t pllNum, uint32_t timeoutus)
| Enables the DPLL-LP. More...
bool | Cy_SysClk_DpllLpIsEnabled (uint32_t pllNum)
| Reports whether or not the selected DPLL-LP is enabled. More...
bool | Cy_SysClk_DpllLpLocked (uint32_t pllNum)
| Reports whether or not the selected DPLL-LP is locked. More...
bool | Cy_SysClk_DpllLpLostLock (uint32_t pllNum)
| Reports whether or not the selected DPLL-LP lost its lock since the last time this function was called. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllLpDisable (uint32_t pllNum)
| Disables the selected DPLL-LP. More...
uint32_t | Cy_SysClk_DpllLpGetFrequency (uint32_t pllNum)
| Gets the frequency of DPLL-LP. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllHpConfigure (uint32_t pllNum, const cy_stc_pll_config_t *config)
| Configures DPLL-HP. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllHpManualConfigure (uint32_t pllNum, const cy_stc_pll_manual_config_t *config)
| Manually configures a DPLL-HP based on user inputs. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllHpGetConfiguration (uint32_t pllNum, cy_stc_pll_manual_config_t *config)
| Reports configuration settings for DPLL-HP. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllHpEnable (uint32_t pllNum, uint32_t timeoutus)
| Enables the DPLL-HP. More...
bool | Cy_SysClk_DpllHpIsEnabled (uint32_t pllNum)
| Reports whether or not the selected DPLL-HP is enabled. More...
bool | Cy_SysClk_DpllHpLocked (uint32_t pllNum)
| Reports whether or not the selected DPLL-HP is locked. More...
bool | Cy_SysClk_DpllHpLostLock (uint32_t pllNum)
| Reports whether or not the selected DPLL-HP lost its lock since the last time this function was called. More...
cy_en_sysclk_status_t | Cy_SysClk_DpllHpDisable (uint32_t pllNum)
| Disables the selected DPLL-HP. More...
uint32_t | Cy_SysClk_DpllHpGetFrequency (uint32_t pllNum)
| Gets the frequency of DPLL-HP. More...

## Function Documentation

## ◆ Cy_SysClk_PllConfigure()

cy_en_sysclk_status_t Cy_SysClk_PllConfigure | ( | uint32_t | clkPath,
|  | const cy_stc_pll_config_t * | config
| ) |  |

Configures a given PLL.

The configuration formula used is: Fout = pll_clk * (P / Q / div_out), where: Fout is the desired output frequency pll_clk is the frequency of the input source P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. Q is the reference divider. Its value is in bitfield REFERENCE_DIV. div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.

Parameters

  clkPath | Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
  config | cy_stc_pll_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully configured
  CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call this function after changing the PLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.
  Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.
  Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.
  Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.

Function Usage
  /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
  The IMO sources the PLL at 8MHz. Startup time is not an issue
  and manual configuration of the PLL is not needed. */
  cy_stc_pll_config_t pllConfig =
  {
  /*.inputFreq =*/ 8000000UL, /* PLL input: 8 MHz IMO */
  /*.outputFreq =*/ 100000000UL, /* PLL output: 100 MHz */
  /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
  /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
  };
  /* Set the PLL source (path 1 mux) to be the IMO.
  Note: Path 0 is not valid for PLL. */
  (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
  /* Configure Path 1 PLL with the settings in pllConfig struct */
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &pllConfig))
  {
  /* Insert error handling */
  }
  /* Enable the Path 1 PLL with 2000 microsecond timeout */
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
  {
  /* Insert error handling */
  }
  /* Set the HFCLK0 source to clock path 1 */
  (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
  CY_SYSCLK_CLKHF_IN_CLKPATH1
  @ CY_SYSCLK_CLKHF_IN_CLKPATH1
  clkHf input is Clock Path 1
  Definition: cy_sysclk.h:2528
  Cy_SysClk_ClkHfSetSource
  cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source)
  Selects the source of the selected clkHf.
  Definition: cy_sysclk_v2.c:3244
  CY_SYSCLK_CLKPATH_IN_IMO
  @ CY_SYSCLK_CLKPATH_IN_IMO
  Select the IMO as the output of the path mux.
  Definition: cy_sysclk.h:832
  Cy_SysClk_ClkPathSetSource
  cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source)
  Configures the source for the specified clock path.
  Definition: cy_sysclk_v2.c:4693
  CY_SYSCLK_FLLPLL_OUTPUT_AUTO
  @ CY_SYSCLK_FLLPLL_OUTPUT_AUTO
  Output FLL/PLL input source when not locked, and FLL/PLL output when locked.
  Definition: cy_sysclk.h:993
  Cy_SysClk_PllEnable
  cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus)
  Enables the PLL.
  Definition: cy_sysclk_v2.c:7436
  Cy_SysClk_PllConfigure
  cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config)
  Configures a given PLL.
  Definition: cy_sysclk_v2.c:7304
  cy_stc_pll_config_t
  Structure containing information for configuration of a PLL.
  Definition: cy_sysclk.h:1013
  CY_SYSCLK_SUCCESS
  @ CY_SYSCLK_SUCCESS
  Command completed with no errors.
  Definition: cy_sysclk.h:501

## ◆ Cy_SysClk_PllManualConfigure()

cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure | ( | uint32_t | clkPath,
|  | const cy_stc_pll_manual_config_t * | config
| ) |  |

Manually configures a PLL based on user inputs.

Parameters

  clkPath | Selects which PLL to configure. 1 is the first PLL; 0 is invalid.
  config | cy_stc_pll_manual_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully configured
  CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call this function after changing the PLL input frequency; for example if Cy_SysClk_ClkPathSetSource() is called.
  Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.
  Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.
  Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.

Function Usage
  /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
  The IMO sources the PLL at 8MHz. The characteristics of the
  PLL lock parameters are already known and the startup time
  for the PLL configuration must be minimized. */
  /* Refer to the TRM for the full set of equations used to calculate the parameters */
  cy_stc_pll_manual_config_t pllConfig =
  {
  /*.feedbackDiv =*/ 25u, /* Feedback divider */
  /*.referenceDiv =*/ 1u, /* Reference divider */
  /*.outputDiv =*/ 2u, /* Output divider */
  /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
  /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO, /* Output 100 MHz when locked. Otherwise 8 MHz */
  #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
  /*.fracDiv =*/ 5u, /* FRAC_DIV bits, only for CAT1C devices */
  /*.fracDitherEn =*/ false, /* FRAC_DITHER_EN bit, only for CAT1C devices */
  /*.fracEn =*/ true, /* FRAC_EN bit, only for CAT1C devices */
  /*.sscgDepth =*/ 0, /* SSCG_DEPTH bits, only for CAT1C devices */
  /*.sscgRate =*/ 0, /* SSCG_RATE bits, only for CAT1C devices */
  /*.sscgEn =*/ false, /* SSCG_EN bit, only for CAT1C devices */
  #endif
  };
  /* Set the PLL source (path 1 mux) to be the IMO.
  Note: Path 0 is not valid for PLL. */
  (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
  /* Configure Path 1 PLL with the settings in pllConfig struct */
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1UL, &pllConfig))
  {
  /* Insert error handling */
  }
  /* Enable the path 1 PLL with 2000 microsecond timeout */
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
  {
  /* Insert error handling */
  }
  /* Set the HFCLK0 source to clock path 1 */
  (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
  Cy_SysClk_PllManualConfigure
  cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config)
  Manually configures a PLL based on user inputs.
  Definition: cy_sysclk_v2.c:7348
  cy_stc_pll_manual_config_t
  Structure containing information for manual configuration of a PLL.
  Definition: cy_sysclk.h:1145

## ◆ Cy_SysClk_PllGetConfiguration()

cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration | ( | uint32_t | clkPath,
|  | cy_stc_pll_manual_config_t * | config
| ) |  |

Reports configuration settings for a PLL.

Parameters

  clkPath | Selects which PLL to report. 1 is the first PLL; 0 is invalid.
  config | cy_stc_pll_manual_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL data successfully reported
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Function Usage
  /* Scenario: The calculated PLL parameters need to be checked. */
  cy_stc_pll_config_t autoPllConfig =
  {
  /*.inputFreq =*/ 8000000UL, /* PLL input: 8 MHz IMO */
  /*.outputFreq =*/ 100000000UL, /* PLL output: 100 MHz */
  /*.lfMode =*/ true, /* Enable low frequency mode (VCO = 170~200 MHz) */
  /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO /* Output 100 MHz when locked. Otherwise 8 MHz */
  };
  cy_stc_pll_manual_config_t getPllParams;
  /* Configure Path 1 PLL with the settings in pllConfig struct */
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &autoPllConfig))
  {
  /* Insert error handling */
  }
  /* Retrieve the calculated parameters of Path 1 PLL */
  (void)Cy_SysClk_PllGetConfiguration(1UL, &getPllParams);
  Cy_SysClk_PllGetConfiguration
  cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config)
  Reports configuration settings for a PLL.
  Definition: cy_sysclk_v2.c:7392

## ◆ Cy_SysClk_PllEnable()

cy_en_sysclk_status_t Cy_SysClk_PllEnable | ( | uint32_t | clkPath,
|  | uint32_t | timeoutus
| ) |  |

Enables the PLL.

The PLL should be configured before calling this function.

Parameters

  clkPath | Selects which PLL to enable. 1 is the first PLL; 0 is invalid.
  timeoutus | amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked.

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully enabled
  CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.
  Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.
  Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.
  Take into account the possible platform specific clkHf (and further clocking chain links) frequency limitations while using this API.

Function Usage
  /* Scenario: PLL is configured and needs to be enabled within 2 ms */
  /* Enable the Path 1 PLL with a timeout of 2000 microsecond */
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
  {
  /* Insert error handling */
  }

## ◆ Cy_SysClk_PllIsEnabled()

bool Cy_SysClk_PllIsEnabled | ( | uint32_t | clkPath | ) |

Reports whether or not the selected PLL is enabled.

Parameters

  clkPath | Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns
  false = disabled
  true = enabled

Function Usage
  /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
  PLL is no longer used and hence needs to be disabled. */
  if (Cy_SysClk_PllIsEnabled(1UL))
  {
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
  {
  /* Insert error handling */
  }
  }
  /* The clocks that relied on the PLL will now run off of the clock that
  was used to source the FLL (e.g. IMO or ECO). */
  Cy_SysClk_PllDisable
  cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath)
  Disables the selected PLL.
  Definition: cy_sysclk_v2.c:7259
  Cy_SysClk_PllIsEnabled
  bool Cy_SysClk_PllIsEnabled(uint32_t clkPath)
  Reports whether or not the selected PLL is enabled.
  Definition: cy_sysclk_v2.c:7130

## ◆ Cy_SysClk_PllLocked()

bool Cy_SysClk_PllLocked | ( | uint32_t | clkPath | ) |

Reports whether or not the selected PLL is locked.

Parameters

  clkPath | Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns
  false = not locked
  true = locked

Function Usage
  /* Scenario: PLL is configured and needs to be enabled in a non-blocking way */
  /* Enable the Path 1 PLL without timeout */
  (void)Cy_SysClk_PllEnable(1UL, 0UL);
  /* Check the status of the lock */
  while(Cy_SysClk_PllLocked(1UL))
  {
  /* Perform other actions while the PLL is locking */
  }
  /* PLL Locked. Proceed with further configuration */
  Cy_SysClk_PllLocked
  bool Cy_SysClk_PllLocked(uint32_t clkPath)
  Reports whether or not the selected PLL is locked.
  Definition: cy_sysclk_v2.c:7171

## ◆ Cy_SysClk_PllLostLock()

bool Cy_SysClk_PllLostLock | ( | uint32_t | clkPath | ) |

Reports whether or not the selected PLL lost its lock since the last time this function was called.

Clears the lost lock indicator.

Parameters

  clkPath | Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns
  false = did not lose lock
  true = lost lock

Function Usage
  /* Scenario: Suspicious change in Path 1 clock frequency was encountered
  in the application. Check if the Path 1 PLL lost the lock. */
  if(Cy_SysClk_PllLostLock(1UL))
  {
  /* Insert error handling */
  }
  Cy_SysClk_PllLostLock
  bool Cy_SysClk_PllLostLock(uint32_t clkPath)
  Reports whether or not the selected PLL lost its lock since the last time this function was called.
  Definition: cy_sysclk_v2.c:7215

## ◆ Cy_SysClk_PllDisable()

cy_en_sysclk_status_t Cy_SysClk_PllDisable | ( | uint32_t | clkPath | ) |

Disables the selected PLL.

Parameters

  clkPath | Selects which PLL to disable. 1 is the first PLL; 0 is invalid.

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully disabled
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.
  Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.
  Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.

Side Effects
  This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. If AUTO mode should be used, call Cy_SysClk_PllConfigure or Cy_SysClk_PllManualConfigure before calling Cy_SysClk_PllEnable.

Function Usage
  /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
  PLL is no longer used and hence needs to be disabled. */
  if (Cy_SysClk_PllIsEnabled(1UL))
  {
  if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
  {
  /* Insert error handling */
  }
  }
  /* The clocks that relied on the PLL will now run off of the clock that
  was used to source the FLL (e.g. IMO or ECO). */

## ◆ Cy_SysClk_PllGetFrequency()

uint32_t Cy_SysClk_PllGetFrequency | ( | uint32_t | clkPath | ) |

Returns the output frequency of the PLL.

Parameters

  clkPath | Selects the path on which the PLL frequency has to be obtained.

Returns
  The output frequency of the path PLL.

Note
  If the return value equals zero, that means PLL is disabled.

Function Usage
  uint32_t freq = Cy_SysClk_PllGetFrequency(1UL);
  (void) freq; /* Suppress 'unused variable' warning */
  Cy_SysClk_PllGetFrequency
  uint32_t Cy_SysClk_PllGetFrequency(uint32_t clkPath)
  Returns the output frequency of the PLL.
  Definition: cy_sysclk_v2.c:7480

## ◆ Cy_SysClk_DpllLpConfigure()

cy_en_sysclk_status_t Cy_SysClk_DpllLpConfigure | ( | uint32_t | pllNum,
|  | const cy_stc_pll_config_t * | config
| ) |  |

Configures DPLL-LP.

The configuration formula used is: Fout = pll_clk * (P / Q / div_out), where: Fout is the desired output frequency pll_clk is the frequency of the input source P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. Q is the reference divider. Its value is in bitfield REFERENCE_DIV. div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.

Parameters

  pllNum | Selects which DPLL-LP to configure
  config | cy_stc_pll_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully configured
  CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call this function after changing the PLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.
  Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

## ◆ Cy_SysClk_DpllLpManualConfigure()

cy_en_sysclk_status_t Cy_SysClk_DpllLpManualConfigure | ( | uint32_t | pllNum,
|  | const cy_stc_pll_manual_config_t * | config
| ) |  |

Manually configures a DPLL-LP based on user inputs.

Parameters

  pllNum | Selects which DPLL-LP to configure.
  config | cy_stc_pll_manual_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully configured
  CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call this function after changing the PLL input frequency; for example if Cy_SysClk_ClkPathSetSource() is called.
  Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

## ◆ Cy_SysClk_DpllLpGetConfiguration()

cy_en_sysclk_status_t Cy_SysClk_DpllLpGetConfiguration | ( | uint32_t | pllNum,
|  | cy_stc_pll_manual_config_t * | config
| ) |  |

Reports configuration settings for DPLL-LP.

Parameters

  pllNum | Selects which DPLL-LP to report.
  config | cy_stc_pll_manual_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL data successfully reported
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

## ◆ Cy_SysClk_DpllLpEnable()

cy_en_sysclk_status_t Cy_SysClk_DpllLpEnable | ( | uint32_t | pllNum,
|  | uint32_t | timeoutus
| ) |  |

Enables the DPLL-LP.

The PLL should be configured before calling this function.

Parameters

  pllNum | Selects which DPLL-LP to enable.
  timeoutus | amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked.

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully enabled
  CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

## ◆ Cy_SysClk_DpllLpIsEnabled()

bool Cy_SysClk_DpllLpIsEnabled | ( | uint32_t | pllNum | ) |

Reports whether or not the selected DPLL-LP is enabled.

Parameters

  pllNum | Selects which DPLL-LP to check.

Returns
  false = disabled
  true = enabled

## ◆ Cy_SysClk_DpllLpLocked()

bool Cy_SysClk_DpllLpLocked | ( | uint32_t | pllNum | ) |

Reports whether or not the selected DPLL-LP is locked.

Parameters

  pllNum | Selects which DPLL-LP to check.

Returns
  false = not locked
  true = locked

## ◆ Cy_SysClk_DpllLpLostLock()

bool Cy_SysClk_DpllLpLostLock | ( | uint32_t | pllNum | ) |

Reports whether or not the selected DPLL-LP lost its lock since the last time this function was called.

Clears the lost lock indicator.

Parameters

  pllNum | Selects which DPLL-LP to check.

Returns
  false = did not lose lock
  true = lost lock

## ◆ Cy_SysClk_DpllLpDisable()

cy_en_sysclk_status_t Cy_SysClk_DpllLpDisable | ( | uint32_t | pllNum | ) |

Disables the selected DPLL-LP.

Parameters

  pllNum | Selects which DPLL-LP to disable.

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully disabled
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

Side Effects
  This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. If AUTO mode should be used, call Cy_SysClk_DpllLpConfigure or Cy_SysClk_DpllLpManualConfigure before calling Cy_SysClk_DpllLpEnable.

## ◆ Cy_SysClk_DpllLpGetFrequency()

uint32_t Cy_SysClk_DpllLpGetFrequency | ( | uint32_t | pllNum | ) |

Gets the frequency of DPLL-LP.

Parameters

  pllNum | Selects which DPLL-LP to check.

Returns
  DPLL-LP Frequency

## ◆ Cy_SysClk_DpllHpConfigure()

cy_en_sysclk_status_t Cy_SysClk_DpllHpConfigure | ( | uint32_t | pllNum,
|  | const cy_stc_pll_config_t * | config
| ) |  |

Configures DPLL-HP.

The configuration formula used is: Fout = (pll_clk * NDIV) / (PDIV * KDIV), where: Fout is the desired output frequency pll_clk is the frequency of the input source NDIV is the Ratio between DCO frequency and reference frequency. PDIV is the reference divider. KDIV is the post divider.

Parameters

  pllNum | Selects which DPLL-HP to configure
  config | cy_stc_pll_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully configured
  CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call this function after changing the PLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.
  Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

## ◆ Cy_SysClk_DpllHpManualConfigure()

cy_en_sysclk_status_t Cy_SysClk_DpllHpManualConfigure | ( | uint32_t | pllNum,
|  | const cy_stc_pll_manual_config_t * | config
| ) |  |

Manually configures a DPLL-HP based on user inputs.

Parameters

  pllNum | Selects which DPLL-HP to configure.
  config | cy_stc_pll_manual_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully configured
  CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call this function after changing the PLL input frequency; for example if Cy_SysClk_ClkPathSetSource() is called.
  Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

## ◆ Cy_SysClk_DpllHpGetConfiguration()

cy_en_sysclk_status_t Cy_SysClk_DpllHpGetConfiguration | ( | uint32_t | pllNum,
|  | cy_stc_pll_manual_config_t * | config
| ) |  |

Reports configuration settings for DPLL-HP.

Parameters

  pllNum | Selects which DPLL-HP to report.
  config | cy_stc_pll_manual_config_t

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL data successfully reported
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

## ◆ Cy_SysClk_DpllHpEnable()

cy_en_sysclk_status_t Cy_SysClk_DpllHpEnable | ( | uint32_t | pllNum,
|  | uint32_t | timeoutus
| ) |  |

Enables the DPLL-HP.

The PLL should be configured before calling this function.

Parameters

  pllNum | Selects which DPLL-HP to enable.
  timeoutus | amount of time in microseconds to wait for the PLL to lock. If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked.

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully enabled
  CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

## ◆ Cy_SysClk_DpllHpIsEnabled()

bool Cy_SysClk_DpllHpIsEnabled | ( | uint32_t | pllNum | ) |

Reports whether or not the selected DPLL-HP is enabled.

Parameters

  pllNum | Selects which DPLL-HP to check.

Returns
  false = disabled
  true = enabled

## ◆ Cy_SysClk_DpllHpLocked()

bool Cy_SysClk_DpllHpLocked | ( | uint32_t | pllNum | ) |

Reports whether or not the selected DPLL-HP is locked.

Parameters

  pllNum | Selects which DPLL-HP to check.

Returns
  false = not locked
  true = locked

## ◆ Cy_SysClk_DpllHpLostLock()

bool Cy_SysClk_DpllHpLostLock | ( | uint32_t | pllNum | ) |

Reports whether or not the selected DPLL-HP lost its lock since the last time this function was called.

Clears the lost lock indicator.

Parameters

  pllNum | Selects which DPLL-HP to check.

Returns
  false = did not lose lock
  true = lost lock

## ◆ Cy_SysClk_DpllHpDisable()

cy_en_sysclk_status_t Cy_SysClk_DpllHpDisable | ( | uint32_t | pllNum | ) |

Disables the selected DPLL-HP.

Parameters

  pllNum | Selects which DPLL-HP to disable.

Returns
  Error / status code:
  CY_SYSCLK_SUCCESS - PLL successfully disabled
  CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled
  CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present

Note
  Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

Side Effects
  This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. If AUTO mode should be used, call Cy_SysClk_DpllHpConfigure or Cy_SysClk_DpllHpManualConfigure before calling Cy_SysClk_DpllHpEnable.

## ◆ Cy_SysClk_DpllHpGetFrequency()

uint32_t Cy_SysClk_DpllHpGetFrequency | ( | uint32_t | pllNum | ) |

Gets the frequency of DPLL-HP.

Parameters

  pllNum | Selects which DPLL-HP to check.

Returns
  DPLL-LP Frequency