PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
I3C_Type Struct Reference

## Description

I3C controller top (I3C)

## Data Fields
I3C_CORE_Type | CORE
__IM uint32_t | RESERVED [64]
__IOM uint32_t | CTRL
__IM uint32_t | RESERVED1 [5]
__IM uint32_t | TGT_STATUS
__IM uint32_t | RESERVED2 [2]
__IOM uint32_t | CCC_GETSTATUS
__IM uint32_t | RESERVED3
__IOM uint32_t | TIMING_CNT_CTRL
__IM uint32_t | TIMING_CNT0
__IM uint32_t | TIMING_CNT1

## Field Documentation

## ◆ CORE

I3C_CORE_Type I3C_Type::CORE

0x00000000 registers in I3C IP core

## ◆ RESERVED

__IM uint32_t I3C_Type::RESERVED[64]

## ◆ CTRL

__IOM uint32_t I3C_Type::CTRL

0x00000400 I3C Block Control

## ◆ RESERVED1

__IM uint32_t I3C_Type::RESERVED1[5]

## ◆ TGT_STATUS

__IM uint32_t I3C_Type::TGT_STATUS

0x00000418 This register provides additional status information when functioning as a Target.

## ◆ RESERVED2

__IM uint32_t I3C_Type::RESERVED2[2]

## ◆ CCC_GETSTATUS

__IOM uint32_t I3C_Type::CCC_GETSTATUS

0x00000424 This register provides additional information on GETSTATUS CCCs received when functioning as a Target.

## ◆ RESERVED3

__IM uint32_t I3C_Type::RESERVED3

## ◆ TIMING_CNT_CTRL

__IOM uint32_t I3C_Type::TIMING_CNT_CTRL

0x0000042C Controls the Counter used for timestamping I3C-relevant events, especially when communicating with Asynchronous Timing Control Mode 0 enabled.

## ◆ TIMING_CNT0

__IM uint32_t I3C_Type::TIMING_CNT0

0x00000430 Most Significant Bits of the Counter

## ◆ TIMING_CNT1

__IM uint32_t I3C_Type::TIMING_CNT1

0x00000434 Least Significant Bits of the Counter