/* ##########################  GIC functions  ###################################### */
/**
\defgroup GIC_functions Generic Interrupt Controller Functions
\ingroup CMSIS_Core_FunctionInterface
\brief The Generic Interrupt Controller Functions grant access to the configuration, control and
status registers of the Generic Interrupt Controller (GIC).

Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069c/index.html">Generic Interrupt Controller Architecture Specificaton</a>.

The following table shows the register naming of CMSIS in correlation with various technical reference manuals.

| CMSIS Register Name                                                  | Cortex-A5 TRM  | Cortex-A7 TRM    | Cortex-A9 TRM  | 
| :------------------------------------------------------------------- | :------------- | :--------------- | :------------- | 
| <b>GIC Distributor</b>                                               |                |                  |                |
| \ref GICDistributor_Type::CTLR "GICDistributor->CTLR"                | ICDDCR         | GICD_CTLR        | ICDDCR         | 
| \ref GICDistributor_Type::TYPER "GICDistributor->TYPER"              | ICDICTR        | GICD_TYPER       | ICDICTR        | 
| \ref GICDistributor_Type::IIDR "GICDistributor->IIDR"                | ICDIIDR        | GICD_IIDR        | ICDIIDR        | 
| \ref GICDistributor_Type::STATUSR "GICDistributor->STATUSR"          |                |                  |                | 
| \ref GICDistributor_Type::SETSPI_NSR "GICDistributor->SETSPI_NSR"    |                |                  |                | 
| \ref GICDistributor_Type::CLRSPI_NSR "GICDistributor->CLRSPI_NSR"    |                |                  |                | 
| \ref GICDistributor_Type::IGROUPR "GICDistributor->IGROUPR[]"        | ICDISR         | GICD_IGROUPRn    | ICDISRn        | 
| \ref GICDistributor_Type::ISENABLER "GICDistributor->ISENABLER[]"    | ICDISER        | GICD_ISENABLERn  | ICDISERn       | 
| \ref GICDistributor_Type::ICENABLER "GICDistributor->ICENABLER[]"    | ICDICER        | GICD_ICENABLERn  | ICDICERn       | 
| \ref GICDistributor_Type::ISPENDR "GICDistributor->ISPENDR[]"        | ICDISPR        | GICD_ISPENDRn    | ICDISPRn       | 
| \ref GICDistributor_Type::ICPENDR "GICDistributor->ICPENDR[]"        | ICDICPR        | GICD_ICPENDRn    | ICDICPRn       | 
| \ref GICDistributor_Type::ISACTIVER "GICDistributor->ISACTIVER[]"    | ICDABR         | GICD_ISACTIVERn  | ICDABRn        | 
| \ref GICDistributor_Type::ICACTIVER "GICDistributor->ICACTIVER[]"    |                | GICD_ICACTIVERn  |                | 
| \ref GICDistributor_Type::IPRIORITYR "GICDistributor->IPRIORITYR[]"  | ICDIPR         | GICD_IPRIORITYRn | ICDIPRn        | 
| \ref GICDistributor_Type::ITARGETSR "GICDistributor->ITARGETSR[]"    | ICDIPTR        | GICD_ITARGETSRn  | ICDIPTRn       | 
| \ref GICDistributor_Type::ICFGR "GICDistributor->ICFGR[]"            | ICDICFR        | GICD_ICFGRn      | ICDICFRn       | 
| \ref GICDistributor_Type::IGRPMODR "GICDistributor->IGRPMODR[0]"     | ICDPPIS        | GICD_PPISR       | ppi_status     | 
| \ref GICDistributor_Type::IGRPMODR "GICDistributor->IGRPMODR[31:1]"  | ICDSPIS        | GICD_SPISRn      | spi_status     | 
| \ref GICDistributor_Type::NSACR "GICDistributor->NSACR[]"            |                |                  |                | 
| \ref GICDistributor_Type::SGIR "GICDistributor->SGIR"                | ICDSGIR        | GICD_SGIR        | ICDSGIR        |
| \ref GICDistributor_Type::CPENDSGIR "GICDistributor->CPENDSGIR[]"    |                | GICD_CPENDSGIRn  |                | 
| \ref GICDistributor_Type::SPENDSGIR "GICDistributor->SPENDSGIR[]"    |                | GICD_SPENDSGIRn  |                | 
| \ref GICDistributor_Type::IROUTER "GICDistributor->IROUTER[]"        |                |                  |                | 
| <b>GIC Interface</b>                                                 |                |                  |                |
| \ref GICInterface_Type::CTLR "GICInterface->CTLR"                    | ICPICR         | GICC_CTLR        | ICCICR         | 
| \ref GICInterface_Type::PMR "GICInterface->PMR"                      | ICCIPMR        | GICC_PMRn        | ICCPMR         | 
| \ref GICInterface_Type::BPR "GICInterface->BPR"                      | ICCBPR         | GICC_BPR         | ICCBPR         | 
| \ref GICInterface_Type::IAR "GICInterface->IAR"                      | ICCIAR         | GICC_IAR         | ICCIAR         | 
| \ref GICInterface_Type::EOIR "GICInterface->EOIR"                    | ICCEOIR        | GICC_EOIR        | ICCEOIR        | 
| \ref GICInterface_Type::RPR "GICInterface->RPR"                      | ICCRPR         | GICC_RPR         | ICCRPR         | 
| \ref GICInterface_Type::HPPIR "GICInterface->HPPIR"                  | ICCHPIR        | GICC_HPPIR       | ICCHPIR        | 
| \ref GICInterface_Type::ABPR "GICInterface->ABPR"                    | ICCABPR        | GICC_ABPR        | ICCABPR        | 
| \ref GICInterface_Type::AIAR "GICInterface->AIAR"                    |                | GICC_AIAR        |                | 
| \ref GICInterface_Type::AEOIR "GICInterface->AEOIR"                  |                | GICC_AEOIR       |                | 
| \ref GICInterface_Type::AHPPIR "GICInterface->AHPPIR"                |                | GICC_AHPPIR      |                | 
| \ref GICInterface_Type::STATUSR "GICInterface->STATUSR"              |                |                  |                | 
| \ref GICInterface_Type::APR "GICInterface->APR[]"                    |                | GICC_APR0        |                | 
| \ref GICInterface_Type::NSAPR "GICInterface->NSAPR[]"                |                | GICC_NSAPR0      |                | 
| \ref GICInterface_Type::IIDR "GICInterface->IIDR"                    | ICCIIDR        | GICC_IIDR        | ICCIDR         | 
| \ref GICInterface_Type::DIR "GICInterface->DIR"                      |                | GICC_DIR         |                | 

*/

/** @{ */

/**
\fn __STATIC_INLINE void GIC_EnableDistributor(void)
\details Globally enable the forwarding of interrupts to the CPU interfaces.

\fn __STATIC_INLINE void GIC_DisableDistributor(void)
\details Globally disable the forwarding of interrupts to the CPU interfaces.
\see GIC_EnableDistributor

\fn __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
\details 
Provides information about the configuration of the GIC. It indicates:
 - whether the GIC implements the Security Extensions
 - the maximum number of interrupt IDs that the GIC supports
 - the number of CPU interfaces implemented
 - if the GIC implements the Security Extensions, the maximum number of
implemented Lockable Shared Peripheral Interrupts (LSPIs).

\fn __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
\details
Provides information about the implementer and revision of the Distributor.

\fn __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
\details 
The \ref GICDistributor_Type.ITARGETSR "ITARGETSR" registers provide an 8-bit CPU targets field
for each interrupt supported by the GIC. This field stores the list of target processors for the
interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the
interrupt if it is asserted and has sufficient priority.

\fn __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
\details
Read the current interrupt to CPU assignment for the given interrupt.
\see GIC_SetTarget

\fn __STATIC_INLINE void GIC_EnableInterface(void)
\details
Sets the Enable bit in the local CPUs \ref GICInterface_Type.CTLR "CTLR" register.
Only the CPU executing the call is affected.

\fn __STATIC_INLINE void GIC_DisableInterface(void)
\details
Resets the Enable bit in the local CPUs \ref GICInterface_Type.CTLR "CTLR" register.
Only the CPU executing the call is affected.

\fn __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
\details 
Provides the interrupt number of the highest priority interrupt pending.
A read of this register acts as an acknowledge for the interrupt.

The read returns a spurious interrupt number of 1023 if any of the following apply:
 - Forwarding of interrupts by the Distributor to the CPU interface is disabled.
 - Signaling of interrupts by the CPU interface to the connected PE is disabled.
 - There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.

\see GIC_EndInterrupt
 
\fn __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
A write to this register performs priority drop for the specified interrupt.

For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt
acknowledgement, i.e. calls to \ref GIC_AcknowledgePending. Behavior is UNPREDICTABLE if:
 - This ordering constraint is not maintained.
 - The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.
 - The given interrupt number does not match the last valid interrupt value returned by \ref GIC_AcknowledgePending.
 
\fn __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
\details 
Enables forwarding of the corresponding interrupt to the CPU interfaces.

\fn __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
\details
Disables forwarding of the corresponding interrupt to the CPU interfaces.

\fn __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
\details
Adds the pending state to the corresponding interrupt.

\fn __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
\details
Removes the pending state from the corresponding interrupt.

\fn __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\details 
Configures the priority of the given interrupt.

The available interrupt priorities are IMPLEMENTATION DEFINED. In order to
query the actual priorities one can 

\code
GIC_SetPriority(IRQn_TIM1, UINT32_MAX);       // try to configure lowest possible priority
uint32_t actual = GIC_GetPriority(IRQn_TIM1); // retrieve actual lowest priority usable
\endcode

\fn __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
\details 
Can be used to retrieve the actual priority depending on the GIC implementation.
\see GIC_SetPriority

\fn __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
\details
Only interrupts with a higher priority (lower values) than the value provided are signaled.

\fn __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
\see GIC_SetInterfacePriorityMask

\fn __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
\details
The binary point defines the amount of priority bits used as a group priority and subpriorities.

Interrupts sharing the same group priority do not preempt each other. But interrupts having a
higher group priority (lower value) preempt interrups with a lower group priority.

The subpriority defines the execution sequence of interrupts with the same group priority if
multiple are pending at time.

\fn __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
\details
\see GIC_SetBinaryPoint

\fn __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
\details 
The return value is a combination of GIC's \ref GICDistributor_Type::ISACTIVER "ISACTIVER" 
and \ref GICDistributor_Type::ISPENDR "ISPENDR" registers.

Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts
active bit (interrupt is currently handled).

\fn __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
\fn __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) 
\fn __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
\fn __STATIC_INLINE void GIC_DistInit(void)
\details
All shared peripheral interrupts (SPIs) are initialized to be
 - disabled
 - level-sensitive, 1-N model
 - priority 0x7F
 - targeting CPU0
and the distributor is enabled.
 
\see
GIC_DisableIRQ\n
GIC_SetLevelModel\n
GIC_SetPriority\n
GIC_SetTarget\n
GIC_EnableDistributor

\fn __STATIC_INLINE void GIC_CPUInterfaceInit(void)
\details
All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be
 - disabled
 - level-sensitive, 1-N model
 - priority 0x7F
and the interrupt interface is enabled.

The binary point is set to zero. 

The interrupt priority mask is set to 0xFF.

\see
GIC_DisableIRQ\n
GIC_SetLevelModel\n
GIC_SetPriority\n
GIC_EnableInterface\n
GIC_SetBinaryPoint\n
GIC_SetInterfacePriorityMask\n

\fn __STATIC_INLINE void GIC_Enable(void)
\details
Initializes the distributor and the cpu interface.

\see
GIC_DistInit
GIC_CPUInterfaceInit
*/

/**
\def GICDistributor
\details
Use GICDistributor to access the GIC Distributor registers.

\b Example:
\code
GICDistributor->CTRL |= 1; // Enable group 0 interrupts
\endcode
*/

/**
\def GICInterface
\details
Use GICInterface to access the GIC Interface registers.

\b Example:
\code
GICInterface->CTLR |= 1; // Enable interrupt signaling
\endcode
*/

/**
\struct GICInterface_Type

\struct GICDistributor_Type
*/

/** @} */

/* ########################## GICInterface_Type Member ########################## */
/**
\var __IOM uint32_t GICInterface_Type::CTLR
\details CPU Interface Control Register

Enables the signaling of interrupts by the CPU interface to the connected processor, and
provides additional top-level control of the CPU interface. In a GICv2 implementation, this
includes control of the end of interrupt (EOI) behavior.

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:1]  | -             | Reserved.                                                      |
| [0]     | Enable        | Interrupt signaling: 0 - Disable. 1 - Enable.                  |

\var __IM uint32_t GICInterface_Type::IAR
\details CPU Interface Interrupt Acknowledge Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:24] | -             | Reserved.                                                      |
| [23:0]  | INTID         | The interrupt number of the signaled interrupt.                |

\var __OM uint32_t GICInterface_Type::EOIR
\details CPU Interface End Of Interrupt Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:24] | -             | Reserved.                                                      |
| [23:0]  | INTID         | The interrupt number of the finished interrupt.                |
 
 \var __IM uint32_t GICInterface_Type::HPPIR
\details CPU Interface Highest Priority Pending Interrupt Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:13] | -             | Reserved.                                                      |
| [12:10] | CPUID         | On a multiprocessor implementation this identifies the processor that generated the interrupt |
|  [9:0]  | INTID         | The INTID of the signaled interrupt.                           |

\var  __IM uint32_t GICInterface_Type::IIDR
\details CPU Interface Identification Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:20] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
| [19:16] | Arch_version  | The version of the GIC architecture that is implemented.       |
| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number for the CPU interface. |
| [11:0]  | Implementer   | Contains the JEP106 code of the company that implemented the CPU interface. |


\var __IOM uint32_t GICInterface_Type::PMR
\details CPU Interface Priority Mask Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:8]  | -             | Reserved.                                                      |
| [7:0]   | Priority      | The priority mask level for the CPU interface.                 |

\note IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.
 
\var __IOM uint32_t GICInterface_Type::BPR
\details CPU Interface Binary Point Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:3]  | -             | Reserved.                                                      |
| [2:0]   | Binary_Point  | Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. |

The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please
refer to the section Interrupt prioritization in the
<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a>
for details.

\var __IOM uint32_t GICInterface_Type::ABPR
\details CPU Interface Aliased Binary Point Register
\see GICInterface_Type::BPR

\var __OM uint32_t GICInterface_Type::AEOIR
\details CPU Interface Aliased End Of Interrupt Register
\see GICInterface_Type::EOIR

\var __IM uint32_t GICInterface_Type::AHPPIR
\details CPU Interface Aliased Highest Priority Pending Interrupt Register
\see GICInterface_Type::HPPIR

\var __IM uint32_t GICInterface_Type::AIAR
\details CPU Interface Aliased Interrupt Acknowledge Register
\see GICInterface_Type::IAR

\var __IOM uint32_t GICInterface_Type::APR[4]
\details CPU Interface Active Priorities Registers
\note The register values are IMPLEMENTATION DEFINED.

\var __OM uint32_t GICInterface_Type::DIR
\details CPU Interface Deactivate Interrupt Register

| Bits    | Name  | Function                                                       |
| :------ | :---- | :------------------------------------------------------------- |
| [31:24] | -     | Reserved.                                                      |
| [23:0]  | INTID | The INTID of the interrupt to be disabled.                     |

\var __IOM uint32_t GICInterface_Type::NSAPR[4]
\details CPU Interface Non-secure Active Priorities Registers
\note The register values are IMPLEMENTATION DEFINED.
\see GICInterface_Type::APR[4]

\var __IM uint32_t GICInterface_Type::RPR
\details CPU Interface Running Priority Register

| Bits    | Name     | Function                                                       |
| :------ | :------- | :------------------------------------------------------------- |
| [31:8]  | -        | Reserved.                                                      |
| [7:0]   | Priority | The current running priority on the CPU interface.             |

\var __IOM uint32_t GICInterface_Type::STATUSR
\details CPU Interface Status Register

| Bits    | Name     | Function                                                       |
| :------ | :------- | :------------------------------------------------------------- |
| [31:5]  | -        | Reserved.                                                      |
| [4]     | ASV      | Attempted security violation.                                  |
| [3]     | WROD     | Write to an RO location.                                       |
| [2]     | RWOD     | Read of a WO location.                                         |
| [1]     | WRD      | Write to a reserved location.                                  |
| [0]     | RRD      | Read of a reserved location.                                   |
*/

/* ########################## GICDistributor_Type Member ########################## */
/**
\var __IOM uint32_t GICDistributor_Type::CTLR
\details Distributor Control Register

When access is Secure, in a system that supports two Security states:

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
| [30:8]  | -             | Reserved.                                                      |
| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
| [6]     | DS            | Disable Security.                                              |
| [5]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
| [4]     | ARE_S         | Affinity Routing Enable, Secure state.                         |
| [3]     | -             | Reserved.                                                      |
| [2]     | EnableGrp1S   | Enable Secure Group 1 interrupts.                              |
| [1]     | EnableGrp1NS  | Enable Non-secure Group 1 interrupts.                          |
| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |

When access is Non-secure, in a system that supports two Security states:

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
| [30:5]  | -             | Reserved.                                                      |
| [4]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
| [3:2]   | -             | Reserved.                                                      |
| [1]     | EnableGrp1A   | Enable Non-secure Group 1 interrupts.                          |
| [0]     | EnableGrp1    | Enable Non-secure Group 1 interrupts.                          |

When in a system that supports only a single Security state:

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
| [30:8]  | -             | Reserved.                                                      |
| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
| [6]     | DS            | Disable Security.                                              |
| [5]     | -             | Reserved.                                                      |
| [4]     | ARE           | Affinity Routing Enable.                                       |
| [3:2]   | -             | Reserved.                                                      |
| [1]     | EnableGrp1    | Enable Group 1 interrupts.                                     |
| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |

\var __IM uint32_t GICDistributor_Type::TYPER
\details Interrupt Controller Type Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:16] | -             | Reserved.                                                      |
| [15:11] | LSPI          | Maximum number of lockable shared interrupts.                  |
| [10]    | SecurityExtn  | Security Extensions: 0 - not implemented. 1 - implemented.     |
| [9:8]   | -             | Reserved.                                                      |
| [7:5]   | CPUNumber     | Number of implemented CPU interfaces [=CPUNumber+1]            |
| [4:0]   | ITLinesNumber | Maximum number of interrups supported [=32*(ITLinesNumber+1)]. |

\var __IM uint32_t GICDistributor_Type::IIDR
\details Distributor Implementer Identification Register

| Bits    | Name          | Function                                                       |
| :------ | :------------ | :------------------------------------------------------------- |
| [31:24] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
| [23:20] | -             | Reserved.                                                      |
| [19:16] | Variant       | An IMPLEMENTATION DEFINED variant number.                      |
| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number.                     |
| [11:0]  | Implementer   | Contains the JEP106 code of the company implemented the GICD.  |

\var __IOM uint8_t GICDistributor_Type::ITARGETSR[1020]
\details Interrupt Processor Targets Registers

Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds
to an unimplemented CPU interface is RAZ/WI.

| CPU target field value | Interrupt targets |
| :--------------------- | :---------------- |
| 0bxxxxxxx1             | CPU interface 0   |
| 0bxxxxxx1x             | CPU interface 1   |
| 0bxxxxx1xx             | CPU interface 2   |
| 0bxxxx1xxx             | CPU interface 3   |
| 0bxxx1xxxx             | CPU interface 4   |
| 0bxx1xxxxx             | CPU interface 5   |
| 0bx1xxxxxx             | CPU interface 6   |
| 0b1xxxxxxx             | CPU interface 7   |

\var __IOM uint32_t GICDistributor_Type::IGROUPR[32]
\details Interrupt Group Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32
 
And the value denotes:
- 0 When \ref GICDistributor_Type::CTLR "CTLR".DS==1, the corresponding interrupt is Group 0\n
    When \ref GICDistributor_Type::CTLR "CTLR".DS==0, the corresponding interrupt is Secure.
- 1 When \ref GICDistributor_Type::CTLR "CTLR".DS==1, the corresponding interrupt is Group 1.\n
    When \ref GICDistributor_Type::CTLR "CTLR".DS==0, the corresponding interrupt is Non-secure Group 1.
 
\var __IO uint32_t GICDistributor_Type::CLRSPI_NSR
\details Clear Non-secure SPI Pending Register

| Bits    | Name          | Function                                          |
| :------ | :------------ | :------------------------------------------------ | 
| [31:10] | -             | Reserved.                                         |
| [9:0]   | INTID         | The interrupt number to clear pending state from. |

\var __IO uint32_t GICDistributor_Type::CLRSPI_SR
\details Clear Secure SPI Pending Register

| Bits    | Name          | Function                                          |
| :------ | :------------ | :------------------------------------------------ | 
| [31:10] | -             | Reserved.                                         |
| [9:0]   | INTID         | The interrupt number to clear pending state from. |

\var __IOM uint32_t GICDistributor_Type::IGRPMODR[32]
\details Interrupt Group Modifier Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32
 
\var __IOM uint64_t GICDistributor_Type::IROUTER[988]
\details Interrupt Routing Registers

| Bits    | Name          | Function                                                      |
| :------ | :------------ | :------------------------------------------------------------ | 
| [63:40] | -             | Reserved.                                                     |
| [39:32] | Aff3          | Affinity level 3, the least significant affinity level field. |
| [31]    | IRM           | Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. |
| [30:24] | -             | Reserved.                                                     |
| [23:16] | Aff2          | Affinity level 2, an intermediate affinity level field.       | 
| [15:8]  | Aff1          | Affinity level 1, an intermediate affinity level field.       |
| [7:0]   | Aff0          | Affinity level 0, the most significant affinity level field.  |

\var __IOM uint32_t GICDistributor_Type::NSACR[64]
\details Non-secure Access Control Registers

Each two bits corresponds to one interrupt:
 - Register index is given by INTID/16
 - Bit number is given by 2*INTID%16

The possible values of each 2-bit field are:
 - 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
 - 01 - Non-secure accesses are only permitted to requesting fields.
 - 10 - As 01, additionally accesses to clearing field are permitted.
 - 11 - As 10, additionally accesses to target and routing fields are permitted.
 
\var __IO uint32_t GICDistributor_Type::SETSPI_NSR
\details Set Non-secure SPI Pending Register

| Bits    | Name          | Function                                          |
| :------ | :------------ | :------------------------------------------------ | 
| [31:10] | -             | Reserved.                                         |
| [9:0]   | INTID         | The interrupt number to set pending state for.    |

\var __IO uint32_t GICDistributor_Type::SETSPI_SR
\details Set Secure SPI Pending Register

| Bits    | Name          | Function                                          |
| :------ | :------------ | :------------------------------------------------ | 
| [31:10] | -             | Reserved.                                         |
| [9:0]   | INTID         | The interrupt number to set pending state for.    |

\var __IOM uint8_t GICDistributor_Type::SPENDSGIR[16]
\details SGI Set-Pending Registers
Each register corresponds to one software generated interrupt (SGI).

Reading from this register reveals
 - 0 - interrupt is not pending
 - 1 - interrupt is pending
 
Writing to this register causes
 - 0 - no effect
 - 1 - adds the pending state
 
\var __IOM uint8_t GICDistributor_Type::CPENDSGIR[16]
\details SGI Clear-Pending Registers
Each register corresponds to one software generated interrupt (SGI).

Reading from this register reveals
 - 0 - interrupt is not pending
 - 1 - interrupt is pending
 
Writing to this register causes
 - 0 - no effect
 - 1 - removes the pending state

\var __IOM uint32_t GICDistributor_Type::STATUSR
\details Error Reporting Status Register

| Bits    | Name          | Function                                          |
| :------ | :------------ | :------------------------------------------------ | 
| [31:4]  | -             | Reserved.                                         |
| [3]     | WROD          | Write to an RO location.                          |
| [2]     | RWOD          | Read of a WO location.                            |
| [1]     | WRD           | Write to a reserved location.                     |
| [0]     | RRD           | Read of a reserved location.                      |

\var __IOM uint32_t GICDistributor_Type::ISENABLER[32]
\details Interrupt Set-Enable Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32

\note Bits corresponding to unimplemented interrupts are RAZ/WI.

\var __IOM uint32_t GICDistributor_Type::ICENABLER[32]
\details Interrupt Clear-Enable Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32

\note Bits corresponding to unimplemented interrupts are RAZ/WI.

\var __IOM uint32_t GICDistributor_Type::ISPENDR[32]
\details Interrupt Set-Pending Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32

\note Bits corresponding to unimplemented interrupts are RAZ/WI.

\var __IOM uint32_t GICDistributor_Type::ICPENDR[32]
\details Interrupt Clear-Pending Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32
 
\note Bits corresponding to unimplemented interrupts are RAZ/WI.

\var __IOM uint32_t GICDistributor_Type::ICFGR[64]
\details Interrupt Configuration Registers

Each interrupt can be configured by two corresponding bits:

| Bits           | Name          | Function                                                       |
| :------------- | :------------ | :------------------------------------------------------------- |
| [2*INTID%16+1] | Edge          | Interrupt is: 0 - level sensitive, 1 - edge triggered          |
| [2*INTID%16]   | Model         | 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported          |

\var __IOM uint8_t GICDistributor_Type::IPRIORITYR[1020]
\details Interrupt Priority Registers

A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each
field. In each field, unimplemented bits are RAZ/WI.

\note A register field corresponding to an unimplemented interrupt is RAZ/WI.

\var __IOM uint32_t GICDistributor_Type::ISACTIVER[32]
\details Interrupt Set-Active Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32
 
\note Bits corresponding to unimplemented interrupts are RAZ/WI.

\var __IOM uint32_t GICDistributor_Type::ICACTIVER[32]
\details Interrupt Clear-Active Registers

Each bit corresponds to one interrupt:
 - Register index is given by INTID/32
 - Bit number is given by INTID%32

\note Bits corresponding to unimplemented interrupts are RAZ/WI.

\var __OM uint32_t GICDistributor_Type::SGIR
\details Software Generated Interrupt Register

| Bits    | Name             | Function                                                         |
| :------ | :------------    | :--------------------------------------------------------------- |
| [31:26] | -                | Reserved.                                                        |
| [25:24] | TargetFilterList | Determines how the Distributor processes the requested SGI.      |
| [23:16] | CPUTargetList    | When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. |
| [15]    | NSATT            | Specifies the required group of the SGI.                         |
| [14:4]  | -                | Reserved.                                                        |
| [3:0]   | INTID            | The INTID of the SGI to forward to the specified CPU interfaces. |

Refer to \ref GICDistributor_Type::ITARGETSR "ITARGETSR" for details on TargetFilterList field.

*/
