PSOC E8XXGP Device Support Library

| PSOC E8XXGP Device Support Library

Data Fields
GFXSS_DC_MXDC_Type Struct Reference

## Description

Platform IP standard configuration for DC.

(GFXSS_DC_MXDC)

## Data Fields
__IOM uint32_t | CTL
__IOM uint32_t | CLK_CTL
__IOM uint32_t | IO_CTL
__IM uint32_t | STATUS
__IOM uint32_t | INTR
__IOM uint32_t | INTR_SET
__IOM uint32_t | INTR_MASK
__IM uint32_t | INTR_MASKED
__IOM uint32_t | ADDR0_INT
__IOM uint32_t | ADDR1_INT
__IOM uint32_t | ADDR2_INT
__IOM uint32_t | ADDR3_INT
__IM uint32_t | RESERVED [4]
__IOM uint32_t | RLAD_CTL
__IOM uint32_t | RLAD_IMG
__IOM uint32_t | RLAD_ENC
__IOM uint32_t | RLAD_BUF0
__IOM uint32_t | RLAD_BUF1
__IM uint32_t | RLAD_STATUS
__IM uint32_t | RESERVED1 [6]
__IM uint32_t | IPIDENTIFIER
__IM uint32_t | RESERVED2 [3]

## Field Documentation

## ◆ CTL

__IOM uint32_t GFXSS_DC_MXDC_Type::CTL

0x00000000 IP control.

## ◆ CLK_CTL

__IOM uint32_t GFXSS_DC_MXDC_Type::CLK_CTL

0x00000004 Clock control.

## ◆ IO_CTL

__IOM uint32_t GFXSS_DC_MXDC_Type::IO_CTL

0x00000008 IO enable control.

## ◆ STATUS

__IM uint32_t GFXSS_DC_MXDC_Type::STATUS

0x0000000C IP status.

## ◆ INTR

__IOM uint32_t GFXSS_DC_MXDC_Type::INTR

0x00000010 Interrupt status.

## ◆ INTR_SET

__IOM uint32_t GFXSS_DC_MXDC_Type::INTR_SET

0x00000014 Interrupt set bits.

## ◆ INTR_MASK

__IOM uint32_t GFXSS_DC_MXDC_Type::INTR_MASK

0x00000018 Interrupt mask bits.

## ◆ INTR_MASKED

__IM uint32_t GFXSS_DC_MXDC_Type::INTR_MASKED

0x0000001C Interrupt masked bits.

## ◆ ADDR0_INT

__IOM uint32_t GFXSS_DC_MXDC_Type::ADDR0_INT

0x00000020 Address 0 for interrupt generation.

## ◆ ADDR1_INT

__IOM uint32_t GFXSS_DC_MXDC_Type::ADDR1_INT

0x00000024 Address 1 for interrupt generation.

## ◆ ADDR2_INT

__IOM uint32_t GFXSS_DC_MXDC_Type::ADDR2_INT

0x00000028 Address 2 for interrupt generation.

## ◆ ADDR3_INT

__IOM uint32_t GFXSS_DC_MXDC_Type::ADDR3_INT

0x0000002C Address 3 for interrupt generation.

## ◆ RESERVED

__IM uint32_t GFXSS_DC_MXDC_Type::RESERVED[4]

## ◆ RLAD_CTL

__IOM uint32_t GFXSS_DC_MXDC_Type::RLAD_CTL

0x00000040 Control options for the RLAD decoder.

## ◆ RLAD_IMG

__IOM uint32_t GFXSS_DC_MXDC_Type::RLAD_IMG

0x00000044 Properties of the uncompressed image.

## ◆ RLAD_ENC

__IOM uint32_t GFXSS_DC_MXDC_Type::RLAD_ENC

0x00000048 Configuration of the encoder that compressed the image.

## ◆ RLAD_BUF0

__IOM uint32_t GFXSS_DC_MXDC_Type::RLAD_BUF0

0x0000004C Properties of the compressed image data buffer.

## ◆ RLAD_BUF1

__IOM uint32_t GFXSS_DC_MXDC_Type::RLAD_BUF1

0x00000050 Properties of the compressed image data buffer.

## ◆ RLAD_STATUS

__IM uint32_t GFXSS_DC_MXDC_Type::RLAD_STATUS

0x00000054 RLAD decoder status.

## ◆ RESERVED1

__IM uint32_t GFXSS_DC_MXDC_Type::RESERVED1[6]

## ◆ IPIDENTIFIER

__IM uint32_t GFXSS_DC_MXDC_Type::IPIDENTIFIER

0x00000070 GFXSS IP and desig release identification (with DC, GPU and MIPIDSI).

## ◆ RESERVED2

__IM uint32_t GFXSS_DC_MXDC_Type::RESERVED2[3]