SHORT L2 cache bandwidth in MBytes/s

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
FIXC3 TOPDOWN_SLOTS
PMC0  L1D_REPLACEMENT
PMC1  L2_TRANS_L1D_WB
PMC2  ICACHE_TAG_MISS

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
L2 load bandwidth [MBytes/s]  1.0E-06*PMC0*64.0/time
L2 load data volume [GBytes]  1.0E-09*PMC0*64.0
L2 evict bandwidth [MBytes/s]  1.0E-06*PMC1*64.0/time
L2 evict data volume [GBytes]  1.0E-09*PMC1*64.0
L2 bandwidth [MBytes/s] 1.0E-06*(PMC0+PMC1+PMC2)*64.0/time
L2 data volume [GBytes] 1.0E-09*(PMC0+PMC1+PMC2)*64.0

LONG
Formulas:
L2 load bandwidth [MBytes/s] = 1.0E-06*L1D_REPLACEMENT*64.0/time
L2 load data volume [GBytes] = 1.0E-09*L1D_REPLACEMENT*64.0
L2 evict bandwidth [MBytes/s] = 1.0E-06*L2_TRANS_L1D_WB*64.0/time
L2 evict data volume [GBytes] = 1.0E-09*L2_TRANS_L1D_WB*64.0
L2 bandwidth [MBytes/s] = 1.0E-06*(L1D_REPLACEMENT+L2_TRANS_L1D_WB+ICACHE_TAG_MISS)*64/time
L2 data volume [GBytes] = 1.0E-09*(L1D_REPLACEMENT+L2_TRANS_L1D_WB+ICACHE_TAG_MISS)*64
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Profiling group to measure L2 load cache bandwidth. The bandwidth is computed by the
number of cache line allocated/replaced in the L1 and cache lines evicted to L2. The
events to measure the evicted cache lines and the loads issues by the L1 instruction
cache are not officially supported by Intel.
