rfc9669xml2.original.xml   rfc9669.xml 
<?xml version="1.0" encoding="UTF-8"?> <?xml version='1.0' encoding='utf-8'?>
<?xml-stylesheet type="text/xsl" href="rfc2629.xslt"?>
<!-- generated by https://github.com/dthaler/rst2rfcxml version 0.1 -->
<!DOCTYPE rfc [ <!DOCTYPE rfc [
<!ENTITY nbsp "&#160;">
<!ENTITY zwsp "&#8203;">
<!ENTITY nbhy "&#8209;">
<!ENTITY wj "&#8288;">
]> ]>
<?rfc rfcedstyle="yes"?> <rfc xmlns:xi="http://www.w3.org/2001/XInclude" ipr="trust200902" docName="draft
<?rfc toc="yes"?> -ietf-bpf-isa-04" number="9669" updates="" obsoletes="" consensus="true" catego
<?rfc tocindent="yes"?> ry="std" submissionType="IETF" tocInclude="true" sortRefs="true" symRefs="true"
<?rfc sortrefs="yes"?> version="3" xml:lang="en">
<?rfc symrefs="yes"?>
<?rfc strict="yes"?>
<?rfc comments="yes"?>
<?rfc inline="yes"?>
<?rfc text-list-symbols="-o*+"?>
<?rfc docmapping="yes"?>
<rfc ipr="trust200902" docName="draft-ietf-bpf-isa-04" category="std" submission <front>
Type="IETF"> <title abbrev="BPF ISA">BPF Instruction Set Architecture (ISA)</title>
<front> <seriesInfo name="RFC" value="9669"/>
<title abbrev="BPF ISA"> <author initials="D." surname="Thaler" fullname="Dave Thaler" role="editor">
BPF Instruction Set Architecture (ISA) <address>
</title> <postal>
<author initials="D." surname="Thaler" fullname="Dave Thaler" role="editor"> <city>Redmond</city>
<address> <code>98052</code>
<postal> <country>United States of America</country>
<city>Redmond</city> <region>WA</region>
<code>98052</code> </postal>
<country>USA</country> <email>dave.thaler.ietf@gmail.com</email>
<region>WA</region> </address>
</postal> </author>
<email>dave.thaler.ietf@gmail.com</email> <date month="October" year="2024"/>
</address> <area>INT</area>
</author> <workgroup>bdf</workgroup>
<abstract>
<t> <!-- [rfced] Please insert any keywords (beyond those that appear in
eBPF (which is no longer an acronym for anything), also commonly referred to the title) for use on https://www.rfc-editor.org/search. -->
as BPF, is a technology with origins in the Linux kernel that can run untrusted
programs in a privileged context such as an operating system kernel. This docum <keyword>example</keyword>
ent specifies the BPF instruction set architecture (ISA).
</t> <abstract>
</abstract> <t> eBPF (which is no longer an acronym for anything), also commonly
</front> referred to as BPF, is a technology with origins in the Linux kernel
<middle> that can run untrusted programs in a privileged context such as an
<section anchor="introduction" title="Introduction"> operating system kernel. This document specifies the BPF instruction set
<t> architecture (ISA).
</t>
</abstract>
</front>
<middle>
<section anchor="introduction">
<name>Introduction</name>
<t>
eBPF, also commonly eBPF, also commonly
referred to as BPF, is a technology with origins in the Linux kernel referred to as BPF, is a technology with origins in the Linux kernel
that can run untrusted programs in a privileged context such as an that can run untrusted programs in a privileged context such as an
operating system kernel. This document specifies the BPF instruction operating system kernel. This document specifies the BPF instruction
set architecture (ISA). set architecture (ISA).
</t> </t>
<t> <t>
As a historical note, BPF originally stood for Berkeley Packet Filter, As a historical note, BPF originally stood for Berkeley Packet Filter,
but now that it can do so much more than packet filtering, the acronym but now that it can do so much more than packet filtering, the acronym
no longer makes sense. BPF is now considered a standalone term that no longer makes sense. BPF is now considered a standalone term that
does not stand for anything. The original BPF is sometimes referred to does not stand for anything. The original BPF is sometimes referred to
as cBPF (classic BPF) to distinguish it from the now widely deployed as cBPF (classic BPF) to distinguish it from the now widely deployed
eBPF (extended BPF). eBPF (extended BPF).
</t> </t>
</section> </section>
<section anchor="documentation-conventions" title="Documentation conventions"> <section anchor="documentation-conventions">
<t> <name>Documentation Conventions</name>
The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", <t>
"SHOULD", "SHOULD NOT", "RECOMMENDED", "NOT RECOMMENDED", "MAY", and The key words "<bcp14>MUST</bcp14>", "<bcp14>MUST NOT</bcp14>",
"OPTIONAL" in this document are to be interpreted as described in "<bcp14>REQUIRED</bcp14>", "<bcp14>SHALL</bcp14>", "<bcp14>SHALL NOT</bcp14>
BCP 14 <xref target="RFC2119"></xref> ",
<xref target="RFC8174"></xref> "<bcp14>SHOULD</bcp14>", "<bcp14>SHOULD NOT</bcp14>",
when, and only when, they appear in all capitals, as shown here. "<bcp14>RECOMMENDED</bcp14>", "<bcp14>NOT RECOMMENDED</bcp14>",
</t> "<bcp14>MAY</bcp14>", and "<bcp14>OPTIONAL</bcp14>" in this document are to
<t> be
interpreted as described in BCP&nbsp;14 <xref target="RFC2119"/> <xref
target="RFC8174"/> when, and only when, they appear in all capitals, as
shown here.
</t>
<t>
For brevity and consistency, this document refers to families For brevity and consistency, this document refers to families
of types using a shorthand syntax and refers to several expository, of types using a shorthand syntax and refers to several expository,
mnemonic functions when describing the semantics of instructions. mnemonic functions when describing the semantics of instructions.
The range of valid values for those types and the semantics of those The range of valid values for those types and the semantics of those
functions are defined in the following subsections. functions are defined in the following subsections.
</t> </t>
<section anchor="types" title="Types"> <section anchor="types">
<t> <name>Types</name>
<!-- [rfced] Are italics needed here? Because the text refers to "notation", it
may be confusing as to whether the underscores (that appear in the text outpu)
are part of the notation. The corresponding values in tables 1 and 3 do not use
underscores. May we remove them here?
Original:
This document refers to integer types with the notation _SN_ to
specify a type's signedness (_S_) and bit width (_N_), respectively.
-->
<t>
This document refers to integer types with the notation <em>SN</em> to spec ify This document refers to integer types with the notation <em>SN</em> to spec ify
a type's signedness (<em>S</em>) and bit width (<em>N</em>), respectively. a type's signedness (<em>S</em>) and bit width (<em>N</em>), respectively.
</t>
<table>
<name>Meaning of signedness notation</name>
<thead>
<tr>
<th>S</th>
<th>Meaning</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
u
</t> </t>
</td> <table>
<td> <name>Meaning of Signedness Notation</name>
<t> <thead>
<tr>
<th>S</th>
<th>Meaning</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
u
</t>
</td>
<td>
<t>
unsigned unsigned
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
s s
</t> </t>
</td> </td>
<td> <td>
<t> <t>
signed signed
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<table> <table>
<name>Meaning of bit-width notation</name> <name>Meaning of Bit-Width Notation</name>
<thead> <thead>
<tr> <tr>
<th>N</th> <th>N</th>
<th>Bit width</th> <th>Bit Width</th>
</tr> </tr>
</thead> </thead>
<tbody> <tbody>
<tr> <tr>
<td> <td>
<t> <t>
8 8
</t> </t>
</td> </td>
<td> <td>
<t> <t>
8 bits 8 bits
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
16 16
</t> </t>
</td> </td>
<td> <td>
<t> <t>
16 bits 16 bits
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
32 32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
32 bits 32 bits
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
64 64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
64 bits 64 bits
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
128 128
</t> </t>
</td> </td>
<td> <td>
<t> <t>
128 bits 128 bits
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
For example, <em>u32</em> is a type whose valid values are all the 32-bit u nsigned For example, <em>u32</em> is a type whose valid values are all the 32-bit u nsigned
numbers and <em>s16</em> is a type whose valid values are all the 16-bit si gned numbers and <em>s16</em> is a type whose valid values are all the 16-bit si gned
numbers. numbers.
</t> </t>
</section> </section>
<section anchor="functions" title="Functions"> <section anchor="functions">
<t> <name>Functions</name>
The following byteswap functions are direction-agnostic. That is, <t>
The following byte swap functions are direction agnostic. That is,
the same function is used for conversion in either direction discussed the same function is used for conversion in either direction discussed
below. below.
</t> </t>
<ul> <ul>
<li> <li>
be16: Takes an unsigned 16-bit number and converts it between be16: Takes an unsigned 16-bit number and converts it between
host byte order and big-endian host byte order and big-endian
(<xref target="IEN137">IEN137</xref>) byte order. (<xref target="IEN137">IEN137</xref>) byte order.
</li> </li>
<li> <li>
be32: Takes an unsigned 32-bit number and converts it between be32: Takes an unsigned 32-bit number and converts it between
host byte order and big-endian byte order. host byte order and big-endian byte order.
</li> </li>
<li> <li>
be64: Takes an unsigned 64-bit number and converts it between be64: Takes an unsigned 64-bit number and converts it between
host byte order and big-endian byte order. host byte order and big-endian byte order.
</li> </li>
<li> <li>
bswap16: Takes an unsigned 16-bit number in either big- or little-endian bswap16: Takes an unsigned 16-bit number in either big- or little-endian
format and returns the equivalent number with the same bit width but format and returns the equivalent number with the same bit width but
opposite endianness. opposite endianness.
</li> </li>
<li> <li>
bswap32: Takes an unsigned 32-bit number in either big- or little-endian bswap32: Takes an unsigned 32-bit number in either big- or little-endian
format and returns the equivalent number with the same bit width but format and returns the equivalent number with the same bit width but
opposite endianness. opposite endianness.
</li> </li>
<li> <li>
bswap64: Takes an unsigned 64-bit number in either big- or little-endian bswap64: Takes an unsigned 64-bit number in either big- or little-endian
format and returns the equivalent number with the same bit width but format and returns the equivalent number with the same bit width but
opposite endianness. opposite endianness.
</li> </li>
<li> <li>
le16: Takes an unsigned 16-bit number and converts it between le16: Takes an unsigned 16-bit number and converts it between
host byte order and little-endian byte order. host byte order and little-endian byte order.
</li> </li>
<li> <li>
le32: Takes an unsigned 32-bit number and converts it between le32: Takes an unsigned 32-bit number and converts it between
host byte order and little-endian byte order. host byte order and little-endian byte order.
</li> </li>
<li> <li>
le64: Takes an unsigned 64-bit number and converts it between le64: Takes an unsigned 64-bit number and converts it between
host byte order and little-endian byte order. host byte order and little-endian byte order.
</li> </li>
</ul> </ul>
</section> </section>
<section anchor="definitions" title="Definitions"> <section anchor="definitions">
<dl> <name>Definitions</name>
<dt anchor="term-sign-extend"> <dl>
Sign Extend <!-- [rfced] We are having a tough time understanding this sentence. Is the inte
</dt> nt for "sign extend" to appear in italics (i.e., move "an" outside of <em>)? Do
<dd> es "-bit number, A, to a" and "-bit number, B," need to appear in italics? Perh
<t> aps just the variables A and B should appear in italics?
To <em>sign extend an</em> <tt>X</tt> <em>-bit number, A, to a</em> <tt>Y
</tt> <em>-bit number, B ,</em> means to Original:
</t> 2.3. Definitions
<ol>
Sign Extend To _sign extend an_ X _-bit number, A, to a_ Y _-bit
number, B ,_ means to
1. Copy all X bits from _A_ to the lower X bits of _B_.
2. Set the value of the remaining Y - X bits of _B_ to the value
of the most-significant bit of _A_.
Is this what is intended?
Sign Extend: To _sign extend_ X-bit number, _A_, to a Y-bit number, _B_, mea
ns
to
...
-->
<dt anchor="term-sign-extend">
Sign Extend:
</dt>
<dd>
<t>
To <em>sign extend an</em> <tt>X</tt> <em>-bit number, A, to a</em> <tt>Y
</tt> <em>-bit number, B,</em> means to
</t>
<t> To <em>sign extend</em> <tt>X</tt>-bit number, <em>A</em>, to a <tt>Y<
/tt>-bit
number, <em>B</em>, means to
</t>
<ol>
<li> <li>
Copy all <tt>X</tt> bits from <em>A</em> to the lower <tt>X</tt> bits of <em>B</em>. Copy all <tt>X</tt> bits from <em>A</em> to the lower <tt>X</tt> bits of <em>B</em>.
</li> </li>
<li> <li>
Set the value of the remaining <tt>Y</tt> - <tt>X</tt> bits of <em>B</em > to the value of Set the value of the remaining <tt>Y</tt> - <tt>X</tt> bits of <em>B</em > to the value of
the most-significant bit of <em>A</em>. the most significant bit of <em>A</em>.
</li> </li>
</ol> </ol>
</dd> </dd>
</dl> </dl>
<aside> <aside>
<t><strong>Example</strong></t> <t><strong>Example</strong></t>
<t> <t>
Sign extend an 8-bit number <tt>A</tt> to a 16-bit number <tt>B</tt> on a big-endian platform: Sign extend an 8-bit number <tt>A</tt> to a 16-bit number <tt>B</tt> on a big-endian platform:
</t> </t>
<artwork> <artwork><![CDATA[
A: 10000110 A: 10000110
B: 11111111 10000110 B: 11111111 10000110
</artwork> ]]></artwork>
</aside> </aside>
</section> </section>
<section anchor="conformance-groups" title="Conformance groups"> <section anchor="conformance-groups">
<t> <name>Conformance Groups</name>
<t>
An implementation does not need to support all instructions specified in th is An implementation does not need to support all instructions specified in th is
document (e.g., deprecated instructions). Instead, a number of conformance document (e.g., deprecated instructions). Instead, a number of conformance
groups are specified. An implementation MUST support the base32 conformanc groups are specified. An implementation <bcp14>MUST</bcp14> support the ba
e se32 conformance
group and MAY support additional conformance groups, where supporting a group and <bcp14>MAY</bcp14> support additional conformance groups, where s
conformance group means it MUST support all instructions in that conformanc upporting a
e conformance group means it <bcp14>MUST</bcp14> support all instructions in
that conformance
group. group.
</t> </t>
<t> <t>
The use of named conformance groups enables interoperability between a runt ime The use of named conformance groups enables interoperability between a runt ime
that executes instructions, and tools such as compilers that generate that executes instructions, and tools such as compilers that generate
instructions for the runtime. Thus, capability discovery in terms of instructions for the runtime. Thus, capability discovery in terms of
conformance groups might be done manually by users or automatically by tool s. conformance groups might be done manually by users or automatically by tool s.
</t> </t>
<t> <t>
Each conformance group has a short ASCII label (e.g., "base32") that Each conformance group has a short ASCII label (e.g., "base32") that
corresponds to a set of instructions that are mandatory. That is, each corresponds to a set of instructions that are mandatory. That is, each
instruction has one or more conformance groups of which it is a member. instruction has one or more conformance groups of which it is a member.
</t> </t>
<t> <t>
This document defines the following conformance groups: This document defines the following conformance groups:
</t> </t>
<ul> <dl>
<li> <dt>base32:</dt><dd> includes all instructions defined in this
base32: includes all instructions defined in this specification unless otherwise noted.</dd>
specification unless otherwise noted. <dt>
</li> base64:</dt><dd> includes base32, plus instructions explicitly noted
<li> as being in the base64 conformance group.</dd>
base64: includes base32, plus instructions explicitly noted
as being in the base64 conformance group. <dt>
</li> atomic32:</dt><dd> includes 32-bit atomic operation instructions (see <xre
<li> f target="atomic-operations">Atomic operations</xref>).</dd>
atomic32: includes 32-bit atomic operation instructions (see <xref target=
"atomic-operations">Atomic operations</xref>). <dt>
</li> atomic64:</dt><dd> includes atomic32, plus 64-bit atomic operation instruc
<li> tions.
atomic64: includes atomic32, plus 64-bit atomic operation instructions. </dd>
</li> <dt>
<li> divmul32:</dt><dd> includes 32-bit division, multiplication, and modulo in
divmul32: includes 32-bit division, multiplication, and modulo instruction structions.
s. </dd>
</li> <dt>
<li> divmul64:</dt><dd> includes divmul32, plus 64-bit division, multiplication
divmul64: includes divmul32, plus 64-bit division, multiplication, ,
and modulo instructions. and modulo instructions.
</li> </dd>
<li> <dt>
packet: deprecated packet access instructions. packet:</dt> <dd>deprecated packet access instructions.
</li> </dd>
</ul> </dl>
</section> </section>
</section> </section>
<section anchor="instruction-encoding" title="Instruction encoding"> <section anchor="instruction-encoding">
<t> <name>Instruction Encoding</name>
<t>
BPF has two instruction encodings: BPF has two instruction encodings:
</t> </t>
<ul> <ul>
<li> <li>
the basic instruction encoding, which uses 64 bits to encode an instruction the basic instruction encoding, which uses 64 bits to encode an instruction
</li> </li>
<li> <li>
the wide instruction encoding, which appends a second 64 bits the wide instruction encoding, which appends a second 64 bits
after the basic instruction for a total of 128 bits. after the basic instruction for a total of 128 bits.
</li> </li>
</ul> </ul>
<section anchor="basic-instruction-encoding" title="Basic instruction encodin <section anchor="basic-instruction-encoding">
g"> <name>Basic Instruction Encoding</name>
<t> <t>
A basic instruction is encoded as follows: A basic instruction is encoded as follows:
</t> </t>
<artwork> <artwork><![CDATA[
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| opcode | regs | offset | | opcode | regs | offset |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| imm | | imm |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
</artwork> ]]></artwork>
<dl> <dl>
<dt anchor="term---opcode--"> <dt anchor="term---opcode--">
<strong>opcode</strong> <strong>opcode:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
operation to perform, encoded as follows: operation to perform, encoded as follows:
</t> </t>
<artwork> <artwork><![CDATA[
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
|specific |class| |specific |class|
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
</artwork> ]]></artwork>
<dl> <dl>
<dt anchor="term---specific--"> <dt anchor="term---specific--">
<strong>specific</strong> <strong>specific:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
The format of these bits varies by instruction class The format of these bits varies by instruction class
</t> </t>
</dd> </dd>
<dt anchor="term---class--"> <dt anchor="term---class--">
<strong>class</strong> <strong>class:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
The instruction class (see <xref target="instruction-classes">Instructi the instruction class (see <xref target="instruction-classes">Instructi
on classes</xref>) on classes</xref>)
</t> </t>
</dd> </dd>
</dl> </dl>
</dd> </dd>
<dt anchor="term---regs--"> <dt anchor="term---regs--">
<strong>regs</strong> <strong>regs:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
The source and destination register numbers, encoded as follows the source and destination register numbers, encoded as follows
on a little-endian host: on a little-endian host:
</t> </t>
<artwork> <artwork><![CDATA[
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
|src_reg|dst_reg| |src_reg|dst_reg|
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
</artwork> ]]></artwork>
<t> <t>
and as follows on a big-endian host: and as follows on a big-endian host:
</t> </t>
<artwork> <artwork><![CDATA[
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
|dst_reg|src_reg| |dst_reg|src_reg|
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
</artwork> ]]></artwork>
<dl> <dl>
<dt anchor="term---src_reg--"> <dt anchor="term---src_reg--">
<strong>src_reg</strong> <strong>src_reg:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
the source register number (0-10), except where otherwise specified the source register number (0-10), except where otherwise specified
(<xref target="-4-bit-immediate-instructions">64-bit immediate instruct (<xref target="_4-bit-immediate-instructions">64-bit immediate instruct
ions</xref> reuse this field for other purposes) ions</xref> reuse this field for other purposes)
</t> </t>
</dd> </dd>
<dt anchor="term---dst_reg--"> <dt anchor="term---dst_reg--">
<strong>dst_reg</strong> <strong>dst_reg:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
destination register number (0-10), unless otherwise specified the destination register number (0-10), unless otherwise specified
(future instructions might reuse this field for other purposes) (future instructions might reuse this field for other purposes)
</t> </t>
</dd> </dd>
</dl> </dl>
</dd> </dd>
<dt anchor="term---offset--"> <dt anchor="term---offset--">
<strong>offset</strong> <strong>offset:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
signed integer offset used with pointer arithmetic, except where signed integer offset used with pointer arithmetic, except where
otherwise specified (some arithmetic instructions reuse this field otherwise specified (some arithmetic instructions reuse this field
for other purposes) for other purposes)
</t> </t>
</dd> </dd>
<dt anchor="term---imm--"> <dt anchor="term---imm--">
<strong>imm</strong> <strong>imm:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
signed integer immediate value signed integer immediate value
</t> </t>
</dd> </dd>
</dl> </dl>
<t> <t>
Note that the contents of multi-byte fields ('offset' and 'imm') are Note that the contents of multi-byte fields ('offset' and 'imm') are
stored using big-endian byte ordering on big-endian hosts and stored using big-endian byte ordering on big-endian hosts and
little-endian byte ordering on little-endian hosts. little-endian byte ordering on little-endian hosts.
</t> </t>
<t> <t>
For example: For example:
</t> </t>
<artwork> <artwork><![CDATA[
opcode offset imm assembly opcode offset imm assembly
src_reg dst_reg src_reg dst_reg
07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little
dst_reg src_reg dst_reg src_reg
07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big
</artwork> ]]></artwork>
<t> <t>
Note that most instructions do not use all of the fields. Note that most instructions do not use all of the fields.
Unused fields SHALL be cleared to zero. Unused fields <bcp14>SHALL</bcp14> be cleared to zero.
</t> </t>
</section> </section>
<section anchor="wide-instruction-encoding" title="Wide instruction encoding" <section anchor="wide-instruction-encoding">
> <name>Wide Instruction Encoding</name>
<t> <t>
Some instructions are defined to use the wide instruction encoding, Some instructions are defined to use the wide instruction encoding,
which uses two 32-bit immediate values. The 64 bits following which uses two 32-bit immediate values. The 64 bits following
the basic instruction format contain a pseudo instruction the basic instruction format contain a pseudo instruction
with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero. with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero.
</t> </t>
<t> <t>
This is depicted in the following figure: This is depicted in the following figure:
</t> </t>
<artwork> <artwork><![CDATA[
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| opcode | regs | offset | | opcode | regs | offset |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| imm | | imm |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| reserved | | reserved |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| next_imm | | next_imm |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
</artwork> ]]></artwork>
<dl> <dl>
<dt anchor="term---opcode---"> <dt anchor="term---opcode---">
<strong>opcode</strong> <strong>opcode:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
operation to perform, encoded as explained above operation to perform, encoded as explained above
</t> </t>
</dd> </dd>
<dt anchor="term---regs---"> <dt anchor="term---regs---">
<strong>regs</strong> <strong>regs:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
The source and destination register numbers (unless otherwise the source and destination register numbers (unless otherwise
specified), encoded as explained above specified), encoded as explained above
</t> </t>
</dd> </dd>
<dt anchor="term---offset---"> <dt anchor="term---offset---">
<strong>offset</strong> <strong>offset:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
signed integer offset used with pointer arithmetic, unless signed integer offset used with pointer arithmetic, unless
otherwise specified otherwise specified
</t> </t>
</dd> </dd>
<dt anchor="term---imm---"> <dt anchor="term---imm---">
<strong>imm</strong> <strong>imm:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
signed integer immediate value signed integer immediate value
</t> </t>
</dd> </dd>
<dt anchor="term---reserved--"> <dt anchor="term---reserved--">
<strong>reserved</strong> <strong>reserved:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
unused, set to zero unused, set to zero
</t> </t>
</dd> </dd>
<dt anchor="term---next_imm--"> <dt anchor="term---next_imm--">
<strong>next_imm</strong> <strong>next_imm:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
second signed integer immediate value second signed integer immediate value
</t> </t>
</dd> </dd>
</dl> </dl>
</section> </section>
<section anchor="instruction-classes" title="Instruction classes"> <section anchor="instruction-classes">
<t> <name>Instruction Classes</name>
The three least significant bits of the 'opcode' field store the instructio
n class:
</t>
<table>
<name>Instruction class</name>
<thead>
<tr>
<th>class</th>
<th>value</th>
<th>description</th>
<th>reference</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t> <t>
LD The three least significant bits of the 'opcode' field store the instructio n class:
</t> </t>
</td> <!-- [rfced] Tables 3 and 8: Please confirm that these tables are not intended t
<td> o be IANA registries.
<t> -->
<table>
<name>Instruction Class</name>
<thead>
<tr>
<th>Class</th>
<th>Value</th>
<th>Description</th>
<th>Reference</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
LD
</t>
</td>
<td>
<t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
non-standard load operations non-standard load operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions< /xref> <xref target="load-and-store-instructions">Load and store instructions< /xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
LDX LDX
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x1 0x1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
load into register operations load into register operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions< /xref> <xref target="load-and-store-instructions">Load and store instructions< /xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ST ST
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x2 0x2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
store from immediate operations store from immediate operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions< /xref> <xref target="load-and-store-instructions">Load and store instructions< /xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
STX STX
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x3 0x3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
store from register operations store from register operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions< /xref> <xref target="load-and-store-instructions">Load and store instructions< /xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ALU ALU
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x4 0x4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
32-bit arithmetic operations 32-bit arithmetic operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref> <xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JMP JMP
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x5 0x5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
64-bit jump operations 64-bit jump operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref> <xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JMP32 JMP32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x6 0x6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
32-bit jump operations 32-bit jump operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref> <xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ALU64 ALU64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x7 0x7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
64-bit arithmetic operations 64-bit arithmetic operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref> <xref target="arithmetic-and-jump-instructions">Arithmetic and jump ins tructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
</section> </section>
</section> </section>
<section anchor="arithmetic-and-jump-instructions" title="Arithmetic and jump <section anchor="arithmetic-and-jump-instructions">
instructions"> <name>Arithmetic and Jump Instructions</name>
<t> <t>
For arithmetic and jump instructions (<tt>ALU</tt>, <tt>ALU64</tt>, <tt>JMP< For arithmetic and jump instructions (<tt>ALU</tt>, <tt>ALU64</tt>, <tt>JMP<
/tt> and /tt>, and
<tt>JMP32</tt>), the 8-bit 'opcode' field is divided into three parts: <tt>JMP32</tt>), the 8-bit 'opcode' field is divided into three parts:
</t> </t>
<artwork> <artwork><![CDATA[
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
| code |s|class| | code |s|class|
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
</artwork> ]]></artwork>
<dl> <dl>
<dt anchor="term---code--"> <dt anchor="term---code--">
<strong>code</strong> <strong>code:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
the operation code, whose meaning varies by instruction class the operation code, whose meaning varies by instruction class
</t> </t>
</dd> </dd>
<dt anchor="term---s--source---"> <dt anchor="term---s--source---">
<strong>s (source)</strong> <strong>s (source):</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
the source operand location, which unless otherwise specified is one of: the source operand location, which unless otherwise specified is one of:
</t> </t>
<table> <table>
<name>Source operand location</name> <name>Source Operand Location</name>
<thead> <thead>
<tr> <tr>
<th>source</th> <th>Source</th>
<th>value</th> <th>Value</th>
<th>description</th> <th>Description</th>
</tr> </tr>
</thead> </thead>
<tbody> <tbody>
<tr> <tr>
<td> <td>
<t> <t>
K K
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
use 32-bit 'imm' value as source operand use 32-bit 'imm' value as source operand
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
X X
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
use 'src_reg' register value as source operand use 'src_reg' register value as source operand
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
</dd> </dd>
<dt anchor="term---instruction-class--"> <dt anchor="term---instruction-class--">
<strong>instruction class</strong> <strong>instruction class:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
the instruction class (see <xref target="instruction-classes">Instruction classes</xref>) the instruction class (see <xref target="instruction-classes">Instruction classes</xref>)
</t> </t>
</dd> </dd>
</dl> </dl>
<section anchor="arithmetic-instructions" title="Arithmetic instructions"> <section anchor="arithmetic-instructions">
<t> <name>Arithmetic Instructions</name>
<t>
<tt>ALU</tt> uses 32-bit wide operands while <tt>ALU64</tt> uses 64-bit wid e operands for <tt>ALU</tt> uses 32-bit wide operands while <tt>ALU64</tt> uses 64-bit wid e operands for
otherwise identical operations. <tt>ALU64</tt> instructions belong to the otherwise identical operations. <tt>ALU64</tt> instructions belong to the
base64 conformance group unless noted otherwise. base64 conformance group unless noted otherwise.
The 'code' field encodes the operation as below, where 'src' refers to the The 'code' field encodes the operation as below, where 'src' refers to the
the source operand and 'dst' refers to the value of the destination source operand and 'dst' refers to the value of the destination
register. register.
</t>
<table>
<name>Arithmetic instructions</name>
<thead>
<tr>
<th>name</th>
<th>code</th>
<th>offset</th>
<th>description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
ADD
</t> </t>
</td> <table>
<td> <name>Arithmetic Instructions</name>
<t> <thead>
<tr>
<th>Name</th>
<th>Code</th>
<th>Offset</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
ADD
</t>
</td>
<td>
<t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst += src dst += src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
SUB SUB
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x1 0x1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst -= src dst -= src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
MUL MUL
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x2 0x2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst *= src dst *= src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
DIV DIV
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x3 0x3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst / src) : 0 dst = (src != 0) ? (dst / src) : 0
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
SDIV SDIV
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x3 0x3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst s/ src) : 0 dst = (src != 0) ? (dst s/ src) : 0
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
OR OR
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x4 0x4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst |= src dst |= src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
AND AND
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x5 0x5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &amp;= src dst &amp;= src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
LSH LSH
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x6 0x6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &lt;&lt;= (src &amp; mask) dst &lt;&lt;= (src &amp; mask)
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
RSH RSH
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x7 0x7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &gt;&gt;= (src &amp; mask) dst &gt;&gt;= (src &amp; mask)
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
NEG NEG
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x8 0x8
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = -dst dst = -dst
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
MOD MOD
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x9 0x9
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst % src) : dst dst = (src != 0) ? (dst % src) : dst
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
SMOD SMOD
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x9 0x9
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst s% src) : dst dst = (src != 0) ? (dst s% src) : dst
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
XOR XOR
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xa 0xa
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst ^= src dst ^= src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
MOV MOV
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xb 0xb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = src dst = src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
MOVSX MOVSX
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xb 0xb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
8/16/32 8/16/32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (s8,s16,s32)src dst = (s8,s16,s32)src
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ARSH ARSH
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xc 0xc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="term-sign-extend">sign extending</xref> dst &gt;&gt;= (sr c &amp; mask) <xref target="term-sign-extend">sign extending</xref> dst &gt;&gt;= (sr c &amp; mask)
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
END END
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xd 0xd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
byte swap operations (see <xref target="byte-swap-instructions">Byte sw ap instructions</xref> below) byte swap operations (see <xref target="byte-swap-instructions">Byte sw ap instructions</xref> below)
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
Underflow and overflow are allowed during arithmetic operations, meaning Underflow and overflow are allowed during arithmetic operations, meaning
the 64-bit or 32-bit value will wrap. If BPF program execution would the 64-bit or 32-bit value will wrap. If BPF program execution would
result in division by zero, the destination register is instead set to zero . result in division by zero, the destination register is instead set to zero .
If execution would result in modulo by zero, for <tt>ALU64</tt> the value o f If execution would result in modulo by zero, for <tt>ALU64</tt> the value o f
the destination register is unchanged whereas for <tt>ALU</tt> the upper the destination register is unchanged whereas for <tt>ALU</tt> the upper
32 bits of the destination register are zeroed. 32 bits of the destination register are zeroed.
</t> </t>
<t> <t>
<tt>{ADD, X, ALU}</tt>, where 'code' = <tt>ADD</tt>, 'source' = <tt>X</tt>, and 'class' = <tt>ALU</tt>, means: <tt>{ADD, X, ALU}</tt>, where 'code' = <tt>ADD</tt>, 'source' = <tt>X</tt>, and 'class' = <tt>ALU</tt>, means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = (u32) ((u32) dst + (u32) src) dst = (u32) ((u32) dst + (u32) src)
</artwork> ]]></artwork>
<t> <t>
where '(u32)' indicates that the upper 32 bits are zeroed. where '(u32)' indicates that the upper 32 bits are zeroed.
</t> </t>
<t> <t>
<tt>{ADD, X, ALU64}</tt> means: <tt>{ADD, X, ALU64}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = dst + src dst = dst + src
</artwork> ]]></artwork>
<t> <t>
<tt>{XOR, K, ALU}</tt> means: <tt>{XOR, K, ALU}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = (u32) dst ^ (u32) imm dst = (u32) dst ^ (u32) imm
</artwork> ]]></artwork>
<t> <t>
<tt>{XOR, K, ALU64}</tt> means: <tt>{XOR, K, ALU64}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = dst ^ imm dst = dst ^ imm
</artwork> ]]></artwork>
<t> <t>
Note that most arithmetic instructions have 'offset' set to 0. Only three i nstructions Note that most arithmetic instructions have 'offset' set to 0. Only three i nstructions
(<tt>SDIV</tt>, <tt>SMOD</tt>, <tt>MOVSX</tt>) have a non-zero 'offset'. (<tt>SDIV</tt>, <tt>SMOD</tt>, <tt>MOVSX</tt>) have a non-zero 'offset'.
</t> </t>
<t> <t>
Division, multiplication, and modulo operations for <tt>ALU</tt> are part Division, multiplication, and modulo operations for <tt>ALU</tt> are part
of the "divmul32" conformance group, and division, multiplication, and of the "divmul32" conformance group, and division, multiplication, and
modulo operations for <tt>ALU64</tt> are part of the "divmul64" conformance modulo operations for <tt>ALU64</tt> are part of the "divmul64" conformance
group. group.
The division and modulo operations support both unsigned and signed flavors . The division and modulo operations support both unsigned and signed flavors .
</t> </t>
<t> <t>
For unsigned operations (<tt>DIV</tt> and <tt>MOD</tt>), for <tt>ALU</tt>, For unsigned operations (<tt>DIV</tt> and <tt>MOD</tt>), for <tt>ALU</tt>,
'imm' is interpreted as a 32-bit unsigned value. For <tt>ALU64</tt>, 'imm' is interpreted as a 32-bit unsigned value. For <tt>ALU64</tt>,
'imm' is first <xref target="term-sign-extend">sign extended</xref> from 32 to 64 bits, and then 'imm' is first <xref target="term-sign-extend">sign extended</xref> from 32 to 64 bits, and then
interpreted as a 64-bit unsigned value. interpreted as a 64-bit unsigned value.
</t> </t>
<t> <t>
For signed operations (<tt>SDIV</tt> and <tt>SMOD</tt>), for <tt>ALU</tt>, For signed operations (<tt>SDIV</tt> and <tt>SMOD</tt>), for <tt>ALU</tt>,
'imm' is interpreted as a 32-bit signed value. For <tt>ALU64</tt>, 'imm' 'imm' is interpreted as a 32-bit signed value. For <tt>ALU64</tt>, 'imm'
is first <xref target="term-sign-extend">sign extended</xref> from 32 to 64 bits, and then is first <xref target="term-sign-extend">sign extended</xref> from 32 to 64 bits, and then
interpreted as a 64-bit signed value. interpreted as a 64-bit signed value.
</t> </t>
<t> <t>
Note that there are varying definitions of the signed modulo operation Note that there are varying definitions of the signed modulo operation
when the dividend or divisor are negative, where implementations often when the dividend or divisor are negative, where implementations often
vary by language such that Python, Ruby, etc. differ from C, Go, Java, vary by language such that Python, Ruby, etc. differ from C, Go, Java,
etc. This specification requires that signed modulo MUST use truncated divi sion etc. This specification requires that signed modulo <bcp14>MUST</bcp14> use truncated division
(where -13 % 3 == -1) as implemented in C, Go, etc.: (where -13 % 3 == -1) as implemented in C, Go, etc.:
</t> </t>
<artwork> <artwork><![CDATA[
a % n = a - n * trunc(a / n) a % n = a - n * trunc(a / n)
</artwork> ]]></artwork>
<t> <t>
The <tt>MOVSX</tt> instruction does a move operation with sign extension. The <tt>MOVSX</tt> instruction does a move operation with sign extension.
<tt>{MOVSX, X, ALU}</tt> <xref target="term-sign-extend">sign extends</xref > 8-bit and 16-bit operands into <tt>{MOVSX, X, ALU}</tt> <xref target="term-sign-extend">sign extends</xref > 8-bit and 16-bit operands into
32-bit operands, and zeroes the remaining upper 32 bits. 32-bit operands, and zeroes the remaining upper 32 bits.
<tt>{MOVSX, X, ALU64}</tt> <xref target="term-sign-extend">sign extends</xr ef> 8-bit, 16-bit, and 32-bit <tt>{MOVSX, X, ALU64}</tt> <xref target="term-sign-extend">sign extends</xr ef> 8-bit, 16-bit, and 32-bit
operands into 64-bit operands. Unlike other arithmetic instructions, operands into 64-bit operands. Unlike other arithmetic instructions,
<tt>MOVSX</tt> is only defined for register source operands (<tt>X</tt>). <tt>MOVSX</tt> is only defined for register source operands (<tt>X</tt>).
</t> </t>
<t> <t>
<tt>{MOV, K, ALU64}</tt> means: <tt>{MOV, K, ALU64}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = (s64)imm dst = (s64)imm
</artwork> ]]></artwork>
<t> <t>
<tt>{MOV, X, ALU}</tt> means: <tt>{MOV, X, ALU}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = (u32)src dst = (u32)src
</artwork> ]]></artwork>
<t> <t>
<tt>{MOVSX, X, ALU}</tt> with 'offset' 8 means: <tt>{MOVSX, X, ALU}</tt> with 'offset' 8 means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = (u32)(s32)(s8)src dst = (u32)(s32)(s8)src
]]></artwork>
</artwork> <t>
<t>
The <tt>NEG</tt> instruction is only defined when the source bit is clear The <tt>NEG</tt> instruction is only defined when the source bit is clear
(<tt>K</tt>). (<tt>K</tt>).
</t> </t>
<t> <t>
Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31 ) Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31 )
for 32-bit operations. for 32-bit operations.
</t> </t>
</section> </section>
<section anchor="byte-swap-instructions" title="Byte swap instructions"> <section anchor="byte-swap-instructions">
<t> <name>Byte Swap Instructions</name>
<t>
The byte swap instructions use instruction classes of <tt>ALU</tt> and <tt> ALU64</tt> The byte swap instructions use instruction classes of <tt>ALU</tt> and <tt> ALU64</tt>
and a 4-bit 'code' field of <tt>END</tt>. and a 4-bit 'code' field of <tt>END</tt>.
</t> </t>
<t> <t>
The byte swap instructions operate on the destination register The byte swap instructions operate on the destination register
only and do not use a separate source register or immediate value. only and do not use a separate source register or immediate value.
</t> </t>
<t> <t>
For <tt>ALU</tt>, the 1-bit source operand field in the opcode is used to For <tt>ALU</tt>, the 1-bit source operand field in the opcode is used to
select what byte order the operation converts from or to. For select what byte order the operation converts from or to. For
<tt>ALU64</tt>, the 1-bit source operand field in the opcode is reserved <tt>ALU64</tt>, the 1-bit source operand field in the opcode is reserved
and MUST be set to 0. and <bcp14>MUST</bcp14> be set to 0.
</t>
<table>
<name>Byte swap instructions</name>
<thead>
<tr>
<th>class</th>
<th>source</th>
<th>value</th>
<th>description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
ALU
</t> </t>
</td> <table>
<td> <name>Byte Swap Instructions</name>
<t> <thead>
<tr>
<th>Class</th>
<th>Source</th>
<th>Value</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
ALU
</t>
</td>
<td>
<t>
LE LE
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
convert between host byte order and little endian convert between host byte order and little endian
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ALU ALU
</t> </t>
</td> </td>
<td> <td>
<t> <t>
BE BE
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
convert between host byte order and big endian convert between host byte order and big endian
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ALU64 ALU64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Reserved Reserved
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
do byte swap unconditionally do byte swap unconditionally
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
The 'imm' field encodes the width of the swap operations. The following wi dths The 'imm' field encodes the width of the swap operations. The following wi dths
are supported: 16, 32 and 64. Width 64 operations belong to the base64 are supported: 16, 32, and 64. Width 64 operations belong to the base64
conformance group and other swap operations belong to the base32 conformance group and other swap operations belong to the base32
conformance group. conformance group.
</t> </t>
<t> <t>
Examples: Examples:
</t> </t>
<t> <t>
<tt>{END, LE, ALU}</tt> with 'imm' = 16/32/64 means: <tt>{END, LE, ALU}</tt> with 'imm' = 16/32/64 means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = le16(dst) dst = le16(dst)
dst = le32(dst) dst = le32(dst)
dst = le64(dst) dst = le64(dst)]]></artwork>
</artwork> <t>
<t>
<tt>{END, BE, ALU}</tt> with 'imm' = 16/32/64 means: <tt>{END, BE, ALU}</tt> with 'imm' = 16/32/64 means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = be16(dst) dst = be16(dst)
dst = be32(dst) dst = be32(dst)
dst = be64(dst) dst = be64(dst)]]></artwork>
</artwork> <t>
<t>
<tt>{END, TO, ALU64}</tt> with 'imm' = 16/32/64 means: <tt>{END, TO, ALU64}</tt> with 'imm' = 16/32/64 means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = bswap16(dst) dst = bswap16(dst)
dst = bswap32(dst) dst = bswap32(dst)
dst = bswap64(dst) dst = bswap64(dst)]]></artwork>
</artwork> </section>
</section> <section anchor="jump-instructions">
<section anchor="jump-instructions" title="Jump instructions"> <name>Jump Instructions</name>
<t> <t>
<!-- [rfced] Section 4.3: As we believe "and indicates the base64 conformance gr
oup" is related to JMP using 64-bit wide operands, we suggest the following upda
te for clarity:
Original:
JMP32 uses 32-bit wide operands and indicates the base32 conformance
group, while JMP uses 64-bit wide operands for otherwise identical
operations, and indicates the base64 conformance group unless
otherwise specified.
Perhaps:
JMP32 uses 32-bit wide operands and indicates the base32 conformance
group; JMP uses 64-bit wide operands for otherwise identical
operations and indicates the base64 conformance group unless
otherwise specified.
-->
<tt>JMP32</tt> uses 32-bit wide operands and indicates the base32 <tt>JMP32</tt> uses 32-bit wide operands and indicates the base32
conformance group, while <tt>JMP</tt> uses 64-bit wide operands for conformance group, while <tt>JMP</tt> uses 64-bit wide operands for
otherwise identical operations, and indicates the base64 conformance otherwise identical operations, and indicates the base64 conformance
group unless otherwise specified. group unless otherwise specified.
The 'code' field encodes the operation as below: The 'code' field encodes the operation as below:
</t>
<table>
<name>Jump instructions</name>
<thead>
<tr>
<th>code</th>
<th>value</th>
<th>src_reg</th>
<th>description</th>
<th>notes</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
JA
</t> </t>
</td> <table>
<td> <name>Jump Instructions</name>
<t> <thead>
<tr>
<th>Code</th>
<th>Value</th>
<th>src_reg</th>
<th>Description</th>
<th>Notes</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
JA
</t>
</td>
<td>
<t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset PC += offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
{JA, K, JMP} only {JA, K, JMP} only
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JA JA
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += imm PC += imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
{JA, K, JMP32} only {JA, K, JMP32} only
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JEQ JEQ
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x1 0x1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst == src PC += offset if dst == src
</t> </t>
</td> </td>
<td> <td>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JGT JGT
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x2 0x2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &gt; src PC += offset if dst &gt; src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
unsigned unsigned
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JGE JGE
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x3 0x3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &gt;= src PC += offset if dst &gt;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
unsigned unsigned
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JSET JSET
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x4 0x4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &amp; src PC += offset if dst &amp; src
</t> </t>
</td> </td>
<td> <td>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JNE JNE
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x5 0x5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst != src PC += offset if dst != src
</t> </t>
</td> </td>
<td> <td>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JSGT JSGT
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x6 0x6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &gt; src PC += offset if dst &gt; src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
signed signed
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JSGE JSGE
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x7 0x7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &gt;= src PC += offset if dst &gt;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
signed signed
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
CALL CALL
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x8 0x8
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
call helper function by static ID call helper function by static ID
</t> </t>
</td> </td>
<td> <td>
<t> <t>
{CALL, K, JMP} only, see <xref target="helper-functions">Helper functio ns</xref> {CALL, K, JMP} only, see <xref target="helper-functions">Helper functio ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
CALL CALL
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x8 0x8
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x1 0x1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
call PC += imm call PC += imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
{CALL, K, JMP} only, see <xref target="program-local-functions">Program -local functions</xref> {CALL, K, JMP} only, see <xref target="program-local-functions">Program -local functions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
CALL CALL
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x8 0x8
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x2 0x2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
call helper function by BTF ID call helper function by BTF ID
</t> </t>
</td> </td>
<td> <td>
<t> <t>
{CALL, K, JMP} only, see <xref target="helper-functions">Helper functio ns</xref> {CALL, K, JMP} only, see <xref target="helper-functions">Helper functio ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
EXIT EXIT
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x9 0x9
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
return return
</t> </t>
</td> </td>
<td> <td>
<t> <t>
{CALL, K, JMP} only {CALL, K, JMP} only
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JLT JLT
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xa 0xa
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &lt; src PC += offset if dst &lt; src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
unsigned unsigned
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JLE JLE
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xb 0xb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &lt;= src PC += offset if dst &lt;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
unsigned unsigned
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JSLT JSLT
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xc 0xc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &lt; src PC += offset if dst &lt; src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
signed signed
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
JSLE JSLE
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xd 0xd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
PC += offset if dst &lt;= src PC += offset if dst &lt;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
signed signed
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
where 'PC' denotes the program counter, and the offset to increment by where 'PC' denotes the program counter, and the offset to increment by
is in units of 64-bit instructions relative to the instruction following is in units of 64-bit instructions relative to the instruction following
the jump instruction. Thus 'PC += 1' skips execution of the next the jump instruction. Thus 'PC += 1' skips execution of the next
instruction if it's a basic instruction or results in undefined behavior instruction if it's a basic instruction or results in undefined behavior
if the next instruction is a 128-bit wide instruction. if the next instruction is a 128-bit wide instruction.
</t> </t>
<t> <t>
Example: Example:
</t> </t>
<t> <t>
<tt>{JSGE, X, JMP32}</tt> means: <tt>{JSGE, X, JMP32}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
if (s32)dst s&gt;= (s32)src goto +offset if (s32)dst s>= (s32)src goto +offset]]></artwork>
</artwork> <t>
<t>
where 's&gt;=' indicates a signed '&gt;=' comparison. where 's&gt;=' indicates a signed '&gt;=' comparison.
</t> </t>
<t> <t>
<tt>{JLE, K, JMP}</tt> means: <tt>{JLE, K, JMP}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
if dst &lt;= (u64)(s64)imm goto +offset if dst <= (u64)(s64)imm goto +offset]]></artwork>
</artwork> <t>
<t>
<tt>{JA, K, JMP32}</tt> means: <tt>{JA, K, JMP32}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
gotol +imm gotol +imm]]></artwork>
</artwork> <t>
<t>
where 'imm' means the branch offset comes from the 'imm' field. where 'imm' means the branch offset comes from the 'imm' field.
</t> </t>
<t> <t>
Note that there are two flavors of <tt>JA</tt> instructions. The Note that there are two flavors of <tt>JA</tt> instructions. The
<tt>JMP</tt> class permits a 16-bit jump offset specified by the 'offset' <tt>JMP</tt> class permits a 16-bit jump offset specified by the 'offset'
field, whereas the <tt>JMP32</tt> class permits a 32-bit jump offset field, whereas the <tt>JMP32</tt> class permits a 32-bit jump offset
specified by the 'imm' field. A &gt; 16-bit conditional jump may be specified by the 'imm' field. A conditional jump greater than 16 bits may b
converted to a &lt; 16-bit conditional jump plus a 32-bit unconditional e
converted to a conditional jump less than 16 bits plus a 32-bit uncondition
al
jump. jump.
</t> </t>
<t> <t>
All <tt>CALL</tt> and <tt>JA</tt> instructions belong to the All <tt>CALL</tt> and <tt>JA</tt> instructions belong to the
base32 conformance group. base32 conformance group.
</t> </t>
<section anchor="helper-functions" title="Helper functions"> <section anchor="helper-functions">
<t> <name>Helper Functions</name>
<t>
Helper functions are a concept whereby BPF programs can call into a Helper functions are a concept whereby BPF programs can call into a
set of function calls exposed by the underlying platform. set of function calls exposed by the underlying platform.
</t> </t>
<t> <t>
Historically, each helper function was identified by a static ID Historically, each helper function was identified by a static ID
encoded in the 'imm' field. Further documentation of helper functions encoded in the 'imm' field. Further documentation of helper functions
is outside the scope of this document and standardization is left for is outside the scope of this document and standardization is left for
future work, but use is widely deployed and more information can be future work, but use is widely deployed and more information can be
found in platform-specific documentation (e.g., Linux kernel documentation ). found in platform-specific documentation (e.g., Linux kernel documentation ).
</t> </t>
<t> <t>
Platforms that support the BPF Type Format (BTF) support identifying Platforms that support the BPF Type Format (BTF) support identifying
a helper function by a BTF ID encoded in the 'imm' field, where the BTF ID a helper function by a BTF ID encoded in the 'imm' field, where the BTF ID
identifies the helper name and type. Further documentation of BTF identifies the helper name and type. Further documentation of BTF
is outside the scope of this document and standardization is left for is outside the scope of this document and standardization is left for
future work, but use is widely deployed and more information can be future work, but use is widely deployed and more information can be
found in platform-specific documentation (e.g., Linux kernel documentation ). found in platform-specific documentation (e.g., Linux kernel documentation ).
</t> </t>
</section> </section>
<section anchor="program-local-functions" title="Program-local functions"> <section anchor="program-local-functions">
<t> <name>Program-Local Functions</name>
<t>
Program-local functions are functions exposed by the same BPF program as t he Program-local functions are functions exposed by the same BPF program as t he
caller, and are referenced by offset from the instruction following the ca ll caller, and are referenced by offset from the instruction following the ca ll
instruction, similar to <tt>JA</tt>. The offset is encoded in the 'imm' f ield of instruction, similar to <tt>JA</tt>. The offset is encoded in the 'imm' f ield of
the call instruction. An <tt>EXIT</tt> within the program-local function w ill the call instruction. An <tt>EXIT</tt> within the program-local function w ill
return to the caller. return to the caller.
</t> </t>
</section>
</section>
</section> </section>
</section> <section anchor="load-and-store-instructions">
</section> <name>Load and Store Instructions</name>
<section anchor="load-and-store-instructions" title="Load and store instructio <t>
ns">
<t>
For load and store instructions (<tt>LD</tt>, <tt>LDX</tt>, <tt>ST</tt>, and <tt>STX</tt>), the For load and store instructions (<tt>LD</tt>, <tt>LDX</tt>, <tt>ST</tt>, and <tt>STX</tt>), the
8-bit 'opcode' field is divided as follows: 8-bit 'opcode' field is divided as follows:
</t> </t>
<artwork> <artwork><![CDATA[
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
|mode |sz |class| |mode |sz |class|
+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+
</artwork> ]]></artwork>
<dl> <dl>
<dt anchor="term---mode--"> <dt anchor="term---mode--">
<strong>mode</strong> <strong>mode:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
The mode modifier is one of: The mode modifier is one of:
</t> </t>
<table> <table>
<name>Mode modifier</name> <name>Mode Modifier</name>
<thead> <thead>
<tr> <tr>
<th>mode modifier</th> <th>Mode Modifier</th>
<th>value</th> <th>Value</th>
<th>description</th> <th>Description</th>
<th>reference</th> <th>Reference</th>
</tr> </tr>
</thead> </thead>
<tbody> <tbody>
<tr> <tr>
<td> <td>
<t> <t>
IMM IMM
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
64-bit immediate instructions 64-bit immediate instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instruct <xref target="_4-bit-immediate-instructions">64-bit immediate instruct
ions</xref> ions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ABS ABS
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
legacy BPF packet access (absolute) legacy BPF packet access (absolute)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet access instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet access instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
IND IND
</t> </t>
</td> </td>
<td> <td>
<t> <t>
2 2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
legacy BPF packet access (indirect) legacy BPF packet access (indirect)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet access instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet access instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
MEM MEM
</t> </t>
</td> </td>
<td> <td>
<t> <t>
3 3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
regular load and store operations regular load and store operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="regular-load-and-store-operations">Regular load and stor e operations</xref> <xref target="regular-load-and-store-operations">Regular load and stor e operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
MEMSX MEMSX
</t> </t>
</td> </td>
<td> <td>
<t> <t>
4 4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
sign-extension load operations sign-extension load operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="sign-extension-load-operations">Sign-extension load oper ations</xref> <xref target="sign-extension-load-operations">Sign-extension load oper ations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ATOMIC ATOMIC
</t> </t>
</td> </td>
<td> <td>
<t> <t>
6 6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic operations atomic operations
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
</dd> </dd>
<dt anchor="term---sz--size---"> <dt anchor="term---sz--size---">
<strong>sz (size)</strong> <strong>sz (size):</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
The size modifier is one of: The size modifier is one of:
</t> </t>
<table> <table>
<name>Size modifier</name> <name>Size Modifier</name>
<thead> <thead>
<tr> <tr>
<th>size</th> <th>Size</th>
<th>value</th> <th>Value</th>
<th>description</th> <th>Description</th>
</tr> </tr>
</thead> </thead>
<tbody> <tbody>
<tr> <tr>
<td> <td>
<t> <t>
W W
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
word (4 bytes) word (4 bytes)
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
H H
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
half word (2 bytes) half word (2 bytes)
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
B B
</t> </t>
</td> </td>
<td> <td>
<t> <t>
2 2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
byte byte
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
DW DW
</t> </t>
</td> </td>
<td> <td>
<t> <t>
3 3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
double word (8 bytes) double word (8 bytes)
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
Instructions using <tt>DW</tt> belong to the base64 conformance group. Instructions using <tt>DW</tt> belong to the base64 conformance group.
</t> </t>
</dd> </dd>
<dt anchor="term---class---"> <dt anchor="term---class---">
<strong>class</strong> <strong>class:</strong>
</dt> </dt>
<dd> <dd>
<t> <t>
The instruction class (see <xref target="instruction-classes">Instruction classes</xref>) The instruction class (see <xref target="instruction-classes">Instruction classes</xref>)
</t> </t>
</dd> </dd>
</dl> </dl>
<section anchor="regular-load-and-store-operations" title="Regular load and s <section anchor="regular-load-and-store-operations">
tore operations"> <name>Regular Load and Store Operations</name>
<t> <t>
The <tt>MEM</tt> mode modifier is used to encode regular load and store The <tt>MEM</tt> mode modifier is used to encode regular load and store
instructions that transfer data between a register and memory. instructions that transfer data between a register and memory.
</t> </t>
<t> <t>
<tt>{MEM, &lt;size&gt;, STX}</tt> means: <tt>{MEM, &lt;size&gt;, STX}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
*(size *) (dst + offset) = src *(size *) (dst + offset) = src]]></artwork>
</artwork> <t>
<t>
<tt>{MEM, &lt;size&gt;, ST}</tt> means: <tt>{MEM, &lt;size&gt;, ST}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
*(size *) (dst + offset) = imm *(size *) (dst + offset) = imm]]></artwork>
</artwork> <t>
<t>
<tt>{MEM, &lt;size&gt;, LDX}</tt> means: <tt>{MEM, &lt;size&gt;, LDX}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = *(unsigned size *) (src + offset) dst = *(unsigned size *) (src + offset)]]></artwork>
</artwork> <t>
<t>
Where '&lt;size&gt;' is one of: <tt>B</tt>, <tt>H</tt>, <tt>W</tt>, or <tt> DW</tt>, and Where '&lt;size&gt;' is one of: <tt>B</tt>, <tt>H</tt>, <tt>W</tt>, or <tt> DW</tt>, and
'unsigned size' is one of: u8, u16, u32, or u64. 'unsigned size' is one of: u8, u16, u32, or u64.
</t> </t>
</section> </section>
<section anchor="sign-extension-load-operations" title="Sign-extension load o <section anchor="sign-extension-load-operations">
perations"> <name>Sign-Extension Load Operations</name>
<t> <t>
The <tt>MEMSX</tt> mode modifier is used to encode <xref target="term-sign- extend">sign-extension</xref> load The <tt>MEMSX</tt> mode modifier is used to encode <xref target="term-sign- extend">sign-extension</xref> load
instructions that transfer data between a register and memory. instructions that transfer data between a register and memory.
</t> </t>
<t> <t>
<tt>{MEMSX, &lt;size&gt;, LDX}</tt> means: <tt>{MEMSX, &lt;size&gt;, LDX}</tt> means:
</t> </t>
<artwork> <artwork><![CDATA[
dst = *(signed size *) (src + offset) dst = *(signed size *) (src + offset)]]></artwork>
</artwork> <t>
<t>
Where '&lt;size&gt;' is one of: <tt>B</tt>, <tt>H</tt>, or <tt>W</tt>, and Where '&lt;size&gt;' is one of: <tt>B</tt>, <tt>H</tt>, or <tt>W</tt>, and
'signed size' is one of: s8, s16, or s32. 'signed size' is one of: s8, s16, or s32.
</t> </t>
</section> </section>
<section anchor="atomic-operations" title="Atomic operations"> <section anchor="atomic-operations">
<t> <name>Atomic Operations</name>
Atomic operations are operations that operate on memory and can not be <t>
Atomic operations operate on memory and cannot be
interrupted or corrupted by other access to the same memory region interrupted or corrupted by other access to the same memory region
by other BPF programs or means outside of this specification. by other BPF programs or means outside of this specification.
</t> </t>
<t> <t>
All atomic operations supported by BPF are encoded as store operations All atomic operations supported by BPF are encoded as store operations
that use the <tt>ATOMIC</tt> mode modifier as follows: that use the <tt>ATOMIC</tt> mode modifier as follows:
</t> </t>
<ul> <ul>
<li> <li>
<tt>{ATOMIC, W, STX}</tt> for 32-bit operations, which are <tt>{ATOMIC, W, STX}</tt> for 32-bit operations, which are
part of the "atomic32" conformance group. part of the "atomic32" conformance group.
</li> </li>
<li> <li>
<tt>{ATOMIC, DW, STX}</tt> for 64-bit operations, which are <tt>{ATOMIC, DW, STX}</tt> for 64-bit operations, which are
part of the "atomic64" conformance group. part of the "atomic64" conformance group.
</li> </li>
<li> <li>
8-bit and 16-bit wide atomic operations are not supported. 8-bit and 16-bit wide atomic operations are not supported.
</li> </li>
</ul> </ul>
<t> <t>
The 'imm' field is used to encode the actual atomic operation. The 'imm' field is used to encode the actual atomic operation.
Simple atomic operation use a subset of the values defined to encode Simple atomic operations use a subset of the values defined to encode
arithmetic operations in the 'imm' field to encode the atomic operation: arithmetic operations in the 'imm' field to encode the atomic operation:
</t>
<table>
<name>Simple atomic operations</name>
<thead>
<tr>
<th>imm</th>
<th>value</th>
<th>description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
ADD
</t> </t>
</td> <table>
<td> <name>Simple Atomic Operations</name>
<t> <thead>
<tr>
<th>imm</th>
<th>Value</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
ADD
</t>
</td>
<td>
<t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic add atomic add
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
OR OR
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x40 0x40
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic or atomic or
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
AND AND
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x50 0x50
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic and atomic and
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
XOR XOR
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xa0 0xa0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic xor atomic xor
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t>
<tt>{ATOMIC, W, STX}</tt> with 'imm' = ADD means:
</t>
<artwork>
*(u32 *)(dst + offset) += src
</artwork>
<t>
<tt>{ATOMIC, DW, STX}</tt> with 'imm' = ADD means:
</t>
<artwork>
*(u64 *)(dst + offset) += src
</artwork>
<t>
In addition to the simple atomic operations, there also is a modifier and
two complex atomic operations:
</t>
<table>
<name>Complex atomic operations</name>
<thead>
<tr>
<th>imm</th>
<th>value</th>
<th>description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t> <t>
FETCH <tt>{ATOMIC, W, STX}</tt> with 'imm' = ADD means:
</t> </t>
</td> <artwork><![CDATA[
<td> *(u32 *)(dst + offset) += src]]></artwork>
<t> <t>
0x01 <tt>{ATOMIC, DW, STX}</tt> with 'imm' = ADD means:
</t> </t>
</td> <artwork><![CDATA[
<td> *(u64 *)(dst + offset) += src]]></artwork>
<t> <t>
modifier: return old value In addition to the simple atomic operations, there is also a modifier and
two complex atomic operations:
</t> </t>
</td> <!-- [rfced] Table 11: Is the table title accurate since a modifier is also incl
</tr> uded? Is the modifier part of the complex atomic operations?
<tr>
<td> Current:
<t> Table 11: Complex Atomic Operations
Perhaps:
Table 11: Complex Atomic Operations and a Modifier
-->
<table>
<name>Complex Atomic Operations</name>
<thead>
<tr>
<th>imm</th>
<th>Value</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
FETCH
</t>
</td>
<td>
<t>
0x01
</t>
</td>
<td>
<t>
modifier: return old value
</t>
</td>
</tr>
<tr>
<td>
<t>
XCHG XCHG
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xe0 | FETCH 0xe0 | FETCH
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic exchange atomic exchange
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
CMPXCHG CMPXCHG
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xf0 | FETCH 0xf0 | FETCH
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic compare and exchange atomic compare and exchange
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
The <tt>FETCH</tt> modifier is optional for simple atomic operations, and The <tt>FETCH</tt> modifier is optional for simple atomic operations and
always set for the complex atomic operations. If the <tt>FETCH</tt> flag is always set for the complex atomic operations. If the <tt>FETCH</tt> fla
g
is set, then the operation also overwrites <tt>src</tt> with the value that is set, then the operation also overwrites <tt>src</tt> with the value that
was in memory before it was modified. was in memory before it was modified.
</t> </t>
<t> <t>
The <tt>XCHG</tt> operation atomically exchanges <tt>src</tt> with the valu e The <tt>XCHG</tt> operation atomically exchanges <tt>src</tt> with the valu e
addressed by <tt>dst + offset</tt>. addressed by <tt>dst + offset</tt>.
</t> </t>
<t> <t>
The <tt>CMPXCHG</tt> operation atomically compares the value addressed by The <tt>CMPXCHG</tt> operation atomically compares the value addressed by
<tt>dst + offset</tt> with <tt>R0</tt>. If they match, the value addressed by <tt>dst + offset</tt> with <tt>R0</tt>. If they match, the value addressed by
<tt>dst + offset</tt> is replaced with <tt>src</tt>. In either case, the <tt>dst + offset</tt> is replaced with <tt>src</tt>. In either case, the
value that was at <tt>dst + offset</tt> before the operation is zero-extend ed value that was at <tt>dst + offset</tt> before the operation is zero-extend ed
and loaded back to <tt>R0</tt>. and loaded back to <tt>R0</tt>.
</t> </t>
</section> </section>
<section anchor="-4-bit-immediate-instructions" title="64-bit immediate instr <section anchor="_4-bit-immediate-instructions">
uctions"> <name>64-bit Immediate Instructions</name>
<t> <t>
Instructions with the <tt>IMM</tt> 'mode' modifier use the wide instruction Instructions with the <tt>IMM</tt> 'mode' modifier use the wide instruction
encoding defined in <xref target="instruction-encoding">Instruction encodin g</xref>, and use the 'src_reg' field of the encoding defined in <xref target="instruction-encoding">Instruction encodin g</xref>, and use the 'src_reg' field of the
basic instruction to hold an opcode subtype. basic instruction to hold an opcode subtype.
</t> </t>
<t> <t>
The following table defines a set of <tt>{IMM, DW, LD}</tt> instructions The following table defines a set of <tt>{IMM, DW, LD}</tt> instructions
with opcode subtypes in the 'src_reg' field, using new terms such as "map" with opcode subtypes in the 'src_reg' field, using new terms such as "map"
defined further below: defined further below:
</t>
<table>
<name>64-bit immediate instructions</name>
<thead>
<tr>
<th>src_reg</th>
<th>pseudocode</th>
<th>imm type</th>
<th>dst type</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
0x0
</t> </t>
</td> <table>
<td> <name>64-bit Immediate Instructions</name>
<t> <thead>
<tr>
<th>src_reg</th>
<th>Pseudocode</th>
<th>imm Type</th>
<th>dst Type</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
0x0
</t>
</td>
<td>
<t>
dst = (next_imm &lt;&lt; 32) | imm dst = (next_imm &lt;&lt; 32) | imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
integer integer
</t> </t>
</td> </td>
<td> <td>
<t> <t>
integer integer
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x1 0x1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_by_fd(imm) dst = map_by_fd(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
map fd map fd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
map map
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x2 0x2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_val(map_by_fd(imm)) + next_imm dst = map_val(map_by_fd(imm)) + next_imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
map fd map fd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
data address data address
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x3 0x3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = var_addr(imm) dst = var_addr(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
variable id variable id
</t> </t>
</td> </td>
<td> <td>
<t> <t>
data address data address
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x4 0x4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = code_addr(imm) dst = code_addr(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
integer integer
</t> </t>
</td> </td>
<td> <td>
<t> <t>
code address code address
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x5 0x5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_by_idx(imm) dst = map_by_idx(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
map index map index
</t> </t>
</td> </td>
<td> <td>
<t> <t>
map map
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x6 0x6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_val(map_by_idx(imm)) + next_imm dst = map_val(map_by_idx(imm)) + next_imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
map index map index
</t> </t>
</td> </td>
<td> <td>
<t> <t>
data address data address
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
where where
</t> </t>
<ul> <ul>
<li> <li>
map_by_fd(imm) means to convert a 32-bit file descriptor into an address o f a map (see <xref target="maps">Maps</xref>) map_by_fd(imm) means to convert a 32-bit file descriptor into an address o f a map (see <xref target="maps">Maps</xref>)
</li> </li>
<li> <li>
map_by_idx(imm) means to convert a 32-bit index into an address of a map map_by_idx(imm) means to convert a 32-bit index into an address of a map
</li> </li>
<li> <li>
map_val(map) gets the address of the first value in a given map map_val(map) gets the address of the first value in a given map
</li> </li>
<li> <li>
var_addr(imm) gets the address of a platform variable (see <xref target="p latform-variables">Platform Variables</xref>) with a given id var_addr(imm) gets the address of a platform variable (see <xref target="p latform-variables">Platform Variables</xref>) with a given id
</li> </li>
<li> <li>
code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions
</li> </li>
<li> <li>
the 'imm type' can be used by disassemblers for display the 'imm type' can be used by disassemblers for display
</li> </li>
<li>
the 'dst type' can be used for verification and JIT compilation purposes <li>
the 'dst type' can be used for verification and just-in-time compilation p
urposes
</li> </li>
</ul> </ul>
<section anchor="maps" title="Maps"> <section anchor="maps">
<t> <name>Maps</name>
<t>
Maps are shared memory regions accessible by BPF programs on some platform s. Maps are shared memory regions accessible by BPF programs on some platform s.
A map can have various semantics as defined in a separate document, and ma y or A map can have various semantics as defined in a separate document, and ma y or
may not have a single contiguous memory region, but the 'map_val(map)' is may not have a single contiguous memory region, but the 'map_val(map)' is
currently only defined for maps that do have a single contiguous memory re gion. currently only defined for maps that do have a single contiguous memory re gion.
</t> </t>
<t> <t>
Each map can have a file descriptor (fd) if supported by the platform, whe re Each map can have a file descriptor (fd) if supported by the platform, whe re
'map_by_fd(imm)' means to get the map with the specified file descriptor. Each 'map_by_fd(imm)' means to get the map with the specified file descriptor. Each
BPF program can also be defined to use a set of maps associated with the BPF program can also be defined to use a set of maps associated with the
program at load time, and 'map_by_idx(imm)' means to get the map with the given program at load time, and 'map_by_idx(imm)' means to get the map with the given
index in the set associated with the BPF program containing the instructio n. index in the set associated with the BPF program containing the instructio n.
</t> </t>
</section> </section>
<section anchor="platform-variables" title="Platform Variables"> <section anchor="platform-variables">
<t> <name>Platform Variables</name>
<t>
Platform variables are memory regions, identified by integer ids, exposed by Platform variables are memory regions, identified by integer ids, exposed by
the runtime and accessible by BPF programs on some platforms. The the runtime, and accessible by BPF programs on some platforms. The
'var_addr(imm)' operation means to get the address of the memory region 'var_addr(imm)' operation means to get the address of the memory region
identified by the given id. identified by the given id.
</t> </t>
</section> </section>
</section> </section>
<section anchor="legacy-bpf-packet-access-instructions" title="Legacy BPF Pac <section anchor="legacy-bpf-packet-access-instructions">
ket access instructions"> <name>Legacy BPF Packet Access Instructions</name>
<t> <t>
BPF previously introduced special instructions for access to packet data th at were BPF previously introduced special instructions for access to packet data th at were
carried over from classic BPF. These instructions used an instruction carried over from classic BPF. These instructions used an instruction
class of <tt>LD</tt>, a size modifier of <tt>W</tt>, <tt>H</tt>, or <tt>B</ tt>, and a class of <tt>LD</tt>, a size modifier of <tt>W</tt>, <tt>H</tt>, or <tt>B</ tt>, and a
mode modifier of <tt>ABS</tt> or <tt>IND</tt>. The 'dst_reg' and 'offset' fields were mode modifier of <tt>ABS</tt> or <tt>IND</tt>. The 'dst_reg' and 'offset' fields were
set to zero, and 'src_reg' was set to zero for <tt>ABS</tt>. However, thes e set to zero, and 'src_reg' was set to zero for <tt>ABS</tt>. However, thes e
instructions are deprecated and SHOULD no longer be used. All legacy packe t instructions are deprecated and <bcp14>SHOULD</bcp14> no longer be used. A ll legacy packet
access instructions belong to the "packet" conformance group. access instructions belong to the "packet" conformance group.
</t> </t>
</section> </section>
</section> </section>
<section anchor="security-considerations" title="Security Considerations"> <section anchor="security-considerations">
<t> <name>Security Considerations</name>
<t>
BPF programs could use BPF instructions to do malicious things with memory, CPU, networking, BPF programs could use BPF instructions to do malicious things with memory, CPU, networking,
or other system resources. This is not fundamentally different from any oth er type of or other system resources. This is not fundamentally different from any oth er type of
software that may run on a device. Execution environments should be careful ly designed software that may run on a device. Execution environments should be careful ly designed
to only run BPF programs that are trusted and verified, and sandboxing and p rivilege level to only run BPF programs that are trusted and verified, and sandboxing and p rivilege level
separation are key strategies for limiting security and abuse impact. For e xample, BPF separation are key strategies for limiting security and abuse impact. For e xample, BPF
verifiers are well-known and widely deployed and are responsible for ensurin g that BPF programs verifiers are well-known and widely deployed and are responsible for ensurin g that BPF programs
will terminate within a reasonable time, only interact with memory in safe w ays, adhere to will terminate within a reasonable time, only interact with memory in safe w ays, adhere to
platform-specified API contracts, and don't use instructions with undefined behavior. platform-specified API contracts, and don't use instructions with undefined behavior.
This level of verification can often provide a stronger level This level of verification can often provide a stronger level
of security assurance than for other software and operating system code. of security assurance than for other software and operating system code.
While the details are out of scope of this document, While the details are out of scope of this document,
<xref target="LINUX">Linux</xref> and <xref target="LINUX">Linux</xref> and
<xref target="PREVAIL">PREVAIL</xref> do provide many details. Future IETF work will document verifier expectations <xref target="PREVAIL">PREVAIL</xref> provide many details. Future IETF wor k will document verifier expectations
and building blocks for allowing safe execution of untrusted BPF programs. and building blocks for allowing safe execution of untrusted BPF programs.
</t> </t>
<t>
<t>
Executing programs using the BPF instruction set also requires either an int erpreter or a compiler Executing programs using the BPF instruction set also requires either an int erpreter or a compiler
to translate them to hardware processor native instructions. In general, int erpreters are considered a to translate them to hardware processor native instructions. In general, int erpreters are considered a
source of insecurity (e.g., gadgets susceptible to side-channel attacks due to speculative execution) source of insecurity (e.g., gadgets susceptible to side-channel attacks due to speculative execution)
whenever one is used in the same memory address space as data with confident iality whenever one is used in the same memory address space as data with confident iality
concerns. As such, use of a compiler is recommended instead. Compilers sho uld be audited concerns. As such, use of a compiler is recommended instead. Compilers sho uld be audited
carefully for vulnerabilities to ensure that compilation of a trusted and ve rified BPF program carefully for vulnerabilities to ensure that compilation of a trusted and ve rified BPF program
to native processor instructions does not introduce vulnerabilities. to native processor instructions does not introduce vulnerabilities.
</t> </t>
<t> <t>
Exposing functionality via BPF extends the interface between the component e xecuting the BPF program and the Exposing functionality via BPF extends the interface between the component e xecuting the BPF program and the
component submitting it. Careful consideration of what functionality is expo sed and how component submitting it. Careful consideration of what functionality is expo sed and how
that impacts the security properties desired is required. that impacts the security properties desired is required.
</t> </t>
</section> </section>
<section anchor="iana-considerations" title="IANA Considerations"> <section anchor="iana-considerations">
<t> <name>IANA Considerations</name>
<t>
This document defines two registries. This document defines two registries.
</t> </t>
<section anchor="bpf-instruction-conformance-group-registry" title="BPF Instr <section anchor="bpf-instruction-conformance-group-registry">
uction Conformance Group Registry"> <name>BPF Instruction Conformance Groups Registry</name>
<t> <t>
This document defines an IANA registry for BPF instruction conformance grou ps, as follows: This document defines an IANA registry for BPF instruction conformance grou ps, as follows:
</t> </t>
<ul> <ul>
<li> <li>
Name of the registry: BPF Instruction Conformance Groups Name of the registry: BPF Instruction Conformance Groups
</li> </li>
<li> <li>
Name of the registry group: BPF Instructions Name of the registry group: BPF Instructions
</li> </li>
<li> <li>
Required information for registrations: See <xref target="bpf-instruction- Required information for registrations: See <xref target="bpf-instruction-
conformance-group-registration-template">BPF Instruction Conformance Group Regis conformance-group-registration-template">BPF Instruction Conformance Groups Regi
tration Template</xref> stration Template</xref>
</li> </li>
<li> <!-- [rfced] Sections 7.1 and 7.2: Should change controller be listed as well?
Section 7.1:
* Syntax of registry entries: Each entry has the following fields:
name, description, includes, excludes, status, and reference. See
BPF Instruction Conformance Group Registration Template
(Section 7.1.1) for more details.
Section 7.2:
* Syntax of registry entries: Each entry has the following fields:
opcode, src, imm, offset, description, groups, and reference. See
BPF Instruction Registration Template (Section 7.2.1) for more
details.
-->
<li>
Syntax of registry entries: Each entry has the following fields: name, des cription, includes, excludes, Syntax of registry entries: Each entry has the following fields: name, des cription, includes, excludes,
status, and reference. See <xref target="bpf-instruction-conformance-group -registration-template">BPF Instruction Conformance Group Registration Template< /xref> for more details. status, and reference. See <xref target="bpf-instruction-conformance-group -registration-template">BPF Instruction Conformance Groups Registration Template </xref> for more details.
</li> </li>
<li> <li>
<t>
Registration policy (see <xref target="RFC8126" section="4"/> for details) : Registration policy (see <xref target="RFC8126" section="4"/> for details) :
<ul> </t>
<li> <ul>
Permanent: Standards action or IESG Approval <li>
Permanent: Standards Action or IESG Approval
</li> </li>
<li> <li>
Provisional: Specification required Provisional: Specification Required
</li> </li>
<li> <li>
Historical: Specification required Historical: Specification Required
</li> </li>
</ul> </ul>
</li> </li>
</ul> </ul>
<t> <!-- [rfced] Sections 7.1 and 7.2: We note that section 7.5 talks about the chan
Initial entries in this registry are as follows: ge controller. However, a change controller is not listed for the initial regis
</t> trations. IANA has listed the IETF as the change controller. May we add a sent
<table> ence like the following to indicate the change controller? We recommend adding
<name>Initial conformance groups</name> text rather than a new column to the table to avoid table width issues.
<thead>
<tr> Perhaps:
<th>name</th> The change controller for the initial entries is the IETF.
<th>description</th>
<th>includes</th> In addition, we note that a Contact is required by the registration templates.
<th>excludes</th> Should a contact be added?
<th>status</th> -->
<th>reference</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t> <t>
atomic32 Initial entries in this registry are as follows:
</t> </t>
</td> <table>
<td> <name>Initial Conformance Groups</name>
<t> <thead>
<tr>
<th>Name</th>
<th>Description</th>
<th>Includes</th>
<th>Excludes</th>
<th>Status</th>
<th>Reference</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
atomic32
</t>
</td>
<td>
<t>
32-bit atomic instructions 32-bit atomic instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
<td> <td>
<t> <!-- [rfced] We recommend removing the section titles from the tables, because t
RFCXXX <xref target="atomic-operations">Atomic operations</xref> he link is redundant with the section link. In addition, removal narrows the ta
</t> ble width to better fit witin the 69-character limit (tables cannot be outdented
</td> ).
</tr> Note: Currently, table 18 is 7 characters over the 69-character limit.
<tr>
<td> Please see tables 13 and 18 in the following. With the adjustments, there are n
<t> o issues with the line lengths.
https://www.rfc-editor.org/authors/rfc9669tablelength.html#table-13
https://www.rfc-editor.org/authors/rfc9669tablelength.html#table-18
https://www.rfc-editor.org/authors/rfc9669tablelength.pdf
https://www.rfc-editor.org/authors/rfc9669tablelength.txt
-->
<!-- [rfced] In general, links to section titles and section numbers are redunda
nt and may be distracting for readers. As such, we recommend removing the links
to section titles throughout the document. Please let us know if this is accep
table.
Please note that that if the linked section titles are to remain, we will update
so the capitalization matches the section titles.
-->
<t>
RFC 9669 <xref target="atomic-operations" format="title">Atomic operati
ons</xref>
</t>
</td>
</tr>
<tr>
<td>
<t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
64-bit atomic instructions 64-bit atomic instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
<td> <td>
<t> <t>
RFCXXX <xref target="atomic-operations">Atomic operations</xref> RFC 9669, <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
32-bit base instructions 32-bit base instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
<td> <td>
<t> <t>
RFCXXX RFC 9669
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
64-bit base instructions 64-bit base instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
<td> <td>
<t> <t>
RFCXXX RFC 9669
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
32-bit division and modulo 32-bit division and modulo
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
<td> <td>
<t> <t>
RFCXXX <xref target="arithmetic-instructions">Arithmetic instructions</ RFC 9669, <xref target="arithmetic-instructions">Arithmetic instruction
xref> s</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
64-bit division and modulo 64-bit division and modulo
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
<td> <td>
<t> <t>
RFCXXX <xref target="arithmetic-instructions">Arithmetic instructions</ RFC 9669, <xref target="arithmetic-instructions">Arithmetic instruction
xref> s</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
packet packet
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Legacy packet instructions Legacy packet instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Historical Historical
</t> </t>
</td> </td>
<td> <td>
<t> <t>
RFCXXX <xref target="legacy-bpf-packet-access-instructions">Legacy BPF RFC 9669, <xref target="legacy-bpf-packet-access-instructions">Legacy B
Packet access instructions</xref> PF Packet access instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t>
NOTE TO RFC-EDITOR: Upon publication, please replace RFCXXX above with refe <section anchor="bpf-instruction-conformance-group-registration-template
rence to this document. ">
</t> <name>BPF Instruction Conformance Groups Registration Template</name>
<section anchor="bpf-instruction-conformance-group-registration-template" ti <t>
tle="BPF Instruction Conformance Group Registration Template"> This template describes the fields that must be supplied in a registration
<t> request:
This template describes the fields that must be supplied in a registration </t>
request <dl>
suitable for adding to the registry: <dt anchor="term-name_">
</t>
<dl>
<dt anchor="term-name:">
Name: Name:
</dt> </dt>
<dd> <dd>
<t> <t>
Alphanumeric label indicating the name of the conformance group. Alphanumeric label indicating the name of the conformance group.
</t> </t>
</dd> </dd>
<dt anchor="term-description:"> <dt anchor="term-description_">
Description: Description:
</dt> </dt>
<dd> <dd>
<t> <t>
Brief description of the conformance group. Brief description of the conformance group.
</t> </t>
</dd> </dd>
<dt anchor="term-includes:"> <dt anchor="term-includes_">
Includes: Includes:
</dt> </dt>
<dd> <dd>
<t> <t>
Any other conformance groups that are included by this group. Any other conformance groups that are included by this group.
</t> </t>
</dd> </dd>
<dt anchor="term-excludes:"> <dt anchor="term-excludes_">
Excludes: Excludes:
</dt> </dt>
<dd> <dd>
<t> <t>
Any other conformance groups that are excluded by this group. Any other conformance groups that are excluded by this group.
</t> </t>
</dd> </dd>
<dt anchor="term-status:"> <dt anchor="term-status_">
Status: Status:
</dt> </dt>
<dd> <dd>
<t> <t>
This reflects the status requested and must be one of 'Permanent', This reflects the status requested and must be one of 'Permanent',
'Provisional', or 'Historical'. 'Provisional', or 'Historical'.
</t> </t>
</dd> </dd>
<dt anchor="term-contact:"> <dt anchor="term-contact_">
Contact: Contact:
</dt> </dt>
<dd> <dd>
<t> <t>
Person (including contact information) to contact for further informatio n. Person (including contact information) to contact for further informatio n.
</t> </t>
</dd> </dd>
<dt anchor="term-change-controller:"> <dt anchor="term-change-controller_">
Change controller: Change Controller:
</dt> </dt>
<dd> <dd>
<t> <!-- [rfced] Sections 7.1.1 and 7.2.1: For clarity, should "often the author" be
"often the author of the defining specification"?
Change controller: Organization or person (often the author),
including contact information, authorized to change this.
-->
<t>
Organization or person (often the author), including contact information , Organization or person (often the author), including contact information ,
authorized to change this. authorized to change this.
</t> </t>
</dd> </dd>
<dt anchor="term-reference:"> <!-- [rfced] Sections 7.1.1 and 7.2.1: Is it correct that the provisional entry
will be updated to permanent when the document is approved for publication as an
RFC?
Original:
Reference: A reference to the defining specification. Include full
citations for all referenced documents. Registration requests for
'Provisional' registration can be included in an Internet-Draft;
when the documents are approved for publication as an RFC, the
registration will be updated.
Perhaps:
Reference: A reference to the defining specification. Include full
citations for all referenced documents. Registration requests for
'Provisional' registration can be included in an Internet-Draft;
when the documents are approved for publication as an RFC, the
registration will be updated to 'Permanent'.
-->
<dt anchor="term-reference_">
Reference: Reference:
</dt> </dt>
<dd> <dd>
<t> <t>
A reference to the defining specification. A reference to the defining specification.
Include full citations for all referenced documents. Include full citations for all referenced documents.
Registration requests for 'Provisional' registration can be Registration requests for 'Provisional' registration can be
included in an Internet-Draft; when the documents are included in an Internet-Draft; when the documents are
approved for publication as an RFC, the registration will be approved for publication as an RFC, the registration will be
updated. updated.
</t> </t>
</dd> </dd>
</dl> </dl>
</section> </section>
</section> </section>
<section anchor="bpf-instruction-set-registry" title="BPF Instruction Set Reg <section anchor="bpf-instruction-set-registry">
istry"> <name>BPF Instruction Set Registry</name>
<t> <t>
This document proposes a new IANA registry for BPF instructions, as follows This document defines an IANA registry for BPF instructions, as follows:
: </t>
</t> <ul>
<ul> <li>
<li>
Name of the registry: BPF Instruction Set Name of the registry: BPF Instruction Set
</li> </li>
<li> <li>
Name of the registry group: BPF Instructions Name of the registry group: BPF Instructions
</li> </li>
<li> <li>
Required information for registrations: See <xref target="bpf-instruction- registration-template">BPF Instruction Registration Template</xref> Required information for registrations: See <xref target="bpf-instruction- registration-template">BPF Instruction Registration Template</xref>
</li> </li>
<li> <!-- [rfced] Section 7.2.1: The registration template specifies "Src". The colum
Syntax of registry entries: Each entry has the following fields: opcode, s n header in the IANA BPF Instruction Set registry is "Src_Reg", which matches th
rc, imm, offset, description, e header in Table 18. Please review and let us know which is correct.
Original:
Src: Either a numeric value indicating the value of the src field,
or "any"
-->
<li>
Syntax of registry entries: Each entry has the following fields: opcode, s
rc, offset, imm, description,
groups, and reference. See <xref target="bpf-instruction-registration-temp late">BPF Instruction Registration Template</xref> for more details. groups, and reference. See <xref target="bpf-instruction-registration-temp late">BPF Instruction Registration Template</xref> for more details.
</li> </li>
<li>
<li>
Registration policy: New instructions require a new entry in the conforman ce group Registration policy: New instructions require a new entry in the conforman ce group
registry and the same registration policies apply. registry and the same registration policies apply.
</li> </li>
<li> <li>
Initial registrations: See the Appendix. Instructions other than those lis Initial registrations: See <xref target="appendix"/>. Instructions other t
ted han those listed
as deprecated are Permanent. Any listed as deprecated are Historical. as deprecated are Permanent. Any listed as deprecated are Historical.
</li> </li>
</ul> </ul>
<section anchor="bpf-instruction-registration-template" title="BPF Instructi <section anchor="bpf-instruction-registration-template">
on Registration Template"> <name>BPF Instruction Registration Template</name>
<t> <!-- [rfced] Section 7.2.1: We have swapped the order of Imm and Offset in the l
This template describes the fields that must be supplied in a registration ist so it matches the order in which they appear in the table of initial registr
request ations. Please let us know any concerns.
suitable for adding to the registry: -->
</t> <t>
<dl> This template describes the fields that must be supplied in a registration
<dt anchor="term-opcode:"> request:
</t>
<dl>
<dt anchor="term-opcode_">
Opcode: Opcode:
</dt> </dt>
<dd> <dd>
<t> <t>
A 1-byte value in hex format indicating the value of the opcode field A 1-byte value in hex format indicating the value of the opcode field.
</t> </t>
</dd> </dd>
<dt anchor="term-src:"> <dt anchor="term-src_">
Src: Src:
</dt> </dt>
<dd> <dd>
<t> <t>
Either a numeric value indicating the value of the src field, or "any" Either a numeric value indicating the value of the src field, or "any".
</t> </t>
</dd> </dd>
<dt anchor="term-imm:">
Imm: <dt anchor="term-offset_">
</dt>
<dd>
<t>
Either a value indicating the value of the imm field, or "any"
</t>
</dd>
<dt anchor="term-offset:">
Offset: Offset:
</dt> </dt>
<dd> <dd>
<t> <t>
Either a numeric value indicating the value of the offset field, or "any Either a numeric value indicating the value of the offset field, or "any
" ".
</t> </t>
</dd> </dd>
<dt anchor="term-description:-">
<dt anchor="term-imm_">
Imm:
</dt>
<dd>
<t>
Either a value indicating the value of the imm field, or "any".
</t>
</dd>
<dt anchor="term-description_-">
Description: Description:
</dt> </dt>
<dd> <dd>
<t> <t>
Description of what the instruction does, typically in pseudocode Description of what the instruction does, typically in pseudocode.
</t> </t>
</dd> </dd>
<dt anchor="term-groups:"> <dt anchor="term-groups_">
Groups: Groups:
</dt> </dt>
<dd> <dd>
<t> <t>
A list of one or more comma-separated conformance groups to which the in A list of one or more comma-separated conformance groups to which the in
struction belongs struction belongs.
</t> </t>
</dd> </dd>
<dt anchor="term-contact:-"> <dt anchor="term-contact_-">
Contact: Contact:
</dt> </dt>
<dd> <dd>
<t> <t>
Person (including contact information) to contact for further informatio n. Person (including contact information) to contact for further informatio n.
</t> </t>
</dd> </dd>
<dt anchor="term-change-controller:-"> <dt anchor="term-change-controller_-">
Change controller: Change Controller:
</dt> </dt>
<dd> <dd>
<t> <t>
Organization or person (often the author), including contact information , Organization or person (often the author), including contact information ,
authorized to change this. authorized to change this.
</t> </t>
</dd> </dd>
<dt anchor="term-reference:-"> <dt anchor="term-reference_-">
Reference: Reference:
</dt> </dt>
<dd> <dd>
<t> <t>
A reference to the defining specification. A reference to the defining specification.
Include full citations for all referenced documents. Include full citations for all referenced documents.
Registration requests for 'Provisional' registration can be Registration requests for 'Provisional' registration can be
included in an Internet-Draft; when the documents are included in an Internet-Draft; when the documents are
approved for publication as an RFC, the registration will be approved for publication as an RFC, the registration will be
updated. updated.
</t> </t>
</dd> </dd>
</dl> </dl>
</section> </section>
</section> </section>
<section anchor="adding-instructions" title="Adding instructions"> <section anchor="adding-instructions">
<t> <name>Adding Instructions</name>
<t>
A specification may add additional instructions to the BPF Instruction Set registry. A specification may add additional instructions to the BPF Instruction Set registry.
Once a conformance group is registered with a set of instructions, Once a conformance group is registered with a set of instructions,
no further instructions can be added to that conformance group. A specifica tion no further instructions can be added to that conformance group. A specifica tion
should instead create a new conformance group that includes the original co nformance group, should instead create a new conformance group that includes the original co nformance group,
plus any newly added instructions. Inclusion of the original conformance g roup is done plus any newly added instructions. Inclusion of the original conformance g roup is done
via the "includes" column of the BPF Instruction Conformance Group Registry via the "includes" column of the BPF Instruction Conformance Groups registr
, and inclusion y, and inclusion
of newly added instructions is done via the "groups" column of the BPF Inst of newly added instructions is done via the "groups" column of the BPF Inst
ruction Set Registry. ruction Set registry.
</t> </t>
<t> <t>
For example, consider an existing hypothetical group called "example" with two instructions in it. For example, consider an existing hypothetical group called "example" with two instructions in it.
One might add two more instructions by first adding an "examplev2" group to the One might add two more instructions by first adding an "examplev2" group to the
BPF Instruction Conformance Group Registry as follows: BPF Instruction Conformance Groups registry as follows:
</t>
<table>
<name>Conformance group example for addition</name>
<thead>
<tr>
<th>name</th>
<th>description</th>
<th>includes</th>
<th>excludes</th>
<th>status</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
example
</t> </t>
</td> <table>
<td> <name>Conformance Group Example for Addition</name>
<t> <thead>
<tr>
<th>Name</th>
<th>Description</th>
<th>Includes</th>
<th>Excludes</th>
<th>Status</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
example
</t>
</td>
<td>
<t>
Original example instructions Original example instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
examplev2 examplev2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Newer set of example instructions Newer set of example instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example example
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t>
And then adding the new instructions into the BPF Instruction Set Registry
as follows:
</t>
<table>
<name>Instruction addition example</name>
<thead>
<tr>
<th>opcode</th>
<th>...</th>
<th>description</th>
<th>groups</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t> <t>
aaa And then adding the new instructions into the BPF Instruction Set registry as follows:
</t> </t>
</td> <table>
<td> <name>Instruction Addition Example</name>
<t> <thead>
<tr>
<th>Opcode</th>
<th>...</th>
<th>Description</th>
<th>Groups</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
aaa
</t>
</td>
<td>
<t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Original example instruction 1 Original example instruction 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example example
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
bbb bbb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Original example instruction 2 Original example instruction 2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example example
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ccc ccc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Added example instruction 3 Added example instruction 3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
examplev2 examplev2
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ddd ddd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Added example instruction 4 Added example instruction 4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
examplev2 examplev2
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
Supporting the "examplev2" group thus requires supporting all four example instructions. Supporting the "examplev2" group thus requires supporting all four example instructions.
</t> </t>
</section> </section>
<section anchor="deprecating-instructions" title="Deprecating instructions"> <section anchor="deprecating-instructions">
<t> <name>Deprecating Instructions</name>
<t>
Deprecating instructions that are part of an existing conformance group can be done by defining a Deprecating instructions that are part of an existing conformance group can be done by defining a
new conformance group for the newly deprecated instructions, and defining a new conformance group new conformance group for the newly deprecated instructions, and defining a new conformance group
that supersedes the existing conformance group containing the instructions, where the new conformance that supersedes the existing conformance group containing the instructions, where the new conformance
group includes the existing one and excludes the deprecated instruction gro up. group includes the existing one and excludes the deprecated instruction gro up.
</t>
<t>
For example, if deprecating an instruction in an existing hypothetical grou
p called "example", two new groups
("legacyexample" and "examplev2") might be registered in the BPF Instructio
n Conformance Group
Registry as follows:
</t>
<table>
<name>Conformance group example for deprecation</name>
<thead>
<tr>
<th>name</th>
<th>description</th>
<th>includes</th>
<th>excludes</th>
<th>status</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
example
</t> </t>
</td>
<td>
<t> <t>
Original example instructions For example, if deprecating an instruction in an existing hypothetical grou
p called "example", two new groups
("legacyexample" and "examplev2") might be registered in the BPF Instructio
n Conformance Groups
registry as follows:
</t> </t>
</td> <table>
<td> <name>Conformance Group Example for Deprecation</name>
<t> <thead>
<tr>
<th>Name</th>
<th>Description</th>
<th>Includes</th>
<th>Excludes</th>
<th>Status</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
example
</t>
</td>
<td>
<t>
Original example instructions
</t>
</td>
<td>
<t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
legacyexample legacyexample
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Legacy example instructions Legacy example instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
- -
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Historical Historical
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
examplev2 examplev2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Example instructions Example instructions
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example example
</t> </t>
</td> </td>
<td> <td>
<t> <t>
legacyexample legacyexample
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Permanent Permanent
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t>
The BPF Instruction Set Registry entries for the deprecated instructions wo
uld then be updated
to add "legacyexample" to the set of groups for those instructions, as foll
ows:
</t>
<table>
<name>Instruction deprecation example</name>
<thead>
<tr>
<th>opcode</th>
<th>...</th>
<th>description</th>
<th>groups</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t> <t>
aaa The BPF Instruction Set registry entries for the deprecated instructions wo
uld then be updated
to add "legacyexample" to the set of groups for those instructions, as foll
ows:
</t> </t>
</td> <table>
<td> <name>Instruction Deprecation Example</name>
<t> <thead>
<tr>
<th>Opcode</th>
<th>...</th>
<th>Description</th>
<th>Groups</th>
</tr>
</thead>
<tbody>
<tr>
<td>
<t>
aaa
</t>
</td>
<td>
<t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Good original instruction 1 Good original instruction 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example example
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
bbb bbb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Good original instruction 2 Good original instruction 2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example example
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ccc ccc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Bad original instruction 3 Bad original instruction 3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example, legacyexample example, legacyexample
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
ddd ddd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
... ...
</t> </t>
</td> </td>
<td> <td>
<t> <t>
Bad original instruction 4 Bad original instruction 4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
example, legacyexample example, legacyexample
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
<t> <t>
Finally, updated implementations that dropped support for the deprecated in structions Finally, updated implementations that dropped support for the deprecated in structions
would then be able to claim conformance to "examplev2" rather than "example ". would then be able to claim conformance to "examplev2" rather than "example ".
</t> </t>
</section> </section>
<section anchor="change-control" title="Change Control"> <section anchor="change-control">
<t> <name>Change Control</name>
<!-- [rfced] Section 7.5: This text makes it sound as though the IESG is the cha
nge controller. The IANA registries list the change controller as the IETF. In
addition, their guidance recommends that the change contoller be listed as the
IETF (see https://www.iana.org/help/protocol-registration). Based on discussion
with Amanda (from IANA), please consider the following update:
Original:
In cases where the original
definition of an entry is contained in an IESG-approved document,
update of the specification also requires IESG approval.
Perhaps:
In cases where the original
definition of an entry is contained in an IESG-approved document,
in which case the IETF would be the change controller,
update of the specification also requires IESG approval.
-->
<t>
Registrations can be updated in a registry by the same mechanism as Registrations can be updated in a registry by the same mechanism as
required for an initial registration. In cases where the original required for an initial registration. In cases where the original
definition of an entry is contained in an IESG-approved document, definition of an entry is contained in an IESG-approved document,
update of the specification also requires IESG approval. update of the specification also requires IESG approval.
</t> </t>
<t> <t>
'Provisional' registrations can be updated by the change controller 'Provisional' registrations can be updated by the change controller
designated in the existing registration. In addition, the designated in the existing registration. In addition, the
IESG can reassign responsibility for a 'Provisional' registration IESG can reassign responsibility for a 'Provisional' registration
or can request specific changes to an entry. or can request specific changes to an entry.
This will enable changes to be made to entries where the original This will enable changes to be made to entries where the original
registrant is out of contact or unwilling or unable to make changes. registrant is out of contact or unwilling or unable to make changes.
</t> </t>
<t> <t>
Transition from 'Provisional' to 'Permanent' status can be requested Transition from 'Provisional' to 'Permanent' status can be requested
and approved in the same manner as a new 'Permanent' registration. and approved in the same manner as a new 'Permanent' registration.
Transition from 'Permanent' to 'Historical' status requires IESG Transition from 'Permanent' to 'Historical' status requires IESG
approval. Transition from 'Provisional' to 'Historical' can be approval. Transition from 'Provisional' to 'Historical' can be
requested by anyone authorized to update the 'Provisional' requested by anyone authorized to update the 'Provisional'
registration. registration.
</t> </t>
</section> </section>
<section anchor="expert-review-instructions" title="Expert Review Instruction <section anchor="expert-review-instructions">
s"> <name>Expert Review Instructions</name>
<t> <t>
The IANA registries established by this document are informed by written The IANA registries established by this document are informed by written
specifications, which themselves are facilitated and approved by specifications, which themselves are facilitated and approved by
an Expert Review <xref target="RFC8126" section="5.3"/> an Expert Review process (see <xref target="RFC8126" section="5.3"/>).
process. </t>
</t> <t>
<t> Designated experts are expected to consult with the active
Designated Experts are expected to consult with the active
BPF working group (e.g., via email to the working group's mailing list) BPF working group (e.g., via email to the working group's mailing list)
if it exists, as well as other interested parties (e.g., via email to if it exists, as well as other interested parties (e.g., via email to
one or more active mailing list(s) for relevant BPF communities and one or more active mailing list(s) for relevant BPF communities and
platforms). The Designed Expert is expected to verify that the encoding platforms). The designated expert is expected to verify that the encoding
and semantics for any new instructions are properly documented in a and semantics for any new instructions are properly documented in a
public-facing specification. In the event of future RFC documents for ISA public-facing specification. In the event of future RFC documents for ISA
extensions, experts may permit early assignment before the RFC document extensions, experts may permit early assignment before the RFC document
is available, as long as a specification exists which satisfies the above is available, as long as a specification that satisfies the above
requirements. requirements exists.
</t> </t>
</section> </section>
</section> </section>
<section anchor="acknowledgements" title="Acknowledgements">
<t> </middle>
This draft was generated from instruction-set.rst in the Linux <back>
kernel repository, to which a number of other individuals have authored cont <references>
ributions <name>References</name>
over time, including Akhil Raj, Alexei Starovoitov, Brendan Jackman, Christo <references>
ph Hellwig, Daniel Borkmann, <name>Normative References</name>
Ilya Leoshkevich, Jiong Wang, Jose E. Marchesi, Kosuke Fujimoto,
Shahab Vahedi, Tiezhu Yang, Will Hawkins, and Zheng Yejian, with review and <reference anchor="IEN137">
suggestions by many others including <front>
Alan Jowett, Andrii Nakryiko, David Vernet, Jim Harris, <title>ON HOLY WARS AND A PLEA FOR PEACE</title>
Quentin Monnet, Song Liu, Shung-Hsi Yu, Stanislav Fomichev, Watson Ladd, and <author fullname="D. Cohen" initials="D." surname="Cohen"/>
Yonghong Song. <date month="April" year="1980" day="1"/>
</t> </front>
</section> <seriesInfo name="IEN" value="137"/>
<section anchor="appendix" title="Appendix"> </reference>
<t>
Initial values for the BPF Instruction sub-registry are given below. <xi:include href="https://bib.ietf.org/public/rfc/bibxml/reference.RFC.2
119.xml"/>
<xi:include href="https://bib.ietf.org/public/rfc/bibxml/reference.RFC.8
126.xml"/>
<xi:include href="https://bib.ietf.org/public/rfc/bibxml/reference.RFC.8
174.xml"/>
</references>
<references>
<name>Informative References</name>
<reference anchor="LINUX" target="https://www.kernel.org/doc/html/latest
/bpf/verifier.html">
<front>
<title>eBPF verifier</title>
<author/>
</front>
</reference>
<reference anchor="PREVAIL">
<front>
<title>Simple and Precise Static Analysis of Untrusted Linux Kernel
Extensions</title>
<author fullname="E. Gershuni" initials="E." surname="Gershuni"/>
<author fullname="N. Amit" initials="N." surname="Amit"/>
<author fullname="A. Gurfinkel" initials="A." surname="Gurfinkel"/>
<author fullname="N. Narodytska" initials="N." surname="Narodytska"/
>
<author fullname="J. Navas" initials="J." surname="Navas"/>
<author fullname="N. Rinetzky" initials="N." surname="Rinetzky"/>
<author fullname="L. Ryzhyk" initials="L." surname="Ryzhyk"/>
<author fullname="M. Sagiv" initials="M." surname="Sagiv"/>
<date month="June" year="2019"/>
</front>
<seriesInfo name="DOI" value="10.1145/3314221.3314590"/>
</reference>
</references>
</references>
<section anchor="appendix">
<name>Initial BPF Instruction Set Values</name>
<!-- [rfced] The Appendix requires a title other than Appenendix, as the section
will appear as "Appendix A. Title". We have updated the title as shown below.
Please let us know if any changes are desired.
Original:
9. Appendix
Current:
Appendix A. Initial BPF Instruction Set Values
-->
<!-- [rfced] Appendix A: Please verify that the section referred to in the refer
ence is authoritative, as opposed to the IANA registry authoritative.
Original:
Initial values for the BPF Instruction sub-registry are given below.
The descriptions in this table are informative. In case of any
discrepancy, the reference is authoritative.
-->
<t>
Initial values for the BPF Instruction Set registry are given below.
The descriptions in this table are informative. In case of any discrepancy, the reference The descriptions in this table are informative. In case of any discrepancy, the reference
is authoritative. is authoritative.
</t> </t>
<table> <table>
<name>BPF Instruction sub-registry initial values</name> <name>Initial BPF Instruction Set Values</name>
<thead> <thead>
<tr> <tr>
<th>opcode</th> <th>Opcode</th>
<th>src_reg</th> <th>src_reg</th>
<th>offset</th> <th>Offset</th>
<th>imm</th> <th>imm</th>
<th>description</th> <th>Description</th>
<th>groups</th> <th>Groups</th>
<th>reference</th> <th>Reference</th>
</tr> </tr>
</thead> </thead>
<tbody> <tbody>
<tr> <tr>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
(additional immediate value) (additional immediate value)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x04 0x04
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((u32)dst + (u32)imm) dst = (u32)((u32)dst + (u32)imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x05 0x05
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
goto +offset goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x06 0x06
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
goto +imm goto +imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x07 0x07
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst += imm dst += imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x0c 0x0c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((u32)dst + (u32)src) dst = (u32)((u32)dst + (u32)src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x0f 0x0f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst += src dst += src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x14 0x14
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((u32)dst - (u32)imm) dst = (u32)((u32)dst - (u32)imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x15 0x15
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst == imm goto +offset if dst == imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x16 0x16
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst == imm goto +offset if (u32)dst == imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x17 0x17
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst -= imm dst -= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x18 0x18
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (next_imm &lt;&lt; 32) | imm dst = (next_imm &lt;&lt; 32) | imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x18 0x18
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x1 0x1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_by_fd(imm) dst = map_by_fd(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x18 0x18
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x2 0x2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_val(map_by_fd(imm)) + next_imm dst = map_val(map_by_fd(imm)) + next_imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x18 0x18
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x3 0x3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = var_addr(imm) dst = var_addr(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x18 0x18
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x4 0x4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = code_addr(imm) dst = code_addr(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x18 0x18
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x5 0x5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_by_idx(imm) dst = map_by_idx(imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x18 0x18
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x6 0x6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = map_val(map_by_idx(imm)) + next_imm dst = map_val(map_by_idx(imm)) + next_imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="-4-bit-immediate-instructions">64-bit immediate instructio <xref target="_4-bit-immediate-instructions">64-bit immediate instructio
ns</xref> ns</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x1c 0x1c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((u32)dst - (u32)src) dst = (u32)((u32)dst - (u32)src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x1d 0x1d
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst == src goto +offset if dst == src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x1e 0x1e
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst == (u32)src goto +offset if (u32)dst == (u32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x1f 0x1f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst -= src dst -= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x20 0x20
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
(deprecated, implementation-specific) (deprecated, implementation-specific)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
packet packet
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x24 0x24
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst * imm) dst = (u32)(dst * imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x25 0x25
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &gt; imm goto +offset if dst &gt; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x26 0x26
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &gt; imm goto +offset if (u32)dst &gt; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x27 0x27
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst *= imm dst *= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x28 0x28
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
(deprecated, implementation-specific) (deprecated, implementation-specific)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
packet packet
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x2c 0x2c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst * src) dst = (u32)(dst * src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x2d 0x2d
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &gt; src goto +offset if dst &gt; src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x2e 0x2e
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &gt; (u32)src goto +offset if (u32)dst &gt; (u32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x2f 0x2f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst *= src dst *= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x30 0x30
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
(deprecated, implementation-specific) (deprecated, implementation-specific)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
packet packet
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x34 0x34
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((imm != 0) ? ((u32)dst / (u32)imm) : 0) dst = (u32)((imm != 0) ? ((u32)dst / (u32)imm) : 0)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x34 0x34
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((imm != 0) ? ((s32)dst s/ imm) : 0) dst = (u32)((imm != 0) ? ((s32)dst s/ imm) : 0)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x35 0x35
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &gt;= imm goto +offset if dst &gt;= imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x36 0x36
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &gt;= imm goto +offset if (u32)dst &gt;= imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x37 0x37
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (imm != 0) ? (dst / (u32)imm) : 0 dst = (imm != 0) ? (dst / (u32)imm) : 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x37 0x37
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (imm != 0) ? (dst s/ imm) : 0 dst = (imm != 0) ? (dst s/ imm) : 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x3c 0x3c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((src != 0) ? ((u32)dst / (u32)src) : 0) dst = (u32)((src != 0) ? ((u32)dst / (u32)src) : 0)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x3c 0x3c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((src != 0) ? ((s32)dst s/(s32)src) : 0) dst = (u32)((src != 0) ? ((s32)dst s/(s32)src) : 0)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x3d 0x3d
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &gt;= src goto +offset if dst &gt;= src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x3e 0x3e
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &gt;= (u32)src goto +offset if (u32)dst &gt;= (u32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x3f 0x3f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst / src) : 0 dst = (src != 0) ? (dst / src) : 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x3f 0x3f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst s/ src) : 0 dst = (src != 0) ? (dst s/ src) : 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x40 0x40
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
(deprecated, implementation-specific) (deprecated, implementation-specific)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
packet packet
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x44 0x44
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst | imm) dst = (u32)(dst | imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x45 0x45
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &amp; imm goto +offset if dst &amp; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x46 0x46
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &amp; imm goto +offset if (u32)dst &amp; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x47 0x47
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst |= imm dst |= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x48 0x48
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
(deprecated, implementation-specific) (deprecated, implementation-specific)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
packet packet
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x4c 0x4c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst | src) dst = (u32)(dst | src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x4d 0x4d
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &amp; src goto +offset if dst &amp; src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x4e 0x4e
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &amp; (u32)src goto +offset if (u32)dst &amp; (u32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x4f 0x4f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst |= src dst |= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x50 0x50
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
(deprecated, implementation-specific) (deprecated, implementation-specific)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
packet packet
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref> <xref target="legacy-bpf-packet-access-instructions">Legacy BPF Packet a ccess instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x54 0x54
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst &amp; imm) dst = (u32)(dst &amp; imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x55 0x55
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst != imm goto +offset if dst != imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x56 0x56
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst != imm goto +offset if (u32)dst != imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x57 0x57
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &amp;= imm dst &amp;= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x5c 0x5c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst &amp; src) dst = (u32)(dst &amp; src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x5d 0x5d
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst != src goto +offset if dst != src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x5e 0x5e
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst != (u32)src goto +offset if (u32)dst != (u32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x5f 0x5f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &amp;= src dst &amp;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x61 0x61
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = *(u32 *)(src + offset) dst = *(u32 *)(src + offset)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x62 0x62
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u32 *)(dst + offset) = imm *(u32 *)(dst + offset) = imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x63 0x63
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u32 *)(dst + offset) = src *(u32 *)(dst + offset) = src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x64 0x64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst &lt;&lt; imm) dst = (u32)(dst &lt;&lt; imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x65 0x65
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&gt; imm goto +offset if dst s&gt; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x66 0x66
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&gt; (s32)imm goto +offset if (s32)dst s&gt; (s32)imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x67 0x67
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &lt;&lt;= imm dst &lt;&lt;= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x69 0x69
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = *(u16 *)(src + offset) dst = *(u16 *)(src + offset)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x6a 0x6a
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u16 *)(dst + offset) = imm *(u16 *)(dst + offset) = imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x6b 0x6b
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u16 *)(dst + offset) = src *(u16 *)(dst + offset) = src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x6c 0x6c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst &lt;&lt; src) dst = (u32)(dst &lt;&lt; src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x6d 0x6d
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&gt; src goto +offset if dst s&gt; src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x6e 0x6e
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&gt; (s32)src goto +offset if (s32)dst s&gt; (s32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x6f 0x6f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &lt;&lt;= src dst &lt;&lt;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x71 0x71
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = *(u8 *)(src + offset) dst = *(u8 *)(src + offset)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x72 0x72
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u8 *)(dst + offset) = imm *(u8 *)(dst + offset) = imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x73 0x73
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u8 *)(dst + offset) = src *(u8 *)(dst + offset) = src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x74 0x74
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst &gt;&gt; imm) dst = (u32)(dst &gt;&gt; imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x75 0x75
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&gt;= imm goto +offset if dst s&gt;= imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x76 0x76
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&gt;= (s32)imm goto +offset if (s32)dst s&gt;= (s32)imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x77 0x77
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &gt;&gt;= imm dst &gt;&gt;= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x79 0x79
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = *(u64 *)(src + offset) dst = *(u64 *)(src + offset)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x7a 0x7a
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u64 *)(dst + offset) = imm *(u64 *)(dst + offset) = imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x7b 0x7b
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
*(u64 *)(dst + offset) = src *(u64 *)(dst + offset) = src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="load-and-store-instructions">Load and store instructions</ xref> <xref target="load-and-store-instructions">Load and store instructions</ xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x7c 0x7c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst &gt;&gt; src) dst = (u32)(dst &gt;&gt; src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x7d 0x7d
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&gt;= src goto +offset if dst s&gt;= src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x7e 0x7e
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&gt;= (s32)src goto +offset if (s32)dst s&gt;= (s32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x7f 0x7f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst &gt;&gt;= src dst &gt;&gt;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x84 0x84
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)-dst dst = (u32)-dst
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x85 0x85
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
call helper function by static ID call helper function by static ID
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="helper-functions">Helper functions</xref> <xref target="helper-functions">Helper functions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x85 0x85
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x1 0x1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
call PC += imm call PC += imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="program-local-functions">Program-local functions</xref> <xref target="program-local-functions">Program-local functions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x85 0x85
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x2 0x2
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
call helper function by BTF ID call helper function by BTF ID
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="helper-functions">Helper functions</xref> <xref target="helper-functions">Helper functions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x87 0x87
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = -dst dst = -dst
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x94 0x94
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((imm != 0)?((u32)dst % (u32)imm) : dst) dst = (u32)((imm != 0)?((u32)dst % (u32)imm) : dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x94 0x94
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((imm != 0) ? ((s32)dst s% imm) : dst) dst = (u32)((imm != 0) ? ((s32)dst s% imm) : dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x95 0x95
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
return return
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x97 0x97
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (imm != 0) ? (dst % (u32)imm) : dst dst = (imm != 0) ? (dst % (u32)imm) : dst
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x97 0x97
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (imm != 0) ? (dst s% imm) : dst dst = (imm != 0) ? (dst s% imm) : dst
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x9c 0x9c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((src != 0)?((u32)dst % (u32)src) : dst) dst = (u32)((src != 0)?((u32)dst % (u32)src) : dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x9c 0x9c
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)((src != 0)?((s32)dst s% (s32)src) :dst) dst = (u32)((src != 0)?((s32)dst s% (s32)src) :dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul32 divmul32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x9f 0x9f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst % src) : dst dst = (src != 0) ? (dst % src) : dst
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0x9f 0x9f
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
1 1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (src != 0) ? (dst s% src) : dst dst = (src != 0) ? (dst s% src) : dst
</t> </t>
</td> </td>
<td> <td>
<t> <t>
divmul64 divmul64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xa4 0xa4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst ^ imm) dst = (u32)(dst ^ imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xa5 0xa5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &lt; imm goto +offset if dst &lt; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xa6 0xa6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &lt; imm goto +offset if (u32)dst &lt; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xa7 0xa7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst ^= imm dst ^= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xac 0xac
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst ^ src) dst = (u32)(dst ^ src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xad 0xad
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &lt; src goto +offset if dst &lt; src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xae 0xae
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &lt; (u32)src goto +offset if (u32)dst &lt; (u32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xaf 0xaf
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst ^= src dst ^= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xb4 0xb4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32) imm dst = (u32) imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xb5 0xb5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &lt;= imm goto +offset if dst &lt;= imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xb6 0xb6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &lt;= imm goto +offset if (u32)dst &lt;= imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xb7 0xb7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = imm dst = imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbc 0xbc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32) src dst = (u32) src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbc 0xbc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
8 8
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32) (s32) (s8) src dst = (u32) (s32) (s8) src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbc 0xbc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
16 16
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32) (s32) (s16) src dst = (u32) (s32) (s16) src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbd 0xbd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst &lt;= src goto +offset if dst &lt;= src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbe 0xbe
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (u32)dst &lt;= (u32)src goto +offset if (u32)dst &lt;= (u32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbf 0xbf
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = src dst = src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbf 0xbf
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
8 8
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (s64) (s8) src dst = (s64) (s8) src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbf 0xbf
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
16 16
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (s64) (s16) src dst = (s64) (s16) src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xbf 0xbf
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
32 32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (s64) (s32) src dst = (s64) (s32) src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u32 *)(dst + offset) += src lock *(u32 *)(dst + offset) += src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x01 0x01
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_add_32((u32 *)(dst + offset), src) src = atomic_fetch_add_32((u32 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x40 0x40
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u32 *)(dst + offset) |= src lock *(u32 *)(dst + offset) |= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x41 0x41
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_or_32((u32 *)(dst + offset), src) src = atomic_fetch_or_32((u32 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x50 0x50
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u32 *)(dst + offset) &amp;= src lock *(u32 *)(dst + offset) &amp;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x51 0x51
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_and_32((u32 *)(dst + offset), src) src = atomic_fetch_and_32((u32 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xa0 0xa0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u32 *)(dst + offset) ^= src lock *(u32 *)(dst + offset) ^= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xa1 0xa1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_xor_32((u32 *)(dst + offset), src) src = atomic_fetch_xor_32((u32 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xe1 0xe1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = xchg_32((u32 *)(dst + offset), src) src = xchg_32((u32 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc3 0xc3
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xf1 0xf1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
r0 = cmpxchg_32((u32 *)(dst + offset), r0, src) r0 = cmpxchg_32((u32 *)(dst + offset), r0, src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic32 atomic32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc4 0xc4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst s&gt;&gt; imm) dst = (u32)(dst s&gt;&gt; imm)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc5 0xc5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&lt; imm goto +offset if dst s&lt; imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc6 0xc6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&lt; (s32)imm goto +offset if (s32)dst s&lt; (s32)imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xc7 0xc7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst s&gt;&gt;= imm dst s&gt;&gt;= imm
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xcc 0xcc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = (u32)(dst s&gt;&gt; src) dst = (u32)(dst s&gt;&gt; src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xcd 0xcd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&lt; src goto +offset if dst s&lt; src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xce 0xce
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&lt; (s32)src goto +offset if (s32)dst s&lt; (s32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xcf 0xcf
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst s&gt;&gt;= src dst s&gt;&gt;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="arithmetic-instructions">Arithmetic instructions</xref> <xref target="arithmetic-instructions">Arithmetic instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd4 0xd4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x10 0x10
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = htole16(dst) dst = htole16(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd4 0xd4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x20 0x20
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = htole32(dst) dst = htole32(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd4 0xd4
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x40 0x40
</t> </t>
</td>
<td> </td>
<t> <td>
<t>
dst = htole64(dst) dst = htole64(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd5 0xd5
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&lt;= imm goto +offset if dst s&lt;= imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd6 0xd6
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&lt;= (s32)imm goto +offset if (s32)dst s&lt;= (s32)imm goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd7 0xd7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x10 0x10
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = bswap16(dst) dst = bswap16(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd7 0xd7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x20 0x20
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = bswap32(dst) dst = bswap32(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xd7 0xd7
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x40 0x40
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = bswap64(dst) dst = bswap64(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u64 *)(dst + offset) += src lock *(u64 *)(dst + offset) += src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x01 0x01
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_add_64((u64 *)(dst + offset), src) src = atomic_fetch_add_64((u64 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x40 0x40
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u64 *)(dst + offset) |= src lock *(u64 *)(dst + offset) |= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x41 0x41
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_or_64((u64 *)(dst + offset), src) src = atomic_fetch_or_64((u64 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x50 0x50
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u64 *)(dst + offset) &amp;= src lock *(u64 *)(dst + offset) &amp;= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x51 0x51
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_and_64((u64 *)(dst + offset), src) src = atomic_fetch_and_64((u64 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xa0 0xa0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
lock *(u64 *)(dst + offset) ^= src lock *(u64 *)(dst + offset) ^= src
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xa1 0xa1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = atomic_fetch_xor_64((u64 *)(dst + offset), src) src = atomic_fetch_xor_64((u64 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xe1 0xe1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
src = xchg_64((u64 *)(dst + offset), src) src = xchg_64((u64 *)(dst + offset), src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdb 0xdb
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0xf1 0xf1
</t> </t>
</td> </td>
<td> <td>
<t> <t>
r0 = cmpxchg_64((u64 *)(dst + offset), r0, src) r0 = cmpxchg_64((u64 *)(dst + offset), r0, src)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
atomic64 atomic64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="atomic-operations">Atomic operations</xref> <xref target="atomic-operations">Atomic operations</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdc 0xdc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x10 0x10
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = htobe16(dst) dst = htobe16(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdc 0xdc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x20 0x20
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = htobe32(dst) dst = htobe32(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdc 0xdc
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x0 0x0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0 0
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x40 0x40
</t> </t>
</td> </td>
<td> <td>
<t> <t>
dst = htobe64(dst) dst = htobe64(dst)
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="byte-swap-instructions">Byte swap instructions</xref> <xref target="byte-swap-instructions">Byte swap instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xdd 0xdd
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if dst s&lt;= src goto +offset if dst s&lt;= src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base64 base64
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
<tr> <tr>
<td> <td>
<t> <t>
0xde 0xde
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
any any
</t> </t>
</td> </td>
<td> <td>
<t> <t>
0x00 0x00
</t> </t>
</td> </td>
<td> <td>
<t> <t>
if (s32)dst s&lt;= (s32)src goto +offset if (s32)dst s&lt;= (s32)src goto +offset
</t> </t>
</td> </td>
<td> <td>
<t> <t>
base32 base32
</t> </t>
</td> </td>
<td> <td>
<t> <t>
<xref target="jump-instructions">Jump instructions</xref> <xref target="jump-instructions">Jump instructions</xref>
</t> </t>
</td> </td>
</tr> </tr>
</tbody> </tbody>
</table> </table>
</section> </section>
</middle> <section anchor="acknowledgements" numbered="false">
<back> <name>Acknowledgements</name>
<references><name>Normative References</name> <t>
<reference anchor="IEN137"> This document was generated from instruction-set.rst in the Linux
<front> kernel repository, to which a number of other individuals have authored cont
<title>On Holy Wars and a Plea for Peace</title> ributions
<author fullname="D. Cohen" initials="D." surname="Cohen"/> over time, including <contact fullname="Akhil Raj"/>, <contact fullname="Ale
<date month="April" year="1980"/> xei Starovoitov"/>, <contact fullname="Brendan Jackman"/>, <contact fullname="Ch
</front> ristoph Hellwig"/>, <contact fullname="Daniel Borkmann"/>,
<seriesInfo name='IEN' value='137'/> <contact fullname="Ilya Leoshkevich"/>, <contact fullname="Jiong Wang"/>, <c
</reference> ontact fullname="Jose E.&nbsp;Marchesi"/>, <contact fullname="Kosuke Fujimoto"/>
<reference anchor="RFC2119"> ,
<front> <contact fullname="Shahab Vahedi"/>, <contact fullname="Tiezhu Yang"/>, <con
<title>Key words for use in RFCs to Indicate Requirement Levels</title> tact fullname="Will Hawkins"/>, and <contact fullname="Zheng Yejian"/>, with rev
<author fullname="S. Bradner" initials="S." surname="Bradner"/> iew and suggestions by many others including
<date month="March" year="1997"/> <contact fullname="Alan Jowett"/>, <contact fullname="Andrii Nakryiko"/>, <c
</front> ontact fullname="David Vernet"/>, <contact fullname="Jim Harris"/>,
<seriesInfo name='BCP' value='14'/> <contact fullname="Quentin Monnet"/>, <contact fullname="Song Liu"/>, <conta
<seriesInfo name='RFC' value='2119'/> ct fullname="Shung-Hsi Yu"/>, <contact fullname="Stanislav Fomichev"/>, <contact
<seriesInfo name='DOI' value='10.17487/RFC2119'/> fullname="Watson Ladd"/>, and <contact fullname="Yonghong Song"/>.
</reference> </t>
<reference anchor="RFC8126"> </section>
<front>
<title>Guidelines for Writing an IANA Considerations Section in RFCs</title> <!-- [rfced] Please review the "Inclusive Language" portion of the online
<author fullname="M. Cotton" initials="M." surname="Cotton"/> Style Guide <https://www.rfc-editor.org/styleguide/part2/#inclusive_language>
<author fullname="B. Leiba" initials="B." surname="Leiba"/> and let us know if any changes are needed. Updates of this nature typically
<author fullname="T. Narten" initials="T." surname="Narten"/> result in more precise language, which is helpful for readers.
<date month="June" year="2017"/>
</front> For example, please consider whether the following should be updated:
<seriesInfo name='BCP' value='26'/> native (2x)
<seriesInfo name='RFC' value='8126'/>
<seriesInfo name='DOI' value='10.17487/RFC8126'/> Is there a more accurate word that can be used instead of "native" as it may mea
</reference> n
<reference anchor="RFC8174"> different things in various contexts? Perhaps "built-in"?
<front>
<title>Ambiguity of Uppercase vs Lowercase in RFC 2119 Key Words</title> Section 6: original
<author fullname="B. Leiba" initials="B." surname="Leiba"/>
<date month="May" year="2017"/> Executing programs using the BPF instruction set also requires either
</front> an interpreter or a compiler to translate them to hardware processor
<seriesInfo name='BCP' value='14'/> native instructions. ... Compilers should be
<seriesInfo name='RFC' value='8174'/> audited carefully for vulnerabilities to ensure that compilation of a
<seriesInfo name='DOI' value='10.17487/RFC8174'/> trusted and verified BPF program to native processor instructions
</reference> does not introduce vulnerabilities.
</references> -->
<references><name>Informative References</name>
<reference anchor="LINUX" target="https://www.kernel.org/doc/html/latest/bpf/v </back>
erifier.html">
<front>
<title>eBPF verifier</title>
<author/>
</front>
</reference>
<reference anchor="PREVAIL">
<front>
<title>Simple and Precise Static Analysis of Untrusted Linux Kernel Extensio
ns</title>
<author fullname="E. Gershuni" initials="E." surname="Gershuni"/>
<author fullname="N. Amit" initials="N." surname="Amit"/>
<author fullname="A. Gurfinkel" initials="A." surname="Gurfinkel"/>
<author fullname="N. Narodytska" initials="N." surname="Narodytska"/>
<author fullname="J. Navas" initials="J." surname="Navas"/>
<author fullname="N. Rinetzky" initials="N." surname="Rinetzky"/>
<author fullname="L. Ryzhyk" initials="L." surname="Ryzhyk"/>
<author fullname="M. Sagiv" initials="M." surname="Sagiv"/>
<date month="June" year="2019"/>
</front>
<seriesInfo name='DOI' value='10.1145/3314221.3314590'/>
</reference>
</references>
</back>
</rfc> </rfc>
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